| /external/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 110 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, argument
117 if (I->UseIdx < UseIdx)
119 if (I->UseIdx > UseIdx)
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| H A D | MCSchedule.h | 79 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
82 unsigned UseIdx; member in struct:llvm::MCReadAdvanceEntry
87 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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| /external/llvm/lib/CodeGen/ |
| H A D | LiveRangeEdit.cpp | 76 /// OrigIdx are also available with the same value at UseIdx.
79 SlotIndex UseIdx) const {
81 UseIdx = UseIdx.getRegSlot(true);
102 if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
105 if (OVNI != li.getVNInfoAt(UseIdx))
112 SlotIndex UseIdx,
135 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
111 canRematerializeAt(Remat &RM, SlotIndex UseIdx, bool cheapAsAMove) argument
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| H A D | TargetSchedule.cpp | 145 unsigned UseIdx = 0; local
149 ++UseIdx;
151 return UseIdx;
203 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); local
204 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
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| H A D | InlineSpiller.cpp | 839 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); local
840 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
849 DEBUG(dbgs() << UseIdx << '\t' << *MI);
861 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
863 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
874 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
905 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
908 NewLI.addRange(LiveRange(DefIdx, UseIdx.getRegSlot(), DefVNI));
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| H A D | MachineVerifier.cpp | 1000 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI); local
1005 LiveRangeQuery LRQ(*LI, UseIdx);
1008 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1023 LiveRangeQuery LRQ(LI, UseIdx);
1026 *OS << UseIdx << " is not live in " << LI << '\n';
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| H A D | SplitKit.cpp | 432 SlotIndex UseIdx,
445 if (Edit->canRematerializeAt(RM, UseIdx, true)) {
430 defFromParent(unsigned RegIdx, VNInfo *ParentVNI, SlotIndex UseIdx, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) argument
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| H A D | TwoAddressInstructionPass.cpp | 1458 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber); local
1459 if (I->end == UseIdx)
1460 LI.removeRange(LastCopyIdx, UseIdx);
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| H A D | MachineInstr.cpp | 1097 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1109 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { argument
1111 MachineOperand &UseMO = getOperand(UseIdx);
1113 assert(UseMO.isUse() && "UseIdx must be a use operand");
1127 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1128 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
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| H A D | RegisterCoalescer.cpp | 631 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); local
632 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
683 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true); local
684 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
703 SlotIndex DefIdx = UseIdx.getRegSlot();
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 832 unsigned UseIdx; local
833 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
834 if (UseMI->getOperand(UseIdx).isReg() &&
835 UseMI->getOperand(UseIdx).getReg() == Reg)
838 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
839 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
841 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
870 UseMI->getOperand(UseIdx)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2867 unsigned UseIdx, unsigned UseAlign) const {
2868 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2870 return ItinData->getOperandCycle(UseClass, UseIdx);
2907 unsigned UseIdx, unsigned UseAlign) const {
2908 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2910 return ItinData->getOperandCycle(UseClass, UseIdx);
2937 unsigned UseIdx, unsigned UseAlign) const {
2941 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2942 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2992 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2864 getVSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument
2904 getSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument
2933 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument
3068 getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) argument
[all...] |