Searched refs:Cycles (Results 1 - 25 of 27) sorted by relevance

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/external/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp40 // Cycles - Number of cycles until return if HasReturn is true, otherwise
42 unsigned int Cycles; member in struct:__anon22493::VisitedBBInfo
44 VisitedBBInfo() : HasReturn(false), Cycles(0) {}
45 VisitedBBInfo(bool HasReturn, unsigned int Cycles) argument
46 : HasReturn(HasReturn), Cycles(Cycles) {}
62 unsigned int Cycles = 0);
65 unsigned int &Cycles);
113 unsigned int Cycles = 0; local
119 Cycles
144 findReturns(MachineBasicBlock *MBB, unsigned int Cycles) argument
168 cyclesUntilReturn(MachineBasicBlock *MBB, unsigned int &Cycles) argument
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/external/llvm/include/llvm/MC/
H A DMCSchedule.h52 unsigned Cycles; member in struct:llvm::MCWriteProcResEntry
55 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
65 int Cycles; member in struct:llvm::MCWriteLatencyEntry
69 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
84 int Cycles; member in struct:llvm::MCReadAdvanceEntry
88 && Cycles == Other.Cycles;
H A DMCSubtargetInfo.h123 return I->Cycles;
/external/llvm/lib/CodeGen/
H A DTargetSchedule.cpp96 static unsigned capLatency(int Cycles) { argument
97 return Cycles >= 0 ? Cycles : 1000;
195 unsigned Latency = capLatency(WLEntry->Cycles);
242 Latency = std::max(Latency, capLatency(WLEntry->Cycles));
H A DMachineTraceMetrics.cpp118 PRCycles[PI->ProcResourceIdx] += PI->Cycles;
573 Cycles.erase(I);
775 unsigned Len = LIR.Height + Cycles[DefMI].Depth;
852 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth;
860 InstrCycles &MICycles = Cycles[UseMI];
1065 unsigned Height = TBI.Succ ? Cycles.lookup(PHI).Height : 0;
1104 InstrCycles &MICycles = Cycles[MI];
1222 PRCycles += (PI->Cycles * TE.MTM.SchedModel.getResourceFactor(K));
H A DMachineScheduler.cpp1386 unsigned countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle);
1471 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1760 /// \param Cycles indicates the number of consecutive (non-pipelined) cycles
1766 countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle) { argument
1768 unsigned Count = Factor * Cycles;
1770 << " +" << Cycles << "x" << Factor << "u\n");
1859 countResource(PI->ProcResourceIdx, PI->Cycles, ReadyCycle);
1999 ResDelta.CritResources += PI->Cycles;
2001 ResDelta.DemandedResources += PI->Cycles;
/external/llvm/include/llvm/CodeGen/
H A DMachineTraceMetrics.h278 return TE.Cycles.lookup(MI);
296 DenseMap<const MachineInstr*, InstrCycles> Cycles; member in class:llvm::MachineTraceMetrics::Ensemble
360 // Cycles consumed on each processor resource per block.
/external/oprofile/events/i386/westmere/
H A Devents23 event:0x14 counters:0,1,2,3 um:arith minimum:2000000 name:ARITH : Cycles the divider is busy
27 event:0x1e counters:0,1,2,3 um:x01 minimum:2000000 name:INST_QUEUE_WRITE_CYCLES : Cycles instructions are written to the instruction queue
42 event:0x63 counters:0,1 um:cache_lock_cycles minimum:2000000 name:CACHE_LOCK_CYCLES : Cycles L1D locked
53 event:0xa8 counters:0,1,2,3 um:x01 minimum:2000000 name:LSD : Cycles when uops were delivered by the LSD
56 event:0xb1 counters:0,1,2,3 um:uops_executed minimum:2000000 name:UOPS_EXECUTED : Cycles Uops executed on any port (core count)
64 event:0xc2 counters:0,1,2,3 um:uops_retired minimum:2000000 name:UOPS_RETIRED : Cycles Uops are being retired
65 event:0xc3 counters:0,1,2,3 um:machine_clears minimum:20000 name:MACHINE_CLEARS : Cycles machine clear asserted
H A Dunit_masks19 0x01 cycles_div_busy Cycles the divider is busy
58 0x01 l1d_l2 Cycles L1D and L2 locked
59 0x02 l1d Cycles L1D locked
61 0x00 thread_p Cycles when thread is not halted (programmable counter)
196 0x01 cycles Cycles machine clear asserted
286 0x01 stall_cycles Cycles no Uops are decoded
296 0x1f core_active_cycles_no_port5 Cycles Uops executed on ports 0-4 (core count)
298 0x3f core_active_cycles Cycles Uops executed on any port (core count)
305 0x01 active_cycles Cycles Uops are being retired
/external/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp90 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
307 int Cycles = Stage->getValueAsInt("Cycles"); local
308 ItinString += " { " + itostr(Cycles) + ", ";
781 std::vector<int64_t> &Cycles,
784 Cycles.resize(PRVec.size(), 1);
803 Cycles.push_back(Cycles[i]);
822 Cycles.push_back(Cycles[
780 ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles, const CodeGenProcModel &PM) argument
961 std::vector<int64_t> Cycles = local
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/external/oprofile/events/i386/atom/
H A Devents22 event:0x14 counters:0,1 um:one minimum:6000 name:CYCLES_DIV_BUSY : Cycles the driver is busy
23 event:0x21 counters:0,1 um:core minimum:6000 name:CORE : Cycles L2 address bus is in use
24 event:0x22 counters:0,1 um:core minimum:6000 name:L2_DBUS_BUSY : Cycles the L2 cache data bus is busy
35 event:0x32 counters:0,1 um:core minimum:6000 name:L2_NO_REQ : Cycles no L2 cache requests are pending
70 event:0xC6 counters:0,1 um:cycles_int_masked minimum:6000 name:CYCLES_INT_MASKED : Cycles during which interrupts are disabled
H A Dunit_masks82 0x01 cycles_int_masked Cycles during which interrupts are disabled
83 0x02 cycles_int_pending_and_masked Cycles during which interrupts are pending and disabled
/external/oprofile/events/x86-64/family11h/
H A Devents25 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles in which the FPU is empty
32 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
78 event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
94 event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
95 event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
128 event:0x1e9 counters:0,1,2,3 um:sideband_signals_and_special_cycles minimum:500 name:SIDEBAND_SIGNALS_AND_SPECIAL_CYCLES : Sideband Signals and Special Cycles
/external/oprofile/events/mips/5K/
H A Devents8 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
/external/oprofile/events/mips/34K/
H A Devents14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
61 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
113 event:0x417 counters:1 um:zero minimum:500 name:SINGLE_THREADED_CYCLES : 23-1 Cycles while one and only one TC is eligible for scheduling
132 event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
141 event:0x430 counters:1 um:zero minimum:500 name:FB_ENTRY_ALLOCATED_CYCLES : 48-1 Cycles while at least one IFU fill buffer is allocated
/external/oprofile/events/x86-64/hammer/
H A Devents23 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles with no FPU ops retired
30 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
58 event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
89 event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
90 event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
/external/llvm/lib/Target/R600/
H A DR600InstrInfo.cpp352 unsigned Cycles[3] = { 2, 1, 0};
353 return Cycles[Op];
356 unsigned Cycles[3] = { 1, 2, 2};
357 return Cycles[Op];
360 unsigned Cycles[3] = { 2, 1, 2};
361 return Cycles[Op];
364 unsigned Cycles[3] = { 2, 2, 1};
365 return Cycles[Op];
/external/oprofile/events/mips/24K/
H A Devents14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
57 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
121 event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
129 event:0x430 counters:1 um:zero minimum:500 name:FB_ENTRY_ALLOCATED_CYCLES : 48-1 Cycles while at least one IFU fill buffer is allocated
/external/oprofile/events/mips/1004K/
H A Devents14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
62 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
121 event:0x417 counters:1 um:zero minimum:500 name:SINGLE_THREADED_CYCLES : 23-1 Cycles while one and only one TC is eligible for scheduling
141 event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
150 event:0x430 counters:1 um:zero minimum:500 name:FB_ENTRY_ALLOCATED_CYCLES : 48-1 Cycles while at least one IFU fill buffer is allocated
/external/oprofile/events/mips/74K/
H A Devents14 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : 0-0 Cycles
29 event:0xb counters:0,2 um:zero minimum:500 name:IFU_IDU_MISS_PRED_UPSTREAM_CYCLES : 11-0 Cycles IFU-IDU gate is closed (to prevent upstream from getting ahead) due to mispredicted branch
30 event:0xc counters:0,2 um:zero minimum:500 name:IFU_IDU_CLOGED_DOWNSTREAM_CYCLES : 12-0 Cycles IFU-IDU gate is closed (waiting for downstream to unclog) due to MTC0/MFC0 sequence in pipe, EHB, or blocked DD, DR, or DS
72 event:0x38 counters:0,2 um:zero minimum:500 name:MISPREDICTION_STALLS : 56-0 Cycles from the time of a pipe kill due to mispredict until the first new instruction graduates
105 event:0x40b counters:1,3 um:zero minimum:500 name:IFU_IDU_NO_FETCH_CYCLES : 11-1 Cycles IFU-IDU gate open but no instructions fetched by IFU
123 event:0x41d counters:1,3 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 29-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
/external/oprofile/events/mips/r10000/
H A Devents6 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
/external/oprofile/events/mips/r12000/
H A Devents4 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : Cycles
/external/oprofile/events/mips/rm7000/
H A Devents28 event:0x18 counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_DUE_MULTIPLIER_BUSY : Slip Cycles due to multiplier busy
/external/chromium_org/content/renderer/pepper/
H A Dv8_var_converter_unittest.cc329 TEST_F(V8VarConverterTest, Cycles) {
/external/oprofile/events/x86-64/family10/
H A Dunit_masks239 0x02 Cycles in speculative phase
240 0x04 Cycles in non-speculative phase (including cache miss penalty)

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