Searched refs:GPR4AlignEncode (Results 1 - 6 of 6) sorted by relevance
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDGPUCodeEmitter.h | 24 virtual unsigned GPR4AlignEncode(const MachineInstr &MI, function in class:llvm::AMDGPUCodeEmitter
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDGPUCodeEmitter.h | 24 virtual unsigned GPR4AlignEncode(const MachineInstr &MI, function in class:llvm::AMDGPUCodeEmitter
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
| H A D | AMDGPUMCCodeEmitter.h | 36 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, function in class:llvm::AMDGPUMCCodeEmitter
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| H A D | SIMCCodeEmitter.cpp | 90 /// GPR4AlignEncode - Encoding for when 4 consectuive registers are used
91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
173 unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI, function in class:SIMCCodeEmitter
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| H A D | AMDGPUMCCodeEmitter.h | 36 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, function in class:llvm::AMDGPUMCCodeEmitter
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| H A D | SIMCCodeEmitter.cpp | 90 /// GPR4AlignEncode - Encoding for when 4 consectuive registers are used
91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
173 unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI, function in class:SIMCCodeEmitter
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