| /external/kernel-headers/original/asm-x86/ |
| H A D | ptrace-abi.h | 35 #define R11 48 macro
52 #define ARGOFFSET R11
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 27 // are still a few places that R11 and R10 are hard wired.
37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 45 case R8: case R9: case R10: case R11:
56 case R8: case R9: case R10: case R11:
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| H A D | Thumb1FrameLowering.cpp | 136 case ARM::R11:
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| H A D | ARMBaseRegisterInfo.cpp | 48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
523 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
|
| H A D | ARMFrameLowering.cpp | 191 case ARM::R11:
219 // into spill area 1, including the FP in R11. In either case, it is
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| H A D | ARMISelLowering.cpp | 3621 ? ARM::R7 : ARM::R11;
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| H A D | sigframe-arm-linux.c | 149 SC2(fp,R11);
328 REST(fp,R11);
|
| H A D | sigframe-amd64-linux.c | 348 SC2(r11,R11);
|
| /external/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 568 Value *R11,*R12; local
570 if (decomposeBitTestICmp(RHS, RHSCC, R11, R12, R2)) {
571 if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) {
572 A = R11; D = R12;
574 A = R12; D = R11;
579 } else if (match(R1, m_And(m_Value(R11), m_Value(R12)))) {
580 if (R11
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 574 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
611 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
647 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
683 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
684 return X86::R11;
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| H A D | X86FrameLowering.cpp | 104 X86::R8, X86::R9, X86::R10, X86::R11, 0
1391 return Primary ? X86::R11 : X86::R12;
1565 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1568 MF.getRegInfo().setPhysRegUsed(X86::R11);
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCAsmPrinter.cpp | 935 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MFLR).addReg(PPC::R11));
939 .addReg(PPC::R11)
940 .addReg(PPC::R11)
951 .addReg(PPC::R11));
995 .addReg(PPC::R11)
1005 .addReg(PPC::R11));
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 172 ENTRY(R11) \
190 ENTRY(R11) \
|
| /external/valgrind/main/VEX/auxprogs/ |
| H A D | genoffsets.c | 111 GENOFFSET(AMD64,amd64,R11);
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86BaseInfo.h | 668 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreFrameLowering.cpp | 104 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
|
| /external/v8/src/ |
| H A D | platform-linux.cc | 957 enum ArmRegisters {R15 = 15, R13 = 13, R11 = 11}; enumerator in enum:v8::internal::ArmRegisters
1060 sample->fp = reinterpret_cast<Address>(mcontext.gregs[R11]);
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| /external/chromium_org/v8/src/ |
| H A D | sampler.cc | 346 state.fp = reinterpret_cast<Address>(mcontext.gregs[R11]);
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 37 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
48 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
|
| /external/libvpx/libvpx/third_party/x86inc/ |
| H A D | x86inc.asm | 405 DECLARE_REG 5, R11, R11D, R11W, R11B, 48
485 DECLARE_REG 8, R11, R11D, R11W, R11B, 24
|
| /external/valgrind/main/memcheck/ |
| H A D | mc_machine.c | 576 if (o == GOF(R11) && is1248) return o;
854 if (o == GOF(R11) && sz == 4) return o;
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2630 .Case("v8", ARM::R11)
2633 .Case("fp", ARM::R11)
2967 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
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| /external/strace/ |
| H A D | process.c | 2680 { 8*R11, "8*R11" },
2796 { 112, "R11(L)" },
2797 { 116, "R11(U)" },
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 854 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
|