| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| H A D | brw_cc.c | 110 cc->cc0.stencil_enable = 1;
111 cc->cc0.stencil_func =
113 cc->cc0.stencil_fail_op =
115 cc->cc0.stencil_pass_depth_fail_op =
117 cc->cc0.stencil_pass_depth_pass_op =
124 cc->cc0.bf_stencil_enable = 1;
125 cc->cc0.bf_stencil_func =
127 cc->cc0.bf_stencil_fail_op =
129 cc->cc0.bf_stencil_pass_depth_fail_op =
131 cc->cc0
[all...] |
| H A D | gen6_cc.c | 221 cc->cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
225 cc->cc0.stencil_ref = ctx->Stencil.Ref[0];
226 cc->cc0.bf_stencil_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace];
|
| H A D | brw_state_dump.c | 390 batch_out(brw, name, offset, 0, "cc0\n");
408 cc->cc0.alpha_test_format ? "FLOAT32" : "UNORM8",
409 cc->cc0.round_disable,
410 cc->cc0.stencil_ref,
411 cc->cc0.bf_stencil_ref);
|
| H A D | brw_structs.h | 259 } cc0; member in struct:gen6_color_calc_state
326 } cc0; member in struct:brw_cc_unit_state
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| H A D | brw_cc.c | 110 cc->cc0.stencil_enable = 1;
111 cc->cc0.stencil_func =
113 cc->cc0.stencil_fail_op =
115 cc->cc0.stencil_pass_depth_fail_op =
117 cc->cc0.stencil_pass_depth_pass_op =
124 cc->cc0.bf_stencil_enable = 1;
125 cc->cc0.bf_stencil_func =
127 cc->cc0.bf_stencil_fail_op =
129 cc->cc0.bf_stencil_pass_depth_fail_op =
131 cc->cc0
[all...] |
| H A D | gen6_cc.c | 221 cc->cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
225 cc->cc0.stencil_ref = ctx->Stencil.Ref[0];
226 cc->cc0.bf_stencil_ref = ctx->Stencil.Ref[ctx->Stencil._BackFace];
|
| H A D | brw_state_dump.c | 390 batch_out(brw, name, offset, 0, "cc0\n");
408 cc->cc0.alpha_test_format ? "FLOAT32" : "UNORM8",
409 cc->cc0.round_disable,
410 cc->cc0.stencil_ref,
411 cc->cc0.bf_stencil_ref);
|
| H A D | brw_structs.h | 259 } cc0; member in struct:gen6_color_calc_state
326 } cc0; member in struct:brw_cc_unit_state
|
| /external/valgrind/main/VEX/priv/ |
| H A D | host_s390_isel.c | 572 HReg cc0, cc1, b2, b6, cc_vex; local
574 cc0 = newVRegI(env);
575 addInstr(env, s390_insn_move(4, cc0, cc_s390));
576 addInstr(env, s390_insn_alu(4, S390_ALU_AND, cc0, s390_opnd_imm(1)));
583 addInstr(env, s390_insn_move(4, b2, cc0));
588 addInstr(env, s390_insn_move(4, b6, cc0));
595 addInstr(env, s390_insn_move(4, cc_vex, cc0));
|
| H A D | guest_ppc_toIR.c | 10032 IRTemp cc0 = newTemp( Ity_I32 ); local
10138 * If QNaN,SNaN, +infinity, -infinity then cc0, cc1 and cc2 are zero
10140 * cc0, cc1 and cc0 reflect the results of the comparisons.
10156 assign( cc0, binop( Iop_And32,
10196 mkexpr( cc0 ),
|
| H A D | guest_s390_toIR.c | 10025 IRTemp cc0 = newTemp(Ity_I32); local
10037 assign(cc0, mkexpr(b0));
10044 return binop(Iop_Or32, mkexpr(cc0), binop(Iop_Shl32, mkexpr(cc1), mkU8(1)));
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 16838 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); local
16842 X86::CondCode tmp = cc0;
16843 cc0 = cc1;
16847 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
16848 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
16854 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
|