/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.h | 75 static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) { argument 77 return isPPC64 ? 16 : 8; 79 return isPPC64 ? 16 : 4; 84 static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) { argument 91 return isPPC64 ? -8U : -4U; 94 return isPPC64 ? -8U : -4U; 99 static unsigned getBasePointerSaveOffset(bool isPPC64, bool isDarwinABI) { argument 101 return isPPC64 ? -16U : -8U; 104 return isPPC64 ? -16U : -8U; 109 static unsigned getLinkageSize(bool isPPC64, boo argument 119 getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) argument 136 getMinCallFrameSize(bool isPPC64, bool isDarwinABI) argument [all...] |
H A D | PPCSubtarget.h | 130 if (isPPC64() && isSVR4ABI()) { 137 return isPPC64() ? "E-p:64:64-f64:64:64-i64:64:64-f128:64:128-n32:64" 148 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode. 150 bool isPPC64() const { return IsPPC64; } function in class:llvm::PPCSubtarget
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H A D | PPCFrameLowering.cpp | 224 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 241 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 375 bool isPPC64 = Subtarget.isPPC64(); local 386 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 396 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 409 PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI); 413 if (isPPC64) { 485 if (!isPPC64) { 603 unsigned Reg = isPPC64 717 bool isPPC64 = Subtarget.isPPC64(); local 963 bool isPPC64 = Subtarget.isPPC64(); local 1321 restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) argument [all...] |
H A D | PPCRegisterInfo.cpp | 60 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, 61 ST.isPPC64() ? 0 : 1, 62 ST.isPPC64() ? 0 : 1), 89 if (Subtarget.isPPC64()) 94 if (Subtarget.isPPC64()) 102 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 109 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 120 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 127 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ? 180 if (Subtarget.isPPC64()) { [all...] |
H A D | PPCAsmPrinter.cpp | 502 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); 534 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); 550 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); 566 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); 586 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); 602 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); 618 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); 638 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); 654 assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC"); 730 if (!Subtarget.isPPC64()) // linu 766 bool isPPC64 = TD->getPointerSizeInBits() == 64; local 896 bool isPPC64 = TM.getDataLayout()->getPointerSizeInBits() == 64; local 1032 bool isPPC64 = TM.getDataLayout()->getPointerSizeInBits() == 64; local [all...] |
H A D | PPCInstrInfo.cpp | 230 bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); local 271 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 282 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 320 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 334 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 398 bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); local 406 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : 407 (isPPC64 862 bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); local 929 bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); local 943 bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); local 965 bool isPPC64 = TM.getSubtargetImpl()->isPPC64(); local [all...] |
H A D | PPCISelLowering.cpp | 71 bool isPPC64 = Subtarget->isPPC64(); local 72 setMinStackArgumentAlignment(isPPC64 ? 8:4); 264 if (isPPC64) { 283 if (Subtarget->isSVR4ABI() && !isPPC64) 326 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64()) 514 if (isPPC64) { 556 if (isPPC64 && Subtarget->isJITCodeModel()) 596 if (PPCSubTarget.isPPC64()) 1142 Base = DAG.getRegister(PPCSubTarget.isPPC64() 1684 bool isPPC64 = (PtrVT == MVT::i64); local 2486 bool isPPC64 = PtrVT == MVT::i64; local 2825 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, bool isPPC64, bool isVarArg, unsigned CC, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, unsigned &nAltivecParamsAtEnd) argument 2993 EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, bool isPPC64, bool isDarwinABI, SDLoc dl) argument 3034 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) argument 3098 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, SDLoc dl) argument 3123 PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, bool isDarwinABI, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) argument 3157 bool isPPC64 = PPCSubTarget.isPPC64(); local 4130 bool isPPC64 = PtrVT == MVT::i64; local 4537 bool isPPC64 = Subtarget.isPPC64(); local 4563 bool isPPC64 = PPCSubTarget.isPPC64(); local 4587 bool isPPC64 = PPCSubTarget.isPPC64(); local 7775 bool isPPC64 = PPCSubTarget.isPPC64(); local 7802 bool isPPC64 = PtrVT == MVT::i64; local [all...] |
H A D | PPCSubtarget.cpp | 177 if (isPPC64())
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H A D | PPCTargetTransformInfo.cpp | 144 if (ST->isPPC64())
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H A D | PPCISelDAGToDAG.cpp | 716 bool isPPC64 = (PtrVT == MVT::i64); local 732 if (isPPC64) break; 756 if (isPPC64) break; 765 if (isPPC64) break; 1183 bool isPPC64 = (PtrVT == MVT::i64); local 1186 if (!isPPC64) 1223 bool IsPPC64 = PPCSubTarget.isPPC64(); 1261 assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI"); 1392 if (PPCSubTarget.isDarwin() || !PPCSubTarget.isPPC64())
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H A D | PPCFastISel.cpp | 323 if (Subtarget->isPPC64() && Subtarget->isSVR4ABI())
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H A D | PPCISelLowering.h | 572 unsigned MinReservedArea, bool isPPC64) const;
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.cpp | 45 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 || local 47 unsigned Flavour = isPPC64 ? 0 : 1; 48 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; 64 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 || local 69 MAI = new PPCMCAsmInfoDarwin(isPPC64); 71 MAI = new PPCLinuxMCAsmInfo(isPPC64); 74 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 185 bool isPPC64() const { return IsPPC64; } function in class:__anon22373::PPCAsmParser 307 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 308 bool isPPC64() const { return IsPPC64; } function in struct:__anon22373::PPCOperand 410 if (isPPC64()) 417 if (isPPC64()) 892 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 896 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 905 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 1111 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64()); 1133 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()); [all...] |