Targets.cpp revision 56e1f1f7abda394b81a5df7f75d3c6e0a570d6c0 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "5621");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.getOS() == llvm::Triple::IOS) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else {
153    // Note that the Driver allows versions which aren't representable in the
154    // define (because we only get a single digit for the minor and micro
155    // revision numbers). So, we limit them to the maximum representable
156    // version.
157    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159    char Str[5];
160    Str[0] = '0' + (Maj / 10);
161    Str[1] = '0' + (Maj % 10);
162    Str[2] = '0' + std::min(Min, 9U);
163    Str[3] = '0' + std::min(Rev, 9U);
164    Str[4] = '\0';
165    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166  }
167
168  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169}
170
171namespace {
172template<typename Target>
173class DarwinTargetInfo : public OSTargetInfo<Target> {
174protected:
175  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                            MacroBuilder &Builder) const {
177    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                     this->PlatformMinVersion);
179  }
180
181public:
182  DarwinTargetInfo(const std::string& triple) :
183    OSTargetInfo<Target>(triple) {
184      llvm::Triple T = llvm::Triple(triple);
185      this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186      this->MCountName = "\01mcount";
187    }
188
189  virtual std::string isValidSectionSpecifier(StringRef SR) const {
190    // Let MCSectionMachO validate this.
191    StringRef Segment, Section;
192    unsigned TAA, StubSize;
193    bool HasTAA;
194    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                       TAA, HasTAA, StubSize);
196  }
197
198  virtual const char *getStaticInitSectionSpecifier() const {
199    // FIXME: We should return 0 when building kexts.
200    return "__TEXT,__StaticInit,regular,pure_instructions";
201  }
202
203  /// Darwin does not support protected visibility.  Darwin's "default"
204  /// is very similar to ELF's "protected";  Darwin requires a "weak"
205  /// attribute on declarations that can be dynamically replaced.
206  virtual bool hasProtectedVisibility() const {
207    return false;
208  }
209};
210
211
212// DragonFlyBSD Target
213template<typename Target>
214class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215protected:
216  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                            MacroBuilder &Builder) const {
218    // DragonFly defines; list based off of gcc output
219    Builder.defineMacro("__DragonFly__");
220    Builder.defineMacro("__DragonFly_cc_version", "100001");
221    Builder.defineMacro("__ELF__");
222    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223    Builder.defineMacro("__tune_i386__");
224    DefineStd(Builder, "unix", Opts);
225  }
226public:
227  DragonFlyBSDTargetInfo(const std::string &triple)
228    : OSTargetInfo<Target>(triple) {
229      this->UserLabelPrefix = "";
230
231      llvm::Triple Triple(triple);
232      switch (Triple.getArch()) {
233        default:
234        case llvm::Triple::x86:
235        case llvm::Triple::x86_64:
236          this->MCountName = ".mcount";
237          break;
238      }
239  }
240};
241
242// FreeBSD Target
243template<typename Target>
244class FreeBSDTargetInfo : public OSTargetInfo<Target> {
245protected:
246  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247                            MacroBuilder &Builder) const {
248    // FreeBSD defines; list based off of gcc output
249
250    unsigned Release = Triple.getOSMajorVersion();
251    if (Release == 0U)
252      Release = 8;
253
254    Builder.defineMacro("__FreeBSD__", Twine(Release));
255    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257    DefineStd(Builder, "unix", Opts);
258    Builder.defineMacro("__ELF__");
259  }
260public:
261  FreeBSDTargetInfo(const std::string &triple)
262    : OSTargetInfo<Target>(triple) {
263      this->UserLabelPrefix = "";
264
265      llvm::Triple Triple(triple);
266      switch (Triple.getArch()) {
267        default:
268        case llvm::Triple::x86:
269        case llvm::Triple::x86_64:
270          this->MCountName = ".mcount";
271          break;
272        case llvm::Triple::mips:
273        case llvm::Triple::mipsel:
274        case llvm::Triple::ppc:
275        case llvm::Triple::ppc64:
276          this->MCountName = "_mcount";
277          break;
278        case llvm::Triple::arm:
279          this->MCountName = "__mcount";
280          break;
281      }
282
283    }
284};
285
286// Minix Target
287template<typename Target>
288class MinixTargetInfo : public OSTargetInfo<Target> {
289protected:
290  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291                            MacroBuilder &Builder) const {
292    // Minix defines
293
294    Builder.defineMacro("__minix", "3");
295    Builder.defineMacro("_EM_WSIZE", "4");
296    Builder.defineMacro("_EM_PSIZE", "4");
297    Builder.defineMacro("_EM_SSIZE", "2");
298    Builder.defineMacro("_EM_LSIZE", "4");
299    Builder.defineMacro("_EM_FSIZE", "4");
300    Builder.defineMacro("_EM_DSIZE", "8");
301    Builder.defineMacro("__ELF__");
302    DefineStd(Builder, "unix", Opts);
303  }
304public:
305  MinixTargetInfo(const std::string &triple)
306    : OSTargetInfo<Target>(triple) {
307      this->UserLabelPrefix = "";
308    }
309};
310
311// Linux target
312template<typename Target>
313class LinuxTargetInfo : public OSTargetInfo<Target> {
314protected:
315  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                            MacroBuilder &Builder) const {
317    // Linux defines; list based off of gcc output
318    DefineStd(Builder, "unix", Opts);
319    DefineStd(Builder, "linux", Opts);
320    Builder.defineMacro("__gnu_linux__");
321    Builder.defineMacro("__ELF__");
322    if (Triple.getEnvironment() == llvm::Triple::Android)
323      Builder.defineMacro("__ANDROID__", "1");
324    if (Opts.POSIXThreads)
325      Builder.defineMacro("_REENTRANT");
326    if (Opts.CPlusPlus)
327      Builder.defineMacro("_GNU_SOURCE");
328  }
329public:
330  LinuxTargetInfo(const std::string& triple)
331    : OSTargetInfo<Target>(triple) {
332    this->UserLabelPrefix = "";
333    this->WIntType = TargetInfo::UnsignedInt;
334  }
335
336  virtual const char *getStaticInitSectionSpecifier() const {
337    return ".text.startup";
338  }
339};
340
341// NetBSD Target
342template<typename Target>
343class NetBSDTargetInfo : public OSTargetInfo<Target> {
344protected:
345  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346                            MacroBuilder &Builder) const {
347    // NetBSD defines; list based off of gcc output
348    Builder.defineMacro("__NetBSD__");
349    Builder.defineMacro("__unix__");
350    Builder.defineMacro("__ELF__");
351    if (Opts.POSIXThreads)
352      Builder.defineMacro("_POSIX_THREADS");
353  }
354public:
355  NetBSDTargetInfo(const std::string &triple)
356    : OSTargetInfo<Target>(triple) {
357      this->UserLabelPrefix = "";
358    }
359};
360
361// OpenBSD Target
362template<typename Target>
363class OpenBSDTargetInfo : public OSTargetInfo<Target> {
364protected:
365  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366                            MacroBuilder &Builder) const {
367    // OpenBSD defines; list based off of gcc output
368
369    Builder.defineMacro("__OpenBSD__");
370    DefineStd(Builder, "unix", Opts);
371    Builder.defineMacro("__ELF__");
372    if (Opts.POSIXThreads)
373      Builder.defineMacro("_REENTRANT");
374  }
375public:
376  OpenBSDTargetInfo(const std::string &triple)
377    : OSTargetInfo<Target>(triple) {
378      this->UserLabelPrefix = "";
379      this->TLSSupported = false;
380
381      llvm::Triple Triple(triple);
382      switch (Triple.getArch()) {
383        default:
384        case llvm::Triple::x86:
385        case llvm::Triple::x86_64:
386        case llvm::Triple::arm:
387        case llvm::Triple::sparc:
388          this->MCountName = "__mcount";
389          break;
390        case llvm::Triple::mips64:
391        case llvm::Triple::mips64el:
392        case llvm::Triple::ppc:
393        case llvm::Triple::sparcv9:
394          this->MCountName = "_mcount";
395          break;
396      }
397  }
398};
399
400// Bitrig Target
401template<typename Target>
402class BitrigTargetInfo : public OSTargetInfo<Target> {
403protected:
404  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405                            MacroBuilder &Builder) const {
406    // Bitrig defines; list based off of gcc output
407
408    Builder.defineMacro("__Bitrig__");
409    DefineStd(Builder, "unix", Opts);
410    Builder.defineMacro("__ELF__");
411    if (Opts.POSIXThreads)
412      Builder.defineMacro("_REENTRANT");
413  }
414public:
415  BitrigTargetInfo(const std::string &triple)
416    : OSTargetInfo<Target>(triple) {
417      this->UserLabelPrefix = "";
418      this->TLSSupported = false;
419      this->MCountName = "__mcount";
420  }
421};
422
423// PSP Target
424template<typename Target>
425class PSPTargetInfo : public OSTargetInfo<Target> {
426protected:
427  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428                            MacroBuilder &Builder) const {
429    // PSP defines; list based on the output of the pspdev gcc toolchain.
430    Builder.defineMacro("PSP");
431    Builder.defineMacro("_PSP");
432    Builder.defineMacro("__psp__");
433    Builder.defineMacro("__ELF__");
434  }
435public:
436  PSPTargetInfo(const std::string& triple)
437    : OSTargetInfo<Target>(triple) {
438    this->UserLabelPrefix = "";
439  }
440};
441
442// PS3 PPU Target
443template<typename Target>
444class PS3PPUTargetInfo : public OSTargetInfo<Target> {
445protected:
446  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                            MacroBuilder &Builder) const {
448    // PS3 PPU defines.
449    Builder.defineMacro("__PPC__");
450    Builder.defineMacro("__PPU__");
451    Builder.defineMacro("__CELLOS_LV2__");
452    Builder.defineMacro("__ELF__");
453    Builder.defineMacro("__LP32__");
454    Builder.defineMacro("_ARCH_PPC64");
455    Builder.defineMacro("__powerpc64__");
456  }
457public:
458  PS3PPUTargetInfo(const std::string& triple)
459    : OSTargetInfo<Target>(triple) {
460    this->UserLabelPrefix = "";
461    this->LongWidth = this->LongAlign = 32;
462    this->PointerWidth = this->PointerAlign = 32;
463    this->IntMaxType = TargetInfo::SignedLongLong;
464    this->UIntMaxType = TargetInfo::UnsignedLongLong;
465    this->Int64Type = TargetInfo::SignedLongLong;
466    this->SizeType = TargetInfo::UnsignedInt;
467    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
469  }
470};
471
472// FIXME: Need a real SPU target.
473// PS3 SPU Target
474template<typename Target>
475class PS3SPUTargetInfo : public OSTargetInfo<Target> {
476protected:
477  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478                            MacroBuilder &Builder) const {
479    // PS3 PPU defines.
480    Builder.defineMacro("__SPU__");
481    Builder.defineMacro("__ELF__");
482  }
483public:
484  PS3SPUTargetInfo(const std::string& triple)
485    : OSTargetInfo<Target>(triple) {
486    this->UserLabelPrefix = "";
487  }
488};
489
490// AuroraUX target
491template<typename Target>
492class AuroraUXTargetInfo : public OSTargetInfo<Target> {
493protected:
494  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                            MacroBuilder &Builder) const {
496    DefineStd(Builder, "sun", Opts);
497    DefineStd(Builder, "unix", Opts);
498    Builder.defineMacro("__ELF__");
499    Builder.defineMacro("__svr4__");
500    Builder.defineMacro("__SVR4");
501  }
502public:
503  AuroraUXTargetInfo(const std::string& triple)
504    : OSTargetInfo<Target>(triple) {
505    this->UserLabelPrefix = "";
506    this->WCharType = this->SignedLong;
507    // FIXME: WIntType should be SignedLong
508  }
509};
510
511// Solaris target
512template<typename Target>
513class SolarisTargetInfo : public OSTargetInfo<Target> {
514protected:
515  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516                            MacroBuilder &Builder) const {
517    DefineStd(Builder, "sun", Opts);
518    DefineStd(Builder, "unix", Opts);
519    Builder.defineMacro("__ELF__");
520    Builder.defineMacro("__svr4__");
521    Builder.defineMacro("__SVR4");
522    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523    // newer, but to 500 for everything else.  feature_test.h has a check to
524    // ensure that you are not using C99 with an old version of X/Open or C89
525    // with a new version.
526    if (Opts.C99 || Opts.C11)
527      Builder.defineMacro("_XOPEN_SOURCE", "600");
528    else
529      Builder.defineMacro("_XOPEN_SOURCE", "500");
530    if (Opts.CPlusPlus)
531      Builder.defineMacro("__C99FEATURES__");
532    Builder.defineMacro("_LARGEFILE_SOURCE");
533    Builder.defineMacro("_LARGEFILE64_SOURCE");
534    Builder.defineMacro("__EXTENSIONS__");
535    Builder.defineMacro("_REENTRANT");
536  }
537public:
538  SolarisTargetInfo(const std::string& triple)
539    : OSTargetInfo<Target>(triple) {
540    this->UserLabelPrefix = "";
541    this->WCharType = this->SignedInt;
542    // FIXME: WIntType should be SignedLong
543  }
544};
545
546// Windows target
547template<typename Target>
548class WindowsTargetInfo : public OSTargetInfo<Target> {
549protected:
550  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551                            MacroBuilder &Builder) const {
552    Builder.defineMacro("_WIN32");
553  }
554  void getVisualStudioDefines(const LangOptions &Opts,
555                              MacroBuilder &Builder) const {
556    if (Opts.CPlusPlus) {
557      if (Opts.RTTI)
558        Builder.defineMacro("_CPPRTTI");
559
560      if (Opts.Exceptions)
561        Builder.defineMacro("_CPPUNWIND");
562    }
563
564    if (!Opts.CharIsSigned)
565      Builder.defineMacro("_CHAR_UNSIGNED");
566
567    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568    //        but it works for now.
569    if (Opts.POSIXThreads)
570      Builder.defineMacro("_MT");
571
572    if (Opts.MSCVersion != 0)
573      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
574
575    if (Opts.MicrosoftExt) {
576      Builder.defineMacro("_MSC_EXTENSIONS");
577
578      if (Opts.CPlusPlus11) {
579        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
582      }
583    }
584
585    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
586  }
587
588public:
589  WindowsTargetInfo(const std::string &triple)
590    : OSTargetInfo<Target>(triple) {}
591};
592
593template <typename Target>
594class NaClTargetInfo : public OSTargetInfo<Target> {
595 protected:
596  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597                            MacroBuilder &Builder) const {
598    if (Opts.POSIXThreads)
599      Builder.defineMacro("_REENTRANT");
600    if (Opts.CPlusPlus)
601      Builder.defineMacro("_GNU_SOURCE");
602
603    DefineStd(Builder, "unix", Opts);
604    Builder.defineMacro("__ELF__");
605    Builder.defineMacro("__native_client__");
606  }
607 public:
608  NaClTargetInfo(const std::string &triple)
609    : OSTargetInfo<Target>(triple) {
610    this->UserLabelPrefix = "";
611    this->LongAlign = 32;
612    this->LongWidth = 32;
613    this->PointerAlign = 32;
614    this->PointerWidth = 32;
615    this->IntMaxType = TargetInfo::SignedLongLong;
616    this->UIntMaxType = TargetInfo::UnsignedLongLong;
617    this->Int64Type = TargetInfo::SignedLongLong;
618    this->DoubleAlign = 64;
619    this->LongDoubleWidth = 64;
620    this->LongDoubleAlign = 64;
621    this->SizeType = TargetInfo::UnsignedInt;
622    this->PtrDiffType = TargetInfo::SignedInt;
623    this->IntPtrType = TargetInfo::SignedInt;
624    // RegParmMax is inherited from the underlying architecture
625    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
626    this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
627                              "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
628  }
629  virtual typename Target::CallingConvCheckResult checkCallingConvention(
630      CallingConv CC) const {
631    return CC == CC_PnaclCall ? Target::CCCR_OK :
632        Target::checkCallingConvention(CC);
633  }
634};
635} // end anonymous namespace.
636
637//===----------------------------------------------------------------------===//
638// Specific target implementations.
639//===----------------------------------------------------------------------===//
640
641namespace {
642// PPC abstract base class
643class PPCTargetInfo : public TargetInfo {
644  static const Builtin::Info BuiltinInfo[];
645  static const char * const GCCRegNames[];
646  static const TargetInfo::GCCRegAlias GCCRegAliases[];
647  std::string CPU;
648public:
649  PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
650    LongDoubleWidth = LongDoubleAlign = 128;
651    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
652  }
653
654  /// \brief Flags for architecture specific defines.
655  typedef enum {
656    ArchDefineNone  = 0,
657    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
658    ArchDefinePpcgr = 1 << 1,
659    ArchDefinePpcsq = 1 << 2,
660    ArchDefine440   = 1 << 3,
661    ArchDefine603   = 1 << 4,
662    ArchDefine604   = 1 << 5,
663    ArchDefinePwr4  = 1 << 6,
664    ArchDefinePwr5  = 1 << 7,
665    ArchDefinePwr5x = 1 << 8,
666    ArchDefinePwr6  = 1 << 9,
667    ArchDefinePwr6x = 1 << 10,
668    ArchDefinePwr7  = 1 << 11,
669    ArchDefineA2    = 1 << 12,
670    ArchDefineA2q   = 1 << 13
671  } ArchDefineTypes;
672
673  // Note: GCC recognizes the following additional cpus:
674  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
675  //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
676  //  titan, rs64.
677  virtual bool setCPU(const std::string &Name) {
678    bool CPUKnown = llvm::StringSwitch<bool>(Name)
679      .Case("generic", true)
680      .Case("440", true)
681      .Case("450", true)
682      .Case("601", true)
683      .Case("602", true)
684      .Case("603", true)
685      .Case("603e", true)
686      .Case("603ev", true)
687      .Case("604", true)
688      .Case("604e", true)
689      .Case("620", true)
690      .Case("630", true)
691      .Case("g3", true)
692      .Case("7400", true)
693      .Case("g4", true)
694      .Case("7450", true)
695      .Case("g4+", true)
696      .Case("750", true)
697      .Case("970", true)
698      .Case("g5", true)
699      .Case("a2", true)
700      .Case("a2q", true)
701      .Case("e500mc", true)
702      .Case("e5500", true)
703      .Case("power3", true)
704      .Case("pwr3", true)
705      .Case("power4", true)
706      .Case("pwr4", true)
707      .Case("power5", true)
708      .Case("pwr5", true)
709      .Case("power5x", true)
710      .Case("pwr5x", true)
711      .Case("power6", true)
712      .Case("pwr6", true)
713      .Case("power6x", true)
714      .Case("pwr6x", true)
715      .Case("power7", true)
716      .Case("pwr7", true)
717      .Case("powerpc", true)
718      .Case("ppc", true)
719      .Case("powerpc64", true)
720      .Case("ppc64", true)
721      .Default(false);
722
723    if (CPUKnown)
724      CPU = Name;
725
726    return CPUKnown;
727  }
728
729  virtual void getTargetBuiltins(const Builtin::Info *&Records,
730                                 unsigned &NumRecords) const {
731    Records = BuiltinInfo;
732    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
733  }
734
735  virtual bool isCLZForZeroUndef() const { return false; }
736
737  virtual void getTargetDefines(const LangOptions &Opts,
738                                MacroBuilder &Builder) const;
739
740  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
741
742  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
743                                 StringRef Name,
744                                 bool Enabled) const;
745
746  virtual bool hasFeature(StringRef Feature) const;
747
748  virtual void getGCCRegNames(const char * const *&Names,
749                              unsigned &NumNames) const;
750  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
751                                unsigned &NumAliases) const;
752  virtual bool validateAsmConstraint(const char *&Name,
753                                     TargetInfo::ConstraintInfo &Info) const {
754    switch (*Name) {
755    default: return false;
756    case 'O': // Zero
757      break;
758    case 'b': // Base register
759    case 'f': // Floating point register
760      Info.setAllowsRegister();
761      break;
762    // FIXME: The following are added to allow parsing.
763    // I just took a guess at what the actions should be.
764    // Also, is more specific checking needed?  I.e. specific registers?
765    case 'd': // Floating point register (containing 64-bit value)
766    case 'v': // Altivec vector register
767      Info.setAllowsRegister();
768      break;
769    case 'w':
770      switch (Name[1]) {
771        case 'd':// VSX vector register to hold vector double data
772        case 'f':// VSX vector register to hold vector float data
773        case 's':// VSX vector register to hold scalar float data
774        case 'a':// Any VSX register
775          break;
776        default:
777          return false;
778      }
779      Info.setAllowsRegister();
780      Name++; // Skip over 'w'.
781      break;
782    case 'h': // `MQ', `CTR', or `LINK' register
783    case 'q': // `MQ' register
784    case 'c': // `CTR' register
785    case 'l': // `LINK' register
786    case 'x': // `CR' register (condition register) number 0
787    case 'y': // `CR' register (condition register)
788    case 'z': // `XER[CA]' carry bit (part of the XER register)
789      Info.setAllowsRegister();
790      break;
791    case 'I': // Signed 16-bit constant
792    case 'J': // Unsigned 16-bit constant shifted left 16 bits
793              //  (use `L' instead for SImode constants)
794    case 'K': // Unsigned 16-bit constant
795    case 'L': // Signed 16-bit constant shifted left 16 bits
796    case 'M': // Constant larger than 31
797    case 'N': // Exact power of 2
798    case 'P': // Constant whose negation is a signed 16-bit constant
799    case 'G': // Floating point constant that can be loaded into a
800              // register with one instruction per word
801    case 'H': // Integer/Floating point constant that can be loaded
802              // into a register using three instructions
803      break;
804    case 'm': // Memory operand. Note that on PowerPC targets, m can
805              // include addresses that update the base register. It
806              // is therefore only safe to use `m' in an asm statement
807              // if that asm statement accesses the operand exactly once.
808              // The asm statement must also use `%U<opno>' as a
809              // placeholder for the "update" flag in the corresponding
810              // load or store instruction. For example:
811              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
812              // is correct but:
813              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
814              // is not. Use es rather than m if you don't want the base
815              // register to be updated.
816    case 'e':
817      if (Name[1] != 's')
818          return false;
819              // es: A "stable" memory operand; that is, one which does not
820              // include any automodification of the base register. Unlike
821              // `m', this constraint can be used in asm statements that
822              // might access the operand several times, or that might not
823              // access it at all.
824      Info.setAllowsMemory();
825      Name++; // Skip over 'e'.
826      break;
827    case 'Q': // Memory operand that is an offset from a register (it is
828              // usually better to use `m' or `es' in asm statements)
829    case 'Z': // Memory operand that is an indexed or indirect from a
830              // register (it is usually better to use `m' or `es' in
831              // asm statements)
832      Info.setAllowsMemory();
833      Info.setAllowsRegister();
834      break;
835    case 'R': // AIX TOC entry
836    case 'a': // Address operand that is an indexed or indirect from a
837              // register (`p' is preferable for asm statements)
838    case 'S': // Constant suitable as a 64-bit mask operand
839    case 'T': // Constant suitable as a 32-bit mask operand
840    case 'U': // System V Release 4 small data area reference
841    case 't': // AND masks that can be performed by two rldic{l, r}
842              // instructions
843    case 'W': // Vector constant that does not require memory
844    case 'j': // Vector constant that is all zeros.
845      break;
846    // End FIXME.
847    }
848    return true;
849  }
850  virtual const char *getClobbers() const {
851    return "";
852  }
853  int getEHDataRegisterNumber(unsigned RegNo) const {
854    if (RegNo == 0) return 3;
855    if (RegNo == 1) return 4;
856    return -1;
857  }
858};
859
860const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
861#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
862#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
863                                              ALL_LANGUAGES },
864#include "clang/Basic/BuiltinsPPC.def"
865};
866
867
868/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
869/// #defines that are not tied to a specific subtarget.
870void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
871                                     MacroBuilder &Builder) const {
872  // Target identification.
873  Builder.defineMacro("__ppc__");
874  Builder.defineMacro("_ARCH_PPC");
875  Builder.defineMacro("__powerpc__");
876  Builder.defineMacro("__POWERPC__");
877  if (PointerWidth == 64) {
878    Builder.defineMacro("_ARCH_PPC64");
879    Builder.defineMacro("__powerpc64__");
880    Builder.defineMacro("__ppc64__");
881  } else {
882    Builder.defineMacro("__ppc__");
883  }
884
885  // Target properties.
886  if (getTriple().getOS() != llvm::Triple::NetBSD &&
887      getTriple().getOS() != llvm::Triple::OpenBSD)
888    Builder.defineMacro("_BIG_ENDIAN");
889  Builder.defineMacro("__BIG_ENDIAN__");
890
891  // Subtarget options.
892  Builder.defineMacro("__NATURAL_ALIGNMENT__");
893  Builder.defineMacro("__REGISTER_PREFIX__", "");
894
895  // FIXME: Should be controlled by command line option.
896  Builder.defineMacro("__LONG_DOUBLE_128__");
897
898  if (Opts.AltiVec) {
899    Builder.defineMacro("__VEC__", "10206");
900    Builder.defineMacro("__ALTIVEC__");
901  }
902
903  // CPU identification.
904  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
905    .Case("440",   ArchDefineName)
906    .Case("450",   ArchDefineName | ArchDefine440)
907    .Case("601",   ArchDefineName)
908    .Case("602",   ArchDefineName | ArchDefinePpcgr)
909    .Case("603",   ArchDefineName | ArchDefinePpcgr)
910    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
911    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
912    .Case("604",   ArchDefineName | ArchDefinePpcgr)
913    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
914    .Case("620",   ArchDefineName | ArchDefinePpcgr)
915    .Case("630",   ArchDefineName | ArchDefinePpcgr)
916    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
917    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
918    .Case("750",   ArchDefineName | ArchDefinePpcgr)
919    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
920                     | ArchDefinePpcsq)
921    .Case("a2",    ArchDefineA2)
922    .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
923    .Case("pwr3",  ArchDefinePpcgr)
924    .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
925    .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
926                     | ArchDefinePpcsq)
927    .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
928                     | ArchDefinePpcgr | ArchDefinePpcsq)
929    .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
930                     | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
931    .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
932                     | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
933                     | ArchDefinePpcsq)
934    .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
935                     | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
936                     | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
937    .Case("power3",  ArchDefinePpcgr)
938    .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
939    .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
940                       | ArchDefinePpcsq)
941    .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
942                       | ArchDefinePpcgr | ArchDefinePpcsq)
943    .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
944                       | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
945    .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
946                       | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
947                       | ArchDefinePpcsq)
948    .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
949                       | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
950                       | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
951    .Default(ArchDefineNone);
952
953  if (defs & ArchDefineName)
954    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
955  if (defs & ArchDefinePpcgr)
956    Builder.defineMacro("_ARCH_PPCGR");
957  if (defs & ArchDefinePpcsq)
958    Builder.defineMacro("_ARCH_PPCSQ");
959  if (defs & ArchDefine440)
960    Builder.defineMacro("_ARCH_440");
961  if (defs & ArchDefine603)
962    Builder.defineMacro("_ARCH_603");
963  if (defs & ArchDefine604)
964    Builder.defineMacro("_ARCH_604");
965  if (defs & ArchDefinePwr4)
966    Builder.defineMacro("_ARCH_PWR4");
967  if (defs & ArchDefinePwr5)
968    Builder.defineMacro("_ARCH_PWR5");
969  if (defs & ArchDefinePwr5x)
970    Builder.defineMacro("_ARCH_PWR5X");
971  if (defs & ArchDefinePwr6)
972    Builder.defineMacro("_ARCH_PWR6");
973  if (defs & ArchDefinePwr6x)
974    Builder.defineMacro("_ARCH_PWR6X");
975  if (defs & ArchDefinePwr7)
976    Builder.defineMacro("_ARCH_PWR7");
977  if (defs & ArchDefineA2)
978    Builder.defineMacro("_ARCH_A2");
979  if (defs & ArchDefineA2q) {
980    Builder.defineMacro("_ARCH_A2Q");
981    Builder.defineMacro("_ARCH_QP");
982  }
983
984  if (getTriple().getVendor() == llvm::Triple::BGQ) {
985    Builder.defineMacro("__bg__");
986    Builder.defineMacro("__THW_BLUEGENE__");
987    Builder.defineMacro("__bgq__");
988    Builder.defineMacro("__TOS_BGQ__");
989  }
990
991  // FIXME: The following are not yet generated here by Clang, but are
992  //        generated by GCC:
993  //
994  //   _SOFT_FLOAT_
995  //   __RECIP_PRECISION__
996  //   __APPLE_ALTIVEC__
997  //   __VSX__
998  //   __RECIP__
999  //   __RECIPF__
1000  //   __RSQRTE__
1001  //   __RSQRTEF__
1002  //   _SOFT_DOUBLE_
1003  //   __NO_LWSYNC__
1004  //   __HAVE_BSWAP__
1005  //   __LONGDOUBLE128
1006  //   __CMODEL_MEDIUM__
1007  //   __CMODEL_LARGE__
1008  //   _CALL_SYSV
1009  //   _CALL_DARWIN
1010  //   __NO_FPRS__
1011}
1012
1013void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1014  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1015    .Case("7400", true)
1016    .Case("g4", true)
1017    .Case("7450", true)
1018    .Case("g4+", true)
1019    .Case("970", true)
1020    .Case("g5", true)
1021    .Case("pwr6", true)
1022    .Case("pwr7", true)
1023    .Case("ppc64", true)
1024    .Default(false);
1025
1026  Features["qpx"] = (CPU == "a2q");
1027}
1028
1029bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1030                                         StringRef Name,
1031                                         bool Enabled) const {
1032  if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1033      Name == "popcntd" || Name == "qpx") {
1034    Features[Name] = Enabled;
1035    return true;
1036  }
1037
1038  return false;
1039}
1040
1041bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1042  return Feature == "powerpc";
1043}
1044
1045
1046const char * const PPCTargetInfo::GCCRegNames[] = {
1047  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1048  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1049  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1050  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1051  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1052  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1053  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1054  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1055  "mq", "lr", "ctr", "ap",
1056  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1057  "xer",
1058  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1059  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1060  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1061  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1062  "vrsave", "vscr",
1063  "spe_acc", "spefscr",
1064  "sfp"
1065};
1066
1067void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1068                                   unsigned &NumNames) const {
1069  Names = GCCRegNames;
1070  NumNames = llvm::array_lengthof(GCCRegNames);
1071}
1072
1073const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1074  // While some of these aliases do map to different registers
1075  // they still share the same register name.
1076  { { "0" }, "r0" },
1077  { { "1"}, "r1" },
1078  { { "2" }, "r2" },
1079  { { "3" }, "r3" },
1080  { { "4" }, "r4" },
1081  { { "5" }, "r5" },
1082  { { "6" }, "r6" },
1083  { { "7" }, "r7" },
1084  { { "8" }, "r8" },
1085  { { "9" }, "r9" },
1086  { { "10" }, "r10" },
1087  { { "11" }, "r11" },
1088  { { "12" }, "r12" },
1089  { { "13" }, "r13" },
1090  { { "14" }, "r14" },
1091  { { "15" }, "r15" },
1092  { { "16" }, "r16" },
1093  { { "17" }, "r17" },
1094  { { "18" }, "r18" },
1095  { { "19" }, "r19" },
1096  { { "20" }, "r20" },
1097  { { "21" }, "r21" },
1098  { { "22" }, "r22" },
1099  { { "23" }, "r23" },
1100  { { "24" }, "r24" },
1101  { { "25" }, "r25" },
1102  { { "26" }, "r26" },
1103  { { "27" }, "r27" },
1104  { { "28" }, "r28" },
1105  { { "29" }, "r29" },
1106  { { "30" }, "r30" },
1107  { { "31" }, "r31" },
1108  { { "fr0" }, "f0" },
1109  { { "fr1" }, "f1" },
1110  { { "fr2" }, "f2" },
1111  { { "fr3" }, "f3" },
1112  { { "fr4" }, "f4" },
1113  { { "fr5" }, "f5" },
1114  { { "fr6" }, "f6" },
1115  { { "fr7" }, "f7" },
1116  { { "fr8" }, "f8" },
1117  { { "fr9" }, "f9" },
1118  { { "fr10" }, "f10" },
1119  { { "fr11" }, "f11" },
1120  { { "fr12" }, "f12" },
1121  { { "fr13" }, "f13" },
1122  { { "fr14" }, "f14" },
1123  { { "fr15" }, "f15" },
1124  { { "fr16" }, "f16" },
1125  { { "fr17" }, "f17" },
1126  { { "fr18" }, "f18" },
1127  { { "fr19" }, "f19" },
1128  { { "fr20" }, "f20" },
1129  { { "fr21" }, "f21" },
1130  { { "fr22" }, "f22" },
1131  { { "fr23" }, "f23" },
1132  { { "fr24" }, "f24" },
1133  { { "fr25" }, "f25" },
1134  { { "fr26" }, "f26" },
1135  { { "fr27" }, "f27" },
1136  { { "fr28" }, "f28" },
1137  { { "fr29" }, "f29" },
1138  { { "fr30" }, "f30" },
1139  { { "fr31" }, "f31" },
1140  { { "cc" }, "cr0" },
1141};
1142
1143void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1144                                     unsigned &NumAliases) const {
1145  Aliases = GCCRegAliases;
1146  NumAliases = llvm::array_lengthof(GCCRegAliases);
1147}
1148} // end anonymous namespace.
1149
1150namespace {
1151class PPC32TargetInfo : public PPCTargetInfo {
1152public:
1153  PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1154    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1155                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1156
1157    switch (getTriple().getOS()) {
1158    case llvm::Triple::Linux:
1159    case llvm::Triple::FreeBSD:
1160    case llvm::Triple::NetBSD:
1161      SizeType = UnsignedInt;
1162      PtrDiffType = SignedInt;
1163      IntPtrType = SignedInt;
1164      break;
1165    default:
1166      break;
1167    }
1168
1169    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1170      LongDoubleWidth = LongDoubleAlign = 64;
1171      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1172    }
1173
1174    // PPC32 supports atomics up to 4 bytes.
1175    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1176  }
1177
1178  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1179    // This is the ELF definition, and is overridden by the Darwin sub-target
1180    return TargetInfo::PowerABIBuiltinVaList;
1181  }
1182};
1183} // end anonymous namespace.
1184
1185namespace {
1186class PPC64TargetInfo : public PPCTargetInfo {
1187public:
1188  PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1189    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1190    IntMaxType = SignedLong;
1191    UIntMaxType = UnsignedLong;
1192    Int64Type = SignedLong;
1193
1194    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1195      LongDoubleWidth = LongDoubleAlign = 64;
1196      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1197      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1198                          "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1199                          "v128:128:128-n32:64";
1200    } else
1201      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1202                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1203                          "v128:128:128-n32:64";
1204
1205    // PPC64 supports atomics up to 8 bytes.
1206    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1207  }
1208  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1209    return TargetInfo::CharPtrBuiltinVaList;
1210  }
1211};
1212} // end anonymous namespace.
1213
1214
1215namespace {
1216class DarwinPPC32TargetInfo :
1217  public DarwinTargetInfo<PPC32TargetInfo> {
1218public:
1219  DarwinPPC32TargetInfo(const std::string& triple)
1220    : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1221    HasAlignMac68kSupport = true;
1222    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1223    LongLongAlign = 32;
1224    SuitableAlign = 128;
1225    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1226                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1227  }
1228  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1229    return TargetInfo::CharPtrBuiltinVaList;
1230  }
1231};
1232
1233class DarwinPPC64TargetInfo :
1234  public DarwinTargetInfo<PPC64TargetInfo> {
1235public:
1236  DarwinPPC64TargetInfo(const std::string& triple)
1237    : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1238    HasAlignMac68kSupport = true;
1239    SuitableAlign = 128;
1240    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1241                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1242  }
1243};
1244} // end anonymous namespace.
1245
1246namespace {
1247  static const unsigned NVPTXAddrSpaceMap[] = {
1248    1,    // opencl_global
1249    3,    // opencl_local
1250    4,    // opencl_constant
1251    1,    // cuda_device
1252    4,    // cuda_constant
1253    3,    // cuda_shared
1254  };
1255  class NVPTXTargetInfo : public TargetInfo {
1256    static const char * const GCCRegNames[];
1257    static const Builtin::Info BuiltinInfo[];
1258    std::vector<StringRef> AvailableFeatures;
1259  public:
1260    NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1261      BigEndian = false;
1262      TLSSupported = false;
1263      LongWidth = LongAlign = 64;
1264      AddrSpaceMap = &NVPTXAddrSpaceMap;
1265      // Define available target features
1266      // These must be defined in sorted order!
1267      NoAsmVariants = true;
1268    }
1269    virtual void getTargetDefines(const LangOptions &Opts,
1270                                  MacroBuilder &Builder) const {
1271      Builder.defineMacro("__PTX__");
1272      Builder.defineMacro("__NVPTX__");
1273    }
1274    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1275                                   unsigned &NumRecords) const {
1276      Records = BuiltinInfo;
1277      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1278    }
1279    virtual bool hasFeature(StringRef Feature) const {
1280      return Feature == "ptx" || Feature == "nvptx";
1281    }
1282
1283    virtual void getGCCRegNames(const char * const *&Names,
1284                                unsigned &NumNames) const;
1285    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1286                                  unsigned &NumAliases) const {
1287      // No aliases.
1288      Aliases = 0;
1289      NumAliases = 0;
1290    }
1291    virtual bool validateAsmConstraint(const char *&Name,
1292                                       TargetInfo::ConstraintInfo &info) const {
1293      // FIXME: implement
1294      return true;
1295    }
1296    virtual const char *getClobbers() const {
1297      // FIXME: Is this really right?
1298      return "";
1299    }
1300    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1301      // FIXME: implement
1302      return TargetInfo::CharPtrBuiltinVaList;
1303    }
1304    virtual bool setCPU(const std::string &Name) {
1305      bool Valid = llvm::StringSwitch<bool>(Name)
1306        .Case("sm_20", true)
1307        .Case("sm_21", true)
1308        .Case("sm_30", true)
1309        .Case("sm_35", true)
1310        .Default(false);
1311
1312      return Valid;
1313    }
1314    virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1315                                   StringRef Name,
1316                                   bool Enabled) const;
1317  };
1318
1319  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1320#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1321#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1322                                              ALL_LANGUAGES },
1323#include "clang/Basic/BuiltinsNVPTX.def"
1324  };
1325
1326  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1327    "r0"
1328  };
1329
1330  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1331                                     unsigned &NumNames) const {
1332    Names = GCCRegNames;
1333    NumNames = llvm::array_lengthof(GCCRegNames);
1334  }
1335
1336  bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1337                                          StringRef Name,
1338                                          bool Enabled) const {
1339    if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1340                          Name)) {
1341      Features[Name] = Enabled;
1342      return true;
1343    } else {
1344      return false;
1345    }
1346  }
1347
1348  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1349  public:
1350    NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1351      PointerWidth = PointerAlign = 32;
1352      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1353      DescriptionString
1354        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1355          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1356          "n16:32:64";
1357  }
1358  };
1359
1360  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1361  public:
1362    NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1363      PointerWidth = PointerAlign = 64;
1364      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1365      DescriptionString
1366        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1367          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1368          "n16:32:64";
1369  }
1370  };
1371}
1372
1373namespace {
1374
1375static const unsigned R600AddrSpaceMap[] = {
1376  1,    // opencl_global
1377  3,    // opencl_local
1378  2,    // opencl_constant
1379  1,    // cuda_device
1380  2,    // cuda_constant
1381  3     // cuda_shared
1382};
1383
1384static const char *DescriptionStringR600 =
1385  "e"
1386  "-p:32:32:32"
1387  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1388  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1389  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1390  "-n32:64";
1391
1392static const char *DescriptionStringR600DoubleOps =
1393  "e"
1394  "-p:32:32:32"
1395  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1396  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1397  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1398  "-n32:64";
1399
1400static const char *DescriptionStringSI =
1401  "e"
1402  "-p:64:64:64"
1403  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1404  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1405  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1406  "-n32:64";
1407
1408class R600TargetInfo : public TargetInfo {
1409  /// \brief The GPU profiles supported by the R600 target.
1410  enum GPUKind {
1411    GK_NONE,
1412    GK_R600,
1413    GK_R600_DOUBLE_OPS,
1414    GK_R700,
1415    GK_R700_DOUBLE_OPS,
1416    GK_EVERGREEN,
1417    GK_EVERGREEN_DOUBLE_OPS,
1418    GK_NORTHERN_ISLANDS,
1419    GK_CAYMAN,
1420    GK_SOUTHERN_ISLANDS
1421  } GPU;
1422
1423public:
1424  R600TargetInfo(const std::string& triple)
1425    : TargetInfo(triple),
1426      GPU(GK_R600) {
1427    DescriptionString = DescriptionStringR600;
1428    AddrSpaceMap = &R600AddrSpaceMap;
1429  }
1430
1431  virtual const char * getClobbers() const {
1432    return "";
1433  }
1434
1435  virtual void getGCCRegNames(const char * const *&Names,
1436                              unsigned &numNames) const  {
1437    Names = NULL;
1438    numNames = 0;
1439  }
1440
1441  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1442                                unsigned &NumAliases) const {
1443    Aliases = NULL;
1444    NumAliases = 0;
1445  }
1446
1447  virtual bool validateAsmConstraint(const char *&Name,
1448                                     TargetInfo::ConstraintInfo &info) const {
1449    return true;
1450  }
1451
1452  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1453                                 unsigned &NumRecords) const {
1454    Records = NULL;
1455    NumRecords = 0;
1456  }
1457
1458
1459  virtual void getTargetDefines(const LangOptions &Opts,
1460                                MacroBuilder &Builder) const {
1461    Builder.defineMacro("__R600__");
1462  }
1463
1464  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1465    return TargetInfo::CharPtrBuiltinVaList;
1466  }
1467
1468  virtual bool setCPU(const std::string &Name) {
1469    GPU = llvm::StringSwitch<GPUKind>(Name)
1470      .Case("r600" ,    GK_R600)
1471      .Case("rv610",    GK_R600)
1472      .Case("rv620",    GK_R600)
1473      .Case("rv630",    GK_R600)
1474      .Case("rv635",    GK_R600)
1475      .Case("rs780",    GK_R600)
1476      .Case("rs880",    GK_R600)
1477      .Case("rv670",    GK_R600_DOUBLE_OPS)
1478      .Case("rv710",    GK_R700)
1479      .Case("rv730",    GK_R700)
1480      .Case("rv740",    GK_R700_DOUBLE_OPS)
1481      .Case("rv770",    GK_R700_DOUBLE_OPS)
1482      .Case("palm",     GK_EVERGREEN)
1483      .Case("cedar",    GK_EVERGREEN)
1484      .Case("sumo",     GK_EVERGREEN)
1485      .Case("sumo2",    GK_EVERGREEN)
1486      .Case("redwood",  GK_EVERGREEN)
1487      .Case("juniper",  GK_EVERGREEN)
1488      .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1489      .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1490      .Case("barts",    GK_NORTHERN_ISLANDS)
1491      .Case("turks",    GK_NORTHERN_ISLANDS)
1492      .Case("caicos",   GK_NORTHERN_ISLANDS)
1493      .Case("cayman",   GK_CAYMAN)
1494      .Case("aruba",    GK_CAYMAN)
1495      .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1496      .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1497      .Case("verde",    GK_SOUTHERN_ISLANDS)
1498      .Case("oland",    GK_SOUTHERN_ISLANDS)
1499      .Default(GK_NONE);
1500
1501    if (GPU == GK_NONE) {
1502      return false;
1503    }
1504
1505    // Set the correct data layout
1506    switch (GPU) {
1507    case GK_NONE:
1508    case GK_R600:
1509    case GK_R700:
1510    case GK_EVERGREEN:
1511    case GK_NORTHERN_ISLANDS:
1512      DescriptionString = DescriptionStringR600;
1513      break;
1514    case GK_R600_DOUBLE_OPS:
1515    case GK_R700_DOUBLE_OPS:
1516    case GK_EVERGREEN_DOUBLE_OPS:
1517    case GK_CAYMAN:
1518      DescriptionString = DescriptionStringR600DoubleOps;
1519      break;
1520    case GK_SOUTHERN_ISLANDS:
1521      DescriptionString = DescriptionStringSI;
1522      break;
1523    }
1524
1525    return true;
1526  }
1527};
1528
1529} // end anonymous namespace
1530
1531namespace {
1532// MBlaze abstract base class
1533class MBlazeTargetInfo : public TargetInfo {
1534  static const char * const GCCRegNames[];
1535  static const TargetInfo::GCCRegAlias GCCRegAliases[];
1536
1537public:
1538  MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1539    DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1540  }
1541
1542  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1543                                 unsigned &NumRecords) const {
1544    // FIXME: Implement.
1545    Records = 0;
1546    NumRecords = 0;
1547  }
1548
1549  virtual void getTargetDefines(const LangOptions &Opts,
1550                                MacroBuilder &Builder) const;
1551
1552  virtual bool hasFeature(StringRef Feature) const {
1553    return Feature == "mblaze";
1554  }
1555
1556  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1557    return TargetInfo::CharPtrBuiltinVaList;
1558  }
1559  virtual const char *getTargetPrefix() const {
1560    return "mblaze";
1561  }
1562  virtual void getGCCRegNames(const char * const *&Names,
1563                              unsigned &NumNames) const;
1564  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1565                                unsigned &NumAliases) const;
1566  virtual bool validateAsmConstraint(const char *&Name,
1567                                     TargetInfo::ConstraintInfo &Info) const {
1568    switch (*Name) {
1569    default: return false;
1570    case 'O': // Zero
1571      return true;
1572    case 'b': // Base register
1573    case 'f': // Floating point register
1574      Info.setAllowsRegister();
1575      return true;
1576    }
1577  }
1578  virtual const char *getClobbers() const {
1579    return "";
1580  }
1581};
1582
1583/// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1584/// #defines that are not tied to a specific subtarget.
1585void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1586                                     MacroBuilder &Builder) const {
1587  // Target identification.
1588  Builder.defineMacro("__microblaze__");
1589  Builder.defineMacro("_ARCH_MICROBLAZE");
1590  Builder.defineMacro("__MICROBLAZE__");
1591
1592  // Target properties.
1593  Builder.defineMacro("_BIG_ENDIAN");
1594  Builder.defineMacro("__BIG_ENDIAN__");
1595
1596  // Subtarget options.
1597  Builder.defineMacro("__REGISTER_PREFIX__", "");
1598}
1599
1600
1601const char * const MBlazeTargetInfo::GCCRegNames[] = {
1602  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1603  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1604  "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1605  "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1606  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1607  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1608  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1609  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1610  "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1611  "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1612};
1613
1614void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1615                                   unsigned &NumNames) const {
1616  Names = GCCRegNames;
1617  NumNames = llvm::array_lengthof(GCCRegNames);
1618}
1619
1620const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1621  { {"f0"},  "r0" },
1622  { {"f1"},  "r1" },
1623  { {"f2"},  "r2" },
1624  { {"f3"},  "r3" },
1625  { {"f4"},  "r4" },
1626  { {"f5"},  "r5" },
1627  { {"f6"},  "r6" },
1628  { {"f7"},  "r7" },
1629  { {"f8"},  "r8" },
1630  { {"f9"},  "r9" },
1631  { {"f10"}, "r10" },
1632  { {"f11"}, "r11" },
1633  { {"f12"}, "r12" },
1634  { {"f13"}, "r13" },
1635  { {"f14"}, "r14" },
1636  { {"f15"}, "r15" },
1637  { {"f16"}, "r16" },
1638  { {"f17"}, "r17" },
1639  { {"f18"}, "r18" },
1640  { {"f19"}, "r19" },
1641  { {"f20"}, "r20" },
1642  { {"f21"}, "r21" },
1643  { {"f22"}, "r22" },
1644  { {"f23"}, "r23" },
1645  { {"f24"}, "r24" },
1646  { {"f25"}, "r25" },
1647  { {"f26"}, "r26" },
1648  { {"f27"}, "r27" },
1649  { {"f28"}, "r28" },
1650  { {"f29"}, "r29" },
1651  { {"f30"}, "r30" },
1652  { {"f31"}, "r31" },
1653};
1654
1655void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1656                                     unsigned &NumAliases) const {
1657  Aliases = GCCRegAliases;
1658  NumAliases = llvm::array_lengthof(GCCRegAliases);
1659}
1660} // end anonymous namespace.
1661
1662namespace {
1663// Namespace for x86 abstract base class
1664const Builtin::Info BuiltinInfo[] = {
1665#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1666#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1667                                              ALL_LANGUAGES },
1668#include "clang/Basic/BuiltinsX86.def"
1669};
1670
1671static const char* const GCCRegNames[] = {
1672  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1673  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1674  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1675  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1676  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1677  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1678  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1679  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1680  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1681};
1682
1683const TargetInfo::AddlRegName AddlRegNames[] = {
1684  { { "al", "ah", "eax", "rax" }, 0 },
1685  { { "bl", "bh", "ebx", "rbx" }, 3 },
1686  { { "cl", "ch", "ecx", "rcx" }, 2 },
1687  { { "dl", "dh", "edx", "rdx" }, 1 },
1688  { { "esi", "rsi" }, 4 },
1689  { { "edi", "rdi" }, 5 },
1690  { { "esp", "rsp" }, 7 },
1691  { { "ebp", "rbp" }, 6 },
1692};
1693
1694// X86 target abstract base class; x86-32 and x86-64 are very close, so
1695// most of the implementation can be shared.
1696class X86TargetInfo : public TargetInfo {
1697  enum X86SSEEnum {
1698    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1699  } SSELevel;
1700  enum MMX3DNowEnum {
1701    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1702  } MMX3DNowLevel;
1703
1704  bool HasAES;
1705  bool HasPCLMUL;
1706  bool HasLZCNT;
1707  bool HasRDRND;
1708  bool HasBMI;
1709  bool HasBMI2;
1710  bool HasPOPCNT;
1711  bool HasRTM;
1712  bool HasPRFCHW;
1713  bool HasRDSEED;
1714  bool HasSSE4a;
1715  bool HasFMA4;
1716  bool HasFMA;
1717  bool HasXOP;
1718  bool HasF16C;
1719
1720  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1721  ///
1722  /// Each enumeration represents a particular CPU supported by Clang. These
1723  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1724  enum CPUKind {
1725    CK_Generic,
1726
1727    /// \name i386
1728    /// i386-generation processors.
1729    //@{
1730    CK_i386,
1731    //@}
1732
1733    /// \name i486
1734    /// i486-generation processors.
1735    //@{
1736    CK_i486,
1737    CK_WinChipC6,
1738    CK_WinChip2,
1739    CK_C3,
1740    //@}
1741
1742    /// \name i586
1743    /// i586-generation processors, P5 microarchitecture based.
1744    //@{
1745    CK_i586,
1746    CK_Pentium,
1747    CK_PentiumMMX,
1748    //@}
1749
1750    /// \name i686
1751    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1752    //@{
1753    CK_i686,
1754    CK_PentiumPro,
1755    CK_Pentium2,
1756    CK_Pentium3,
1757    CK_Pentium3M,
1758    CK_PentiumM,
1759    CK_C3_2,
1760
1761    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1762    /// Clang however has some logic to suport this.
1763    // FIXME: Warn, deprecate, and potentially remove this.
1764    CK_Yonah,
1765    //@}
1766
1767    /// \name Netburst
1768    /// Netburst microarchitecture based processors.
1769    //@{
1770    CK_Pentium4,
1771    CK_Pentium4M,
1772    CK_Prescott,
1773    CK_Nocona,
1774    //@}
1775
1776    /// \name Core
1777    /// Core microarchitecture based processors.
1778    //@{
1779    CK_Core2,
1780
1781    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1782    /// codename which GCC no longer accepts as an option to -march, but Clang
1783    /// has some logic for recognizing it.
1784    // FIXME: Warn, deprecate, and potentially remove this.
1785    CK_Penryn,
1786    //@}
1787
1788    /// \name Atom
1789    /// Atom processors
1790    //@{
1791    CK_Atom,
1792    //@}
1793
1794    /// \name Nehalem
1795    /// Nehalem microarchitecture based processors.
1796    //@{
1797    CK_Corei7,
1798    CK_Corei7AVX,
1799    CK_CoreAVXi,
1800    CK_CoreAVX2,
1801    //@}
1802
1803    /// \name K6
1804    /// K6 architecture processors.
1805    //@{
1806    CK_K6,
1807    CK_K6_2,
1808    CK_K6_3,
1809    //@}
1810
1811    /// \name K7
1812    /// K7 architecture processors.
1813    //@{
1814    CK_Athlon,
1815    CK_AthlonThunderbird,
1816    CK_Athlon4,
1817    CK_AthlonXP,
1818    CK_AthlonMP,
1819    //@}
1820
1821    /// \name K8
1822    /// K8 architecture processors.
1823    //@{
1824    CK_Athlon64,
1825    CK_Athlon64SSE3,
1826    CK_AthlonFX,
1827    CK_K8,
1828    CK_K8SSE3,
1829    CK_Opteron,
1830    CK_OpteronSSE3,
1831    CK_AMDFAM10,
1832    //@}
1833
1834    /// \name Bobcat
1835    /// Bobcat architecture processors.
1836    //@{
1837    CK_BTVER1,
1838    //@}
1839
1840    /// \name Bulldozer
1841    /// Bulldozer architecture processors.
1842    //@{
1843    CK_BDVER1,
1844    CK_BDVER2,
1845    //@}
1846
1847    /// This specification is deprecated and will be removed in the future.
1848    /// Users should prefer \see CK_K8.
1849    // FIXME: Warn on this when the CPU is set to it.
1850    CK_x86_64,
1851    //@}
1852
1853    /// \name Geode
1854    /// Geode processors.
1855    //@{
1856    CK_Geode
1857    //@}
1858  } CPU;
1859
1860public:
1861  X86TargetInfo(const std::string& triple)
1862    : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1863      HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1864      HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1865      HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1866      HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1867    BigEndian = false;
1868    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1869  }
1870  virtual unsigned getFloatEvalMethod() const {
1871    // X87 evaluates with 80 bits "long double" precision.
1872    return SSELevel == NoSSE ? 2 : 0;
1873  }
1874  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1875                                 unsigned &NumRecords) const {
1876    Records = BuiltinInfo;
1877    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1878  }
1879  virtual void getGCCRegNames(const char * const *&Names,
1880                              unsigned &NumNames) const {
1881    Names = GCCRegNames;
1882    NumNames = llvm::array_lengthof(GCCRegNames);
1883  }
1884  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1885                                unsigned &NumAliases) const {
1886    Aliases = 0;
1887    NumAliases = 0;
1888  }
1889  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1890                                  unsigned &NumNames) const {
1891    Names = AddlRegNames;
1892    NumNames = llvm::array_lengthof(AddlRegNames);
1893  }
1894  virtual bool validateAsmConstraint(const char *&Name,
1895                                     TargetInfo::ConstraintInfo &info) const;
1896  virtual std::string convertConstraint(const char *&Constraint) const;
1897  virtual const char *getClobbers() const {
1898    return "~{dirflag},~{fpsr},~{flags}";
1899  }
1900  virtual void getTargetDefines(const LangOptions &Opts,
1901                                MacroBuilder &Builder) const;
1902  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1903                                 StringRef Name,
1904                                 bool Enabled) const;
1905  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1906  virtual bool hasFeature(StringRef Feature) const;
1907  virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1908  virtual const char* getABI() const {
1909    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1910      return "avx";
1911    else if (getTriple().getArch() == llvm::Triple::x86 &&
1912             MMX3DNowLevel == NoMMX3DNow)
1913      return "no-mmx";
1914    return "";
1915  }
1916  virtual bool setCPU(const std::string &Name) {
1917    CPU = llvm::StringSwitch<CPUKind>(Name)
1918      .Case("i386", CK_i386)
1919      .Case("i486", CK_i486)
1920      .Case("winchip-c6", CK_WinChipC6)
1921      .Case("winchip2", CK_WinChip2)
1922      .Case("c3", CK_C3)
1923      .Case("i586", CK_i586)
1924      .Case("pentium", CK_Pentium)
1925      .Case("pentium-mmx", CK_PentiumMMX)
1926      .Case("i686", CK_i686)
1927      .Case("pentiumpro", CK_PentiumPro)
1928      .Case("pentium2", CK_Pentium2)
1929      .Case("pentium3", CK_Pentium3)
1930      .Case("pentium3m", CK_Pentium3M)
1931      .Case("pentium-m", CK_PentiumM)
1932      .Case("c3-2", CK_C3_2)
1933      .Case("yonah", CK_Yonah)
1934      .Case("pentium4", CK_Pentium4)
1935      .Case("pentium4m", CK_Pentium4M)
1936      .Case("prescott", CK_Prescott)
1937      .Case("nocona", CK_Nocona)
1938      .Case("core2", CK_Core2)
1939      .Case("penryn", CK_Penryn)
1940      .Case("atom", CK_Atom)
1941      .Case("corei7", CK_Corei7)
1942      .Case("corei7-avx", CK_Corei7AVX)
1943      .Case("core-avx-i", CK_CoreAVXi)
1944      .Case("core-avx2", CK_CoreAVX2)
1945      .Case("k6", CK_K6)
1946      .Case("k6-2", CK_K6_2)
1947      .Case("k6-3", CK_K6_3)
1948      .Case("athlon", CK_Athlon)
1949      .Case("athlon-tbird", CK_AthlonThunderbird)
1950      .Case("athlon-4", CK_Athlon4)
1951      .Case("athlon-xp", CK_AthlonXP)
1952      .Case("athlon-mp", CK_AthlonMP)
1953      .Case("athlon64", CK_Athlon64)
1954      .Case("athlon64-sse3", CK_Athlon64SSE3)
1955      .Case("athlon-fx", CK_AthlonFX)
1956      .Case("k8", CK_K8)
1957      .Case("k8-sse3", CK_K8SSE3)
1958      .Case("opteron", CK_Opteron)
1959      .Case("opteron-sse3", CK_OpteronSSE3)
1960      .Case("amdfam10", CK_AMDFAM10)
1961      .Case("btver1", CK_BTVER1)
1962      .Case("bdver1", CK_BDVER1)
1963      .Case("bdver2", CK_BDVER2)
1964      .Case("x86-64", CK_x86_64)
1965      .Case("geode", CK_Geode)
1966      .Default(CK_Generic);
1967
1968    // Perform any per-CPU checks necessary to determine if this CPU is
1969    // acceptable.
1970    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1971    // invalid without explaining *why*.
1972    switch (CPU) {
1973    case CK_Generic:
1974      // No processor selected!
1975      return false;
1976
1977    case CK_i386:
1978    case CK_i486:
1979    case CK_WinChipC6:
1980    case CK_WinChip2:
1981    case CK_C3:
1982    case CK_i586:
1983    case CK_Pentium:
1984    case CK_PentiumMMX:
1985    case CK_i686:
1986    case CK_PentiumPro:
1987    case CK_Pentium2:
1988    case CK_Pentium3:
1989    case CK_Pentium3M:
1990    case CK_PentiumM:
1991    case CK_Yonah:
1992    case CK_C3_2:
1993    case CK_Pentium4:
1994    case CK_Pentium4M:
1995    case CK_Prescott:
1996    case CK_K6:
1997    case CK_K6_2:
1998    case CK_K6_3:
1999    case CK_Athlon:
2000    case CK_AthlonThunderbird:
2001    case CK_Athlon4:
2002    case CK_AthlonXP:
2003    case CK_AthlonMP:
2004    case CK_Geode:
2005      // Only accept certain architectures when compiling in 32-bit mode.
2006      if (getTriple().getArch() != llvm::Triple::x86)
2007        return false;
2008
2009      // Fallthrough
2010    case CK_Nocona:
2011    case CK_Core2:
2012    case CK_Penryn:
2013    case CK_Atom:
2014    case CK_Corei7:
2015    case CK_Corei7AVX:
2016    case CK_CoreAVXi:
2017    case CK_CoreAVX2:
2018    case CK_Athlon64:
2019    case CK_Athlon64SSE3:
2020    case CK_AthlonFX:
2021    case CK_K8:
2022    case CK_K8SSE3:
2023    case CK_Opteron:
2024    case CK_OpteronSSE3:
2025    case CK_AMDFAM10:
2026    case CK_BTVER1:
2027    case CK_BDVER1:
2028    case CK_BDVER2:
2029    case CK_x86_64:
2030      return true;
2031    }
2032    llvm_unreachable("Unhandled CPU kind");
2033  }
2034
2035  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2036    // We accept all non-ARM calling conventions
2037    return (CC == CC_X86ThisCall ||
2038            CC == CC_X86FastCall ||
2039            CC == CC_X86StdCall ||
2040            CC == CC_C ||
2041            CC == CC_X86Pascal ||
2042            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2043  }
2044
2045  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2046    return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2047  }
2048};
2049
2050void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2051  // FIXME: This should not be here.
2052  Features["3dnow"] = false;
2053  Features["3dnowa"] = false;
2054  Features["mmx"] = false;
2055  Features["sse"] = false;
2056  Features["sse2"] = false;
2057  Features["sse3"] = false;
2058  Features["ssse3"] = false;
2059  Features["sse41"] = false;
2060  Features["sse42"] = false;
2061  Features["sse4a"] = false;
2062  Features["aes"] = false;
2063  Features["pclmul"] = false;
2064  Features["avx"] = false;
2065  Features["avx2"] = false;
2066  Features["lzcnt"] = false;
2067  Features["rdrand"] = false;
2068  Features["bmi"] = false;
2069  Features["bmi2"] = false;
2070  Features["popcnt"] = false;
2071  Features["rtm"] = false;
2072  Features["prfchw"] = false;
2073  Features["rdseed"] = false;
2074  Features["fma4"] = false;
2075  Features["fma"] = false;
2076  Features["xop"] = false;
2077  Features["f16c"] = false;
2078
2079  // FIXME: This *really* should not be here.
2080
2081  // X86_64 always has SSE2.
2082  if (getTriple().getArch() == llvm::Triple::x86_64)
2083    setFeatureEnabled(Features, "sse2", true);
2084
2085  switch (CPU) {
2086  case CK_Generic:
2087  case CK_i386:
2088  case CK_i486:
2089  case CK_i586:
2090  case CK_Pentium:
2091  case CK_i686:
2092  case CK_PentiumPro:
2093    break;
2094  case CK_PentiumMMX:
2095  case CK_Pentium2:
2096    setFeatureEnabled(Features, "mmx", true);
2097    break;
2098  case CK_Pentium3:
2099  case CK_Pentium3M:
2100    setFeatureEnabled(Features, "sse", true);
2101    break;
2102  case CK_PentiumM:
2103  case CK_Pentium4:
2104  case CK_Pentium4M:
2105  case CK_x86_64:
2106    setFeatureEnabled(Features, "sse2", true);
2107    break;
2108  case CK_Yonah:
2109  case CK_Prescott:
2110  case CK_Nocona:
2111    setFeatureEnabled(Features, "sse3", true);
2112    break;
2113  case CK_Core2:
2114    setFeatureEnabled(Features, "ssse3", true);
2115    break;
2116  case CK_Penryn:
2117    setFeatureEnabled(Features, "sse4.1", true);
2118    break;
2119  case CK_Atom:
2120    setFeatureEnabled(Features, "ssse3", true);
2121    break;
2122  case CK_Corei7:
2123    setFeatureEnabled(Features, "sse4", true);
2124    break;
2125  case CK_Corei7AVX:
2126    setFeatureEnabled(Features, "avx", true);
2127    setFeatureEnabled(Features, "aes", true);
2128    setFeatureEnabled(Features, "pclmul", true);
2129    break;
2130  case CK_CoreAVXi:
2131    setFeatureEnabled(Features, "avx", true);
2132    setFeatureEnabled(Features, "aes", true);
2133    setFeatureEnabled(Features, "pclmul", true);
2134    setFeatureEnabled(Features, "rdrnd", true);
2135    setFeatureEnabled(Features, "f16c", true);
2136    break;
2137  case CK_CoreAVX2:
2138    setFeatureEnabled(Features, "avx2", true);
2139    setFeatureEnabled(Features, "aes", true);
2140    setFeatureEnabled(Features, "pclmul", true);
2141    setFeatureEnabled(Features, "lzcnt", true);
2142    setFeatureEnabled(Features, "rdrnd", true);
2143    setFeatureEnabled(Features, "f16c", true);
2144    setFeatureEnabled(Features, "bmi", true);
2145    setFeatureEnabled(Features, "bmi2", true);
2146    setFeatureEnabled(Features, "rtm", true);
2147    setFeatureEnabled(Features, "fma", true);
2148    break;
2149  case CK_K6:
2150  case CK_WinChipC6:
2151    setFeatureEnabled(Features, "mmx", true);
2152    break;
2153  case CK_K6_2:
2154  case CK_K6_3:
2155  case CK_WinChip2:
2156  case CK_C3:
2157    setFeatureEnabled(Features, "3dnow", true);
2158    break;
2159  case CK_Athlon:
2160  case CK_AthlonThunderbird:
2161  case CK_Geode:
2162    setFeatureEnabled(Features, "3dnowa", true);
2163    break;
2164  case CK_Athlon4:
2165  case CK_AthlonXP:
2166  case CK_AthlonMP:
2167    setFeatureEnabled(Features, "sse", true);
2168    setFeatureEnabled(Features, "3dnowa", true);
2169    break;
2170  case CK_K8:
2171  case CK_Opteron:
2172  case CK_Athlon64:
2173  case CK_AthlonFX:
2174    setFeatureEnabled(Features, "sse2", true);
2175    setFeatureEnabled(Features, "3dnowa", true);
2176    break;
2177  case CK_K8SSE3:
2178  case CK_OpteronSSE3:
2179  case CK_Athlon64SSE3:
2180    setFeatureEnabled(Features, "sse3", true);
2181    setFeatureEnabled(Features, "3dnowa", true);
2182    break;
2183  case CK_AMDFAM10:
2184    setFeatureEnabled(Features, "sse3", true);
2185    setFeatureEnabled(Features, "sse4a", true);
2186    setFeatureEnabled(Features, "3dnowa", true);
2187    setFeatureEnabled(Features, "lzcnt", true);
2188    setFeatureEnabled(Features, "popcnt", true);
2189    break;
2190  case CK_BTVER1:
2191    setFeatureEnabled(Features, "ssse3", true);
2192    setFeatureEnabled(Features, "sse4a", true);
2193    setFeatureEnabled(Features, "lzcnt", true);
2194    setFeatureEnabled(Features, "popcnt", true);
2195    break;
2196  case CK_BDVER1:
2197    setFeatureEnabled(Features, "xop", true);
2198    setFeatureEnabled(Features, "lzcnt", true);
2199    setFeatureEnabled(Features, "aes", true);
2200    setFeatureEnabled(Features, "pclmul", true);
2201    break;
2202  case CK_BDVER2:
2203    setFeatureEnabled(Features, "xop", true);
2204    setFeatureEnabled(Features, "lzcnt", true);
2205    setFeatureEnabled(Features, "aes", true);
2206    setFeatureEnabled(Features, "pclmul", true);
2207    setFeatureEnabled(Features, "bmi", true);
2208    setFeatureEnabled(Features, "fma", true);
2209    setFeatureEnabled(Features, "f16c", true);
2210    break;
2211  case CK_C3_2:
2212    setFeatureEnabled(Features, "sse", true);
2213    break;
2214  }
2215}
2216
2217bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2218                                      StringRef Name,
2219                                      bool Enabled) const {
2220  // FIXME: This *really* should not be here.  We need some way of translating
2221  // options into llvm subtarget features.
2222  if (!Features.count(Name) &&
2223      (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2224       Name != "rdrnd"))
2225    return false;
2226
2227  // FIXME: this should probably use a switch with fall through.
2228
2229  if (Enabled) {
2230    if (Name == "mmx")
2231      Features["mmx"] = true;
2232    else if (Name == "sse")
2233      Features["mmx"] = Features["sse"] = true;
2234    else if (Name == "sse2")
2235      Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2236    else if (Name == "sse3")
2237      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2238        true;
2239    else if (Name == "ssse3")
2240      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2241        Features["ssse3"] = true;
2242    else if (Name == "sse4" || Name == "sse4.2")
2243      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2244        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2245        Features["popcnt"] = true;
2246    else if (Name == "sse4.1")
2247      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2248        Features["ssse3"] = Features["sse41"] = true;
2249    else if (Name == "3dnow")
2250      Features["mmx"] = Features["3dnow"] = true;
2251    else if (Name == "3dnowa")
2252      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2253    else if (Name == "aes")
2254      Features["sse"] = Features["sse2"] = Features["aes"] = true;
2255    else if (Name == "pclmul")
2256      Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2257    else if (Name == "avx")
2258      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2259        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2260        Features["popcnt"] = Features["avx"] = true;
2261    else if (Name == "avx2")
2262      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2263        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2264        Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2265    else if (Name == "fma")
2266      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2267        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2268        Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2269    else if (Name == "fma4")
2270      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2271        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2272        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2273        Features["fma4"] = true;
2274    else if (Name == "xop")
2275      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2276        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2277        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2278        Features["fma4"] = Features["xop"] = true;
2279    else if (Name == "sse4a")
2280      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2281        Features["sse4a"] = true;
2282    else if (Name == "lzcnt")
2283      Features["lzcnt"] = true;
2284    else if (Name == "rdrnd")
2285      Features["rdrand"] = true;
2286    else if (Name == "bmi")
2287      Features["bmi"] = true;
2288    else if (Name == "bmi2")
2289      Features["bmi2"] = true;
2290    else if (Name == "popcnt")
2291      Features["popcnt"] = true;
2292    else if (Name == "f16c")
2293      Features["f16c"] = true;
2294    else if (Name == "rtm")
2295      Features["rtm"] = true;
2296    else if (Name == "prfchw")
2297      Features["prfchw"] = true;
2298    else if (Name == "rdseed")
2299      Features["rdseed"] = true;
2300  } else {
2301    if (Name == "mmx")
2302      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2303    else if (Name == "sse")
2304      Features["sse"] = Features["sse2"] = Features["sse3"] =
2305        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2306        Features["sse4a"] = Features["avx"] = Features["avx2"] =
2307        Features["fma"] = Features["fma4"] = Features["aes"] =
2308        Features["pclmul"] = Features["xop"] = false;
2309    else if (Name == "sse2")
2310      Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2311        Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2312        Features["avx"] = Features["avx2"] = Features["fma"] =
2313        Features["fma4"] = Features["aes"] = Features["pclmul"] =
2314        Features["xop"] = false;
2315    else if (Name == "sse3")
2316      Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2317        Features["sse42"] = Features["sse4a"] = Features["avx"] =
2318        Features["avx2"] = Features["fma"] = Features["fma4"] =
2319        Features["xop"] = false;
2320    else if (Name == "ssse3")
2321      Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2322        Features["avx"] = Features["avx2"] = Features["fma"] = false;
2323    else if (Name == "sse4" || Name == "sse4.1")
2324      Features["sse41"] = Features["sse42"] = Features["avx"] =
2325        Features["avx2"] = Features["fma"] = false;
2326    else if (Name == "sse4.2")
2327      Features["sse42"] = Features["avx"] = Features["avx2"] =
2328        Features["fma"] = false;
2329    else if (Name == "3dnow")
2330      Features["3dnow"] = Features["3dnowa"] = false;
2331    else if (Name == "3dnowa")
2332      Features["3dnowa"] = false;
2333    else if (Name == "aes")
2334      Features["aes"] = false;
2335    else if (Name == "pclmul")
2336      Features["pclmul"] = false;
2337    else if (Name == "avx")
2338      Features["avx"] = Features["avx2"] = Features["fma"] =
2339        Features["fma4"] = Features["xop"] = false;
2340    else if (Name == "avx2")
2341      Features["avx2"] = false;
2342    else if (Name == "fma")
2343      Features["fma"] = false;
2344    else if (Name == "sse4a")
2345      Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2346    else if (Name == "lzcnt")
2347      Features["lzcnt"] = false;
2348    else if (Name == "rdrnd")
2349      Features["rdrand"] = false;
2350    else if (Name == "bmi")
2351      Features["bmi"] = false;
2352    else if (Name == "bmi2")
2353      Features["bmi2"] = false;
2354    else if (Name == "popcnt")
2355      Features["popcnt"] = false;
2356    else if (Name == "fma4")
2357      Features["fma4"] = Features["xop"] = false;
2358    else if (Name == "xop")
2359      Features["xop"] = false;
2360    else if (Name == "f16c")
2361      Features["f16c"] = false;
2362    else if (Name == "rtm")
2363      Features["rtm"] = false;
2364    else if (Name == "prfchw")
2365      Features["prfchw"] = false;
2366    else if (Name == "rdseed")
2367      Features["rdseed"] = false;
2368  }
2369
2370  return true;
2371}
2372
2373/// HandleTargetOptions - Perform initialization based on the user
2374/// configured set of features.
2375void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2376  // Remember the maximum enabled sselevel.
2377  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2378    // Ignore disabled features.
2379    if (Features[i][0] == '-')
2380      continue;
2381
2382    StringRef Feature = StringRef(Features[i]).substr(1);
2383
2384    if (Feature == "aes") {
2385      HasAES = true;
2386      continue;
2387    }
2388
2389    if (Feature == "pclmul") {
2390      HasPCLMUL = true;
2391      continue;
2392    }
2393
2394    if (Feature == "lzcnt") {
2395      HasLZCNT = true;
2396      continue;
2397    }
2398
2399    if (Feature == "rdrand") {
2400      HasRDRND = true;
2401      continue;
2402    }
2403
2404    if (Feature == "bmi") {
2405      HasBMI = true;
2406      continue;
2407    }
2408
2409    if (Feature == "bmi2") {
2410      HasBMI2 = true;
2411      continue;
2412    }
2413
2414    if (Feature == "popcnt") {
2415      HasPOPCNT = true;
2416      continue;
2417    }
2418
2419    if (Feature == "rtm") {
2420      HasRTM = true;
2421      continue;
2422    }
2423
2424    if (Feature == "prfchw") {
2425      HasPRFCHW = true;
2426      continue;
2427    }
2428
2429    if (Feature == "rdseed") {
2430      HasRDSEED = true;
2431      continue;
2432    }
2433
2434    if (Feature == "sse4a") {
2435      HasSSE4a = true;
2436      continue;
2437    }
2438
2439    if (Feature == "fma4") {
2440      HasFMA4 = true;
2441      continue;
2442    }
2443
2444    if (Feature == "fma") {
2445      HasFMA = true;
2446      continue;
2447    }
2448
2449    if (Feature == "xop") {
2450      HasXOP = true;
2451      continue;
2452    }
2453
2454    if (Feature == "f16c") {
2455      HasF16C = true;
2456      continue;
2457    }
2458
2459    assert(Features[i][0] == '+' && "Invalid target feature!");
2460    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2461      .Case("avx2", AVX2)
2462      .Case("avx", AVX)
2463      .Case("sse42", SSE42)
2464      .Case("sse41", SSE41)
2465      .Case("ssse3", SSSE3)
2466      .Case("sse3", SSE3)
2467      .Case("sse2", SSE2)
2468      .Case("sse", SSE1)
2469      .Default(NoSSE);
2470    SSELevel = std::max(SSELevel, Level);
2471
2472    MMX3DNowEnum ThreeDNowLevel =
2473      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2474        .Case("3dnowa", AMD3DNowAthlon)
2475        .Case("3dnow", AMD3DNow)
2476        .Case("mmx", MMX)
2477        .Default(NoMMX3DNow);
2478
2479    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2480  }
2481
2482  // Don't tell the backend if we're turning off mmx; it will end up disabling
2483  // SSE, which we don't want.
2484  std::vector<std::string>::iterator it;
2485  it = std::find(Features.begin(), Features.end(), "-mmx");
2486  if (it != Features.end())
2487    Features.erase(it);
2488}
2489
2490/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2491/// definitions for this particular subtarget.
2492void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2493                                     MacroBuilder &Builder) const {
2494  // Target identification.
2495  if (getTriple().getArch() == llvm::Triple::x86_64) {
2496    Builder.defineMacro("__amd64__");
2497    Builder.defineMacro("__amd64");
2498    Builder.defineMacro("__x86_64");
2499    Builder.defineMacro("__x86_64__");
2500  } else {
2501    DefineStd(Builder, "i386", Opts);
2502  }
2503
2504  // Subtarget options.
2505  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2506  // truly should be based on -mtune options.
2507  switch (CPU) {
2508  case CK_Generic:
2509    break;
2510  case CK_i386:
2511    // The rest are coming from the i386 define above.
2512    Builder.defineMacro("__tune_i386__");
2513    break;
2514  case CK_i486:
2515  case CK_WinChipC6:
2516  case CK_WinChip2:
2517  case CK_C3:
2518    defineCPUMacros(Builder, "i486");
2519    break;
2520  case CK_PentiumMMX:
2521    Builder.defineMacro("__pentium_mmx__");
2522    Builder.defineMacro("__tune_pentium_mmx__");
2523    // Fallthrough
2524  case CK_i586:
2525  case CK_Pentium:
2526    defineCPUMacros(Builder, "i586");
2527    defineCPUMacros(Builder, "pentium");
2528    break;
2529  case CK_Pentium3:
2530  case CK_Pentium3M:
2531  case CK_PentiumM:
2532    Builder.defineMacro("__tune_pentium3__");
2533    // Fallthrough
2534  case CK_Pentium2:
2535  case CK_C3_2:
2536    Builder.defineMacro("__tune_pentium2__");
2537    // Fallthrough
2538  case CK_PentiumPro:
2539    Builder.defineMacro("__tune_i686__");
2540    Builder.defineMacro("__tune_pentiumpro__");
2541    // Fallthrough
2542  case CK_i686:
2543    Builder.defineMacro("__i686");
2544    Builder.defineMacro("__i686__");
2545    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2546    Builder.defineMacro("__pentiumpro");
2547    Builder.defineMacro("__pentiumpro__");
2548    break;
2549  case CK_Pentium4:
2550  case CK_Pentium4M:
2551    defineCPUMacros(Builder, "pentium4");
2552    break;
2553  case CK_Yonah:
2554  case CK_Prescott:
2555  case CK_Nocona:
2556    defineCPUMacros(Builder, "nocona");
2557    break;
2558  case CK_Core2:
2559  case CK_Penryn:
2560    defineCPUMacros(Builder, "core2");
2561    break;
2562  case CK_Atom:
2563    defineCPUMacros(Builder, "atom");
2564    break;
2565  case CK_Corei7:
2566  case CK_Corei7AVX:
2567  case CK_CoreAVXi:
2568  case CK_CoreAVX2:
2569    defineCPUMacros(Builder, "corei7");
2570    break;
2571  case CK_K6_2:
2572    Builder.defineMacro("__k6_2__");
2573    Builder.defineMacro("__tune_k6_2__");
2574    // Fallthrough
2575  case CK_K6_3:
2576    if (CPU != CK_K6_2) {  // In case of fallthrough
2577      // FIXME: GCC may be enabling these in cases where some other k6
2578      // architecture is specified but -m3dnow is explicitly provided. The
2579      // exact semantics need to be determined and emulated here.
2580      Builder.defineMacro("__k6_3__");
2581      Builder.defineMacro("__tune_k6_3__");
2582    }
2583    // Fallthrough
2584  case CK_K6:
2585    defineCPUMacros(Builder, "k6");
2586    break;
2587  case CK_Athlon:
2588  case CK_AthlonThunderbird:
2589  case CK_Athlon4:
2590  case CK_AthlonXP:
2591  case CK_AthlonMP:
2592    defineCPUMacros(Builder, "athlon");
2593    if (SSELevel != NoSSE) {
2594      Builder.defineMacro("__athlon_sse__");
2595      Builder.defineMacro("__tune_athlon_sse__");
2596    }
2597    break;
2598  case CK_K8:
2599  case CK_K8SSE3:
2600  case CK_x86_64:
2601  case CK_Opteron:
2602  case CK_OpteronSSE3:
2603  case CK_Athlon64:
2604  case CK_Athlon64SSE3:
2605  case CK_AthlonFX:
2606    defineCPUMacros(Builder, "k8");
2607    break;
2608  case CK_AMDFAM10:
2609    defineCPUMacros(Builder, "amdfam10");
2610    break;
2611  case CK_BTVER1:
2612    defineCPUMacros(Builder, "btver1");
2613    break;
2614  case CK_BDVER1:
2615    defineCPUMacros(Builder, "bdver1");
2616    break;
2617  case CK_BDVER2:
2618    defineCPUMacros(Builder, "bdver2");
2619    break;
2620  case CK_Geode:
2621    defineCPUMacros(Builder, "geode");
2622    break;
2623  }
2624
2625  // Target properties.
2626  Builder.defineMacro("__LITTLE_ENDIAN__");
2627  Builder.defineMacro("__REGISTER_PREFIX__", "");
2628
2629  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2630  // functions in glibc header files that use FP Stack inline asm which the
2631  // backend can't deal with (PR879).
2632  Builder.defineMacro("__NO_MATH_INLINES");
2633
2634  if (HasAES)
2635    Builder.defineMacro("__AES__");
2636
2637  if (HasPCLMUL)
2638    Builder.defineMacro("__PCLMUL__");
2639
2640  if (HasLZCNT)
2641    Builder.defineMacro("__LZCNT__");
2642
2643  if (HasRDRND)
2644    Builder.defineMacro("__RDRND__");
2645
2646  if (HasBMI)
2647    Builder.defineMacro("__BMI__");
2648
2649  if (HasBMI2)
2650    Builder.defineMacro("__BMI2__");
2651
2652  if (HasPOPCNT)
2653    Builder.defineMacro("__POPCNT__");
2654
2655  if (HasRTM)
2656    Builder.defineMacro("__RTM__");
2657
2658  if (HasPRFCHW)
2659    Builder.defineMacro("__PRFCHW__");
2660
2661  if (HasRDSEED)
2662    Builder.defineMacro("__RDSEED__");
2663
2664  if (HasSSE4a)
2665    Builder.defineMacro("__SSE4A__");
2666
2667  if (HasFMA4)
2668    Builder.defineMacro("__FMA4__");
2669
2670  if (HasFMA)
2671    Builder.defineMacro("__FMA__");
2672
2673  if (HasXOP)
2674    Builder.defineMacro("__XOP__");
2675
2676  if (HasF16C)
2677    Builder.defineMacro("__F16C__");
2678
2679  // Each case falls through to the previous one here.
2680  switch (SSELevel) {
2681  case AVX2:
2682    Builder.defineMacro("__AVX2__");
2683  case AVX:
2684    Builder.defineMacro("__AVX__");
2685  case SSE42:
2686    Builder.defineMacro("__SSE4_2__");
2687  case SSE41:
2688    Builder.defineMacro("__SSE4_1__");
2689  case SSSE3:
2690    Builder.defineMacro("__SSSE3__");
2691  case SSE3:
2692    Builder.defineMacro("__SSE3__");
2693  case SSE2:
2694    Builder.defineMacro("__SSE2__");
2695    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2696  case SSE1:
2697    Builder.defineMacro("__SSE__");
2698    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2699  case NoSSE:
2700    break;
2701  }
2702
2703  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2704    switch (SSELevel) {
2705    case AVX2:
2706    case AVX:
2707    case SSE42:
2708    case SSE41:
2709    case SSSE3:
2710    case SSE3:
2711    case SSE2:
2712      Builder.defineMacro("_M_IX86_FP", Twine(2));
2713      break;
2714    case SSE1:
2715      Builder.defineMacro("_M_IX86_FP", Twine(1));
2716      break;
2717    default:
2718      Builder.defineMacro("_M_IX86_FP", Twine(0));
2719    }
2720  }
2721
2722  // Each case falls through to the previous one here.
2723  switch (MMX3DNowLevel) {
2724  case AMD3DNowAthlon:
2725    Builder.defineMacro("__3dNOW_A__");
2726  case AMD3DNow:
2727    Builder.defineMacro("__3dNOW__");
2728  case MMX:
2729    Builder.defineMacro("__MMX__");
2730  case NoMMX3DNow:
2731    break;
2732  }
2733
2734  if (CPU >= CK_i486) {
2735    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2736    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2737    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2738  }
2739  if (CPU >= CK_i586)
2740    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2741}
2742
2743bool X86TargetInfo::hasFeature(StringRef Feature) const {
2744  return llvm::StringSwitch<bool>(Feature)
2745      .Case("aes", HasAES)
2746      .Case("avx", SSELevel >= AVX)
2747      .Case("avx2", SSELevel >= AVX2)
2748      .Case("bmi", HasBMI)
2749      .Case("bmi2", HasBMI2)
2750      .Case("fma", HasFMA)
2751      .Case("fma4", HasFMA4)
2752      .Case("lzcnt", HasLZCNT)
2753      .Case("rdrnd", HasRDRND)
2754      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2755      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2756      .Case("mmx", MMX3DNowLevel >= MMX)
2757      .Case("pclmul", HasPCLMUL)
2758      .Case("popcnt", HasPOPCNT)
2759      .Case("rtm", HasRTM)
2760      .Case("prfchw", HasPRFCHW)
2761      .Case("rdseed", HasRDSEED)
2762      .Case("sse", SSELevel >= SSE1)
2763      .Case("sse2", SSELevel >= SSE2)
2764      .Case("sse3", SSELevel >= SSE3)
2765      .Case("ssse3", SSELevel >= SSSE3)
2766      .Case("sse41", SSELevel >= SSE41)
2767      .Case("sse42", SSELevel >= SSE42)
2768      .Case("sse4a", HasSSE4a)
2769      .Case("x86", true)
2770      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2771      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2772      .Case("xop", HasXOP)
2773      .Case("f16c", HasF16C)
2774      .Default(false);
2775}
2776
2777bool
2778X86TargetInfo::validateAsmConstraint(const char *&Name,
2779                                     TargetInfo::ConstraintInfo &Info) const {
2780  switch (*Name) {
2781  default: return false;
2782  case 'Y': // first letter of a pair:
2783    switch (*(Name+1)) {
2784    default: return false;
2785    case '0':  // First SSE register.
2786    case 't':  // Any SSE register, when SSE2 is enabled.
2787    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2788    case 'm':  // any MMX register, when inter-unit moves enabled.
2789      break;   // falls through to setAllowsRegister.
2790  }
2791  case 'a': // eax.
2792  case 'b': // ebx.
2793  case 'c': // ecx.
2794  case 'd': // edx.
2795  case 'S': // esi.
2796  case 'D': // edi.
2797  case 'A': // edx:eax.
2798  case 'f': // any x87 floating point stack register.
2799  case 't': // top of floating point stack.
2800  case 'u': // second from top of floating point stack.
2801  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2802  case 'y': // Any MMX register.
2803  case 'x': // Any SSE register.
2804  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2805  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2806  case 'l': // "Index" registers: any general register that can be used as an
2807            // index in a base+index memory access.
2808    Info.setAllowsRegister();
2809    return true;
2810  case 'C': // SSE floating point constant.
2811  case 'G': // x87 floating point constant.
2812  case 'e': // 32-bit signed integer constant for use with zero-extending
2813            // x86_64 instructions.
2814  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2815            // x86_64 instructions.
2816    return true;
2817  }
2818}
2819
2820
2821std::string
2822X86TargetInfo::convertConstraint(const char *&Constraint) const {
2823  switch (*Constraint) {
2824  case 'a': return std::string("{ax}");
2825  case 'b': return std::string("{bx}");
2826  case 'c': return std::string("{cx}");
2827  case 'd': return std::string("{dx}");
2828  case 'S': return std::string("{si}");
2829  case 'D': return std::string("{di}");
2830  case 'p': // address
2831    return std::string("im");
2832  case 't': // top of floating point stack.
2833    return std::string("{st}");
2834  case 'u': // second from top of floating point stack.
2835    return std::string("{st(1)}"); // second from top of floating point stack.
2836  default:
2837    return std::string(1, *Constraint);
2838  }
2839}
2840} // end anonymous namespace
2841
2842namespace {
2843// X86-32 generic target
2844class X86_32TargetInfo : public X86TargetInfo {
2845public:
2846  X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2847    DoubleAlign = LongLongAlign = 32;
2848    LongDoubleWidth = 96;
2849    LongDoubleAlign = 32;
2850    SuitableAlign = 128;
2851    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2852                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2853                        "a0:0:64-f80:32:32-n8:16:32-S128";
2854    SizeType = UnsignedInt;
2855    PtrDiffType = SignedInt;
2856    IntPtrType = SignedInt;
2857    RegParmMax = 3;
2858
2859    // Use fpret for all types.
2860    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2861                             (1 << TargetInfo::Double) |
2862                             (1 << TargetInfo::LongDouble));
2863
2864    // x86-32 has atomics up to 8 bytes
2865    // FIXME: Check that we actually have cmpxchg8b before setting
2866    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2867    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2868  }
2869  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2870    return TargetInfo::CharPtrBuiltinVaList;
2871  }
2872
2873  int getEHDataRegisterNumber(unsigned RegNo) const {
2874    if (RegNo == 0) return 0;
2875    if (RegNo == 1) return 2;
2876    return -1;
2877  }
2878  virtual bool validateInputSize(StringRef Constraint,
2879                                 unsigned Size) const {
2880    switch (Constraint[0]) {
2881    default: break;
2882    case 'a':
2883    case 'b':
2884    case 'c':
2885    case 'd':
2886      return Size <= 32;
2887    }
2888
2889    return true;
2890  }
2891};
2892} // end anonymous namespace
2893
2894namespace {
2895class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2896public:
2897  NetBSDI386TargetInfo(const std::string &triple) :
2898    NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2899  }
2900
2901  virtual unsigned getFloatEvalMethod() const {
2902    // NetBSD defaults to "double" rounding
2903    return 1;
2904  }
2905};
2906} // end anonymous namespace
2907
2908namespace {
2909class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2910public:
2911  OpenBSDI386TargetInfo(const std::string& triple) :
2912    OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2913    SizeType = UnsignedLong;
2914    IntPtrType = SignedLong;
2915    PtrDiffType = SignedLong;
2916  }
2917};
2918} // end anonymous namespace
2919
2920namespace {
2921class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2922public:
2923  BitrigI386TargetInfo(const std::string& triple) :
2924    BitrigTargetInfo<X86_32TargetInfo>(triple) {
2925    SizeType = UnsignedLong;
2926    IntPtrType = SignedLong;
2927    PtrDiffType = SignedLong;
2928  }
2929};
2930} // end anonymous namespace
2931
2932namespace {
2933class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2934public:
2935  DarwinI386TargetInfo(const std::string& triple) :
2936    DarwinTargetInfo<X86_32TargetInfo>(triple) {
2937    LongDoubleWidth = 128;
2938    LongDoubleAlign = 128;
2939    SuitableAlign = 128;
2940    MaxVectorAlign = 256;
2941    SizeType = UnsignedLong;
2942    IntPtrType = SignedLong;
2943    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2944                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2945                        "a0:0:64-f80:128:128-n8:16:32-S128";
2946    HasAlignMac68kSupport = true;
2947  }
2948
2949};
2950} // end anonymous namespace
2951
2952namespace {
2953// x86-32 Windows target
2954class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2955public:
2956  WindowsX86_32TargetInfo(const std::string& triple)
2957    : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2958    TLSSupported = false;
2959    WCharType = UnsignedShort;
2960    DoubleAlign = LongLongAlign = 64;
2961    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2962                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2963                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2964  }
2965  virtual void getTargetDefines(const LangOptions &Opts,
2966                                MacroBuilder &Builder) const {
2967    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2968  }
2969};
2970} // end anonymous namespace
2971
2972namespace {
2973
2974// x86-32 Windows Visual Studio target
2975class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2976public:
2977  VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2978    : WindowsX86_32TargetInfo(triple) {
2979    LongDoubleWidth = LongDoubleAlign = 64;
2980    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2981  }
2982  virtual void getTargetDefines(const LangOptions &Opts,
2983                                MacroBuilder &Builder) const {
2984    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2985    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2986    // The value of the following reflects processor type.
2987    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2988    // We lost the original triple, so we use the default.
2989    Builder.defineMacro("_M_IX86", "600");
2990  }
2991};
2992} // end anonymous namespace
2993
2994namespace {
2995// x86-32 MinGW target
2996class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
2997public:
2998  MinGWX86_32TargetInfo(const std::string& triple)
2999    : WindowsX86_32TargetInfo(triple) {
3000  }
3001  virtual void getTargetDefines(const LangOptions &Opts,
3002                                MacroBuilder &Builder) const {
3003    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3004    DefineStd(Builder, "WIN32", Opts);
3005    DefineStd(Builder, "WINNT", Opts);
3006    Builder.defineMacro("_X86_");
3007    Builder.defineMacro("__MSVCRT__");
3008    Builder.defineMacro("__MINGW32__");
3009
3010    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3011    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3012    if (Opts.MicrosoftExt)
3013      // Provide "as-is" __declspec.
3014      Builder.defineMacro("__declspec", "__declspec");
3015    else
3016      // Provide alias of __attribute__ like mingw32-gcc.
3017      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3018  }
3019};
3020} // end anonymous namespace
3021
3022namespace {
3023// x86-32 Cygwin target
3024class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3025public:
3026  CygwinX86_32TargetInfo(const std::string& triple)
3027    : X86_32TargetInfo(triple) {
3028    TLSSupported = false;
3029    WCharType = UnsignedShort;
3030    DoubleAlign = LongLongAlign = 64;
3031    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3032                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3033                        "a0:0:64-f80:32:32-n8:16:32-S32";
3034  }
3035  virtual void getTargetDefines(const LangOptions &Opts,
3036                                MacroBuilder &Builder) const {
3037    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3038    Builder.defineMacro("_X86_");
3039    Builder.defineMacro("__CYGWIN__");
3040    Builder.defineMacro("__CYGWIN32__");
3041    DefineStd(Builder, "unix", Opts);
3042    if (Opts.CPlusPlus)
3043      Builder.defineMacro("_GNU_SOURCE");
3044  }
3045};
3046} // end anonymous namespace
3047
3048namespace {
3049// x86-32 Haiku target
3050class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3051public:
3052  HaikuX86_32TargetInfo(const std::string& triple)
3053    : X86_32TargetInfo(triple) {
3054    SizeType = UnsignedLong;
3055    IntPtrType = SignedLong;
3056    PtrDiffType = SignedLong;
3057    ProcessIDType = SignedLong;
3058    this->UserLabelPrefix = "";
3059    this->TLSSupported = false;
3060  }
3061  virtual void getTargetDefines(const LangOptions &Opts,
3062                                MacroBuilder &Builder) const {
3063    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3064    Builder.defineMacro("__INTEL__");
3065    Builder.defineMacro("__HAIKU__");
3066  }
3067};
3068} // end anonymous namespace
3069
3070// RTEMS Target
3071template<typename Target>
3072class RTEMSTargetInfo : public OSTargetInfo<Target> {
3073protected:
3074  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3075                            MacroBuilder &Builder) const {
3076    // RTEMS defines; list based off of gcc output
3077
3078    Builder.defineMacro("__rtems__");
3079    Builder.defineMacro("__ELF__");
3080  }
3081public:
3082  RTEMSTargetInfo(const std::string &triple)
3083    : OSTargetInfo<Target>(triple) {
3084      this->UserLabelPrefix = "";
3085
3086      llvm::Triple Triple(triple);
3087      switch (Triple.getArch()) {
3088        default:
3089        case llvm::Triple::x86:
3090          // this->MCountName = ".mcount";
3091          break;
3092        case llvm::Triple::mips:
3093        case llvm::Triple::mipsel:
3094        case llvm::Triple::ppc:
3095        case llvm::Triple::ppc64:
3096          // this->MCountName = "_mcount";
3097          break;
3098        case llvm::Triple::arm:
3099          // this->MCountName = "__mcount";
3100          break;
3101      }
3102
3103    }
3104};
3105
3106namespace {
3107// x86-32 RTEMS target
3108class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3109public:
3110  RTEMSX86_32TargetInfo(const std::string& triple)
3111    : X86_32TargetInfo(triple) {
3112    SizeType = UnsignedLong;
3113    IntPtrType = SignedLong;
3114    PtrDiffType = SignedLong;
3115    this->UserLabelPrefix = "";
3116  }
3117  virtual void getTargetDefines(const LangOptions &Opts,
3118                                MacroBuilder &Builder) const {
3119    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3120    Builder.defineMacro("__INTEL__");
3121    Builder.defineMacro("__rtems__");
3122  }
3123};
3124} // end anonymous namespace
3125
3126namespace {
3127// x86-64 generic target
3128class X86_64TargetInfo : public X86TargetInfo {
3129public:
3130  X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
3131    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3132    LongDoubleWidth = 128;
3133    LongDoubleAlign = 128;
3134    LargeArrayMinWidth = 128;
3135    LargeArrayAlign = 128;
3136    SuitableAlign = 128;
3137    IntMaxType = SignedLong;
3138    UIntMaxType = UnsignedLong;
3139    Int64Type = SignedLong;
3140    RegParmMax = 6;
3141
3142    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3143                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3144                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3145
3146    // Use fpret only for long double.
3147    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3148
3149    // Use fp2ret for _Complex long double.
3150    ComplexLongDoubleUsesFP2Ret = true;
3151
3152    // x86-64 has atomics up to 16 bytes.
3153    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3154    // on CPUs with cmpxchg16b
3155    MaxAtomicPromoteWidth = 128;
3156    MaxAtomicInlineWidth = 64;
3157  }
3158  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3159    return TargetInfo::X86_64ABIBuiltinVaList;
3160  }
3161
3162  int getEHDataRegisterNumber(unsigned RegNo) const {
3163    if (RegNo == 0) return 0;
3164    if (RegNo == 1) return 1;
3165    return -1;
3166  }
3167
3168  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3169    return (CC == CC_Default ||
3170            CC == CC_C ||
3171            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3172  }
3173
3174  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3175    return CC_C;
3176  }
3177
3178};
3179} // end anonymous namespace
3180
3181namespace {
3182// x86-64 Windows target
3183class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3184public:
3185  WindowsX86_64TargetInfo(const std::string& triple)
3186    : WindowsTargetInfo<X86_64TargetInfo>(triple) {
3187    TLSSupported = false;
3188    WCharType = UnsignedShort;
3189    LongWidth = LongAlign = 32;
3190    DoubleAlign = LongLongAlign = 64;
3191    IntMaxType = SignedLongLong;
3192    UIntMaxType = UnsignedLongLong;
3193    Int64Type = SignedLongLong;
3194    SizeType = UnsignedLongLong;
3195    PtrDiffType = SignedLongLong;
3196    IntPtrType = SignedLongLong;
3197    this->UserLabelPrefix = "";
3198  }
3199  virtual void getTargetDefines(const LangOptions &Opts,
3200                                MacroBuilder &Builder) const {
3201    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3202    Builder.defineMacro("_WIN64");
3203  }
3204  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3205    return TargetInfo::CharPtrBuiltinVaList;
3206  }
3207};
3208} // end anonymous namespace
3209
3210namespace {
3211// x86-64 Windows Visual Studio target
3212class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3213public:
3214  VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
3215    : WindowsX86_64TargetInfo(triple) {
3216    LongDoubleWidth = LongDoubleAlign = 64;
3217    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3218  }
3219  virtual void getTargetDefines(const LangOptions &Opts,
3220                                MacroBuilder &Builder) const {
3221    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3222    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3223    Builder.defineMacro("_M_X64");
3224    Builder.defineMacro("_M_AMD64");
3225  }
3226};
3227} // end anonymous namespace
3228
3229namespace {
3230// x86-64 MinGW target
3231class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3232public:
3233  MinGWX86_64TargetInfo(const std::string& triple)
3234    : WindowsX86_64TargetInfo(triple) {
3235  }
3236  virtual void getTargetDefines(const LangOptions &Opts,
3237                                MacroBuilder &Builder) const {
3238    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3239    DefineStd(Builder, "WIN64", Opts);
3240    Builder.defineMacro("__MSVCRT__");
3241    Builder.defineMacro("__MINGW32__");
3242    Builder.defineMacro("__MINGW64__");
3243
3244    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3245    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3246    if (Opts.MicrosoftExt)
3247      // Provide "as-is" __declspec.
3248      Builder.defineMacro("__declspec", "__declspec");
3249    else
3250      // Provide alias of __attribute__ like mingw32-gcc.
3251      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3252  }
3253};
3254} // end anonymous namespace
3255
3256namespace {
3257class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3258public:
3259  DarwinX86_64TargetInfo(const std::string& triple)
3260      : DarwinTargetInfo<X86_64TargetInfo>(triple) {
3261    Int64Type = SignedLongLong;
3262    MaxVectorAlign = 256;
3263  }
3264};
3265} // end anonymous namespace
3266
3267namespace {
3268class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3269public:
3270  OpenBSDX86_64TargetInfo(const std::string& triple)
3271      : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
3272    IntMaxType = SignedLongLong;
3273    UIntMaxType = UnsignedLongLong;
3274    Int64Type = SignedLongLong;
3275  }
3276};
3277} // end anonymous namespace
3278
3279namespace {
3280class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3281public:
3282  BitrigX86_64TargetInfo(const std::string& triple)
3283      : BitrigTargetInfo<X86_64TargetInfo>(triple) {
3284     IntMaxType = SignedLongLong;
3285     UIntMaxType = UnsignedLongLong;
3286     Int64Type = SignedLongLong;
3287  }
3288};
3289}
3290
3291namespace {
3292class AArch64TargetInfo : public TargetInfo {
3293  static const char * const GCCRegNames[];
3294  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3295public:
3296  AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) {
3297    BigEndian = false;
3298    LongWidth = LongAlign = 64;
3299    LongDoubleWidth = LongDoubleAlign = 128;
3300    PointerWidth = PointerAlign = 64;
3301    SuitableAlign = 128;
3302    DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3303                        "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3304                        "f128:128:128-n32:64-S128";
3305
3306    WCharType = UnsignedInt;
3307    LongDoubleFormat = &llvm::APFloat::IEEEquad;
3308
3309    // AArch64 backend supports 64-bit operations at the moment. In principle
3310    // 128-bit is possible if register-pairs are used.
3311    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3312
3313    TheCXXABI.set(TargetCXXABI::GenericAArch64);
3314  }
3315  virtual void getTargetDefines(const LangOptions &Opts,
3316                                MacroBuilder &Builder) const {
3317    // GCC defines theses currently
3318    Builder.defineMacro("__aarch64__");
3319    Builder.defineMacro("__AARCH64EL__");
3320
3321    // ACLE predefines. Many can only have one possible value on v8 AArch64.
3322
3323    // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3324    // which was intended to be compatible with a 64-bit implementation. They
3325    // will need updating when a real 64-bit ACLE exists. Particularly pressing
3326    // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3327    Builder.defineMacro("__ARM_ACLE",         "101");
3328    Builder.defineMacro("__ARM_ARCH",         "8");
3329    Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3330
3331    Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3332    Builder.defineMacro("__ARM_FEATURE_CLZ");
3333    Builder.defineMacro("__ARM_FEATURE_FMA");
3334
3335    // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3336    // 128-bit LDXP present, at which point this becomes 0x1f.
3337    Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3338
3339    // 0xe implies support for half, single and double precision operations.
3340    Builder.defineMacro("__ARM_FP", "0xe");
3341
3342    // PCS specifies this for SysV variants, which is all we support. Other ABIs
3343    // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3344    Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3345
3346    if (Opts.FastMath || Opts.FiniteMathOnly)
3347      Builder.defineMacro("__ARM_FP_FAST");
3348
3349    if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3350      Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3351
3352    Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3353                        Opts.ShortWChar ? "2" : "4");
3354
3355    Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3356                        Opts.ShortEnums ? "1" : "4");
3357
3358    if (BigEndian)
3359      Builder.defineMacro("__ARM_BIG_ENDIAN");
3360  }
3361  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3362                                 unsigned &NumRecords) const {
3363    Records = 0;
3364    NumRecords = 0;
3365  }
3366  virtual bool hasFeature(StringRef Feature) const {
3367    return Feature == "aarch64";
3368  }
3369  virtual void getGCCRegNames(const char * const *&Names,
3370                              unsigned &NumNames) const;
3371  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3372                                unsigned &NumAliases) const;
3373
3374  virtual bool isCLZForZeroUndef() const { return false; }
3375
3376  virtual bool validateAsmConstraint(const char *&Name,
3377                                     TargetInfo::ConstraintInfo &Info) const {
3378    switch (*Name) {
3379    default: return false;
3380    case 'w': // An FP/SIMD vector register
3381      Info.setAllowsRegister();
3382      return true;
3383    case 'I': // Constant that can be used with an ADD instruction
3384    case 'J': // Constant that can be used with a SUB instruction
3385    case 'K': // Constant that can be used with a 32-bit logical instruction
3386    case 'L': // Constant that can be used with a 64-bit logical instruction
3387    case 'M': // Constant that can be used as a 32-bit MOV immediate
3388    case 'N': // Constant that can be used as a 64-bit MOV immediate
3389    case 'Y': // Floating point constant zero
3390    case 'Z': // Integer constant zero
3391      return true;
3392    case 'Q': // A memory reference with base register and no offset
3393      Info.setAllowsMemory();
3394      return true;
3395    case 'S': // A symbolic address
3396      Info.setAllowsRegister();
3397      return true;
3398    case 'U':
3399      // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3400      // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3401      // Usa: An absolute symbolic address
3402      // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3403      llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3404    }
3405  }
3406
3407  virtual const char *getClobbers() const {
3408    // There are no AArch64 clobbers shared by all asm statements.
3409    return "";
3410  }
3411
3412  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3413    return TargetInfo::AArch64ABIBuiltinVaList;
3414  }
3415};
3416
3417const char * const AArch64TargetInfo::GCCRegNames[] = {
3418  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3419  "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3420  "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3421  "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3422
3423  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3424  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3425  "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3426  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3427
3428  "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3429  "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3430  "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3431  "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3432
3433  "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3434  "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3435  "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3436  "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3437
3438  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3439  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3440  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3441  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3442
3443  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3444  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3445  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3446  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3447
3448  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3449  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3450  "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3451  "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3452};
3453
3454void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3455                                       unsigned &NumNames) const {
3456  Names = GCCRegNames;
3457  NumNames = llvm::array_lengthof(GCCRegNames);
3458}
3459
3460const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3461  { { "x16" }, "ip0"},
3462  { { "x17" }, "ip1"},
3463  { { "x29" }, "fp" },
3464  { { "x30" }, "lr" }
3465};
3466
3467void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3468                                         unsigned &NumAliases) const {
3469  Aliases = GCCRegAliases;
3470  NumAliases = llvm::array_lengthof(GCCRegAliases);
3471
3472}
3473} // end anonymous namespace
3474
3475namespace {
3476class ARMTargetInfo : public TargetInfo {
3477  // Possible FPU choices.
3478  enum FPUMode {
3479    VFP2FPU = (1 << 0),
3480    VFP3FPU = (1 << 1),
3481    VFP4FPU = (1 << 2),
3482    NeonFPU = (1 << 3)
3483  };
3484
3485  static bool FPUModeIsVFP(FPUMode Mode) {
3486    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3487  }
3488
3489  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3490  static const char * const GCCRegNames[];
3491
3492  std::string ABI, CPU;
3493
3494  unsigned FPU : 4;
3495
3496  unsigned IsAAPCS : 1;
3497  unsigned IsThumb : 1;
3498
3499  // Initialized via features.
3500  unsigned SoftFloat : 1;
3501  unsigned SoftFloatABI : 1;
3502
3503  static const Builtin::Info BuiltinInfo[];
3504
3505public:
3506  ARMTargetInfo(const std::string &TripleStr)
3507    : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3508  {
3509    BigEndian = false;
3510    SizeType = UnsignedInt;
3511    PtrDiffType = SignedInt;
3512    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3513    WCharType = UnsignedInt;
3514
3515    // {} in inline assembly are neon specifiers, not assembly variant
3516    // specifiers.
3517    NoAsmVariants = true;
3518
3519    // FIXME: Should we just treat this as a feature?
3520    IsThumb = getTriple().getArchName().startswith("thumb");
3521    if (IsThumb) {
3522      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3523      // so set preferred for small types to 32.
3524      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3525                           "i64:64:64-f32:32:32-f64:64:64-"
3526                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3527    } else {
3528      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3529                           "i64:64:64-f32:32:32-f64:64:64-"
3530                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3531    }
3532
3533    // ARM targets default to using the ARM C++ ABI.
3534    TheCXXABI.set(TargetCXXABI::GenericARM);
3535
3536    // ARM has atomics up to 8 bytes
3537    // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e
3538    MaxAtomicPromoteWidth = 64;
3539
3540    // Do force alignment of members that follow zero length bitfields.  If
3541    // the alignment of the zero-length bitfield is greater than the member
3542    // that follows it, `bar', `bar' will be aligned as the  type of the
3543    // zero length bitfield.
3544    UseZeroLengthBitfieldAlignment = true;
3545  }
3546  virtual const char *getABI() const { return ABI.c_str(); }
3547  virtual bool setABI(const std::string &Name) {
3548    ABI = Name;
3549
3550    // The defaults (above) are for AAPCS, check if we need to change them.
3551    //
3552    // FIXME: We need support for -meabi... we could just mangle it into the
3553    // name.
3554    if (Name == "apcs-gnu") {
3555      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3556      // size_t is unsigned int on FreeBSD.
3557      if (getTriple().getOS() != llvm::Triple::FreeBSD)
3558        SizeType = UnsignedLong;
3559
3560      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3561      WCharType = SignedInt;
3562
3563      // Do not respect the alignment of bit-field types when laying out
3564      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3565      UseBitFieldTypeAlignment = false;
3566
3567      /// gcc forces the alignment to 4 bytes, regardless of the type of the
3568      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3569      /// gcc.
3570      ZeroLengthBitfieldBoundary = 32;
3571
3572      IsAAPCS = false;
3573
3574      if (IsThumb) {
3575        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3576        // so set preferred for small types to 32.
3577        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3578                             "i64:32:64-f32:32:32-f64:32:64-"
3579                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3580      } else {
3581        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3582                             "i64:32:64-f32:32:32-f64:32:64-"
3583                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3584      }
3585
3586      // FIXME: Override "preferred align" for double and long long.
3587    } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3588      IsAAPCS = true;
3589      // FIXME: Enumerated types are variable width in straight AAPCS.
3590    } else if (Name == "aapcs-linux") {
3591      IsAAPCS = true;
3592    } else
3593      return false;
3594
3595    return true;
3596  }
3597
3598  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3599    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3600      Features["vfp2"] = true;
3601    else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3602             CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3603      Features["neon"] = true;
3604    else if (CPU == "swift" || CPU == "cortex-a7") {
3605      Features["vfp4"] = true;
3606      Features["neon"] = true;
3607    }
3608  }
3609
3610  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3611                                 StringRef Name,
3612                                 bool Enabled) const {
3613    if (Name == "soft-float" || Name == "soft-float-abi" ||
3614        Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3615        Name == "d16" || Name == "neonfp") {
3616      Features[Name] = Enabled;
3617    } else
3618      return false;
3619
3620    return true;
3621  }
3622
3623  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3624    FPU = 0;
3625    SoftFloat = SoftFloatABI = false;
3626    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3627      if (Features[i] == "+soft-float")
3628        SoftFloat = true;
3629      else if (Features[i] == "+soft-float-abi")
3630        SoftFloatABI = true;
3631      else if (Features[i] == "+vfp2")
3632        FPU |= VFP2FPU;
3633      else if (Features[i] == "+vfp3")
3634        FPU |= VFP3FPU;
3635      else if (Features[i] == "+vfp4")
3636        FPU |= VFP4FPU;
3637      else if (Features[i] == "+neon")
3638        FPU |= NeonFPU;
3639    }
3640
3641    // Remove front-end specific options which the backend handles differently.
3642    std::vector<std::string>::iterator it;
3643    it = std::find(Features.begin(), Features.end(), "+soft-float");
3644    if (it != Features.end())
3645      Features.erase(it);
3646    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3647    if (it != Features.end())
3648      Features.erase(it);
3649  }
3650
3651  virtual bool hasFeature(StringRef Feature) const {
3652    return llvm::StringSwitch<bool>(Feature)
3653        .Case("arm", true)
3654        .Case("softfloat", SoftFloat)
3655        .Case("thumb", IsThumb)
3656        .Case("neon", FPU == NeonFPU && !SoftFloat &&
3657              StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3658        .Default(false);
3659  }
3660  // FIXME: Should we actually have some table instead of these switches?
3661  static const char *getCPUDefineSuffix(StringRef Name) {
3662    return llvm::StringSwitch<const char*>(Name)
3663      .Cases("arm8", "arm810", "4")
3664      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3665      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3666      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3667      .Case("ep9312", "4T")
3668      .Cases("arm10tdmi", "arm1020t", "5T")
3669      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3670      .Case("arm926ej-s", "5TEJ")
3671      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3672      .Cases("xscale", "iwmmxt", "5TE")
3673      .Case("arm1136j-s", "6J")
3674      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3675      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3676      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3677      .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3678      .Cases("cortex-a9", "cortex-a15", "7A")
3679      .Case("cortex-r5", "7R")
3680      .Case("cortex-a9-mp", "7F")
3681      .Case("swift", "7S")
3682      .Cases("cortex-m3", "cortex-m4", "7M")
3683      .Case("cortex-m0", "6M")
3684      .Default(0);
3685  }
3686  static const char *getCPUProfile(StringRef Name) {
3687    return llvm::StringSwitch<const char*>(Name)
3688      .Cases("cortex-a8", "cortex-a9", "A")
3689      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3690      .Case("cortex-r5", "R")
3691      .Default("");
3692  }
3693  virtual bool setCPU(const std::string &Name) {
3694    if (!getCPUDefineSuffix(Name))
3695      return false;
3696
3697    CPU = Name;
3698    return true;
3699  }
3700  virtual void getTargetDefines(const LangOptions &Opts,
3701                                MacroBuilder &Builder) const {
3702    // Target identification.
3703    Builder.defineMacro("__arm");
3704    Builder.defineMacro("__arm__");
3705
3706    // Target properties.
3707    Builder.defineMacro("__ARMEL__");
3708    Builder.defineMacro("__LITTLE_ENDIAN__");
3709    Builder.defineMacro("__REGISTER_PREFIX__", "");
3710
3711    StringRef CPUArch = getCPUDefineSuffix(CPU);
3712    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3713    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3714    StringRef CPUProfile = getCPUProfile(CPU);
3715    if (!CPUProfile.empty())
3716      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3717
3718    // Subtarget options.
3719
3720    // FIXME: It's more complicated than this and we don't really support
3721    // interworking.
3722    if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3723      Builder.defineMacro("__THUMB_INTERWORK__");
3724
3725    if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3726      // M-class CPUs on Darwin follow AAPCS, but not EABI.
3727      if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3728        Builder.defineMacro("__ARM_EABI__");
3729      Builder.defineMacro("__ARM_PCS", "1");
3730
3731      if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3732        Builder.defineMacro("__ARM_PCS_VFP", "1");
3733    }
3734
3735    if (SoftFloat)
3736      Builder.defineMacro("__SOFTFP__");
3737
3738    if (CPU == "xscale")
3739      Builder.defineMacro("__XSCALE__");
3740
3741    bool IsARMv7 = CPUArch.startswith("7");
3742    if (IsThumb) {
3743      Builder.defineMacro("__THUMBEL__");
3744      Builder.defineMacro("__thumb__");
3745      if (CPUArch == "6T2" || IsARMv7)
3746        Builder.defineMacro("__thumb2__");
3747    }
3748
3749    // Note, this is always on in gcc, even though it doesn't make sense.
3750    Builder.defineMacro("__APCS_32__");
3751
3752    if (FPUModeIsVFP((FPUMode) FPU)) {
3753      Builder.defineMacro("__VFP_FP__");
3754      if (FPU & VFP2FPU)
3755        Builder.defineMacro("__ARM_VFPV2__");
3756      if (FPU & VFP3FPU)
3757        Builder.defineMacro("__ARM_VFPV3__");
3758      if (FPU & VFP4FPU)
3759        Builder.defineMacro("__ARM_VFPV4__");
3760    }
3761
3762    // This only gets set when Neon instructions are actually available, unlike
3763    // the VFP define, hence the soft float and arch check. This is subtly
3764    // different from gcc, we follow the intent which was that it should be set
3765    // when Neon instructions are actually available.
3766    if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3767      Builder.defineMacro("__ARM_NEON__");
3768  }
3769  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3770                                 unsigned &NumRecords) const {
3771    Records = BuiltinInfo;
3772    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3773  }
3774  virtual bool isCLZForZeroUndef() const { return false; }
3775  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3776    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3777  }
3778  virtual void getGCCRegNames(const char * const *&Names,
3779                              unsigned &NumNames) const;
3780  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3781                                unsigned &NumAliases) const;
3782  virtual bool validateAsmConstraint(const char *&Name,
3783                                     TargetInfo::ConstraintInfo &Info) const {
3784    switch (*Name) {
3785    default: break;
3786    case 'l': // r0-r7
3787    case 'h': // r8-r15
3788    case 'w': // VFP Floating point register single precision
3789    case 'P': // VFP Floating point register double precision
3790      Info.setAllowsRegister();
3791      return true;
3792    case 'Q': // A memory address that is a single base register.
3793      Info.setAllowsMemory();
3794      return true;
3795    case 'U': // a memory reference...
3796      switch (Name[1]) {
3797      case 'q': // ...ARMV4 ldrsb
3798      case 'v': // ...VFP load/store (reg+constant offset)
3799      case 'y': // ...iWMMXt load/store
3800      case 't': // address valid for load/store opaque types wider
3801                // than 128-bits
3802      case 'n': // valid address for Neon doubleword vector load/store
3803      case 'm': // valid address for Neon element and structure load/store
3804      case 's': // valid address for non-offset loads/stores of quad-word
3805                // values in four ARM registers
3806        Info.setAllowsMemory();
3807        Name++;
3808        return true;
3809      }
3810    }
3811    return false;
3812  }
3813  virtual std::string convertConstraint(const char *&Constraint) const {
3814    std::string R;
3815    switch (*Constraint) {
3816    case 'U':   // Two-character constraint; add "^" hint for later parsing.
3817      R = std::string("^") + std::string(Constraint, 2);
3818      Constraint++;
3819      break;
3820    case 'p': // 'p' should be translated to 'r' by default.
3821      R = std::string("r");
3822      break;
3823    default:
3824      return std::string(1, *Constraint);
3825    }
3826    return R;
3827  }
3828  virtual bool validateConstraintModifier(StringRef Constraint,
3829                                          const char Modifier,
3830                                          unsigned Size) const {
3831    bool isOutput = (Constraint[0] == '=');
3832    bool isInOut = (Constraint[0] == '+');
3833
3834    // Strip off constraint modifiers.
3835    while (Constraint[0] == '=' ||
3836           Constraint[0] == '+' ||
3837           Constraint[0] == '&')
3838      Constraint = Constraint.substr(1);
3839
3840    switch (Constraint[0]) {
3841    default: break;
3842    case 'r': {
3843      switch (Modifier) {
3844      default:
3845        return isInOut || (isOutput && Size >= 32) ||
3846          (!isOutput && !isInOut && Size <= 32);
3847      case 'q':
3848        // A register of size 32 cannot fit a vector type.
3849        return false;
3850      }
3851    }
3852    }
3853
3854    return true;
3855  }
3856  virtual const char *getClobbers() const {
3857    // FIXME: Is this really right?
3858    return "";
3859  }
3860
3861  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3862    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3863  }
3864
3865  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3866    if (RegNo == 0) return 0;
3867    if (RegNo == 1) return 1;
3868    return -1;
3869  }
3870};
3871
3872const char * const ARMTargetInfo::GCCRegNames[] = {
3873  // Integer registers
3874  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3875  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3876
3877  // Float registers
3878  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3879  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3880  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3881  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3882
3883  // Double registers
3884  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3885  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3886  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3887  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3888
3889  // Quad registers
3890  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3891  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3892};
3893
3894void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3895                                   unsigned &NumNames) const {
3896  Names = GCCRegNames;
3897  NumNames = llvm::array_lengthof(GCCRegNames);
3898}
3899
3900const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3901  { { "a1" }, "r0" },
3902  { { "a2" }, "r1" },
3903  { { "a3" }, "r2" },
3904  { { "a4" }, "r3" },
3905  { { "v1" }, "r4" },
3906  { { "v2" }, "r5" },
3907  { { "v3" }, "r6" },
3908  { { "v4" }, "r7" },
3909  { { "v5" }, "r8" },
3910  { { "v6", "rfp" }, "r9" },
3911  { { "sl" }, "r10" },
3912  { { "fp" }, "r11" },
3913  { { "ip" }, "r12" },
3914  { { "r13" }, "sp" },
3915  { { "r14" }, "lr" },
3916  { { "r15" }, "pc" },
3917  // The S, D and Q registers overlap, but aren't really aliases; we
3918  // don't want to substitute one of these for a different-sized one.
3919};
3920
3921void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3922                                       unsigned &NumAliases) const {
3923  Aliases = GCCRegAliases;
3924  NumAliases = llvm::array_lengthof(GCCRegAliases);
3925}
3926
3927const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3928#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3929#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3930                                              ALL_LANGUAGES },
3931#include "clang/Basic/BuiltinsARM.def"
3932};
3933} // end anonymous namespace.
3934
3935namespace {
3936class DarwinARMTargetInfo :
3937  public DarwinTargetInfo<ARMTargetInfo> {
3938protected:
3939  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3940                            MacroBuilder &Builder) const {
3941    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3942  }
3943
3944public:
3945  DarwinARMTargetInfo(const std::string& triple)
3946    : DarwinTargetInfo<ARMTargetInfo>(triple) {
3947    HasAlignMac68kSupport = true;
3948    // iOS always has 64-bit atomic instructions.
3949    // FIXME: This should be based off of the target features in ARMTargetInfo.
3950    MaxAtomicInlineWidth = 64;
3951
3952    // Darwin on iOS uses a variant of the ARM C++ ABI.
3953    TheCXXABI.set(TargetCXXABI::iOS);
3954  }
3955};
3956} // end anonymous namespace.
3957
3958
3959namespace {
3960// Hexagon abstract base class
3961class HexagonTargetInfo : public TargetInfo {
3962  static const Builtin::Info BuiltinInfo[];
3963  static const char * const GCCRegNames[];
3964  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3965  std::string CPU;
3966public:
3967  HexagonTargetInfo(const std::string& triple) : TargetInfo(triple)  {
3968    BigEndian = false;
3969    DescriptionString = ("e-p:32:32:32-"
3970                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
3971                         "f64:64:64-f32:32:32-a0:0-n32");
3972
3973    // {} in inline assembly are packet specifiers, not assembly variant
3974    // specifiers.
3975    NoAsmVariants = true;
3976  }
3977
3978  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3979                                 unsigned &NumRecords) const {
3980    Records = BuiltinInfo;
3981    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
3982  }
3983
3984  virtual bool validateAsmConstraint(const char *&Name,
3985                                     TargetInfo::ConstraintInfo &Info) const {
3986    return true;
3987  }
3988
3989  virtual void getTargetDefines(const LangOptions &Opts,
3990                                MacroBuilder &Builder) const;
3991
3992  virtual bool hasFeature(StringRef Feature) const {
3993    return Feature == "hexagon";
3994  }
3995
3996  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3997    return TargetInfo::CharPtrBuiltinVaList;
3998  }
3999  virtual void getGCCRegNames(const char * const *&Names,
4000                              unsigned &NumNames) const;
4001  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4002                                unsigned &NumAliases) const;
4003  virtual const char *getClobbers() const {
4004    return "";
4005  }
4006
4007  static const char *getHexagonCPUSuffix(StringRef Name) {
4008    return llvm::StringSwitch<const char*>(Name)
4009      .Case("hexagonv4", "4")
4010      .Case("hexagonv5", "5")
4011      .Default(0);
4012  }
4013
4014  virtual bool setCPU(const std::string &Name) {
4015    if (!getHexagonCPUSuffix(Name))
4016      return false;
4017
4018    CPU = Name;
4019    return true;
4020  }
4021};
4022
4023void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4024                                MacroBuilder &Builder) const {
4025  Builder.defineMacro("qdsp6");
4026  Builder.defineMacro("__qdsp6", "1");
4027  Builder.defineMacro("__qdsp6__", "1");
4028
4029  Builder.defineMacro("hexagon");
4030  Builder.defineMacro("__hexagon", "1");
4031  Builder.defineMacro("__hexagon__", "1");
4032
4033  if(CPU == "hexagonv1") {
4034    Builder.defineMacro("__HEXAGON_V1__");
4035    Builder.defineMacro("__HEXAGON_ARCH__", "1");
4036    if(Opts.HexagonQdsp6Compat) {
4037      Builder.defineMacro("__QDSP6_V1__");
4038      Builder.defineMacro("__QDSP6_ARCH__", "1");
4039    }
4040  }
4041  else if(CPU == "hexagonv2") {
4042    Builder.defineMacro("__HEXAGON_V2__");
4043    Builder.defineMacro("__HEXAGON_ARCH__", "2");
4044    if(Opts.HexagonQdsp6Compat) {
4045      Builder.defineMacro("__QDSP6_V2__");
4046      Builder.defineMacro("__QDSP6_ARCH__", "2");
4047    }
4048  }
4049  else if(CPU == "hexagonv3") {
4050    Builder.defineMacro("__HEXAGON_V3__");
4051    Builder.defineMacro("__HEXAGON_ARCH__", "3");
4052    if(Opts.HexagonQdsp6Compat) {
4053      Builder.defineMacro("__QDSP6_V3__");
4054      Builder.defineMacro("__QDSP6_ARCH__", "3");
4055    }
4056  }
4057  else if(CPU == "hexagonv4") {
4058    Builder.defineMacro("__HEXAGON_V4__");
4059    Builder.defineMacro("__HEXAGON_ARCH__", "4");
4060    if(Opts.HexagonQdsp6Compat) {
4061      Builder.defineMacro("__QDSP6_V4__");
4062      Builder.defineMacro("__QDSP6_ARCH__", "4");
4063    }
4064  }
4065  else if(CPU == "hexagonv5") {
4066    Builder.defineMacro("__HEXAGON_V5__");
4067    Builder.defineMacro("__HEXAGON_ARCH__", "5");
4068    if(Opts.HexagonQdsp6Compat) {
4069      Builder.defineMacro("__QDSP6_V5__");
4070      Builder.defineMacro("__QDSP6_ARCH__", "5");
4071    }
4072  }
4073}
4074
4075const char * const HexagonTargetInfo::GCCRegNames[] = {
4076  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4077  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4078  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4079  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4080  "p0", "p1", "p2", "p3",
4081  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4082};
4083
4084void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4085                                   unsigned &NumNames) const {
4086  Names = GCCRegNames;
4087  NumNames = llvm::array_lengthof(GCCRegNames);
4088}
4089
4090
4091const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4092  { { "sp" }, "r29" },
4093  { { "fp" }, "r30" },
4094  { { "lr" }, "r31" },
4095 };
4096
4097void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4098                                     unsigned &NumAliases) const {
4099  Aliases = GCCRegAliases;
4100  NumAliases = llvm::array_lengthof(GCCRegAliases);
4101}
4102
4103
4104const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4105#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4106#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4107                                              ALL_LANGUAGES },
4108#include "clang/Basic/BuiltinsHexagon.def"
4109};
4110}
4111
4112
4113namespace {
4114// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4115class SparcTargetInfo : public TargetInfo {
4116  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4117  static const char * const GCCRegNames[];
4118  bool SoftFloat;
4119public:
4120  SparcTargetInfo(const std::string &triple) : TargetInfo(triple) {}
4121
4122  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4123                                 StringRef Name,
4124                                 bool Enabled) const {
4125    if (Name == "soft-float")
4126      Features[Name] = Enabled;
4127    else
4128      return false;
4129
4130    return true;
4131  }
4132  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4133    SoftFloat = false;
4134    for (unsigned i = 0, e = Features.size(); i != e; ++i)
4135      if (Features[i] == "+soft-float")
4136        SoftFloat = true;
4137  }
4138  virtual void getTargetDefines(const LangOptions &Opts,
4139                                MacroBuilder &Builder) const {
4140    DefineStd(Builder, "sparc", Opts);
4141    Builder.defineMacro("__REGISTER_PREFIX__", "");
4142
4143    if (SoftFloat)
4144      Builder.defineMacro("SOFT_FLOAT", "1");
4145  }
4146
4147  virtual bool hasFeature(StringRef Feature) const {
4148    return llvm::StringSwitch<bool>(Feature)
4149             .Case("softfloat", SoftFloat)
4150             .Case("sparc", true)
4151             .Default(false);
4152  }
4153
4154  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4155                                 unsigned &NumRecords) const {
4156    // FIXME: Implement!
4157  }
4158  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4159    return TargetInfo::VoidPtrBuiltinVaList;
4160  }
4161  virtual void getGCCRegNames(const char * const *&Names,
4162                              unsigned &NumNames) const;
4163  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4164                                unsigned &NumAliases) const;
4165  virtual bool validateAsmConstraint(const char *&Name,
4166                                     TargetInfo::ConstraintInfo &info) const {
4167    // FIXME: Implement!
4168    return false;
4169  }
4170  virtual const char *getClobbers() const {
4171    // FIXME: Implement!
4172    return "";
4173  }
4174};
4175
4176const char * const SparcTargetInfo::GCCRegNames[] = {
4177  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4178  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4179  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4180  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4181};
4182
4183void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4184                                     unsigned &NumNames) const {
4185  Names = GCCRegNames;
4186  NumNames = llvm::array_lengthof(GCCRegNames);
4187}
4188
4189const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4190  { { "g0" }, "r0" },
4191  { { "g1" }, "r1" },
4192  { { "g2" }, "r2" },
4193  { { "g3" }, "r3" },
4194  { { "g4" }, "r4" },
4195  { { "g5" }, "r5" },
4196  { { "g6" }, "r6" },
4197  { { "g7" }, "r7" },
4198  { { "o0" }, "r8" },
4199  { { "o1" }, "r9" },
4200  { { "o2" }, "r10" },
4201  { { "o3" }, "r11" },
4202  { { "o4" }, "r12" },
4203  { { "o5" }, "r13" },
4204  { { "o6", "sp" }, "r14" },
4205  { { "o7" }, "r15" },
4206  { { "l0" }, "r16" },
4207  { { "l1" }, "r17" },
4208  { { "l2" }, "r18" },
4209  { { "l3" }, "r19" },
4210  { { "l4" }, "r20" },
4211  { { "l5" }, "r21" },
4212  { { "l6" }, "r22" },
4213  { { "l7" }, "r23" },
4214  { { "i0" }, "r24" },
4215  { { "i1" }, "r25" },
4216  { { "i2" }, "r26" },
4217  { { "i3" }, "r27" },
4218  { { "i4" }, "r28" },
4219  { { "i5" }, "r29" },
4220  { { "i6", "fp" }, "r30" },
4221  { { "i7" }, "r31" },
4222};
4223
4224void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4225                                       unsigned &NumAliases) const {
4226  Aliases = GCCRegAliases;
4227  NumAliases = llvm::array_lengthof(GCCRegAliases);
4228}
4229
4230// SPARC v8 is the 32-bit mode selected by Triple::sparc.
4231class SparcV8TargetInfo : public SparcTargetInfo {
4232public:
4233  SparcV8TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4234    // FIXME: Support Sparc quad-precision long double?
4235    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4236                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4237  }
4238
4239  virtual void getTargetDefines(const LangOptions &Opts,
4240                                MacroBuilder &Builder) const {
4241    SparcTargetInfo::getTargetDefines(Opts, Builder);
4242    Builder.defineMacro("__sparcv8");
4243  }
4244};
4245
4246// SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4247class SparcV9TargetInfo : public SparcTargetInfo {
4248public:
4249  SparcV9TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4250    // FIXME: Support Sparc quad-precision long double?
4251    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4252                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4253  }
4254
4255  virtual void getTargetDefines(const LangOptions &Opts,
4256                                MacroBuilder &Builder) const {
4257    SparcTargetInfo::getTargetDefines(Opts, Builder);
4258    Builder.defineMacro("__sparcv9");
4259  }
4260};
4261
4262} // end anonymous namespace.
4263
4264namespace {
4265class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4266public:
4267  AuroraUXSparcV8TargetInfo(const std::string& triple) :
4268      AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
4269    SizeType = UnsignedInt;
4270    PtrDiffType = SignedInt;
4271  }
4272};
4273class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4274public:
4275  SolarisSparcV8TargetInfo(const std::string& triple) :
4276      SolarisTargetInfo<SparcV8TargetInfo>(triple) {
4277    SizeType = UnsignedInt;
4278    PtrDiffType = SignedInt;
4279  }
4280};
4281} // end anonymous namespace.
4282
4283namespace {
4284  class MSP430TargetInfo : public TargetInfo {
4285    static const char * const GCCRegNames[];
4286  public:
4287    MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
4288      BigEndian = false;
4289      TLSSupported = false;
4290      IntWidth = 16; IntAlign = 16;
4291      LongWidth = 32; LongLongWidth = 64;
4292      LongAlign = LongLongAlign = 16;
4293      PointerWidth = 16; PointerAlign = 16;
4294      SuitableAlign = 16;
4295      SizeType = UnsignedInt;
4296      IntMaxType = SignedLong;
4297      UIntMaxType = UnsignedLong;
4298      IntPtrType = SignedShort;
4299      PtrDiffType = SignedInt;
4300      SigAtomicType = SignedLong;
4301      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4302   }
4303    virtual void getTargetDefines(const LangOptions &Opts,
4304                                  MacroBuilder &Builder) const {
4305      Builder.defineMacro("MSP430");
4306      Builder.defineMacro("__MSP430__");
4307      // FIXME: defines for different 'flavours' of MCU
4308    }
4309    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4310                                   unsigned &NumRecords) const {
4311     // FIXME: Implement.
4312      Records = 0;
4313      NumRecords = 0;
4314    }
4315    virtual bool hasFeature(StringRef Feature) const {
4316      return Feature == "msp430";
4317    }
4318    virtual void getGCCRegNames(const char * const *&Names,
4319                                unsigned &NumNames) const;
4320    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4321                                  unsigned &NumAliases) const {
4322      // No aliases.
4323      Aliases = 0;
4324      NumAliases = 0;
4325    }
4326    virtual bool validateAsmConstraint(const char *&Name,
4327                                       TargetInfo::ConstraintInfo &info) const {
4328      // No target constraints for now.
4329      return false;
4330    }
4331    virtual const char *getClobbers() const {
4332      // FIXME: Is this really right?
4333      return "";
4334    }
4335    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4336      // FIXME: implement
4337      return TargetInfo::CharPtrBuiltinVaList;
4338   }
4339  };
4340
4341  const char * const MSP430TargetInfo::GCCRegNames[] = {
4342    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4343    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4344  };
4345
4346  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4347                                        unsigned &NumNames) const {
4348    Names = GCCRegNames;
4349    NumNames = llvm::array_lengthof(GCCRegNames);
4350  }
4351}
4352
4353namespace {
4354
4355  // LLVM and Clang cannot be used directly to output native binaries for
4356  // target, but is used to compile C code to llvm bitcode with correct
4357  // type and alignment information.
4358  //
4359  // TCE uses the llvm bitcode as input and uses it for generating customized
4360  // target processor and program binary. TCE co-design environment is
4361  // publicly available in http://tce.cs.tut.fi
4362
4363  static const unsigned TCEOpenCLAddrSpaceMap[] = {
4364      3, // opencl_global
4365      4, // opencl_local
4366      5, // opencl_constant
4367      0, // cuda_device
4368      0, // cuda_constant
4369      0  // cuda_shared
4370  };
4371
4372  class TCETargetInfo : public TargetInfo{
4373  public:
4374    TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
4375      TLSSupported = false;
4376      IntWidth = 32;
4377      LongWidth = LongLongWidth = 32;
4378      PointerWidth = 32;
4379      IntAlign = 32;
4380      LongAlign = LongLongAlign = 32;
4381      PointerAlign = 32;
4382      SuitableAlign = 32;
4383      SizeType = UnsignedInt;
4384      IntMaxType = SignedLong;
4385      UIntMaxType = UnsignedLong;
4386      IntPtrType = SignedInt;
4387      PtrDiffType = SignedInt;
4388      FloatWidth = 32;
4389      FloatAlign = 32;
4390      DoubleWidth = 32;
4391      DoubleAlign = 32;
4392      LongDoubleWidth = 32;
4393      LongDoubleAlign = 32;
4394      FloatFormat = &llvm::APFloat::IEEEsingle;
4395      DoubleFormat = &llvm::APFloat::IEEEsingle;
4396      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4397      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4398                          "i16:16:32-i32:32:32-i64:32:32-"
4399                          "f32:32:32-f64:32:32-v64:32:32-"
4400                          "v128:32:32-a0:0:32-n32";
4401      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4402    }
4403
4404    virtual void getTargetDefines(const LangOptions &Opts,
4405                                  MacroBuilder &Builder) const {
4406      DefineStd(Builder, "tce", Opts);
4407      Builder.defineMacro("__TCE__");
4408      Builder.defineMacro("__TCE_V1__");
4409    }
4410    virtual bool hasFeature(StringRef Feature) const {
4411      return Feature == "tce";
4412    }
4413
4414    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4415                                   unsigned &NumRecords) const {}
4416    virtual const char *getClobbers() const {
4417      return "";
4418    }
4419    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4420      return TargetInfo::VoidPtrBuiltinVaList;
4421    }
4422    virtual void getGCCRegNames(const char * const *&Names,
4423                                unsigned &NumNames) const {}
4424    virtual bool validateAsmConstraint(const char *&Name,
4425                                       TargetInfo::ConstraintInfo &info) const {
4426      return true;
4427    }
4428    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4429                                  unsigned &NumAliases) const {}
4430  };
4431}
4432
4433namespace {
4434class MipsTargetInfoBase : public TargetInfo {
4435  static const Builtin::Info BuiltinInfo[];
4436  std::string CPU;
4437  bool IsMips16;
4438  bool IsMicromips;
4439  bool IsSingleFloat;
4440  enum MipsFloatABI {
4441    HardFloat, SoftFloat
4442  } FloatABI;
4443  enum DspRevEnum {
4444    NoDSP, DSP1, DSP2
4445  } DspRev;
4446
4447protected:
4448  std::string ABI;
4449
4450public:
4451  MipsTargetInfoBase(const std::string& triple,
4452                     const std::string& ABIStr,
4453                     const std::string& CPUStr)
4454    : TargetInfo(triple),
4455      CPU(CPUStr),
4456      IsMips16(false),
4457      IsMicromips(false),
4458      IsSingleFloat(false),
4459      FloatABI(HardFloat),
4460      DspRev(NoDSP),
4461      ABI(ABIStr)
4462  {}
4463
4464  virtual const char *getABI() const { return ABI.c_str(); }
4465  virtual bool setABI(const std::string &Name) = 0;
4466  virtual bool setCPU(const std::string &Name) {
4467    CPU = Name;
4468    return true;
4469  }
4470  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4471    Features[ABI] = true;
4472    Features[CPU] = true;
4473  }
4474
4475  virtual void getTargetDefines(const LangOptions &Opts,
4476                                MacroBuilder &Builder) const {
4477    DefineStd(Builder, "mips", Opts);
4478    Builder.defineMacro("_mips");
4479    Builder.defineMacro("__REGISTER_PREFIX__", "");
4480
4481    switch (FloatABI) {
4482    case HardFloat:
4483      Builder.defineMacro("__mips_hard_float", Twine(1));
4484      break;
4485    case SoftFloat:
4486      Builder.defineMacro("__mips_soft_float", Twine(1));
4487      break;
4488    }
4489
4490    if (IsSingleFloat)
4491      Builder.defineMacro("__mips_single_float", Twine(1));
4492
4493    if (IsMips16)
4494      Builder.defineMacro("__mips16", Twine(1));
4495
4496    if (IsMicromips)
4497      Builder.defineMacro("__mips_micromips", Twine(1));
4498
4499    switch (DspRev) {
4500    default:
4501      break;
4502    case DSP1:
4503      Builder.defineMacro("__mips_dsp_rev", Twine(1));
4504      Builder.defineMacro("__mips_dsp", Twine(1));
4505      break;
4506    case DSP2:
4507      Builder.defineMacro("__mips_dsp_rev", Twine(2));
4508      Builder.defineMacro("__mips_dspr2", Twine(1));
4509      Builder.defineMacro("__mips_dsp", Twine(1));
4510      break;
4511    }
4512
4513    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4514    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4515    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4516
4517    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4518    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4519  }
4520
4521  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4522                                 unsigned &NumRecords) const {
4523    Records = BuiltinInfo;
4524    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4525  }
4526  virtual bool hasFeature(StringRef Feature) const {
4527    return Feature == "mips";
4528  }
4529  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4530    return TargetInfo::VoidPtrBuiltinVaList;
4531  }
4532  virtual void getGCCRegNames(const char * const *&Names,
4533                              unsigned &NumNames) const {
4534    static const char * const GCCRegNames[] = {
4535      // CPU register names
4536      // Must match second column of GCCRegAliases
4537      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4538      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4539      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4540      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4541      // Floating point register names
4542      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4543      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4544      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4545      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4546      // Hi/lo and condition register names
4547      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4548      "$fcc5","$fcc6","$fcc7"
4549    };
4550    Names = GCCRegNames;
4551    NumNames = llvm::array_lengthof(GCCRegNames);
4552  }
4553  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4554                                unsigned &NumAliases) const = 0;
4555  virtual bool validateAsmConstraint(const char *&Name,
4556                                     TargetInfo::ConstraintInfo &Info) const {
4557    switch (*Name) {
4558    default:
4559      return false;
4560
4561    case 'r': // CPU registers.
4562    case 'd': // Equivalent to "r" unless generating MIPS16 code.
4563    case 'y': // Equivalent to "r", backwards compatibility only.
4564    case 'f': // floating-point registers.
4565    case 'c': // $25 for indirect jumps
4566    case 'l': // lo register
4567    case 'x': // hilo register pair
4568      Info.setAllowsRegister();
4569      return true;
4570    case 'R': // An address that can be used in a non-macro load or store
4571      Info.setAllowsMemory();
4572      return true;
4573    }
4574  }
4575
4576  virtual const char *getClobbers() const {
4577    // FIXME: Implement!
4578    return "";
4579  }
4580
4581  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4582                                 StringRef Name,
4583                                 bool Enabled) const {
4584    if (Name == "soft-float" || Name == "single-float" ||
4585        Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4586        Name == "mips32" || Name == "mips32r2" ||
4587        Name == "mips64" || Name == "mips64r2" ||
4588        Name == "mips16" || Name == "micromips" ||
4589        Name == "dsp" || Name == "dspr2") {
4590      Features[Name] = Enabled;
4591      return true;
4592    } else if (Name == "32") {
4593      Features["o32"] = Enabled;
4594      return true;
4595    } else if (Name == "64") {
4596      Features["n64"] = Enabled;
4597      return true;
4598    }
4599    return false;
4600  }
4601
4602  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4603    IsMips16 = false;
4604    IsMicromips = false;
4605    IsSingleFloat = false;
4606    FloatABI = HardFloat;
4607    DspRev = NoDSP;
4608
4609    for (std::vector<std::string>::iterator it = Features.begin(),
4610         ie = Features.end(); it != ie; ++it) {
4611      if (*it == "+single-float")
4612        IsSingleFloat = true;
4613      else if (*it == "+soft-float")
4614        FloatABI = SoftFloat;
4615      else if (*it == "+mips16")
4616        IsMips16 = true;
4617      else if (*it == "+micromips")
4618        IsMicromips = true;
4619      else if (*it == "+dsp")
4620        DspRev = std::max(DspRev, DSP1);
4621      else if (*it == "+dspr2")
4622        DspRev = std::max(DspRev, DSP2);
4623    }
4624
4625    // Remove front-end specific option.
4626    std::vector<std::string>::iterator it =
4627      std::find(Features.begin(), Features.end(), "+soft-float");
4628    if (it != Features.end())
4629      Features.erase(it);
4630  }
4631
4632  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4633    if (RegNo == 0) return 4;
4634    if (RegNo == 1) return 5;
4635    return -1;
4636  }
4637};
4638
4639const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4640#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4641#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4642                                              ALL_LANGUAGES },
4643#include "clang/Basic/BuiltinsMips.def"
4644};
4645
4646class Mips32TargetInfoBase : public MipsTargetInfoBase {
4647public:
4648  Mips32TargetInfoBase(const std::string& triple) :
4649    MipsTargetInfoBase(triple, "o32", "mips32") {
4650    SizeType = UnsignedInt;
4651    PtrDiffType = SignedInt;
4652    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4653  }
4654  virtual bool setABI(const std::string &Name) {
4655    if ((Name == "o32") || (Name == "eabi")) {
4656      ABI = Name;
4657      return true;
4658    } else if (Name == "32") {
4659      ABI = "o32";
4660      return true;
4661    } else
4662      return false;
4663  }
4664  virtual void getTargetDefines(const LangOptions &Opts,
4665                                MacroBuilder &Builder) const {
4666    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4667
4668    if (ABI == "o32") {
4669      Builder.defineMacro("__mips_o32");
4670      Builder.defineMacro("_ABIO32", "1");
4671      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4672    }
4673    else if (ABI == "eabi")
4674      Builder.defineMacro("__mips_eabi");
4675    else
4676      llvm_unreachable("Invalid ABI for Mips32.");
4677  }
4678  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4679                                unsigned &NumAliases) const {
4680    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4681      { { "at" },  "$1" },
4682      { { "v0" },  "$2" },
4683      { { "v1" },  "$3" },
4684      { { "a0" },  "$4" },
4685      { { "a1" },  "$5" },
4686      { { "a2" },  "$6" },
4687      { { "a3" },  "$7" },
4688      { { "t0" },  "$8" },
4689      { { "t1" },  "$9" },
4690      { { "t2" }, "$10" },
4691      { { "t3" }, "$11" },
4692      { { "t4" }, "$12" },
4693      { { "t5" }, "$13" },
4694      { { "t6" }, "$14" },
4695      { { "t7" }, "$15" },
4696      { { "s0" }, "$16" },
4697      { { "s1" }, "$17" },
4698      { { "s2" }, "$18" },
4699      { { "s3" }, "$19" },
4700      { { "s4" }, "$20" },
4701      { { "s5" }, "$21" },
4702      { { "s6" }, "$22" },
4703      { { "s7" }, "$23" },
4704      { { "t8" }, "$24" },
4705      { { "t9" }, "$25" },
4706      { { "k0" }, "$26" },
4707      { { "k1" }, "$27" },
4708      { { "gp" }, "$28" },
4709      { { "sp","$sp" }, "$29" },
4710      { { "fp","$fp" }, "$30" },
4711      { { "ra" }, "$31" }
4712    };
4713    Aliases = GCCRegAliases;
4714    NumAliases = llvm::array_lengthof(GCCRegAliases);
4715  }
4716};
4717
4718class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4719public:
4720  Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4721    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4722                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4723  }
4724  virtual void getTargetDefines(const LangOptions &Opts,
4725                                MacroBuilder &Builder) const {
4726    DefineStd(Builder, "MIPSEB", Opts);
4727    Builder.defineMacro("_MIPSEB");
4728    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4729  }
4730};
4731
4732class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4733public:
4734  Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4735    BigEndian = false;
4736    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4737                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4738  }
4739  virtual void getTargetDefines(const LangOptions &Opts,
4740                                MacroBuilder &Builder) const {
4741    DefineStd(Builder, "MIPSEL", Opts);
4742    Builder.defineMacro("_MIPSEL");
4743    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4744  }
4745};
4746
4747class Mips64TargetInfoBase : public MipsTargetInfoBase {
4748  virtual void SetDescriptionString(const std::string &Name) = 0;
4749public:
4750  Mips64TargetInfoBase(const std::string& triple) :
4751    MipsTargetInfoBase(triple, "n64", "mips64") {
4752    LongWidth = LongAlign = 64;
4753    PointerWidth = PointerAlign = 64;
4754    LongDoubleWidth = LongDoubleAlign = 128;
4755    LongDoubleFormat = &llvm::APFloat::IEEEquad;
4756    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4757      LongDoubleWidth = LongDoubleAlign = 64;
4758      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4759    }
4760    SuitableAlign = 128;
4761    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4762  }
4763  virtual bool setABI(const std::string &Name) {
4764    SetDescriptionString(Name);
4765    if (Name == "n32") {
4766      LongWidth = LongAlign = 32;
4767      PointerWidth = PointerAlign = 32;
4768      ABI = Name;
4769      return true;
4770    } else if (Name == "n64") {
4771      ABI = Name;
4772      return true;
4773    } else if (Name == "64") {
4774      ABI = "n64";
4775      return true;
4776    } else
4777      return false;
4778  }
4779  virtual void getTargetDefines(const LangOptions &Opts,
4780                                MacroBuilder &Builder) const {
4781    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4782
4783    Builder.defineMacro("__mips64");
4784    Builder.defineMacro("__mips64__");
4785
4786    if (ABI == "n32") {
4787      Builder.defineMacro("__mips_n32");
4788      Builder.defineMacro("_ABIN32", "2");
4789      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4790    }
4791    else if (ABI == "n64") {
4792      Builder.defineMacro("__mips_n64");
4793      Builder.defineMacro("_ABI64", "3");
4794      Builder.defineMacro("_MIPS_SIM", "_ABI64");
4795    }
4796    else
4797      llvm_unreachable("Invalid ABI for Mips64.");
4798  }
4799  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4800                                unsigned &NumAliases) const {
4801    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4802      { { "at" },  "$1" },
4803      { { "v0" },  "$2" },
4804      { { "v1" },  "$3" },
4805      { { "a0" },  "$4" },
4806      { { "a1" },  "$5" },
4807      { { "a2" },  "$6" },
4808      { { "a3" },  "$7" },
4809      { { "a4" },  "$8" },
4810      { { "a5" },  "$9" },
4811      { { "a6" }, "$10" },
4812      { { "a7" }, "$11" },
4813      { { "t0" }, "$12" },
4814      { { "t1" }, "$13" },
4815      { { "t2" }, "$14" },
4816      { { "t3" }, "$15" },
4817      { { "s0" }, "$16" },
4818      { { "s1" }, "$17" },
4819      { { "s2" }, "$18" },
4820      { { "s3" }, "$19" },
4821      { { "s4" }, "$20" },
4822      { { "s5" }, "$21" },
4823      { { "s6" }, "$22" },
4824      { { "s7" }, "$23" },
4825      { { "t8" }, "$24" },
4826      { { "t9" }, "$25" },
4827      { { "k0" }, "$26" },
4828      { { "k1" }, "$27" },
4829      { { "gp" }, "$28" },
4830      { { "sp","$sp" }, "$29" },
4831      { { "fp","$fp" }, "$30" },
4832      { { "ra" }, "$31" }
4833    };
4834    Aliases = GCCRegAliases;
4835    NumAliases = llvm::array_lengthof(GCCRegAliases);
4836  }
4837};
4838
4839class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4840  virtual void SetDescriptionString(const std::string &Name) {
4841    // Change DescriptionString only if ABI is n32.
4842    if (Name == "n32")
4843      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4844                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4845                          "v64:64:64-n32:64-S128";
4846  }
4847public:
4848  Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4849    // Default ABI is n64.
4850    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4851                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4852                        "v64:64:64-n32:64-S128";
4853  }
4854  virtual void getTargetDefines(const LangOptions &Opts,
4855                                MacroBuilder &Builder) const {
4856    DefineStd(Builder, "MIPSEB", Opts);
4857    Builder.defineMacro("_MIPSEB");
4858    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4859  }
4860};
4861
4862class Mips64ELTargetInfo : public Mips64TargetInfoBase {
4863  virtual void SetDescriptionString(const std::string &Name) {
4864    // Change DescriptionString only if ABI is n32.
4865    if (Name == "n32")
4866      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4867                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
4868                          "-v64:64:64-n32:64-S128";
4869  }
4870public:
4871  Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4872    // Default ABI is n64.
4873    BigEndian = false;
4874    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4875                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4876                        "v64:64:64-n32:64-S128";
4877  }
4878  virtual void getTargetDefines(const LangOptions &Opts,
4879                                MacroBuilder &Builder) const {
4880    DefineStd(Builder, "MIPSEL", Opts);
4881    Builder.defineMacro("_MIPSEL");
4882    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4883  }
4884};
4885} // end anonymous namespace.
4886
4887namespace {
4888class PNaClTargetInfo : public TargetInfo {
4889public:
4890  PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
4891    BigEndian = false;
4892    this->UserLabelPrefix = "";
4893    this->LongAlign = 32;
4894    this->LongWidth = 32;
4895    this->PointerAlign = 32;
4896    this->PointerWidth = 32;
4897    this->IntMaxType = TargetInfo::SignedLongLong;
4898    this->UIntMaxType = TargetInfo::UnsignedLongLong;
4899    this->Int64Type = TargetInfo::SignedLongLong;
4900    this->DoubleAlign = 64;
4901    this->LongDoubleWidth = 64;
4902    this->LongDoubleAlign = 64;
4903    this->SizeType = TargetInfo::UnsignedInt;
4904    this->PtrDiffType = TargetInfo::SignedInt;
4905    this->IntPtrType = TargetInfo::SignedInt;
4906    this->RegParmMax = 0; // Disallow regparm
4907    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4908                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
4909  }
4910
4911  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4912  }
4913  virtual void getArchDefines(const LangOptions &Opts,
4914                              MacroBuilder &Builder) const {
4915    Builder.defineMacro("__le32__");
4916    Builder.defineMacro("__pnacl__");
4917  }
4918  virtual void getTargetDefines(const LangOptions &Opts,
4919                                MacroBuilder &Builder) const {
4920    Builder.defineMacro("__LITTLE_ENDIAN__");
4921    getArchDefines(Opts, Builder);
4922  }
4923  virtual bool hasFeature(StringRef Feature) const {
4924    return Feature == "pnacl";
4925  }
4926  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4927                                 unsigned &NumRecords) const {
4928  }
4929  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4930    return TargetInfo::PNaClABIBuiltinVaList;
4931  }
4932  virtual void getGCCRegNames(const char * const *&Names,
4933                              unsigned &NumNames) const;
4934  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4935                                unsigned &NumAliases) const;
4936  virtual bool validateAsmConstraint(const char *&Name,
4937                                     TargetInfo::ConstraintInfo &Info) const {
4938    return false;
4939  }
4940
4941  virtual const char *getClobbers() const {
4942    return "";
4943  }
4944};
4945
4946void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
4947                                     unsigned &NumNames) const {
4948  Names = NULL;
4949  NumNames = 0;
4950}
4951
4952void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4953                                       unsigned &NumAliases) const {
4954  Aliases = NULL;
4955  NumAliases = 0;
4956}
4957} // end anonymous namespace.
4958
4959namespace {
4960  static const unsigned SPIRAddrSpaceMap[] = {
4961    1,    // opencl_global
4962    3,    // opencl_local
4963    2,    // opencl_constant
4964    0,    // cuda_device
4965    0,    // cuda_constant
4966    0     // cuda_shared
4967  };
4968  class SPIRTargetInfo : public TargetInfo {
4969    static const char * const GCCRegNames[];
4970    static const Builtin::Info BuiltinInfo[];
4971    std::vector<StringRef> AvailableFeatures;
4972  public:
4973    SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) {
4974      assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
4975        "SPIR target must use unknown OS");
4976      assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
4977        "SPIR target must use unknown environment type");
4978      BigEndian = false;
4979      TLSSupported = false;
4980      LongWidth = LongAlign = 64;
4981      AddrSpaceMap = &SPIRAddrSpaceMap;
4982      // Define available target features
4983      // These must be defined in sorted order!
4984      NoAsmVariants = true;
4985    }
4986    virtual void getTargetDefines(const LangOptions &Opts,
4987                                  MacroBuilder &Builder) const {
4988      DefineStd(Builder, "SPIR", Opts);
4989    }
4990    virtual bool hasFeature(StringRef Feature) const {
4991      return Feature == "spir";
4992    }
4993
4994    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4995                                   unsigned &NumRecords) const {}
4996    virtual const char *getClobbers() const {
4997      return "";
4998    }
4999    virtual void getGCCRegNames(const char * const *&Names,
5000                                unsigned &NumNames) const {}
5001    virtual bool validateAsmConstraint(const char *&Name,
5002                                       TargetInfo::ConstraintInfo &info) const {
5003      return true;
5004    }
5005    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5006                                  unsigned &NumAliases) const {}
5007    virtual BuiltinVaListKind getBuiltinVaListKind() const {
5008      return TargetInfo::VoidPtrBuiltinVaList;
5009    }
5010  };
5011
5012
5013  class SPIR32TargetInfo : public SPIRTargetInfo {
5014  public:
5015    SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5016      PointerWidth = PointerAlign = 32;
5017      SizeType     = TargetInfo::UnsignedInt;
5018      PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5019      DescriptionString
5020        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5021          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5022          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5023          "v512:512:512-v1024:1024:1024";
5024    }
5025    virtual void getTargetDefines(const LangOptions &Opts,
5026                                  MacroBuilder &Builder) const {
5027      DefineStd(Builder, "SPIR32", Opts);
5028    }
5029  };
5030
5031  class SPIR64TargetInfo : public SPIRTargetInfo {
5032  public:
5033    SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5034      PointerWidth = PointerAlign = 64;
5035      SizeType     = TargetInfo::UnsignedLong;
5036      PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5037      DescriptionString
5038        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5039          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5040          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5041          "v512:512:512-v1024:1024:1024";
5042    }
5043    virtual void getTargetDefines(const LangOptions &Opts,
5044                                  MacroBuilder &Builder) const {
5045      DefineStd(Builder, "SPIR64", Opts);
5046    }
5047  };
5048}
5049
5050
5051//===----------------------------------------------------------------------===//
5052// Driver code
5053//===----------------------------------------------------------------------===//
5054
5055static TargetInfo *AllocateTarget(const std::string &T) {
5056  llvm::Triple Triple(T);
5057  llvm::Triple::OSType os = Triple.getOS();
5058
5059  switch (Triple.getArch()) {
5060  default:
5061    return NULL;
5062
5063  case llvm::Triple::hexagon:
5064    return new HexagonTargetInfo(T);
5065
5066  case llvm::Triple::aarch64:
5067    switch (os) {
5068    case llvm::Triple::Linux:
5069      return new LinuxTargetInfo<AArch64TargetInfo>(T);
5070    default:
5071      return new AArch64TargetInfo(T);
5072    }
5073
5074  case llvm::Triple::arm:
5075  case llvm::Triple::thumb:
5076    if (Triple.isOSDarwin())
5077      return new DarwinARMTargetInfo(T);
5078
5079    switch (os) {
5080    case llvm::Triple::Linux:
5081      return new LinuxTargetInfo<ARMTargetInfo>(T);
5082    case llvm::Triple::FreeBSD:
5083      return new FreeBSDTargetInfo<ARMTargetInfo>(T);
5084    case llvm::Triple::NetBSD:
5085      return new NetBSDTargetInfo<ARMTargetInfo>(T);
5086    case llvm::Triple::OpenBSD:
5087      return new OpenBSDTargetInfo<ARMTargetInfo>(T);
5088    case llvm::Triple::Bitrig:
5089      return new BitrigTargetInfo<ARMTargetInfo>(T);
5090    case llvm::Triple::RTEMS:
5091      return new RTEMSTargetInfo<ARMTargetInfo>(T);
5092    case llvm::Triple::NaCl:
5093      return new NaClTargetInfo<ARMTargetInfo>(T);
5094    default:
5095      return new ARMTargetInfo(T);
5096    }
5097
5098  case llvm::Triple::msp430:
5099    return new MSP430TargetInfo(T);
5100
5101  case llvm::Triple::mips:
5102    switch (os) {
5103    case llvm::Triple::Linux:
5104      return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
5105    case llvm::Triple::RTEMS:
5106      return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
5107    case llvm::Triple::FreeBSD:
5108      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
5109    case llvm::Triple::NetBSD:
5110      return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
5111    default:
5112      return new Mips32EBTargetInfo(T);
5113    }
5114
5115  case llvm::Triple::mipsel:
5116    switch (os) {
5117    case llvm::Triple::Linux:
5118      return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
5119    case llvm::Triple::RTEMS:
5120      return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
5121    case llvm::Triple::FreeBSD:
5122      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
5123    case llvm::Triple::NetBSD:
5124      return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
5125    default:
5126      return new Mips32ELTargetInfo(T);
5127    }
5128
5129  case llvm::Triple::mips64:
5130    switch (os) {
5131    case llvm::Triple::Linux:
5132      return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
5133    case llvm::Triple::RTEMS:
5134      return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
5135    case llvm::Triple::FreeBSD:
5136      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
5137    case llvm::Triple::NetBSD:
5138      return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
5139    case llvm::Triple::OpenBSD:
5140      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
5141    default:
5142      return new Mips64EBTargetInfo(T);
5143    }
5144
5145  case llvm::Triple::mips64el:
5146    switch (os) {
5147    case llvm::Triple::Linux:
5148      return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
5149    case llvm::Triple::RTEMS:
5150      return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
5151    case llvm::Triple::FreeBSD:
5152      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
5153    case llvm::Triple::NetBSD:
5154      return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
5155    case llvm::Triple::OpenBSD:
5156      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
5157    default:
5158      return new Mips64ELTargetInfo(T);
5159    }
5160
5161  case llvm::Triple::le32:
5162    switch (os) {
5163      case llvm::Triple::NaCl:
5164        return new NaClTargetInfo<PNaClTargetInfo>(T);
5165      default:
5166        return NULL;
5167    }
5168
5169  case llvm::Triple::ppc:
5170    if (Triple.isOSDarwin())
5171      return new DarwinPPC32TargetInfo(T);
5172    switch (os) {
5173    case llvm::Triple::Linux:
5174      return new LinuxTargetInfo<PPC32TargetInfo>(T);
5175    case llvm::Triple::FreeBSD:
5176      return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
5177    case llvm::Triple::NetBSD:
5178      return new NetBSDTargetInfo<PPC32TargetInfo>(T);
5179    case llvm::Triple::OpenBSD:
5180      return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
5181    case llvm::Triple::RTEMS:
5182      return new RTEMSTargetInfo<PPC32TargetInfo>(T);
5183    default:
5184      return new PPC32TargetInfo(T);
5185    }
5186
5187  case llvm::Triple::ppc64:
5188    if (Triple.isOSDarwin())
5189      return new DarwinPPC64TargetInfo(T);
5190    switch (os) {
5191    case llvm::Triple::Linux:
5192      return new LinuxTargetInfo<PPC64TargetInfo>(T);
5193    case llvm::Triple::Lv2:
5194      return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
5195    case llvm::Triple::FreeBSD:
5196      return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
5197    case llvm::Triple::NetBSD:
5198      return new NetBSDTargetInfo<PPC64TargetInfo>(T);
5199    default:
5200      return new PPC64TargetInfo(T);
5201    }
5202
5203  case llvm::Triple::nvptx:
5204    return new NVPTX32TargetInfo(T);
5205  case llvm::Triple::nvptx64:
5206    return new NVPTX64TargetInfo(T);
5207
5208  case llvm::Triple::mblaze:
5209    return new MBlazeTargetInfo(T);
5210
5211  case llvm::Triple::r600:
5212    return new R600TargetInfo(T);
5213
5214  case llvm::Triple::sparc:
5215    switch (os) {
5216    case llvm::Triple::Linux:
5217      return new LinuxTargetInfo<SparcV8TargetInfo>(T);
5218    case llvm::Triple::AuroraUX:
5219      return new AuroraUXSparcV8TargetInfo(T);
5220    case llvm::Triple::Solaris:
5221      return new SolarisSparcV8TargetInfo(T);
5222    case llvm::Triple::NetBSD:
5223      return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
5224    case llvm::Triple::OpenBSD:
5225      return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
5226    case llvm::Triple::RTEMS:
5227      return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
5228    default:
5229      return new SparcV8TargetInfo(T);
5230    }
5231
5232  case llvm::Triple::sparcv9:
5233    switch (os) {
5234    case llvm::Triple::Linux:
5235      return new LinuxTargetInfo<SparcV9TargetInfo>(T);
5236    case llvm::Triple::AuroraUX:
5237      return new AuroraUXTargetInfo<SparcV9TargetInfo>(T);
5238    case llvm::Triple::Solaris:
5239      return new SolarisTargetInfo<SparcV9TargetInfo>(T);
5240    case llvm::Triple::NetBSD:
5241      return new NetBSDTargetInfo<SparcV9TargetInfo>(T);
5242    case llvm::Triple::OpenBSD:
5243      return new OpenBSDTargetInfo<SparcV9TargetInfo>(T);
5244    case llvm::Triple::FreeBSD:
5245      return new FreeBSDTargetInfo<SparcV9TargetInfo>(T);
5246    default:
5247      return new SparcV9TargetInfo(T);
5248    }
5249
5250  case llvm::Triple::tce:
5251    return new TCETargetInfo(T);
5252
5253  case llvm::Triple::x86:
5254    if (Triple.isOSDarwin())
5255      return new DarwinI386TargetInfo(T);
5256
5257    switch (os) {
5258    case llvm::Triple::AuroraUX:
5259      return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
5260    case llvm::Triple::Linux:
5261      return new LinuxTargetInfo<X86_32TargetInfo>(T);
5262    case llvm::Triple::DragonFly:
5263      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
5264    case llvm::Triple::NetBSD:
5265      return new NetBSDI386TargetInfo(T);
5266    case llvm::Triple::OpenBSD:
5267      return new OpenBSDI386TargetInfo(T);
5268    case llvm::Triple::Bitrig:
5269      return new BitrigI386TargetInfo(T);
5270    case llvm::Triple::FreeBSD:
5271      return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
5272    case llvm::Triple::Minix:
5273      return new MinixTargetInfo<X86_32TargetInfo>(T);
5274    case llvm::Triple::Solaris:
5275      return new SolarisTargetInfo<X86_32TargetInfo>(T);
5276    case llvm::Triple::Cygwin:
5277      return new CygwinX86_32TargetInfo(T);
5278    case llvm::Triple::MinGW32:
5279      return new MinGWX86_32TargetInfo(T);
5280    case llvm::Triple::Win32:
5281      return new VisualStudioWindowsX86_32TargetInfo(T);
5282    case llvm::Triple::Haiku:
5283      return new HaikuX86_32TargetInfo(T);
5284    case llvm::Triple::RTEMS:
5285      return new RTEMSX86_32TargetInfo(T);
5286    case llvm::Triple::NaCl:
5287      return new NaClTargetInfo<X86_32TargetInfo>(T);
5288    default:
5289      return new X86_32TargetInfo(T);
5290    }
5291
5292  case llvm::Triple::x86_64:
5293    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5294      return new DarwinX86_64TargetInfo(T);
5295
5296    switch (os) {
5297    case llvm::Triple::AuroraUX:
5298      return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
5299    case llvm::Triple::Linux:
5300      return new LinuxTargetInfo<X86_64TargetInfo>(T);
5301    case llvm::Triple::DragonFly:
5302      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
5303    case llvm::Triple::NetBSD:
5304      return new NetBSDTargetInfo<X86_64TargetInfo>(T);
5305    case llvm::Triple::OpenBSD:
5306      return new OpenBSDX86_64TargetInfo(T);
5307    case llvm::Triple::Bitrig:
5308      return new BitrigX86_64TargetInfo(T);
5309    case llvm::Triple::FreeBSD:
5310      return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
5311    case llvm::Triple::Solaris:
5312      return new SolarisTargetInfo<X86_64TargetInfo>(T);
5313    case llvm::Triple::MinGW32:
5314      return new MinGWX86_64TargetInfo(T);
5315    case llvm::Triple::Win32:   // This is what Triple.h supports now.
5316      return new VisualStudioWindowsX86_64TargetInfo(T);
5317    case llvm::Triple::NaCl:
5318      return new NaClTargetInfo<X86_64TargetInfo>(T);
5319    default:
5320      return new X86_64TargetInfo(T);
5321    }
5322
5323    case llvm::Triple::spir: {
5324      llvm::Triple Triple(T);
5325      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5326        Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5327        return NULL;
5328      return new SPIR32TargetInfo(T);
5329    }
5330    case llvm::Triple::spir64: {
5331      llvm::Triple Triple(T);
5332      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5333        Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5334        return NULL;
5335      return new SPIR64TargetInfo(T);
5336    }
5337  }
5338}
5339
5340/// CreateTargetInfo - Return the target info object for the specified target
5341/// triple.
5342TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5343                                         TargetOptions *Opts) {
5344  llvm::Triple Triple(Opts->Triple);
5345
5346  // Construct the target
5347  OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
5348  if (!Target) {
5349    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5350    return 0;
5351  }
5352  Target->setTargetOpts(Opts);
5353
5354  // Set the target CPU if specified.
5355  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5356    Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5357    return 0;
5358  }
5359
5360  // Set the target ABI if specified.
5361  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5362    Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5363    return 0;
5364  }
5365
5366  // Set the target C++ ABI.
5367  if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5368    Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5369    return 0;
5370  }
5371
5372  // Compute the default target features, we need the target to handle this
5373  // because features may have dependencies on one another.
5374  llvm::StringMap<bool> Features;
5375  Target->getDefaultFeatures(Features);
5376
5377  // Apply the user specified deltas.
5378  // First the enables.
5379  for (std::vector<std::string>::const_iterator
5380         it = Opts->FeaturesAsWritten.begin(),
5381         ie = Opts->FeaturesAsWritten.end();
5382       it != ie; ++it) {
5383    const char *Name = it->c_str();
5384
5385    if (Name[0] != '+')
5386      continue;
5387
5388    // Apply the feature via the target.
5389    if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5390      Diags.Report(diag::err_target_invalid_feature) << Name;
5391      return 0;
5392    }
5393  }
5394
5395  // Then the disables.
5396  for (std::vector<std::string>::const_iterator
5397         it = Opts->FeaturesAsWritten.begin(),
5398         ie = Opts->FeaturesAsWritten.end();
5399       it != ie; ++it) {
5400    const char *Name = it->c_str();
5401
5402    if (Name[0] == '+')
5403      continue;
5404
5405    // Apply the feature via the target.
5406    if (Name[0] != '-' ||
5407        !Target->setFeatureEnabled(Features, Name + 1, false)) {
5408      Diags.Report(diag::err_target_invalid_feature) << Name;
5409      return 0;
5410    }
5411  }
5412
5413  // Add the features to the compile options.
5414  //
5415  // FIXME: If we are completely confident that we have the right set, we only
5416  // need to pass the minuses.
5417  Opts->Features.clear();
5418  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5419         ie = Features.end(); it != ie; ++it)
5420    Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5421  Target->HandleTargetFeatures(Opts->Features);
5422
5423  return Target.take();
5424}
5425