Targets.cpp revision 612db2aa100453710ce9eb9032268ae30b902d4e 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/MC/MCSectionMachO.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Type.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "5621");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.SanitizeAddress) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.getOS() == llvm::Triple::IOS) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else {
153    // Note that the Driver allows versions which aren't representable in the
154    // define (because we only get a single digit for the minor and micro
155    // revision numbers). So, we limit them to the maximum representable
156    // version.
157    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159    char Str[5];
160    Str[0] = '0' + (Maj / 10);
161    Str[1] = '0' + (Maj % 10);
162    Str[2] = '0' + std::min(Min, 9U);
163    Str[3] = '0' + std::min(Rev, 9U);
164    Str[4] = '\0';
165    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166  }
167
168  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169}
170
171namespace {
172template<typename Target>
173class DarwinTargetInfo : public OSTargetInfo<Target> {
174protected:
175  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                            MacroBuilder &Builder) const {
177    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                     this->PlatformMinVersion);
179  }
180
181public:
182  DarwinTargetInfo(const std::string& triple) :
183    OSTargetInfo<Target>(triple) {
184      llvm::Triple T = llvm::Triple(triple);
185      this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186      this->MCountName = "\01mcount";
187    }
188
189  virtual std::string isValidSectionSpecifier(StringRef SR) const {
190    // Let MCSectionMachO validate this.
191    StringRef Segment, Section;
192    unsigned TAA, StubSize;
193    bool HasTAA;
194    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                       TAA, HasTAA, StubSize);
196  }
197
198  virtual const char *getStaticInitSectionSpecifier() const {
199    // FIXME: We should return 0 when building kexts.
200    return "__TEXT,__StaticInit,regular,pure_instructions";
201  }
202
203  /// Darwin does not support protected visibility.  Darwin's "default"
204  /// is very similar to ELF's "protected";  Darwin requires a "weak"
205  /// attribute on declarations that can be dynamically replaced.
206  virtual bool hasProtectedVisibility() const {
207    return false;
208  }
209};
210
211
212// DragonFlyBSD Target
213template<typename Target>
214class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215protected:
216  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                            MacroBuilder &Builder) const {
218    // DragonFly defines; list based off of gcc output
219    Builder.defineMacro("__DragonFly__");
220    Builder.defineMacro("__DragonFly_cc_version", "100001");
221    Builder.defineMacro("__ELF__");
222    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223    Builder.defineMacro("__tune_i386__");
224    DefineStd(Builder, "unix", Opts);
225  }
226public:
227  DragonFlyBSDTargetInfo(const std::string &triple)
228    : OSTargetInfo<Target>(triple) {
229      this->UserLabelPrefix = "";
230
231      llvm::Triple Triple(triple);
232      switch (Triple.getArch()) {
233        default:
234        case llvm::Triple::x86:
235        case llvm::Triple::x86_64:
236          this->MCountName = ".mcount";
237          break;
238      }
239  }
240};
241
242// FreeBSD Target
243template<typename Target>
244class FreeBSDTargetInfo : public OSTargetInfo<Target> {
245protected:
246  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247                            MacroBuilder &Builder) const {
248    // FreeBSD defines; list based off of gcc output
249
250    unsigned Release = Triple.getOSMajorVersion();
251    if (Release == 0U)
252      Release = 8;
253
254    Builder.defineMacro("__FreeBSD__", Twine(Release));
255    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257    DefineStd(Builder, "unix", Opts);
258    Builder.defineMacro("__ELF__");
259  }
260public:
261  FreeBSDTargetInfo(const std::string &triple)
262    : OSTargetInfo<Target>(triple) {
263      this->UserLabelPrefix = "";
264
265      llvm::Triple Triple(triple);
266      switch (Triple.getArch()) {
267        default:
268        case llvm::Triple::x86:
269        case llvm::Triple::x86_64:
270          this->MCountName = ".mcount";
271          break;
272        case llvm::Triple::mips:
273        case llvm::Triple::mipsel:
274        case llvm::Triple::ppc:
275        case llvm::Triple::ppc64:
276          this->MCountName = "_mcount";
277          break;
278        case llvm::Triple::arm:
279          this->MCountName = "__mcount";
280          break;
281      }
282
283    }
284};
285
286// Minix Target
287template<typename Target>
288class MinixTargetInfo : public OSTargetInfo<Target> {
289protected:
290  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291                            MacroBuilder &Builder) const {
292    // Minix defines
293
294    Builder.defineMacro("__minix", "3");
295    Builder.defineMacro("_EM_WSIZE", "4");
296    Builder.defineMacro("_EM_PSIZE", "4");
297    Builder.defineMacro("_EM_SSIZE", "2");
298    Builder.defineMacro("_EM_LSIZE", "4");
299    Builder.defineMacro("_EM_FSIZE", "4");
300    Builder.defineMacro("_EM_DSIZE", "8");
301    Builder.defineMacro("__ELF__");
302    DefineStd(Builder, "unix", Opts);
303  }
304public:
305  MinixTargetInfo(const std::string &triple)
306    : OSTargetInfo<Target>(triple) {
307      this->UserLabelPrefix = "";
308    }
309};
310
311// Linux target
312template<typename Target>
313class LinuxTargetInfo : public OSTargetInfo<Target> {
314protected:
315  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                            MacroBuilder &Builder) const {
317    // Linux defines; list based off of gcc output
318    DefineStd(Builder, "unix", Opts);
319    DefineStd(Builder, "linux", Opts);
320    Builder.defineMacro("__gnu_linux__");
321    Builder.defineMacro("__ELF__");
322    if (Triple.getEnvironment() == llvm::Triple::Android)
323      Builder.defineMacro("__ANDROID__", "1");
324    if (Opts.POSIXThreads)
325      Builder.defineMacro("_REENTRANT");
326    if (Opts.CPlusPlus)
327      Builder.defineMacro("_GNU_SOURCE");
328  }
329public:
330  LinuxTargetInfo(const std::string& triple)
331    : OSTargetInfo<Target>(triple) {
332    this->UserLabelPrefix = "";
333    this->WIntType = TargetInfo::UnsignedInt;
334  }
335
336  virtual const char *getStaticInitSectionSpecifier() const {
337    return ".text.startup";
338  }
339};
340
341// NetBSD Target
342template<typename Target>
343class NetBSDTargetInfo : public OSTargetInfo<Target> {
344protected:
345  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346                            MacroBuilder &Builder) const {
347    // NetBSD defines; list based off of gcc output
348    Builder.defineMacro("__NetBSD__");
349    Builder.defineMacro("__unix__");
350    Builder.defineMacro("__ELF__");
351    if (Opts.POSIXThreads)
352      Builder.defineMacro("_POSIX_THREADS");
353  }
354public:
355  NetBSDTargetInfo(const std::string &triple)
356    : OSTargetInfo<Target>(triple) {
357      this->UserLabelPrefix = "";
358    }
359};
360
361// OpenBSD Target
362template<typename Target>
363class OpenBSDTargetInfo : public OSTargetInfo<Target> {
364protected:
365  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366                            MacroBuilder &Builder) const {
367    // OpenBSD defines; list based off of gcc output
368
369    Builder.defineMacro("__OpenBSD__");
370    DefineStd(Builder, "unix", Opts);
371    Builder.defineMacro("__ELF__");
372    if (Opts.POSIXThreads)
373      Builder.defineMacro("_REENTRANT");
374  }
375public:
376  OpenBSDTargetInfo(const std::string &triple)
377    : OSTargetInfo<Target>(triple) {
378      this->UserLabelPrefix = "";
379      this->TLSSupported = false;
380
381      llvm::Triple Triple(triple);
382      switch (Triple.getArch()) {
383        default:
384        case llvm::Triple::x86:
385        case llvm::Triple::x86_64:
386        case llvm::Triple::arm:
387        case llvm::Triple::sparc:
388          this->MCountName = "__mcount";
389          break;
390        case llvm::Triple::mips64:
391        case llvm::Triple::mips64el:
392        case llvm::Triple::ppc:
393        case llvm::Triple::sparcv9:
394          this->MCountName = "_mcount";
395          break;
396      }
397  }
398};
399
400// Bitrig Target
401template<typename Target>
402class BitrigTargetInfo : public OSTargetInfo<Target> {
403protected:
404  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405                            MacroBuilder &Builder) const {
406    // Bitrig defines; list based off of gcc output
407
408    Builder.defineMacro("__Bitrig__");
409    DefineStd(Builder, "unix", Opts);
410    Builder.defineMacro("__ELF__");
411    if (Opts.POSIXThreads)
412      Builder.defineMacro("_REENTRANT");
413  }
414public:
415  BitrigTargetInfo(const std::string &triple)
416    : OSTargetInfo<Target>(triple) {
417      this->UserLabelPrefix = "";
418      this->TLSSupported = false;
419      this->MCountName = "__mcount";
420  }
421};
422
423// PSP Target
424template<typename Target>
425class PSPTargetInfo : public OSTargetInfo<Target> {
426protected:
427  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428                            MacroBuilder &Builder) const {
429    // PSP defines; list based on the output of the pspdev gcc toolchain.
430    Builder.defineMacro("PSP");
431    Builder.defineMacro("_PSP");
432    Builder.defineMacro("__psp__");
433    Builder.defineMacro("__ELF__");
434  }
435public:
436  PSPTargetInfo(const std::string& triple)
437    : OSTargetInfo<Target>(triple) {
438    this->UserLabelPrefix = "";
439  }
440};
441
442// PS3 PPU Target
443template<typename Target>
444class PS3PPUTargetInfo : public OSTargetInfo<Target> {
445protected:
446  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                            MacroBuilder &Builder) const {
448    // PS3 PPU defines.
449    Builder.defineMacro("__PPC__");
450    Builder.defineMacro("__PPU__");
451    Builder.defineMacro("__CELLOS_LV2__");
452    Builder.defineMacro("__ELF__");
453    Builder.defineMacro("__LP32__");
454    Builder.defineMacro("_ARCH_PPC64");
455    Builder.defineMacro("__powerpc64__");
456  }
457public:
458  PS3PPUTargetInfo(const std::string& triple)
459    : OSTargetInfo<Target>(triple) {
460    this->UserLabelPrefix = "";
461    this->LongWidth = this->LongAlign = 32;
462    this->PointerWidth = this->PointerAlign = 32;
463    this->IntMaxType = TargetInfo::SignedLongLong;
464    this->UIntMaxType = TargetInfo::UnsignedLongLong;
465    this->Int64Type = TargetInfo::SignedLongLong;
466    this->SizeType = TargetInfo::UnsignedInt;
467    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
469  }
470};
471
472// FIXME: Need a real SPU target.
473// PS3 SPU Target
474template<typename Target>
475class PS3SPUTargetInfo : public OSTargetInfo<Target> {
476protected:
477  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478                            MacroBuilder &Builder) const {
479    // PS3 PPU defines.
480    Builder.defineMacro("__SPU__");
481    Builder.defineMacro("__ELF__");
482  }
483public:
484  PS3SPUTargetInfo(const std::string& triple)
485    : OSTargetInfo<Target>(triple) {
486    this->UserLabelPrefix = "";
487  }
488};
489
490// AuroraUX target
491template<typename Target>
492class AuroraUXTargetInfo : public OSTargetInfo<Target> {
493protected:
494  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                            MacroBuilder &Builder) const {
496    DefineStd(Builder, "sun", Opts);
497    DefineStd(Builder, "unix", Opts);
498    Builder.defineMacro("__ELF__");
499    Builder.defineMacro("__svr4__");
500    Builder.defineMacro("__SVR4");
501  }
502public:
503  AuroraUXTargetInfo(const std::string& triple)
504    : OSTargetInfo<Target>(triple) {
505    this->UserLabelPrefix = "";
506    this->WCharType = this->SignedLong;
507    // FIXME: WIntType should be SignedLong
508  }
509};
510
511// Solaris target
512template<typename Target>
513class SolarisTargetInfo : public OSTargetInfo<Target> {
514protected:
515  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516                            MacroBuilder &Builder) const {
517    DefineStd(Builder, "sun", Opts);
518    DefineStd(Builder, "unix", Opts);
519    Builder.defineMacro("__ELF__");
520    Builder.defineMacro("__svr4__");
521    Builder.defineMacro("__SVR4");
522    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523    // newer, but to 500 for everything else.  feature_test.h has a check to
524    // ensure that you are not using C99 with an old version of X/Open or C89
525    // with a new version.
526    if (Opts.C99 || Opts.C11)
527      Builder.defineMacro("_XOPEN_SOURCE", "600");
528    else
529      Builder.defineMacro("_XOPEN_SOURCE", "500");
530    if (Opts.CPlusPlus)
531      Builder.defineMacro("__C99FEATURES__");
532    Builder.defineMacro("_LARGEFILE_SOURCE");
533    Builder.defineMacro("_LARGEFILE64_SOURCE");
534    Builder.defineMacro("__EXTENSIONS__");
535    Builder.defineMacro("_REENTRANT");
536  }
537public:
538  SolarisTargetInfo(const std::string& triple)
539    : OSTargetInfo<Target>(triple) {
540    this->UserLabelPrefix = "";
541    this->WCharType = this->SignedInt;
542    // FIXME: WIntType should be SignedLong
543  }
544};
545
546// Windows target
547template<typename Target>
548class WindowsTargetInfo : public OSTargetInfo<Target> {
549protected:
550  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551                            MacroBuilder &Builder) const {
552    Builder.defineMacro("_WIN32");
553  }
554  void getVisualStudioDefines(const LangOptions &Opts,
555                              MacroBuilder &Builder) const {
556    if (Opts.CPlusPlus) {
557      if (Opts.RTTI)
558        Builder.defineMacro("_CPPRTTI");
559
560      if (Opts.Exceptions)
561        Builder.defineMacro("_CPPUNWIND");
562    }
563
564    if (!Opts.CharIsSigned)
565      Builder.defineMacro("_CHAR_UNSIGNED");
566
567    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568    //        but it works for now.
569    if (Opts.POSIXThreads)
570      Builder.defineMacro("_MT");
571
572    if (Opts.MSCVersion != 0)
573      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
574
575    if (Opts.MicrosoftExt) {
576      Builder.defineMacro("_MSC_EXTENSIONS");
577
578      if (Opts.CPlusPlus0x) {
579        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
582      }
583    }
584
585    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
586  }
587
588public:
589  WindowsTargetInfo(const std::string &triple)
590    : OSTargetInfo<Target>(triple) {}
591};
592
593template <typename Target>
594class NaClTargetInfo : public OSTargetInfo<Target> {
595 protected:
596  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597                            MacroBuilder &Builder) const {
598    if (Opts.POSIXThreads)
599      Builder.defineMacro("_REENTRANT");
600    if (Opts.CPlusPlus)
601      Builder.defineMacro("_GNU_SOURCE");
602
603    DefineStd(Builder, "unix", Opts);
604    Builder.defineMacro("__ELF__");
605    Builder.defineMacro("__native_client__");
606  }
607 public:
608  NaClTargetInfo(const std::string &triple)
609    : OSTargetInfo<Target>(triple) {
610    this->UserLabelPrefix = "";
611    this->LongAlign = 32;
612    this->LongWidth = 32;
613    this->PointerAlign = 32;
614    this->PointerWidth = 32;
615    this->IntMaxType = TargetInfo::SignedLongLong;
616    this->UIntMaxType = TargetInfo::UnsignedLongLong;
617    this->Int64Type = TargetInfo::SignedLongLong;
618    this->DoubleAlign = 64;
619    this->LongDoubleWidth = 64;
620    this->LongDoubleAlign = 64;
621    this->SizeType = TargetInfo::UnsignedInt;
622    this->PtrDiffType = TargetInfo::SignedInt;
623    this->IntPtrType = TargetInfo::SignedInt;
624    this->RegParmMax = 2;
625    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
626    this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
627                              "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
628  }
629  virtual typename Target::CallingConvCheckResult checkCallingConvention(
630      CallingConv CC) const {
631    return CC == CC_PnaclCall ? Target::CCCR_OK :
632        Target::checkCallingConvention(CC);
633  }
634};
635} // end anonymous namespace.
636
637//===----------------------------------------------------------------------===//
638// Specific target implementations.
639//===----------------------------------------------------------------------===//
640
641namespace {
642// PPC abstract base class
643class PPCTargetInfo : public TargetInfo {
644  static const Builtin::Info BuiltinInfo[];
645  static const char * const GCCRegNames[];
646  static const TargetInfo::GCCRegAlias GCCRegAliases[];
647  std::string CPU;
648public:
649  PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
650    LongDoubleWidth = LongDoubleAlign = 128;
651    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
652  }
653
654  /// \brief Flags for architecture specific defines.
655  typedef enum {
656    ArchDefineNone  = 0,
657    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
658    ArchDefinePpcgr = 1 << 1,
659    ArchDefinePpcsq = 1 << 2,
660    ArchDefine440   = 1 << 3,
661    ArchDefine603   = 1 << 4,
662    ArchDefine604   = 1 << 5,
663    ArchDefinePwr4  = 1 << 6,
664    ArchDefinePwr6  = 1 << 7
665  } ArchDefineTypes;
666
667  virtual bool setCPU(const std::string &Name) {
668    bool CPUKnown = llvm::StringSwitch<bool>(Name)
669      .Case("generic", true)
670      .Case("440", true)
671      .Case("450", true)
672      .Case("601", true)
673      .Case("602", true)
674      .Case("603", true)
675      .Case("603e", true)
676      .Case("603ev", true)
677      .Case("604", true)
678      .Case("604e", true)
679      .Case("620", true)
680      .Case("g3", true)
681      .Case("7400", true)
682      .Case("g4", true)
683      .Case("7450", true)
684      .Case("g4+", true)
685      .Case("750", true)
686      .Case("970", true)
687      .Case("g5", true)
688      .Case("a2", true)
689      .Case("e500mc", true)
690      .Case("e5500", true)
691      .Case("pwr6", true)
692      .Case("pwr7", true)
693      .Case("ppc", true)
694      .Case("ppc64", true)
695      .Default(false);
696
697    if (CPUKnown)
698      CPU = Name;
699
700    return CPUKnown;
701  }
702
703  virtual void getTargetBuiltins(const Builtin::Info *&Records,
704                                 unsigned &NumRecords) const {
705    Records = BuiltinInfo;
706    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
707  }
708
709  virtual bool isCLZForZeroUndef() const { return false; }
710
711  virtual void getTargetDefines(const LangOptions &Opts,
712                                MacroBuilder &Builder) const;
713
714  virtual bool hasFeature(StringRef Feature) const;
715
716  virtual void getGCCRegNames(const char * const *&Names,
717                              unsigned &NumNames) const;
718  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
719                                unsigned &NumAliases) const;
720  virtual bool validateAsmConstraint(const char *&Name,
721                                     TargetInfo::ConstraintInfo &Info) const {
722    switch (*Name) {
723    default: return false;
724    case 'O': // Zero
725      break;
726    case 'b': // Base register
727    case 'f': // Floating point register
728      Info.setAllowsRegister();
729      break;
730    // FIXME: The following are added to allow parsing.
731    // I just took a guess at what the actions should be.
732    // Also, is more specific checking needed?  I.e. specific registers?
733    case 'd': // Floating point register (containing 64-bit value)
734    case 'v': // Altivec vector register
735      Info.setAllowsRegister();
736      break;
737    case 'w':
738      switch (Name[1]) {
739        case 'd':// VSX vector register to hold vector double data
740        case 'f':// VSX vector register to hold vector float data
741        case 's':// VSX vector register to hold scalar float data
742        case 'a':// Any VSX register
743          break;
744        default:
745          return false;
746      }
747      Info.setAllowsRegister();
748      Name++; // Skip over 'w'.
749      break;
750    case 'h': // `MQ', `CTR', or `LINK' register
751    case 'q': // `MQ' register
752    case 'c': // `CTR' register
753    case 'l': // `LINK' register
754    case 'x': // `CR' register (condition register) number 0
755    case 'y': // `CR' register (condition register)
756    case 'z': // `XER[CA]' carry bit (part of the XER register)
757      Info.setAllowsRegister();
758      break;
759    case 'I': // Signed 16-bit constant
760    case 'J': // Unsigned 16-bit constant shifted left 16 bits
761              //  (use `L' instead for SImode constants)
762    case 'K': // Unsigned 16-bit constant
763    case 'L': // Signed 16-bit constant shifted left 16 bits
764    case 'M': // Constant larger than 31
765    case 'N': // Exact power of 2
766    case 'P': // Constant whose negation is a signed 16-bit constant
767    case 'G': // Floating point constant that can be loaded into a
768              // register with one instruction per word
769    case 'H': // Integer/Floating point constant that can be loaded
770              // into a register using three instructions
771      break;
772    case 'm': // Memory operand. Note that on PowerPC targets, m can
773              // include addresses that update the base register. It
774              // is therefore only safe to use `m' in an asm statement
775              // if that asm statement accesses the operand exactly once.
776              // The asm statement must also use `%U<opno>' as a
777              // placeholder for the "update" flag in the corresponding
778              // load or store instruction. For example:
779              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
780              // is correct but:
781              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
782              // is not. Use es rather than m if you don't want the base
783              // register to be updated.
784    case 'e':
785      if (Name[1] != 's')
786          return false;
787              // es: A "stable" memory operand; that is, one which does not
788              // include any automodification of the base register. Unlike
789              // `m', this constraint can be used in asm statements that
790              // might access the operand several times, or that might not
791              // access it at all.
792      Info.setAllowsMemory();
793      Name++; // Skip over 'e'.
794      break;
795    case 'Q': // Memory operand that is an offset from a register (it is
796              // usually better to use `m' or `es' in asm statements)
797    case 'Z': // Memory operand that is an indexed or indirect from a
798              // register (it is usually better to use `m' or `es' in
799              // asm statements)
800      Info.setAllowsMemory();
801      Info.setAllowsRegister();
802      break;
803    case 'R': // AIX TOC entry
804    case 'a': // Address operand that is an indexed or indirect from a
805              // register (`p' is preferable for asm statements)
806    case 'S': // Constant suitable as a 64-bit mask operand
807    case 'T': // Constant suitable as a 32-bit mask operand
808    case 'U': // System V Release 4 small data area reference
809    case 't': // AND masks that can be performed by two rldic{l, r}
810              // instructions
811    case 'W': // Vector constant that does not require memory
812    case 'j': // Vector constant that is all zeros.
813      break;
814    // End FIXME.
815    }
816    return true;
817  }
818  virtual const char *getClobbers() const {
819    return "";
820  }
821};
822
823const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
824#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
825#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
826                                              ALL_LANGUAGES },
827#include "clang/Basic/BuiltinsPPC.def"
828};
829
830
831/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
832/// #defines that are not tied to a specific subtarget.
833void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
834                                     MacroBuilder &Builder) const {
835  // Target identification.
836  Builder.defineMacro("__ppc__");
837  Builder.defineMacro("_ARCH_PPC");
838  Builder.defineMacro("__powerpc__");
839  Builder.defineMacro("__POWERPC__");
840  if (PointerWidth == 64) {
841    Builder.defineMacro("_ARCH_PPC64");
842    Builder.defineMacro("__powerpc64__");
843    Builder.defineMacro("__ppc64__");
844  } else {
845    Builder.defineMacro("__ppc__");
846  }
847
848  // Target properties.
849  if (getTriple().getOS() != llvm::Triple::NetBSD &&
850      getTriple().getOS() != llvm::Triple::OpenBSD)
851    Builder.defineMacro("_BIG_ENDIAN");
852  Builder.defineMacro("__BIG_ENDIAN__");
853
854  // Subtarget options.
855  Builder.defineMacro("__NATURAL_ALIGNMENT__");
856  Builder.defineMacro("__REGISTER_PREFIX__", "");
857
858  // FIXME: Should be controlled by command line option.
859  Builder.defineMacro("__LONG_DOUBLE_128__");
860
861  if (Opts.AltiVec) {
862    Builder.defineMacro("__VEC__", "10206");
863    Builder.defineMacro("__ALTIVEC__");
864  }
865
866  // CPU identification.
867  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
868    .Case("440",   ArchDefineName)
869    .Case("450",   ArchDefineName | ArchDefine440)
870    .Case("601",   ArchDefineName)
871    .Case("602",   ArchDefineName | ArchDefinePpcgr)
872    .Case("603",   ArchDefineName | ArchDefinePpcgr)
873    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
874    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
875    .Case("604",   ArchDefineName | ArchDefinePpcgr)
876    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
877    .Case("620",   ArchDefineName | ArchDefinePpcgr)
878    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
879    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
880    .Case("750",   ArchDefineName | ArchDefinePpcgr)
881    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
882                     | ArchDefinePpcsq)
883    .Case("pwr6",  ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
884    .Case("pwr7",  ArchDefineName | ArchDefinePwr6 | ArchDefinePpcgr
885                     | ArchDefinePpcsq)
886    .Default(ArchDefineNone);
887
888  if (defs & ArchDefineName)
889    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
890  if (defs & ArchDefinePpcgr)
891    Builder.defineMacro("_ARCH_PPCGR");
892  if (defs & ArchDefinePpcsq)
893    Builder.defineMacro("_ARCH_PPCSQ");
894  if (defs & ArchDefine440)
895    Builder.defineMacro("_ARCH_440");
896  if (defs & ArchDefine603)
897    Builder.defineMacro("_ARCH_603");
898  if (defs & ArchDefine604)
899    Builder.defineMacro("_ARCH_604");
900  if (defs & (ArchDefinePwr4 | ArchDefinePwr6))
901    Builder.defineMacro("_ARCH_PWR4");
902  if (defs & ArchDefinePwr6) {
903    Builder.defineMacro("_ARCH_PWR5");
904    Builder.defineMacro("_ARCH_PWR6");
905  }
906}
907
908bool PPCTargetInfo::hasFeature(StringRef Feature) const {
909  return Feature == "powerpc";
910}
911
912
913const char * const PPCTargetInfo::GCCRegNames[] = {
914  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
915  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
916  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
917  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
918  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
919  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
920  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
921  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
922  "mq", "lr", "ctr", "ap",
923  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
924  "xer",
925  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
926  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
927  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
928  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
929  "vrsave", "vscr",
930  "spe_acc", "spefscr",
931  "sfp"
932};
933
934void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
935                                   unsigned &NumNames) const {
936  Names = GCCRegNames;
937  NumNames = llvm::array_lengthof(GCCRegNames);
938}
939
940const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
941  // While some of these aliases do map to different registers
942  // they still share the same register name.
943  { { "0" }, "r0" },
944  { { "1"}, "r1" },
945  { { "2" }, "r2" },
946  { { "3" }, "r3" },
947  { { "4" }, "r4" },
948  { { "5" }, "r5" },
949  { { "6" }, "r6" },
950  { { "7" }, "r7" },
951  { { "8" }, "r8" },
952  { { "9" }, "r9" },
953  { { "10" }, "r10" },
954  { { "11" }, "r11" },
955  { { "12" }, "r12" },
956  { { "13" }, "r13" },
957  { { "14" }, "r14" },
958  { { "15" }, "r15" },
959  { { "16" }, "r16" },
960  { { "17" }, "r17" },
961  { { "18" }, "r18" },
962  { { "19" }, "r19" },
963  { { "20" }, "r20" },
964  { { "21" }, "r21" },
965  { { "22" }, "r22" },
966  { { "23" }, "r23" },
967  { { "24" }, "r24" },
968  { { "25" }, "r25" },
969  { { "26" }, "r26" },
970  { { "27" }, "r27" },
971  { { "28" }, "r28" },
972  { { "29" }, "r29" },
973  { { "30" }, "r30" },
974  { { "31" }, "r31" },
975  { { "fr0" }, "f0" },
976  { { "fr1" }, "f1" },
977  { { "fr2" }, "f2" },
978  { { "fr3" }, "f3" },
979  { { "fr4" }, "f4" },
980  { { "fr5" }, "f5" },
981  { { "fr6" }, "f6" },
982  { { "fr7" }, "f7" },
983  { { "fr8" }, "f8" },
984  { { "fr9" }, "f9" },
985  { { "fr10" }, "f10" },
986  { { "fr11" }, "f11" },
987  { { "fr12" }, "f12" },
988  { { "fr13" }, "f13" },
989  { { "fr14" }, "f14" },
990  { { "fr15" }, "f15" },
991  { { "fr16" }, "f16" },
992  { { "fr17" }, "f17" },
993  { { "fr18" }, "f18" },
994  { { "fr19" }, "f19" },
995  { { "fr20" }, "f20" },
996  { { "fr21" }, "f21" },
997  { { "fr22" }, "f22" },
998  { { "fr23" }, "f23" },
999  { { "fr24" }, "f24" },
1000  { { "fr25" }, "f25" },
1001  { { "fr26" }, "f26" },
1002  { { "fr27" }, "f27" },
1003  { { "fr28" }, "f28" },
1004  { { "fr29" }, "f29" },
1005  { { "fr30" }, "f30" },
1006  { { "fr31" }, "f31" },
1007  { { "cc" }, "cr0" },
1008};
1009
1010void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1011                                     unsigned &NumAliases) const {
1012  Aliases = GCCRegAliases;
1013  NumAliases = llvm::array_lengthof(GCCRegAliases);
1014}
1015} // end anonymous namespace.
1016
1017namespace {
1018class PPC32TargetInfo : public PPCTargetInfo {
1019public:
1020  PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1021    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1022                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1023
1024    switch (getTriple().getOS()) {
1025    case llvm::Triple::Linux:
1026    case llvm::Triple::FreeBSD:
1027    case llvm::Triple::NetBSD:
1028      SizeType = UnsignedInt;
1029      PtrDiffType = SignedInt;
1030      IntPtrType = SignedInt;
1031      break;
1032    default:
1033      break;
1034    }
1035
1036    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1037      LongDoubleWidth = LongDoubleAlign = 64;
1038      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1039    }
1040  }
1041
1042  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1043    // This is the ELF definition, and is overridden by the Darwin sub-target
1044    return TargetInfo::PowerABIBuiltinVaList;
1045  }
1046};
1047} // end anonymous namespace.
1048
1049namespace {
1050class PPC64TargetInfo : public PPCTargetInfo {
1051public:
1052  PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1053    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1054    IntMaxType = SignedLong;
1055    UIntMaxType = UnsignedLong;
1056    Int64Type = SignedLong;
1057
1058    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1059      LongDoubleWidth = LongDoubleAlign = 64;
1060      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1061      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1062                          "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1063                          "v128:128:128-n32:64";
1064    } else
1065      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1066                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1067                          "v128:128:128-n32:64";
1068
1069  }
1070  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1071    return TargetInfo::CharPtrBuiltinVaList;
1072  }
1073};
1074} // end anonymous namespace.
1075
1076
1077namespace {
1078class DarwinPPC32TargetInfo :
1079  public DarwinTargetInfo<PPC32TargetInfo> {
1080public:
1081  DarwinPPC32TargetInfo(const std::string& triple)
1082    : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1083    HasAlignMac68kSupport = true;
1084    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1085    LongLongAlign = 32;
1086    SuitableAlign = 128;
1087    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1088                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1089  }
1090  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1091    return TargetInfo::CharPtrBuiltinVaList;
1092  }
1093};
1094
1095class DarwinPPC64TargetInfo :
1096  public DarwinTargetInfo<PPC64TargetInfo> {
1097public:
1098  DarwinPPC64TargetInfo(const std::string& triple)
1099    : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1100    HasAlignMac68kSupport = true;
1101    SuitableAlign = 128;
1102    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1103                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1104  }
1105};
1106} // end anonymous namespace.
1107
1108namespace {
1109  static const unsigned NVPTXAddrSpaceMap[] = {
1110    1,    // opencl_global
1111    3,    // opencl_local
1112    4,    // opencl_constant
1113    1,    // cuda_device
1114    4,    // cuda_constant
1115    3,    // cuda_shared
1116  };
1117  class NVPTXTargetInfo : public TargetInfo {
1118    static const char * const GCCRegNames[];
1119    static const Builtin::Info BuiltinInfo[];
1120    std::vector<llvm::StringRef> AvailableFeatures;
1121  public:
1122    NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1123      BigEndian = false;
1124      TLSSupported = false;
1125      LongWidth = LongAlign = 64;
1126      AddrSpaceMap = &NVPTXAddrSpaceMap;
1127      // Define available target features
1128      // These must be defined in sorted order!
1129      NoAsmVariants = true;
1130    }
1131    virtual void getTargetDefines(const LangOptions &Opts,
1132                                  MacroBuilder &Builder) const {
1133      Builder.defineMacro("__PTX__");
1134      Builder.defineMacro("__NVPTX__");
1135    }
1136    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1137                                   unsigned &NumRecords) const {
1138      Records = BuiltinInfo;
1139      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1140    }
1141    virtual bool hasFeature(StringRef Feature) const {
1142      return Feature == "ptx" || Feature == "nvptx";
1143    }
1144
1145    virtual void getGCCRegNames(const char * const *&Names,
1146                                unsigned &NumNames) const;
1147    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1148                                  unsigned &NumAliases) const {
1149      // No aliases.
1150      Aliases = 0;
1151      NumAliases = 0;
1152    }
1153    virtual bool validateAsmConstraint(const char *&Name,
1154                                       TargetInfo::ConstraintInfo &info) const {
1155      // FIXME: implement
1156      return true;
1157    }
1158    virtual const char *getClobbers() const {
1159      // FIXME: Is this really right?
1160      return "";
1161    }
1162    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1163      // FIXME: implement
1164      return TargetInfo::CharPtrBuiltinVaList;
1165    }
1166    virtual bool setCPU(const std::string &Name) {
1167      return Name == "sm_10" || Name == "sm_13" || Name == "sm_20";
1168    }
1169    virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1170                                   StringRef Name,
1171                                   bool Enabled) const;
1172  };
1173
1174  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1175#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1176#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1177                                              ALL_LANGUAGES },
1178#include "clang/Basic/BuiltinsNVPTX.def"
1179  };
1180
1181  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1182    "r0"
1183  };
1184
1185  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1186                                     unsigned &NumNames) const {
1187    Names = GCCRegNames;
1188    NumNames = llvm::array_lengthof(GCCRegNames);
1189  }
1190
1191  bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1192                                          StringRef Name,
1193                                          bool Enabled) const {
1194    if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1195                          Name)) {
1196      Features[Name] = Enabled;
1197      return true;
1198    } else {
1199      return false;
1200    }
1201  }
1202
1203  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1204  public:
1205    NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1206      PointerWidth = PointerAlign = 32;
1207      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1208      DescriptionString
1209        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1210          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1211          "n16:32:64";
1212  }
1213  };
1214
1215  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1216  public:
1217    NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1218      PointerWidth = PointerAlign = 64;
1219      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1220      DescriptionString
1221        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1222          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1223          "n16:32:64";
1224  }
1225  };
1226}
1227
1228namespace {
1229
1230static const unsigned R600AddrSpaceMap[] = {
1231  1,    // opencl_global
1232  3,    // opencl_local
1233  2,    // opencl_constant
1234  1,    // cuda_device
1235  2,    // cuda_constant
1236  3     // cuda_shared
1237};
1238
1239class R600TargetInfo : public TargetInfo {
1240public:
1241  R600TargetInfo(const std::string& triple) : TargetInfo(triple) {
1242    DescriptionString =
1243          "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16"
1244          "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"
1245          "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"
1246          "-v96:128:128-v128:128:128-v192:256:256-v256:256:256"
1247          "-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1248          "-n8:16:32:64";
1249    AddrSpaceMap = &R600AddrSpaceMap;
1250  }
1251
1252  virtual const char * getClobbers() const {
1253    return "";
1254  }
1255
1256  virtual void getGCCRegNames(const char * const *&Names,
1257                              unsigned &numNames) const  {
1258    Names = NULL;
1259    numNames = 0;
1260  }
1261
1262  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1263                                unsigned &NumAliases) const {
1264    Aliases = NULL;
1265    NumAliases = 0;
1266  }
1267
1268  virtual bool validateAsmConstraint(const char *&Name,
1269                                     TargetInfo::ConstraintInfo &info) const {
1270    return true;
1271  }
1272
1273  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1274                                 unsigned &NumRecords) const {
1275    Records = NULL;
1276    NumRecords = 0;
1277  }
1278
1279
1280  virtual void getTargetDefines(const LangOptions &Opts,
1281                                MacroBuilder &Builder) const {
1282    Builder.defineMacro("__R600__");
1283  }
1284
1285  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1286    return TargetInfo::CharPtrBuiltinVaList;
1287  }
1288
1289};
1290
1291} // end anonymous namespace
1292
1293namespace {
1294// MBlaze abstract base class
1295class MBlazeTargetInfo : public TargetInfo {
1296  static const char * const GCCRegNames[];
1297  static const TargetInfo::GCCRegAlias GCCRegAliases[];
1298
1299public:
1300  MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1301    DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1302  }
1303
1304  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1305                                 unsigned &NumRecords) const {
1306    // FIXME: Implement.
1307    Records = 0;
1308    NumRecords = 0;
1309  }
1310
1311  virtual void getTargetDefines(const LangOptions &Opts,
1312                                MacroBuilder &Builder) const;
1313
1314  virtual bool hasFeature(StringRef Feature) const {
1315    return Feature == "mblaze";
1316  }
1317
1318  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1319    return TargetInfo::CharPtrBuiltinVaList;
1320  }
1321  virtual const char *getTargetPrefix() const {
1322    return "mblaze";
1323  }
1324  virtual void getGCCRegNames(const char * const *&Names,
1325                              unsigned &NumNames) const;
1326  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1327                                unsigned &NumAliases) const;
1328  virtual bool validateAsmConstraint(const char *&Name,
1329                                     TargetInfo::ConstraintInfo &Info) const {
1330    switch (*Name) {
1331    default: return false;
1332    case 'O': // Zero
1333      return true;
1334    case 'b': // Base register
1335    case 'f': // Floating point register
1336      Info.setAllowsRegister();
1337      return true;
1338    }
1339  }
1340  virtual const char *getClobbers() const {
1341    return "";
1342  }
1343};
1344
1345/// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1346/// #defines that are not tied to a specific subtarget.
1347void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1348                                     MacroBuilder &Builder) const {
1349  // Target identification.
1350  Builder.defineMacro("__microblaze__");
1351  Builder.defineMacro("_ARCH_MICROBLAZE");
1352  Builder.defineMacro("__MICROBLAZE__");
1353
1354  // Target properties.
1355  Builder.defineMacro("_BIG_ENDIAN");
1356  Builder.defineMacro("__BIG_ENDIAN__");
1357
1358  // Subtarget options.
1359  Builder.defineMacro("__REGISTER_PREFIX__", "");
1360}
1361
1362
1363const char * const MBlazeTargetInfo::GCCRegNames[] = {
1364  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1365  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1366  "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1367  "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1368  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1369  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1370  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1371  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1372  "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1373  "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1374};
1375
1376void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1377                                   unsigned &NumNames) const {
1378  Names = GCCRegNames;
1379  NumNames = llvm::array_lengthof(GCCRegNames);
1380}
1381
1382const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1383  { {"f0"},  "r0" },
1384  { {"f1"},  "r1" },
1385  { {"f2"},  "r2" },
1386  { {"f3"},  "r3" },
1387  { {"f4"},  "r4" },
1388  { {"f5"},  "r5" },
1389  { {"f6"},  "r6" },
1390  { {"f7"},  "r7" },
1391  { {"f8"},  "r8" },
1392  { {"f9"},  "r9" },
1393  { {"f10"}, "r10" },
1394  { {"f11"}, "r11" },
1395  { {"f12"}, "r12" },
1396  { {"f13"}, "r13" },
1397  { {"f14"}, "r14" },
1398  { {"f15"}, "r15" },
1399  { {"f16"}, "r16" },
1400  { {"f17"}, "r17" },
1401  { {"f18"}, "r18" },
1402  { {"f19"}, "r19" },
1403  { {"f20"}, "r20" },
1404  { {"f21"}, "r21" },
1405  { {"f22"}, "r22" },
1406  { {"f23"}, "r23" },
1407  { {"f24"}, "r24" },
1408  { {"f25"}, "r25" },
1409  { {"f26"}, "r26" },
1410  { {"f27"}, "r27" },
1411  { {"f28"}, "r28" },
1412  { {"f29"}, "r29" },
1413  { {"f30"}, "r30" },
1414  { {"f31"}, "r31" },
1415};
1416
1417void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1418                                     unsigned &NumAliases) const {
1419  Aliases = GCCRegAliases;
1420  NumAliases = llvm::array_lengthof(GCCRegAliases);
1421}
1422} // end anonymous namespace.
1423
1424namespace {
1425// Namespace for x86 abstract base class
1426const Builtin::Info BuiltinInfo[] = {
1427#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1428#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1429                                              ALL_LANGUAGES },
1430#include "clang/Basic/BuiltinsX86.def"
1431};
1432
1433static const char* const GCCRegNames[] = {
1434  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1435  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1436  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1437  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1438  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1439  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1440  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1441  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1442  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1443};
1444
1445const TargetInfo::AddlRegName AddlRegNames[] = {
1446  { { "al", "ah", "eax", "rax" }, 0 },
1447  { { "bl", "bh", "ebx", "rbx" }, 3 },
1448  { { "cl", "ch", "ecx", "rcx" }, 2 },
1449  { { "dl", "dh", "edx", "rdx" }, 1 },
1450  { { "esi", "rsi" }, 4 },
1451  { { "edi", "rdi" }, 5 },
1452  { { "esp", "rsp" }, 7 },
1453  { { "ebp", "rbp" }, 6 },
1454};
1455
1456// X86 target abstract base class; x86-32 and x86-64 are very close, so
1457// most of the implementation can be shared.
1458class X86TargetInfo : public TargetInfo {
1459  enum X86SSEEnum {
1460    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1461  } SSELevel;
1462  enum MMX3DNowEnum {
1463    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1464  } MMX3DNowLevel;
1465
1466  bool HasAES;
1467  bool HasPCLMUL;
1468  bool HasLZCNT;
1469  bool HasRDRND;
1470  bool HasBMI;
1471  bool HasBMI2;
1472  bool HasPOPCNT;
1473  bool HasRTM;
1474  bool HasSSE4a;
1475  bool HasFMA4;
1476  bool HasFMA;
1477  bool HasXOP;
1478  bool HasF16C;
1479
1480  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1481  ///
1482  /// Each enumeration represents a particular CPU supported by Clang. These
1483  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1484  enum CPUKind {
1485    CK_Generic,
1486
1487    /// \name i386
1488    /// i386-generation processors.
1489    //@{
1490    CK_i386,
1491    //@}
1492
1493    /// \name i486
1494    /// i486-generation processors.
1495    //@{
1496    CK_i486,
1497    CK_WinChipC6,
1498    CK_WinChip2,
1499    CK_C3,
1500    //@}
1501
1502    /// \name i586
1503    /// i586-generation processors, P5 microarchitecture based.
1504    //@{
1505    CK_i586,
1506    CK_Pentium,
1507    CK_PentiumMMX,
1508    //@}
1509
1510    /// \name i686
1511    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1512    //@{
1513    CK_i686,
1514    CK_PentiumPro,
1515    CK_Pentium2,
1516    CK_Pentium3,
1517    CK_Pentium3M,
1518    CK_PentiumM,
1519    CK_C3_2,
1520
1521    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1522    /// Clang however has some logic to suport this.
1523    // FIXME: Warn, deprecate, and potentially remove this.
1524    CK_Yonah,
1525    //@}
1526
1527    /// \name Netburst
1528    /// Netburst microarchitecture based processors.
1529    //@{
1530    CK_Pentium4,
1531    CK_Pentium4M,
1532    CK_Prescott,
1533    CK_Nocona,
1534    //@}
1535
1536    /// \name Core
1537    /// Core microarchitecture based processors.
1538    //@{
1539    CK_Core2,
1540
1541    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1542    /// codename which GCC no longer accepts as an option to -march, but Clang
1543    /// has some logic for recognizing it.
1544    // FIXME: Warn, deprecate, and potentially remove this.
1545    CK_Penryn,
1546    //@}
1547
1548    /// \name Atom
1549    /// Atom processors
1550    //@{
1551    CK_Atom,
1552    //@}
1553
1554    /// \name Nehalem
1555    /// Nehalem microarchitecture based processors.
1556    //@{
1557    CK_Corei7,
1558    CK_Corei7AVX,
1559    CK_CoreAVXi,
1560    CK_CoreAVX2,
1561    //@}
1562
1563    /// \name K6
1564    /// K6 architecture processors.
1565    //@{
1566    CK_K6,
1567    CK_K6_2,
1568    CK_K6_3,
1569    //@}
1570
1571    /// \name K7
1572    /// K7 architecture processors.
1573    //@{
1574    CK_Athlon,
1575    CK_AthlonThunderbird,
1576    CK_Athlon4,
1577    CK_AthlonXP,
1578    CK_AthlonMP,
1579    //@}
1580
1581    /// \name K8
1582    /// K8 architecture processors.
1583    //@{
1584    CK_Athlon64,
1585    CK_Athlon64SSE3,
1586    CK_AthlonFX,
1587    CK_K8,
1588    CK_K8SSE3,
1589    CK_Opteron,
1590    CK_OpteronSSE3,
1591    CK_AMDFAM10,
1592    //@}
1593
1594    /// \name Bobcat
1595    /// Bobcat architecture processors.
1596    //@{
1597    CK_BTVER1,
1598    //@}
1599
1600    /// \name Bulldozer
1601    /// Bulldozer architecture processors.
1602    //@{
1603    CK_BDVER1,
1604    CK_BDVER2,
1605    //@}
1606
1607    /// This specification is deprecated and will be removed in the future.
1608    /// Users should prefer \see CK_K8.
1609    // FIXME: Warn on this when the CPU is set to it.
1610    CK_x86_64,
1611    //@}
1612
1613    /// \name Geode
1614    /// Geode processors.
1615    //@{
1616    CK_Geode
1617    //@}
1618  } CPU;
1619
1620public:
1621  X86TargetInfo(const std::string& triple)
1622    : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1623      HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1624      HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1625      HasSSE4a(false), HasFMA4(false), HasFMA(false), HasXOP(false),
1626      HasF16C(false), CPU(CK_Generic) {
1627    BigEndian = false;
1628    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1629  }
1630  virtual unsigned getFloatEvalMethod() const {
1631    // X87 evaluates with 80 bits "long double" precision.
1632    return SSELevel == NoSSE ? 2 : 0;
1633  }
1634  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1635                                 unsigned &NumRecords) const {
1636    Records = BuiltinInfo;
1637    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1638  }
1639  virtual void getGCCRegNames(const char * const *&Names,
1640                              unsigned &NumNames) const {
1641    Names = GCCRegNames;
1642    NumNames = llvm::array_lengthof(GCCRegNames);
1643  }
1644  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1645                                unsigned &NumAliases) const {
1646    Aliases = 0;
1647    NumAliases = 0;
1648  }
1649  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1650                                  unsigned &NumNames) const {
1651    Names = AddlRegNames;
1652    NumNames = llvm::array_lengthof(AddlRegNames);
1653  }
1654  virtual bool validateAsmConstraint(const char *&Name,
1655                                     TargetInfo::ConstraintInfo &info) const;
1656  virtual std::string convertConstraint(const char *&Constraint) const;
1657  virtual const char *getClobbers() const {
1658    return "~{dirflag},~{fpsr},~{flags}";
1659  }
1660  virtual void getTargetDefines(const LangOptions &Opts,
1661                                MacroBuilder &Builder) const;
1662  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1663                                 StringRef Name,
1664                                 bool Enabled) const;
1665  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1666  virtual bool hasFeature(StringRef Feature) const;
1667  virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1668  virtual const char* getABI() const {
1669    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1670      return "avx";
1671    else if (getTriple().getArch() == llvm::Triple::x86 &&
1672             MMX3DNowLevel == NoMMX3DNow)
1673      return "no-mmx";
1674    return "";
1675  }
1676  virtual bool setCPU(const std::string &Name) {
1677    CPU = llvm::StringSwitch<CPUKind>(Name)
1678      .Case("i386", CK_i386)
1679      .Case("i486", CK_i486)
1680      .Case("winchip-c6", CK_WinChipC6)
1681      .Case("winchip2", CK_WinChip2)
1682      .Case("c3", CK_C3)
1683      .Case("i586", CK_i586)
1684      .Case("pentium", CK_Pentium)
1685      .Case("pentium-mmx", CK_PentiumMMX)
1686      .Case("i686", CK_i686)
1687      .Case("pentiumpro", CK_PentiumPro)
1688      .Case("pentium2", CK_Pentium2)
1689      .Case("pentium3", CK_Pentium3)
1690      .Case("pentium3m", CK_Pentium3M)
1691      .Case("pentium-m", CK_PentiumM)
1692      .Case("c3-2", CK_C3_2)
1693      .Case("yonah", CK_Yonah)
1694      .Case("pentium4", CK_Pentium4)
1695      .Case("pentium4m", CK_Pentium4M)
1696      .Case("prescott", CK_Prescott)
1697      .Case("nocona", CK_Nocona)
1698      .Case("core2", CK_Core2)
1699      .Case("penryn", CK_Penryn)
1700      .Case("atom", CK_Atom)
1701      .Case("corei7", CK_Corei7)
1702      .Case("corei7-avx", CK_Corei7AVX)
1703      .Case("core-avx-i", CK_CoreAVXi)
1704      .Case("core-avx2", CK_CoreAVX2)
1705      .Case("k6", CK_K6)
1706      .Case("k6-2", CK_K6_2)
1707      .Case("k6-3", CK_K6_3)
1708      .Case("athlon", CK_Athlon)
1709      .Case("athlon-tbird", CK_AthlonThunderbird)
1710      .Case("athlon-4", CK_Athlon4)
1711      .Case("athlon-xp", CK_AthlonXP)
1712      .Case("athlon-mp", CK_AthlonMP)
1713      .Case("athlon64", CK_Athlon64)
1714      .Case("athlon64-sse3", CK_Athlon64SSE3)
1715      .Case("athlon-fx", CK_AthlonFX)
1716      .Case("k8", CK_K8)
1717      .Case("k8-sse3", CK_K8SSE3)
1718      .Case("opteron", CK_Opteron)
1719      .Case("opteron-sse3", CK_OpteronSSE3)
1720      .Case("amdfam10", CK_AMDFAM10)
1721      .Case("btver1", CK_BTVER1)
1722      .Case("bdver1", CK_BDVER1)
1723      .Case("bdver2", CK_BDVER2)
1724      .Case("x86-64", CK_x86_64)
1725      .Case("geode", CK_Geode)
1726      .Default(CK_Generic);
1727
1728    // Perform any per-CPU checks necessary to determine if this CPU is
1729    // acceptable.
1730    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1731    // invalid without explaining *why*.
1732    switch (CPU) {
1733    case CK_Generic:
1734      // No processor selected!
1735      return false;
1736
1737    case CK_i386:
1738    case CK_i486:
1739    case CK_WinChipC6:
1740    case CK_WinChip2:
1741    case CK_C3:
1742    case CK_i586:
1743    case CK_Pentium:
1744    case CK_PentiumMMX:
1745    case CK_i686:
1746    case CK_PentiumPro:
1747    case CK_Pentium2:
1748    case CK_Pentium3:
1749    case CK_Pentium3M:
1750    case CK_PentiumM:
1751    case CK_Yonah:
1752    case CK_C3_2:
1753    case CK_Pentium4:
1754    case CK_Pentium4M:
1755    case CK_Prescott:
1756    case CK_K6:
1757    case CK_K6_2:
1758    case CK_K6_3:
1759    case CK_Athlon:
1760    case CK_AthlonThunderbird:
1761    case CK_Athlon4:
1762    case CK_AthlonXP:
1763    case CK_AthlonMP:
1764    case CK_Geode:
1765      // Only accept certain architectures when compiling in 32-bit mode.
1766      if (getTriple().getArch() != llvm::Triple::x86)
1767        return false;
1768
1769      // Fallthrough
1770    case CK_Nocona:
1771    case CK_Core2:
1772    case CK_Penryn:
1773    case CK_Atom:
1774    case CK_Corei7:
1775    case CK_Corei7AVX:
1776    case CK_CoreAVXi:
1777    case CK_CoreAVX2:
1778    case CK_Athlon64:
1779    case CK_Athlon64SSE3:
1780    case CK_AthlonFX:
1781    case CK_K8:
1782    case CK_K8SSE3:
1783    case CK_Opteron:
1784    case CK_OpteronSSE3:
1785    case CK_AMDFAM10:
1786    case CK_BTVER1:
1787    case CK_BDVER1:
1788    case CK_BDVER2:
1789    case CK_x86_64:
1790      return true;
1791    }
1792    llvm_unreachable("Unhandled CPU kind");
1793  }
1794
1795  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
1796    // We accept all non-ARM calling conventions
1797    return (CC == CC_X86ThisCall ||
1798            CC == CC_X86FastCall ||
1799            CC == CC_X86StdCall ||
1800            CC == CC_C ||
1801            CC == CC_X86Pascal) ? CCCR_OK : CCCR_Warning;
1802  }
1803
1804  virtual CallingConv getDefaultCallingConv() const {
1805    return CC_C;
1806  }
1807};
1808
1809void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1810  // FIXME: This should not be here.
1811  Features["3dnow"] = false;
1812  Features["3dnowa"] = false;
1813  Features["mmx"] = false;
1814  Features["sse"] = false;
1815  Features["sse2"] = false;
1816  Features["sse3"] = false;
1817  Features["ssse3"] = false;
1818  Features["sse41"] = false;
1819  Features["sse42"] = false;
1820  Features["sse4a"] = false;
1821  Features["aes"] = false;
1822  Features["pclmul"] = false;
1823  Features["avx"] = false;
1824  Features["avx2"] = false;
1825  Features["lzcnt"] = false;
1826  Features["rdrand"] = false;
1827  Features["bmi"] = false;
1828  Features["bmi2"] = false;
1829  Features["popcnt"] = false;
1830  Features["rtm"] = false;
1831  Features["fma4"] = false;
1832  Features["fma"] = false;
1833  Features["xop"] = false;
1834  Features["f16c"] = false;
1835
1836  // FIXME: This *really* should not be here.
1837
1838  // X86_64 always has SSE2.
1839  if (getTriple().getArch() == llvm::Triple::x86_64)
1840    setFeatureEnabled(Features, "sse2", true);
1841
1842  switch (CPU) {
1843  case CK_Generic:
1844  case CK_i386:
1845  case CK_i486:
1846  case CK_i586:
1847  case CK_Pentium:
1848  case CK_i686:
1849  case CK_PentiumPro:
1850    break;
1851  case CK_PentiumMMX:
1852  case CK_Pentium2:
1853    setFeatureEnabled(Features, "mmx", true);
1854    break;
1855  case CK_Pentium3:
1856  case CK_Pentium3M:
1857    setFeatureEnabled(Features, "sse", true);
1858    break;
1859  case CK_PentiumM:
1860  case CK_Pentium4:
1861  case CK_Pentium4M:
1862  case CK_x86_64:
1863    setFeatureEnabled(Features, "sse2", true);
1864    break;
1865  case CK_Yonah:
1866  case CK_Prescott:
1867  case CK_Nocona:
1868    setFeatureEnabled(Features, "sse3", true);
1869    break;
1870  case CK_Core2:
1871    setFeatureEnabled(Features, "ssse3", true);
1872    break;
1873  case CK_Penryn:
1874    setFeatureEnabled(Features, "sse4.1", true);
1875    break;
1876  case CK_Atom:
1877    setFeatureEnabled(Features, "ssse3", true);
1878    break;
1879  case CK_Corei7:
1880    setFeatureEnabled(Features, "sse4", true);
1881    break;
1882  case CK_Corei7AVX:
1883    setFeatureEnabled(Features, "avx", true);
1884    setFeatureEnabled(Features, "aes", true);
1885    setFeatureEnabled(Features, "pclmul", true);
1886    break;
1887  case CK_CoreAVXi:
1888    setFeatureEnabled(Features, "avx", true);
1889    setFeatureEnabled(Features, "aes", true);
1890    setFeatureEnabled(Features, "pclmul", true);
1891    setFeatureEnabled(Features, "rdrnd", true);
1892    break;
1893  case CK_CoreAVX2:
1894    setFeatureEnabled(Features, "avx2", true);
1895    setFeatureEnabled(Features, "aes", true);
1896    setFeatureEnabled(Features, "pclmul", true);
1897    setFeatureEnabled(Features, "lzcnt", true);
1898    setFeatureEnabled(Features, "rdrnd", true);
1899    setFeatureEnabled(Features, "bmi", true);
1900    setFeatureEnabled(Features, "bmi2", true);
1901    setFeatureEnabled(Features, "rtm", true);
1902    setFeatureEnabled(Features, "fma", true);
1903    break;
1904  case CK_K6:
1905  case CK_WinChipC6:
1906    setFeatureEnabled(Features, "mmx", true);
1907    break;
1908  case CK_K6_2:
1909  case CK_K6_3:
1910  case CK_WinChip2:
1911  case CK_C3:
1912    setFeatureEnabled(Features, "3dnow", true);
1913    break;
1914  case CK_Athlon:
1915  case CK_AthlonThunderbird:
1916  case CK_Geode:
1917    setFeatureEnabled(Features, "3dnowa", true);
1918    break;
1919  case CK_Athlon4:
1920  case CK_AthlonXP:
1921  case CK_AthlonMP:
1922    setFeatureEnabled(Features, "sse", true);
1923    setFeatureEnabled(Features, "3dnowa", true);
1924    break;
1925  case CK_K8:
1926  case CK_Opteron:
1927  case CK_Athlon64:
1928  case CK_AthlonFX:
1929    setFeatureEnabled(Features, "sse2", true);
1930    setFeatureEnabled(Features, "3dnowa", true);
1931    break;
1932  case CK_K8SSE3:
1933  case CK_OpteronSSE3:
1934  case CK_Athlon64SSE3:
1935    setFeatureEnabled(Features, "sse3", true);
1936    setFeatureEnabled(Features, "3dnowa", true);
1937    break;
1938  case CK_AMDFAM10:
1939    setFeatureEnabled(Features, "sse3", true);
1940    setFeatureEnabled(Features, "sse4a", true);
1941    setFeatureEnabled(Features, "3dnowa", true);
1942    break;
1943  case CK_BTVER1:
1944    setFeatureEnabled(Features, "ssse3", true);
1945    setFeatureEnabled(Features, "sse4a", true);
1946    break;
1947  case CK_BDVER1:
1948  case CK_BDVER2:
1949    setFeatureEnabled(Features, "avx", true);
1950    setFeatureEnabled(Features, "xop", true);
1951    setFeatureEnabled(Features, "aes", true);
1952    setFeatureEnabled(Features, "pclmul", true);
1953    break;
1954  case CK_C3_2:
1955    setFeatureEnabled(Features, "sse", true);
1956    break;
1957  }
1958}
1959
1960bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1961                                      StringRef Name,
1962                                      bool Enabled) const {
1963  // FIXME: This *really* should not be here.  We need some way of translating
1964  // options into llvm subtarget features.
1965  if (!Features.count(Name) &&
1966      (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
1967       Name != "rdrnd"))
1968    return false;
1969
1970  // FIXME: this should probably use a switch with fall through.
1971
1972  if (Enabled) {
1973    if (Name == "mmx")
1974      Features["mmx"] = true;
1975    else if (Name == "sse")
1976      Features["mmx"] = Features["sse"] = true;
1977    else if (Name == "sse2")
1978      Features["mmx"] = Features["sse"] = Features["sse2"] = true;
1979    else if (Name == "sse3")
1980      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1981        true;
1982    else if (Name == "ssse3")
1983      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1984        Features["ssse3"] = true;
1985    else if (Name == "sse4" || Name == "sse4.2")
1986      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1987        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
1988        Features["popcnt"] = true;
1989    else if (Name == "sse4.1")
1990      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1991        Features["ssse3"] = Features["sse41"] = true;
1992    else if (Name == "3dnow")
1993      Features["mmx"] = Features["3dnow"] = true;
1994    else if (Name == "3dnowa")
1995      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
1996    else if (Name == "aes")
1997      Features["sse"] = Features["sse2"] = Features["aes"] = true;
1998    else if (Name == "pclmul")
1999      Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2000    else if (Name == "avx")
2001      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2002        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2003        Features["popcnt"] = Features["avx"] = true;
2004    else if (Name == "avx2")
2005      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2006        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2007        Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2008    else if (Name == "fma")
2009      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2010        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2011        Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2012    else if (Name == "fma4")
2013      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2014        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2015        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2016        Features["fma4"] = true;
2017    else if (Name == "xop")
2018      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2019        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2020        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2021        Features["fma4"] = Features["xop"] = true;
2022    else if (Name == "sse4a")
2023      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2024        Features["sse4a"] = true;
2025    else if (Name == "lzcnt")
2026      Features["lzcnt"] = true;
2027    else if (Name == "rdrnd")
2028      Features["rdrand"] = true;
2029    else if (Name == "bmi")
2030      Features["bmi"] = true;
2031    else if (Name == "bmi2")
2032      Features["bmi2"] = true;
2033    else if (Name == "popcnt")
2034      Features["popcnt"] = true;
2035    else if (Name == "f16c")
2036      Features["f16c"] = true;
2037    else if (Name == "rtm")
2038      Features["rtm"] = true;
2039  } else {
2040    if (Name == "mmx")
2041      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2042    else if (Name == "sse")
2043      Features["sse"] = Features["sse2"] = Features["sse3"] =
2044        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2045        Features["sse4a"] = Features["avx"] = Features["avx2"] =
2046        Features["fma"] = Features["fma4"] = Features["aes"] =
2047        Features["pclmul"] = Features["xop"] = false;
2048    else if (Name == "sse2")
2049      Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2050        Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2051        Features["avx"] = Features["avx2"] = Features["fma"] =
2052        Features["fma4"] = Features["aes"] = Features["pclmul"] =
2053        Features["xop"] = false;
2054    else if (Name == "sse3")
2055      Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2056        Features["sse42"] = Features["sse4a"] = Features["avx"] =
2057        Features["avx2"] = Features["fma"] = Features["fma4"] =
2058        Features["xop"] = false;
2059    else if (Name == "ssse3")
2060      Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2061        Features["avx"] = Features["avx2"] = Features["fma"] = false;
2062    else if (Name == "sse4" || Name == "sse4.1")
2063      Features["sse41"] = Features["sse42"] = Features["avx"] =
2064        Features["avx2"] = Features["fma"] = false;
2065    else if (Name == "sse4.2")
2066      Features["sse42"] = Features["avx"] = Features["avx2"] =
2067        Features["fma"] = false;
2068    else if (Name == "3dnow")
2069      Features["3dnow"] = Features["3dnowa"] = false;
2070    else if (Name == "3dnowa")
2071      Features["3dnowa"] = false;
2072    else if (Name == "aes")
2073      Features["aes"] = false;
2074    else if (Name == "pclmul")
2075      Features["pclmul"] = false;
2076    else if (Name == "avx")
2077      Features["avx"] = Features["avx2"] = Features["fma"] =
2078        Features["fma4"] = Features["xop"] = false;
2079    else if (Name == "avx2")
2080      Features["avx2"] = false;
2081    else if (Name == "fma")
2082      Features["fma"] = false;
2083    else if (Name == "sse4a")
2084      Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2085    else if (Name == "lzcnt")
2086      Features["lzcnt"] = false;
2087    else if (Name == "rdrnd")
2088      Features["rdrand"] = false;
2089    else if (Name == "bmi")
2090      Features["bmi"] = false;
2091    else if (Name == "bmi2")
2092      Features["bmi2"] = false;
2093    else if (Name == "popcnt")
2094      Features["popcnt"] = false;
2095    else if (Name == "fma4")
2096      Features["fma4"] = Features["xop"] = false;
2097    else if (Name == "xop")
2098      Features["xop"] = false;
2099    else if (Name == "f16c")
2100      Features["f16c"] = false;
2101    else if (Name == "rtm")
2102      Features["rtm"] = false;
2103  }
2104
2105  return true;
2106}
2107
2108/// HandleTargetOptions - Perform initialization based on the user
2109/// configured set of features.
2110void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2111  // Remember the maximum enabled sselevel.
2112  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2113    // Ignore disabled features.
2114    if (Features[i][0] == '-')
2115      continue;
2116
2117    StringRef Feature = StringRef(Features[i]).substr(1);
2118
2119    if (Feature == "aes") {
2120      HasAES = true;
2121      continue;
2122    }
2123
2124    if (Feature == "pclmul") {
2125      HasPCLMUL = true;
2126      continue;
2127    }
2128
2129    if (Feature == "lzcnt") {
2130      HasLZCNT = true;
2131      continue;
2132    }
2133
2134    if (Feature == "rdrand") {
2135      HasRDRND = true;
2136      continue;
2137    }
2138
2139    if (Feature == "bmi") {
2140      HasBMI = true;
2141      continue;
2142    }
2143
2144    if (Feature == "bmi2") {
2145      HasBMI2 = true;
2146      continue;
2147    }
2148
2149    if (Feature == "popcnt") {
2150      HasPOPCNT = true;
2151      continue;
2152    }
2153
2154    if (Feature == "rtm") {
2155      HasRTM = true;
2156      continue;
2157    }
2158
2159    if (Feature == "sse4a") {
2160      HasSSE4a = true;
2161      continue;
2162    }
2163
2164    if (Feature == "fma4") {
2165      HasFMA4 = true;
2166      continue;
2167    }
2168
2169    if (Feature == "fma") {
2170      HasFMA = true;
2171      continue;
2172    }
2173
2174    if (Feature == "xop") {
2175      HasXOP = true;
2176      continue;
2177    }
2178
2179    if (Feature == "f16c") {
2180      HasF16C = true;
2181      continue;
2182    }
2183
2184    assert(Features[i][0] == '+' && "Invalid target feature!");
2185    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2186      .Case("avx2", AVX2)
2187      .Case("avx", AVX)
2188      .Case("sse42", SSE42)
2189      .Case("sse41", SSE41)
2190      .Case("ssse3", SSSE3)
2191      .Case("sse3", SSE3)
2192      .Case("sse2", SSE2)
2193      .Case("sse", SSE1)
2194      .Default(NoSSE);
2195    SSELevel = std::max(SSELevel, Level);
2196
2197    MMX3DNowEnum ThreeDNowLevel =
2198      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2199        .Case("3dnowa", AMD3DNowAthlon)
2200        .Case("3dnow", AMD3DNow)
2201        .Case("mmx", MMX)
2202        .Default(NoMMX3DNow);
2203
2204    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2205  }
2206
2207  // Don't tell the backend if we're turning off mmx; it will end up disabling
2208  // SSE, which we don't want.
2209  std::vector<std::string>::iterator it;
2210  it = std::find(Features.begin(), Features.end(), "-mmx");
2211  if (it != Features.end())
2212    Features.erase(it);
2213}
2214
2215/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2216/// definitions for this particular subtarget.
2217void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2218                                     MacroBuilder &Builder) const {
2219  // Target identification.
2220  if (getTriple().getArch() == llvm::Triple::x86_64) {
2221    Builder.defineMacro("__amd64__");
2222    Builder.defineMacro("__amd64");
2223    Builder.defineMacro("__x86_64");
2224    Builder.defineMacro("__x86_64__");
2225  } else {
2226    DefineStd(Builder, "i386", Opts);
2227  }
2228
2229  // Subtarget options.
2230  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2231  // truly should be based on -mtune options.
2232  switch (CPU) {
2233  case CK_Generic:
2234    break;
2235  case CK_i386:
2236    // The rest are coming from the i386 define above.
2237    Builder.defineMacro("__tune_i386__");
2238    break;
2239  case CK_i486:
2240  case CK_WinChipC6:
2241  case CK_WinChip2:
2242  case CK_C3:
2243    defineCPUMacros(Builder, "i486");
2244    break;
2245  case CK_PentiumMMX:
2246    Builder.defineMacro("__pentium_mmx__");
2247    Builder.defineMacro("__tune_pentium_mmx__");
2248    // Fallthrough
2249  case CK_i586:
2250  case CK_Pentium:
2251    defineCPUMacros(Builder, "i586");
2252    defineCPUMacros(Builder, "pentium");
2253    break;
2254  case CK_Pentium3:
2255  case CK_Pentium3M:
2256  case CK_PentiumM:
2257    Builder.defineMacro("__tune_pentium3__");
2258    // Fallthrough
2259  case CK_Pentium2:
2260  case CK_C3_2:
2261    Builder.defineMacro("__tune_pentium2__");
2262    // Fallthrough
2263  case CK_PentiumPro:
2264    Builder.defineMacro("__tune_i686__");
2265    Builder.defineMacro("__tune_pentiumpro__");
2266    // Fallthrough
2267  case CK_i686:
2268    Builder.defineMacro("__i686");
2269    Builder.defineMacro("__i686__");
2270    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2271    Builder.defineMacro("__pentiumpro");
2272    Builder.defineMacro("__pentiumpro__");
2273    break;
2274  case CK_Pentium4:
2275  case CK_Pentium4M:
2276    defineCPUMacros(Builder, "pentium4");
2277    break;
2278  case CK_Yonah:
2279  case CK_Prescott:
2280  case CK_Nocona:
2281    defineCPUMacros(Builder, "nocona");
2282    break;
2283  case CK_Core2:
2284  case CK_Penryn:
2285    defineCPUMacros(Builder, "core2");
2286    break;
2287  case CK_Atom:
2288    defineCPUMacros(Builder, "atom");
2289    break;
2290  case CK_Corei7:
2291  case CK_Corei7AVX:
2292  case CK_CoreAVXi:
2293  case CK_CoreAVX2:
2294    defineCPUMacros(Builder, "corei7");
2295    break;
2296  case CK_K6_2:
2297    Builder.defineMacro("__k6_2__");
2298    Builder.defineMacro("__tune_k6_2__");
2299    // Fallthrough
2300  case CK_K6_3:
2301    if (CPU != CK_K6_2) {  // In case of fallthrough
2302      // FIXME: GCC may be enabling these in cases where some other k6
2303      // architecture is specified but -m3dnow is explicitly provided. The
2304      // exact semantics need to be determined and emulated here.
2305      Builder.defineMacro("__k6_3__");
2306      Builder.defineMacro("__tune_k6_3__");
2307    }
2308    // Fallthrough
2309  case CK_K6:
2310    defineCPUMacros(Builder, "k6");
2311    break;
2312  case CK_Athlon:
2313  case CK_AthlonThunderbird:
2314  case CK_Athlon4:
2315  case CK_AthlonXP:
2316  case CK_AthlonMP:
2317    defineCPUMacros(Builder, "athlon");
2318    if (SSELevel != NoSSE) {
2319      Builder.defineMacro("__athlon_sse__");
2320      Builder.defineMacro("__tune_athlon_sse__");
2321    }
2322    break;
2323  case CK_K8:
2324  case CK_K8SSE3:
2325  case CK_x86_64:
2326  case CK_Opteron:
2327  case CK_OpteronSSE3:
2328  case CK_Athlon64:
2329  case CK_Athlon64SSE3:
2330  case CK_AthlonFX:
2331    defineCPUMacros(Builder, "k8");
2332    break;
2333  case CK_AMDFAM10:
2334    defineCPUMacros(Builder, "amdfam10");
2335    break;
2336  case CK_BTVER1:
2337    defineCPUMacros(Builder, "btver1");
2338    break;
2339  case CK_BDVER1:
2340    defineCPUMacros(Builder, "bdver1");
2341    break;
2342  case CK_BDVER2:
2343    defineCPUMacros(Builder, "bdver2");
2344    break;
2345  case CK_Geode:
2346    defineCPUMacros(Builder, "geode");
2347    break;
2348  }
2349
2350  // Target properties.
2351  Builder.defineMacro("__LITTLE_ENDIAN__");
2352  Builder.defineMacro("__REGISTER_PREFIX__", "");
2353
2354  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2355  // functions in glibc header files that use FP Stack inline asm which the
2356  // backend can't deal with (PR879).
2357  Builder.defineMacro("__NO_MATH_INLINES");
2358
2359  if (HasAES)
2360    Builder.defineMacro("__AES__");
2361
2362  if (HasPCLMUL)
2363    Builder.defineMacro("__PCLMUL__");
2364
2365  if (HasLZCNT)
2366    Builder.defineMacro("__LZCNT__");
2367
2368  if (HasRDRND)
2369    Builder.defineMacro("__RDRND__");
2370
2371  if (HasBMI)
2372    Builder.defineMacro("__BMI__");
2373
2374  if (HasBMI2)
2375    Builder.defineMacro("__BMI2__");
2376
2377  if (HasPOPCNT)
2378    Builder.defineMacro("__POPCNT__");
2379
2380  if (HasRTM)
2381    Builder.defineMacro("__RTM__");
2382
2383  if (HasSSE4a)
2384    Builder.defineMacro("__SSE4A__");
2385
2386  if (HasFMA4)
2387    Builder.defineMacro("__FMA4__");
2388
2389  if (HasFMA)
2390    Builder.defineMacro("__FMA__");
2391
2392  if (HasXOP)
2393    Builder.defineMacro("__XOP__");
2394
2395  if (HasF16C)
2396    Builder.defineMacro("__F16C__");
2397
2398  // Each case falls through to the previous one here.
2399  switch (SSELevel) {
2400  case AVX2:
2401    Builder.defineMacro("__AVX2__");
2402  case AVX:
2403    Builder.defineMacro("__AVX__");
2404  case SSE42:
2405    Builder.defineMacro("__SSE4_2__");
2406  case SSE41:
2407    Builder.defineMacro("__SSE4_1__");
2408  case SSSE3:
2409    Builder.defineMacro("__SSSE3__");
2410  case SSE3:
2411    Builder.defineMacro("__SSE3__");
2412  case SSE2:
2413    Builder.defineMacro("__SSE2__");
2414    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2415  case SSE1:
2416    Builder.defineMacro("__SSE__");
2417    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2418  case NoSSE:
2419    break;
2420  }
2421
2422  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2423    switch (SSELevel) {
2424    case AVX2:
2425    case AVX:
2426    case SSE42:
2427    case SSE41:
2428    case SSSE3:
2429    case SSE3:
2430    case SSE2:
2431      Builder.defineMacro("_M_IX86_FP", Twine(2));
2432      break;
2433    case SSE1:
2434      Builder.defineMacro("_M_IX86_FP", Twine(1));
2435      break;
2436    default:
2437      Builder.defineMacro("_M_IX86_FP", Twine(0));
2438    }
2439  }
2440
2441  // Each case falls through to the previous one here.
2442  switch (MMX3DNowLevel) {
2443  case AMD3DNowAthlon:
2444    Builder.defineMacro("__3dNOW_A__");
2445  case AMD3DNow:
2446    Builder.defineMacro("__3dNOW__");
2447  case MMX:
2448    Builder.defineMacro("__MMX__");
2449  case NoMMX3DNow:
2450    break;
2451  }
2452}
2453
2454bool X86TargetInfo::hasFeature(StringRef Feature) const {
2455  return llvm::StringSwitch<bool>(Feature)
2456      .Case("aes", HasAES)
2457      .Case("avx", SSELevel >= AVX)
2458      .Case("avx2", SSELevel >= AVX2)
2459      .Case("bmi", HasBMI)
2460      .Case("bmi2", HasBMI2)
2461      .Case("fma", HasFMA)
2462      .Case("fma4", HasFMA4)
2463      .Case("lzcnt", HasLZCNT)
2464      .Case("rdrnd", HasRDRND)
2465      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2466      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2467      .Case("mmx", MMX3DNowLevel >= MMX)
2468      .Case("pclmul", HasPCLMUL)
2469      .Case("popcnt", HasPOPCNT)
2470      .Case("rtm", HasRTM)
2471      .Case("sse", SSELevel >= SSE1)
2472      .Case("sse2", SSELevel >= SSE2)
2473      .Case("sse3", SSELevel >= SSE3)
2474      .Case("ssse3", SSELevel >= SSSE3)
2475      .Case("sse41", SSELevel >= SSE41)
2476      .Case("sse42", SSELevel >= SSE42)
2477      .Case("sse4a", HasSSE4a)
2478      .Case("x86", true)
2479      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2480      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2481      .Case("xop", HasXOP)
2482      .Case("f16c", HasF16C)
2483      .Default(false);
2484}
2485
2486bool
2487X86TargetInfo::validateAsmConstraint(const char *&Name,
2488                                     TargetInfo::ConstraintInfo &Info) const {
2489  switch (*Name) {
2490  default: return false;
2491  case 'Y': // first letter of a pair:
2492    switch (*(Name+1)) {
2493    default: return false;
2494    case '0':  // First SSE register.
2495    case 't':  // Any SSE register, when SSE2 is enabled.
2496    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2497    case 'm':  // any MMX register, when inter-unit moves enabled.
2498      break;   // falls through to setAllowsRegister.
2499  }
2500  case 'a': // eax.
2501  case 'b': // ebx.
2502  case 'c': // ecx.
2503  case 'd': // edx.
2504  case 'S': // esi.
2505  case 'D': // edi.
2506  case 'A': // edx:eax.
2507  case 'f': // any x87 floating point stack register.
2508  case 't': // top of floating point stack.
2509  case 'u': // second from top of floating point stack.
2510  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2511  case 'y': // Any MMX register.
2512  case 'x': // Any SSE register.
2513  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2514  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2515  case 'l': // "Index" registers: any general register that can be used as an
2516            // index in a base+index memory access.
2517    Info.setAllowsRegister();
2518    return true;
2519  case 'C': // SSE floating point constant.
2520  case 'G': // x87 floating point constant.
2521  case 'e': // 32-bit signed integer constant for use with zero-extending
2522            // x86_64 instructions.
2523  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2524            // x86_64 instructions.
2525    return true;
2526  }
2527}
2528
2529
2530std::string
2531X86TargetInfo::convertConstraint(const char *&Constraint) const {
2532  switch (*Constraint) {
2533  case 'a': return std::string("{ax}");
2534  case 'b': return std::string("{bx}");
2535  case 'c': return std::string("{cx}");
2536  case 'd': return std::string("{dx}");
2537  case 'S': return std::string("{si}");
2538  case 'D': return std::string("{di}");
2539  case 'p': // address
2540    return std::string("im");
2541  case 't': // top of floating point stack.
2542    return std::string("{st}");
2543  case 'u': // second from top of floating point stack.
2544    return std::string("{st(1)}"); // second from top of floating point stack.
2545  default:
2546    return std::string(1, *Constraint);
2547  }
2548}
2549} // end anonymous namespace
2550
2551namespace {
2552// X86-32 generic target
2553class X86_32TargetInfo : public X86TargetInfo {
2554public:
2555  X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2556    DoubleAlign = LongLongAlign = 32;
2557    LongDoubleWidth = 96;
2558    LongDoubleAlign = 32;
2559    SuitableAlign = 128;
2560    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2561                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2562                        "a0:0:64-f80:32:32-n8:16:32-S128";
2563    SizeType = UnsignedInt;
2564    PtrDiffType = SignedInt;
2565    IntPtrType = SignedInt;
2566    RegParmMax = 3;
2567
2568    // Use fpret for all types.
2569    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2570                             (1 << TargetInfo::Double) |
2571                             (1 << TargetInfo::LongDouble));
2572
2573    // x86-32 has atomics up to 8 bytes
2574    // FIXME: Check that we actually have cmpxchg8b before setting
2575    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2576    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2577  }
2578  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2579    return TargetInfo::CharPtrBuiltinVaList;
2580  }
2581
2582  int getEHDataRegisterNumber(unsigned RegNo) const {
2583    if (RegNo == 0) return 0;
2584    if (RegNo == 1) return 2;
2585    return -1;
2586  }
2587  virtual bool validateInputSize(StringRef Constraint,
2588                                 unsigned Size) const {
2589    switch (Constraint[0]) {
2590    default: break;
2591    case 'a':
2592    case 'b':
2593    case 'c':
2594    case 'd':
2595      return Size <= 32;
2596    }
2597
2598    return true;
2599  }
2600};
2601} // end anonymous namespace
2602
2603namespace {
2604class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2605public:
2606  NetBSDI386TargetInfo(const std::string &triple) :
2607    NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2608  }
2609
2610  virtual unsigned getFloatEvalMethod() const {
2611    // NetBSD defaults to "double" rounding
2612    return 1;
2613  }
2614};
2615} // end anonymous namespace
2616
2617namespace {
2618class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2619public:
2620  OpenBSDI386TargetInfo(const std::string& triple) :
2621    OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2622    SizeType = UnsignedLong;
2623    IntPtrType = SignedLong;
2624    PtrDiffType = SignedLong;
2625  }
2626};
2627} // end anonymous namespace
2628
2629namespace {
2630class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2631public:
2632  BitrigI386TargetInfo(const std::string& triple) :
2633    BitrigTargetInfo<X86_32TargetInfo>(triple) {
2634    SizeType = UnsignedLong;
2635    IntPtrType = SignedLong;
2636    PtrDiffType = SignedLong;
2637  }
2638};
2639} // end anonymous namespace
2640
2641namespace {
2642class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2643public:
2644  DarwinI386TargetInfo(const std::string& triple) :
2645    DarwinTargetInfo<X86_32TargetInfo>(triple) {
2646    LongDoubleWidth = 128;
2647    LongDoubleAlign = 128;
2648    SuitableAlign = 128;
2649    MaxVectorAlign = 256;
2650    SizeType = UnsignedLong;
2651    IntPtrType = SignedLong;
2652    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2653                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2654                        "a0:0:64-f80:128:128-n8:16:32-S128";
2655    HasAlignMac68kSupport = true;
2656  }
2657
2658};
2659} // end anonymous namespace
2660
2661namespace {
2662// x86-32 Windows target
2663class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2664public:
2665  WindowsX86_32TargetInfo(const std::string& triple)
2666    : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2667    TLSSupported = false;
2668    WCharType = UnsignedShort;
2669    DoubleAlign = LongLongAlign = 64;
2670    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2671                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2672                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2673  }
2674  virtual void getTargetDefines(const LangOptions &Opts,
2675                                MacroBuilder &Builder) const {
2676    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2677  }
2678};
2679} // end anonymous namespace
2680
2681namespace {
2682
2683// x86-32 Windows Visual Studio target
2684class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2685public:
2686  VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2687    : WindowsX86_32TargetInfo(triple) {
2688    LongDoubleWidth = LongDoubleAlign = 64;
2689    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2690  }
2691  virtual void getTargetDefines(const LangOptions &Opts,
2692                                MacroBuilder &Builder) const {
2693    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2694    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2695    // The value of the following reflects processor type.
2696    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2697    // We lost the original triple, so we use the default.
2698    Builder.defineMacro("_M_IX86", "600");
2699  }
2700};
2701} // end anonymous namespace
2702
2703namespace {
2704// x86-32 MinGW target
2705class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
2706public:
2707  MinGWX86_32TargetInfo(const std::string& triple)
2708    : WindowsX86_32TargetInfo(triple) {
2709  }
2710  virtual void getTargetDefines(const LangOptions &Opts,
2711                                MacroBuilder &Builder) const {
2712    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2713    DefineStd(Builder, "WIN32", Opts);
2714    DefineStd(Builder, "WINNT", Opts);
2715    Builder.defineMacro("_X86_");
2716    Builder.defineMacro("__MSVCRT__");
2717    Builder.defineMacro("__MINGW32__");
2718
2719    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
2720    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
2721    if (Opts.MicrosoftExt)
2722      // Provide "as-is" __declspec.
2723      Builder.defineMacro("__declspec", "__declspec");
2724    else
2725      // Provide alias of __attribute__ like mingw32-gcc.
2726      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
2727  }
2728};
2729} // end anonymous namespace
2730
2731namespace {
2732// x86-32 Cygwin target
2733class CygwinX86_32TargetInfo : public X86_32TargetInfo {
2734public:
2735  CygwinX86_32TargetInfo(const std::string& triple)
2736    : X86_32TargetInfo(triple) {
2737    TLSSupported = false;
2738    WCharType = UnsignedShort;
2739    DoubleAlign = LongLongAlign = 64;
2740    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2741                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
2742                        "a0:0:64-f80:32:32-n8:16:32-S32";
2743  }
2744  virtual void getTargetDefines(const LangOptions &Opts,
2745                                MacroBuilder &Builder) const {
2746    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2747    Builder.defineMacro("__CYGWIN__");
2748    Builder.defineMacro("__CYGWIN32__");
2749    DefineStd(Builder, "unix", Opts);
2750    if (Opts.CPlusPlus)
2751      Builder.defineMacro("_GNU_SOURCE");
2752  }
2753};
2754} // end anonymous namespace
2755
2756namespace {
2757// x86-32 Haiku target
2758class HaikuX86_32TargetInfo : public X86_32TargetInfo {
2759public:
2760  HaikuX86_32TargetInfo(const std::string& triple)
2761    : X86_32TargetInfo(triple) {
2762    SizeType = UnsignedLong;
2763    IntPtrType = SignedLong;
2764    PtrDiffType = SignedLong;
2765    this->UserLabelPrefix = "";
2766    this->TLSSupported = false;
2767  }
2768  virtual void getTargetDefines(const LangOptions &Opts,
2769                                MacroBuilder &Builder) const {
2770    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2771    Builder.defineMacro("__INTEL__");
2772    Builder.defineMacro("__HAIKU__");
2773  }
2774};
2775} // end anonymous namespace
2776
2777// RTEMS Target
2778template<typename Target>
2779class RTEMSTargetInfo : public OSTargetInfo<Target> {
2780protected:
2781  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
2782                            MacroBuilder &Builder) const {
2783    // RTEMS defines; list based off of gcc output
2784
2785    Builder.defineMacro("__rtems__");
2786    Builder.defineMacro("__ELF__");
2787  }
2788public:
2789  RTEMSTargetInfo(const std::string &triple)
2790    : OSTargetInfo<Target>(triple) {
2791      this->UserLabelPrefix = "";
2792
2793      llvm::Triple Triple(triple);
2794      switch (Triple.getArch()) {
2795        default:
2796        case llvm::Triple::x86:
2797          // this->MCountName = ".mcount";
2798          break;
2799        case llvm::Triple::mips:
2800        case llvm::Triple::mipsel:
2801        case llvm::Triple::ppc:
2802        case llvm::Triple::ppc64:
2803          // this->MCountName = "_mcount";
2804          break;
2805        case llvm::Triple::arm:
2806          // this->MCountName = "__mcount";
2807          break;
2808      }
2809
2810    }
2811};
2812
2813namespace {
2814// x86-32 RTEMS target
2815class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
2816public:
2817  RTEMSX86_32TargetInfo(const std::string& triple)
2818    : X86_32TargetInfo(triple) {
2819    SizeType = UnsignedLong;
2820    IntPtrType = SignedLong;
2821    PtrDiffType = SignedLong;
2822    this->UserLabelPrefix = "";
2823  }
2824  virtual void getTargetDefines(const LangOptions &Opts,
2825                                MacroBuilder &Builder) const {
2826    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2827    Builder.defineMacro("__INTEL__");
2828    Builder.defineMacro("__rtems__");
2829  }
2830};
2831} // end anonymous namespace
2832
2833namespace {
2834// x86-64 generic target
2835class X86_64TargetInfo : public X86TargetInfo {
2836public:
2837  X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
2838    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
2839    LongDoubleWidth = 128;
2840    LongDoubleAlign = 128;
2841    LargeArrayMinWidth = 128;
2842    LargeArrayAlign = 128;
2843    SuitableAlign = 128;
2844    IntMaxType = SignedLong;
2845    UIntMaxType = UnsignedLong;
2846    Int64Type = SignedLong;
2847    RegParmMax = 6;
2848
2849    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2850                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
2851                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
2852
2853    // Use fpret only for long double.
2854    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
2855
2856    // Use fp2ret for _Complex long double.
2857    ComplexLongDoubleUsesFP2Ret = true;
2858
2859    // x86-64 has atomics up to 16 bytes.
2860    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
2861    // on CPUs with cmpxchg16b
2862    MaxAtomicPromoteWidth = 128;
2863    MaxAtomicInlineWidth = 64;
2864  }
2865  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2866    return TargetInfo::X86_64ABIBuiltinVaList;
2867  }
2868
2869  int getEHDataRegisterNumber(unsigned RegNo) const {
2870    if (RegNo == 0) return 0;
2871    if (RegNo == 1) return 1;
2872    return -1;
2873  }
2874
2875  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2876    return TargetInfo::checkCallingConvention(CC);
2877  }
2878
2879  virtual CallingConv getDefaultCallingConv() const {
2880    return CC_Default;
2881  }
2882
2883};
2884} // end anonymous namespace
2885
2886namespace {
2887// x86-64 Windows target
2888class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
2889public:
2890  WindowsX86_64TargetInfo(const std::string& triple)
2891    : WindowsTargetInfo<X86_64TargetInfo>(triple) {
2892    TLSSupported = false;
2893    WCharType = UnsignedShort;
2894    LongWidth = LongAlign = 32;
2895    DoubleAlign = LongLongAlign = 64;
2896    IntMaxType = SignedLongLong;
2897    UIntMaxType = UnsignedLongLong;
2898    Int64Type = SignedLongLong;
2899    SizeType = UnsignedLongLong;
2900    PtrDiffType = SignedLongLong;
2901    IntPtrType = SignedLongLong;
2902    this->UserLabelPrefix = "";
2903  }
2904  virtual void getTargetDefines(const LangOptions &Opts,
2905                                MacroBuilder &Builder) const {
2906    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
2907    Builder.defineMacro("_WIN64");
2908  }
2909  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2910    return TargetInfo::CharPtrBuiltinVaList;
2911  }
2912};
2913} // end anonymous namespace
2914
2915namespace {
2916// x86-64 Windows Visual Studio target
2917class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
2918public:
2919  VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
2920    : WindowsX86_64TargetInfo(triple) {
2921    LongDoubleWidth = LongDoubleAlign = 64;
2922    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2923  }
2924  virtual void getTargetDefines(const LangOptions &Opts,
2925                                MacroBuilder &Builder) const {
2926    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
2927    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
2928    Builder.defineMacro("_M_X64");
2929    Builder.defineMacro("_M_AMD64");
2930  }
2931};
2932} // end anonymous namespace
2933
2934namespace {
2935// x86-64 MinGW target
2936class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
2937public:
2938  MinGWX86_64TargetInfo(const std::string& triple)
2939    : WindowsX86_64TargetInfo(triple) {
2940  }
2941  virtual void getTargetDefines(const LangOptions &Opts,
2942                                MacroBuilder &Builder) const {
2943    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
2944    DefineStd(Builder, "WIN64", Opts);
2945    Builder.defineMacro("__MSVCRT__");
2946    Builder.defineMacro("__MINGW32__");
2947    Builder.defineMacro("__MINGW64__");
2948
2949    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
2950    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
2951    if (Opts.MicrosoftExt)
2952      // Provide "as-is" __declspec.
2953      Builder.defineMacro("__declspec", "__declspec");
2954    else
2955      // Provide alias of __attribute__ like mingw32-gcc.
2956      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
2957  }
2958};
2959} // end anonymous namespace
2960
2961namespace {
2962class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
2963public:
2964  DarwinX86_64TargetInfo(const std::string& triple)
2965      : DarwinTargetInfo<X86_64TargetInfo>(triple) {
2966    Int64Type = SignedLongLong;
2967    MaxVectorAlign = 256;
2968  }
2969};
2970} // end anonymous namespace
2971
2972namespace {
2973class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
2974public:
2975  OpenBSDX86_64TargetInfo(const std::string& triple)
2976      : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
2977    IntMaxType = SignedLongLong;
2978    UIntMaxType = UnsignedLongLong;
2979    Int64Type = SignedLongLong;
2980  }
2981};
2982} // end anonymous namespace
2983
2984namespace {
2985class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
2986public:
2987  BitrigX86_64TargetInfo(const std::string& triple)
2988      : BitrigTargetInfo<X86_64TargetInfo>(triple) {
2989     IntMaxType = SignedLongLong;
2990     UIntMaxType = UnsignedLongLong;
2991     Int64Type = SignedLongLong;
2992  }
2993};
2994} // end anonymous namespace
2995
2996namespace {
2997class ARMTargetInfo : public TargetInfo {
2998  // Possible FPU choices.
2999  enum FPUMode {
3000    VFP2FPU = (1 << 0),
3001    VFP3FPU = (1 << 1),
3002    VFP4FPU = (1 << 2),
3003    NeonFPU = (1 << 3)
3004  };
3005
3006  static bool FPUModeIsVFP(FPUMode Mode) {
3007    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3008  }
3009
3010  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3011  static const char * const GCCRegNames[];
3012
3013  std::string ABI, CPU;
3014
3015  unsigned FPU : 4;
3016
3017  unsigned IsAAPCS : 1;
3018  unsigned IsThumb : 1;
3019
3020  // Initialized via features.
3021  unsigned SoftFloat : 1;
3022  unsigned SoftFloatABI : 1;
3023
3024  static const Builtin::Info BuiltinInfo[];
3025
3026public:
3027  ARMTargetInfo(const std::string &TripleStr)
3028    : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3029  {
3030    BigEndian = false;
3031    SizeType = UnsignedInt;
3032    PtrDiffType = SignedInt;
3033    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3034    WCharType = UnsignedInt;
3035
3036    // {} in inline assembly are neon specifiers, not assembly variant
3037    // specifiers.
3038    NoAsmVariants = true;
3039
3040    // FIXME: Should we just treat this as a feature?
3041    IsThumb = getTriple().getArchName().startswith("thumb");
3042    if (IsThumb) {
3043      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3044      // so set preferred for small types to 32.
3045      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3046                           "i64:64:64-f32:32:32-f64:64:64-"
3047                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3048    } else {
3049      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3050                           "i64:64:64-f32:32:32-f64:64:64-"
3051                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3052    }
3053
3054    // ARM targets default to using the ARM C++ ABI.
3055    CXXABI = CXXABI_ARM;
3056
3057    // ARM has atomics up to 8 bytes
3058    // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e
3059    MaxAtomicPromoteWidth = 64;
3060
3061    // Do force alignment of members that follow zero length bitfields.  If
3062    // the alignment of the zero-length bitfield is greater than the member
3063    // that follows it, `bar', `bar' will be aligned as the  type of the
3064    // zero length bitfield.
3065    UseZeroLengthBitfieldAlignment = true;
3066  }
3067  virtual const char *getABI() const { return ABI.c_str(); }
3068  virtual bool setABI(const std::string &Name) {
3069    ABI = Name;
3070
3071    // The defaults (above) are for AAPCS, check if we need to change them.
3072    //
3073    // FIXME: We need support for -meabi... we could just mangle it into the
3074    // name.
3075    if (Name == "apcs-gnu") {
3076      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3077      SizeType = UnsignedLong;
3078
3079      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3080      WCharType = SignedInt;
3081
3082      // Do not respect the alignment of bit-field types when laying out
3083      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3084      UseBitFieldTypeAlignment = false;
3085
3086      /// gcc forces the alignment to 4 bytes, regardless of the type of the
3087      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3088      /// gcc.
3089      ZeroLengthBitfieldBoundary = 32;
3090
3091      IsAAPCS = false;
3092
3093      if (IsThumb) {
3094        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3095        // so set preferred for small types to 32.
3096        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3097                             "i64:32:64-f32:32:32-f64:32:64-"
3098                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3099      } else {
3100        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3101                             "i64:32:64-f32:32:32-f64:32:64-"
3102                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3103      }
3104
3105      // FIXME: Override "preferred align" for double and long long.
3106    } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3107      IsAAPCS = true;
3108      // FIXME: Enumerated types are variable width in straight AAPCS.
3109    } else if (Name == "aapcs-linux") {
3110      IsAAPCS = true;
3111    } else
3112      return false;
3113
3114    return true;
3115  }
3116
3117  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3118    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3119      Features["vfp2"] = true;
3120    else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3121             CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3122      Features["neon"] = true;
3123    else if (CPU == "swift") {
3124      Features["vfp4"] = true;
3125      Features["neon"] = true;
3126    }
3127  }
3128
3129  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3130                                 StringRef Name,
3131                                 bool Enabled) const {
3132    if (Name == "soft-float" || Name == "soft-float-abi" ||
3133        Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3134        Name == "d16" || Name == "neonfp") {
3135      Features[Name] = Enabled;
3136    } else
3137      return false;
3138
3139    return true;
3140  }
3141
3142  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3143    FPU = 0;
3144    SoftFloat = SoftFloatABI = false;
3145    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3146      if (Features[i] == "+soft-float")
3147        SoftFloat = true;
3148      else if (Features[i] == "+soft-float-abi")
3149        SoftFloatABI = true;
3150      else if (Features[i] == "+vfp2")
3151        FPU |= VFP2FPU;
3152      else if (Features[i] == "+vfp3")
3153        FPU |= VFP3FPU;
3154      else if (Features[i] == "+vfp4")
3155        FPU |= VFP4FPU;
3156      else if (Features[i] == "+neon")
3157        FPU |= NeonFPU;
3158    }
3159
3160    // Remove front-end specific options which the backend handles differently.
3161    std::vector<std::string>::iterator it;
3162    it = std::find(Features.begin(), Features.end(), "+soft-float");
3163    if (it != Features.end())
3164      Features.erase(it);
3165    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3166    if (it != Features.end())
3167      Features.erase(it);
3168  }
3169
3170  virtual bool hasFeature(StringRef Feature) const {
3171    return llvm::StringSwitch<bool>(Feature)
3172        .Case("arm", true)
3173        .Case("softfloat", SoftFloat)
3174        .Case("thumb", IsThumb)
3175        .Case("neon", FPU == NeonFPU && !SoftFloat &&
3176              StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3177        .Default(false);
3178  }
3179  // FIXME: Should we actually have some table instead of these switches?
3180  static const char *getCPUDefineSuffix(StringRef Name) {
3181    return llvm::StringSwitch<const char*>(Name)
3182      .Cases("arm8", "arm810", "4")
3183      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3184      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3185      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3186      .Case("ep9312", "4T")
3187      .Cases("arm10tdmi", "arm1020t", "5T")
3188      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3189      .Case("arm926ej-s", "5TEJ")
3190      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3191      .Cases("xscale", "iwmmxt", "5TE")
3192      .Case("arm1136j-s", "6J")
3193      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3194      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3195      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3196      .Cases("cortex-a8", "cortex-a9", "cortex-a15", "7A")
3197      .Case("cortex-a9-mp", "7F")
3198      .Case("swift", "7S")
3199      .Cases("cortex-m3", "cortex-m4", "7M")
3200      .Case("cortex-m0", "6M")
3201      .Default(0);
3202  }
3203  static const char *getCPUProfile(StringRef Name) {
3204    return llvm::StringSwitch<const char*>(Name)
3205      .Cases("cortex-a8", "cortex-a9", "A")
3206      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3207      .Default("");
3208  }
3209  virtual bool setCPU(const std::string &Name) {
3210    if (!getCPUDefineSuffix(Name))
3211      return false;
3212
3213    CPU = Name;
3214    return true;
3215  }
3216  virtual void getTargetDefines(const LangOptions &Opts,
3217                                MacroBuilder &Builder) const {
3218    // Target identification.
3219    Builder.defineMacro("__arm");
3220    Builder.defineMacro("__arm__");
3221
3222    // Target properties.
3223    Builder.defineMacro("__ARMEL__");
3224    Builder.defineMacro("__LITTLE_ENDIAN__");
3225    Builder.defineMacro("__REGISTER_PREFIX__", "");
3226
3227    StringRef CPUArch = getCPUDefineSuffix(CPU);
3228    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3229    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3230    StringRef CPUProfile = getCPUProfile(CPU);
3231    if (!CPUProfile.empty())
3232      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3233
3234    // Subtarget options.
3235
3236    // FIXME: It's more complicated than this and we don't really support
3237    // interworking.
3238    if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3239      Builder.defineMacro("__THUMB_INTERWORK__");
3240
3241    if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3242      // M-class CPUs on Darwin follow AAPCS, but not EABI.
3243      if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3244        Builder.defineMacro("__ARM_EABI__");
3245      Builder.defineMacro("__ARM_PCS", "1");
3246
3247      if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3248        Builder.defineMacro("__ARM_PCS_VFP", "1");
3249    }
3250
3251    if (SoftFloat)
3252      Builder.defineMacro("__SOFTFP__");
3253
3254    if (CPU == "xscale")
3255      Builder.defineMacro("__XSCALE__");
3256
3257    bool IsARMv7 = CPUArch.startswith("7");
3258    if (IsThumb) {
3259      Builder.defineMacro("__THUMBEL__");
3260      Builder.defineMacro("__thumb__");
3261      if (CPUArch == "6T2" || IsARMv7)
3262        Builder.defineMacro("__thumb2__");
3263    }
3264
3265    // Note, this is always on in gcc, even though it doesn't make sense.
3266    Builder.defineMacro("__APCS_32__");
3267
3268    if (FPUModeIsVFP((FPUMode) FPU)) {
3269      Builder.defineMacro("__VFP_FP__");
3270      if (FPU & VFP2FPU)
3271        Builder.defineMacro("__ARM_VFPV2__");
3272      if (FPU & VFP3FPU)
3273        Builder.defineMacro("__ARM_VFPV3__");
3274      if (FPU & VFP4FPU)
3275        Builder.defineMacro("__ARM_VFPV4__");
3276    }
3277
3278    // This only gets set when Neon instructions are actually available, unlike
3279    // the VFP define, hence the soft float and arch check. This is subtly
3280    // different from gcc, we follow the intent which was that it should be set
3281    // when Neon instructions are actually available.
3282    if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3283      Builder.defineMacro("__ARM_NEON__");
3284  }
3285  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3286                                 unsigned &NumRecords) const {
3287    Records = BuiltinInfo;
3288    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3289  }
3290  virtual bool isCLZForZeroUndef() const { return false; }
3291  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3292    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3293  }
3294  virtual void getGCCRegNames(const char * const *&Names,
3295                              unsigned &NumNames) const;
3296  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3297                                unsigned &NumAliases) const;
3298  virtual bool validateAsmConstraint(const char *&Name,
3299                                     TargetInfo::ConstraintInfo &Info) const {
3300    switch (*Name) {
3301    default: break;
3302    case 'l': // r0-r7
3303    case 'h': // r8-r15
3304    case 'w': // VFP Floating point register single precision
3305    case 'P': // VFP Floating point register double precision
3306      Info.setAllowsRegister();
3307      return true;
3308    case 'Q': // A memory address that is a single base register.
3309      Info.setAllowsMemory();
3310      return true;
3311    case 'U': // a memory reference...
3312      switch (Name[1]) {
3313      case 'q': // ...ARMV4 ldrsb
3314      case 'v': // ...VFP load/store (reg+constant offset)
3315      case 'y': // ...iWMMXt load/store
3316      case 't': // address valid for load/store opaque types wider
3317                // than 128-bits
3318      case 'n': // valid address for Neon doubleword vector load/store
3319      case 'm': // valid address for Neon element and structure load/store
3320      case 's': // valid address for non-offset loads/stores of quad-word
3321                // values in four ARM registers
3322        Info.setAllowsMemory();
3323        Name++;
3324        return true;
3325      }
3326    }
3327    return false;
3328  }
3329  virtual std::string convertConstraint(const char *&Constraint) const {
3330    std::string R;
3331    switch (*Constraint) {
3332    case 'U':   // Two-character constraint; add "^" hint for later parsing.
3333      R = std::string("^") + std::string(Constraint, 2);
3334      Constraint++;
3335      break;
3336    case 'p': // 'p' should be translated to 'r' by default.
3337      R = std::string("r");
3338      break;
3339    default:
3340      return std::string(1, *Constraint);
3341    }
3342    return R;
3343  }
3344  virtual bool validateConstraintModifier(StringRef Constraint,
3345                                          const char Modifier,
3346                                          unsigned Size) const {
3347    // Strip off constraint modifiers.
3348    while (Constraint[0] == '=' ||
3349           Constraint[0] == '+' ||
3350           Constraint[0] == '&')
3351      Constraint = Constraint.substr(1);
3352
3353    switch (Constraint[0]) {
3354    default: break;
3355    case 'r': {
3356      switch (Modifier) {
3357      default:
3358        return Size == 32;
3359      case 'q':
3360        // A register of size 32 cannot fit a vector type.
3361        return false;
3362      }
3363    }
3364    }
3365
3366    return true;
3367  }
3368  virtual const char *getClobbers() const {
3369    // FIXME: Is this really right?
3370    return "";
3371  }
3372
3373  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3374    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3375  }
3376};
3377
3378const char * const ARMTargetInfo::GCCRegNames[] = {
3379  // Integer registers
3380  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3381  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3382
3383  // Float registers
3384  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3385  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3386  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3387  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3388
3389  // Double registers
3390  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3391  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3392  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3393  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3394
3395  // Quad registers
3396  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3397  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3398};
3399
3400void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3401                                   unsigned &NumNames) const {
3402  Names = GCCRegNames;
3403  NumNames = llvm::array_lengthof(GCCRegNames);
3404}
3405
3406const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3407  { { "a1" }, "r0" },
3408  { { "a2" }, "r1" },
3409  { { "a3" }, "r2" },
3410  { { "a4" }, "r3" },
3411  { { "v1" }, "r4" },
3412  { { "v2" }, "r5" },
3413  { { "v3" }, "r6" },
3414  { { "v4" }, "r7" },
3415  { { "v5" }, "r8" },
3416  { { "v6", "rfp" }, "r9" },
3417  { { "sl" }, "r10" },
3418  { { "fp" }, "r11" },
3419  { { "ip" }, "r12" },
3420  { { "r13" }, "sp" },
3421  { { "r14" }, "lr" },
3422  { { "r15" }, "pc" },
3423  // The S, D and Q registers overlap, but aren't really aliases; we
3424  // don't want to substitute one of these for a different-sized one.
3425};
3426
3427void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3428                                       unsigned &NumAliases) const {
3429  Aliases = GCCRegAliases;
3430  NumAliases = llvm::array_lengthof(GCCRegAliases);
3431}
3432
3433const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3434#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3435#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3436                                              ALL_LANGUAGES },
3437#include "clang/Basic/BuiltinsARM.def"
3438};
3439} // end anonymous namespace.
3440
3441namespace {
3442class DarwinARMTargetInfo :
3443  public DarwinTargetInfo<ARMTargetInfo> {
3444protected:
3445  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3446                            MacroBuilder &Builder) const {
3447    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3448  }
3449
3450public:
3451  DarwinARMTargetInfo(const std::string& triple)
3452    : DarwinTargetInfo<ARMTargetInfo>(triple) {
3453    HasAlignMac68kSupport = true;
3454    // iOS always has 64-bit atomic instructions.
3455    // FIXME: This should be based off of the target features in ARMTargetInfo.
3456    MaxAtomicInlineWidth = 64;
3457  }
3458};
3459} // end anonymous namespace.
3460
3461
3462namespace {
3463// Hexagon abstract base class
3464class HexagonTargetInfo : public TargetInfo {
3465  static const Builtin::Info BuiltinInfo[];
3466  static const char * const GCCRegNames[];
3467  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3468  std::string CPU;
3469public:
3470  HexagonTargetInfo(const std::string& triple) : TargetInfo(triple)  {
3471    BigEndian = false;
3472    DescriptionString = ("e-p:32:32:32-"
3473                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32"
3474                         "f64:64:64-f32:32:32-a0:0-n32");
3475
3476    // {} in inline assembly are packet specifiers, not assembly variant
3477    // specifiers.
3478    NoAsmVariants = true;
3479  }
3480
3481  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3482                                 unsigned &NumRecords) const {
3483    Records = BuiltinInfo;
3484    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
3485  }
3486
3487  virtual bool validateAsmConstraint(const char *&Name,
3488                                     TargetInfo::ConstraintInfo &Info) const {
3489    return true;
3490  }
3491
3492  virtual void getTargetDefines(const LangOptions &Opts,
3493                                MacroBuilder &Builder) const;
3494
3495  virtual bool hasFeature(StringRef Feature) const {
3496    return Feature == "hexagon";
3497  }
3498
3499  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3500    return TargetInfo::CharPtrBuiltinVaList;
3501  }
3502  virtual void getGCCRegNames(const char * const *&Names,
3503                              unsigned &NumNames) const;
3504  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3505                                unsigned &NumAliases) const;
3506  virtual const char *getClobbers() const {
3507    return "";
3508  }
3509
3510  static const char *getHexagonCPUSuffix(StringRef Name) {
3511    return llvm::StringSwitch<const char*>(Name)
3512      .Case("hexagonv2", "2")
3513      .Case("hexagonv3", "3")
3514      .Case("hexagonv4", "4")
3515      .Case("hexagonv5", "5")
3516      .Default(0);
3517  }
3518
3519  virtual bool setCPU(const std::string &Name) {
3520    if (!getHexagonCPUSuffix(Name))
3521      return false;
3522
3523    CPU = Name;
3524    return true;
3525  }
3526};
3527
3528void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
3529                                MacroBuilder &Builder) const {
3530  Builder.defineMacro("qdsp6");
3531  Builder.defineMacro("__qdsp6", "1");
3532  Builder.defineMacro("__qdsp6__", "1");
3533
3534  Builder.defineMacro("hexagon");
3535  Builder.defineMacro("__hexagon", "1");
3536  Builder.defineMacro("__hexagon__", "1");
3537
3538  if(CPU == "hexagonv1") {
3539    Builder.defineMacro("__HEXAGON_V1__");
3540    Builder.defineMacro("__HEXAGON_ARCH__", "1");
3541    if(Opts.HexagonQdsp6Compat) {
3542      Builder.defineMacro("__QDSP6_V1__");
3543      Builder.defineMacro("__QDSP6_ARCH__", "1");
3544    }
3545  }
3546  else if(CPU == "hexagonv2") {
3547    Builder.defineMacro("__HEXAGON_V2__");
3548    Builder.defineMacro("__HEXAGON_ARCH__", "2");
3549    if(Opts.HexagonQdsp6Compat) {
3550      Builder.defineMacro("__QDSP6_V2__");
3551      Builder.defineMacro("__QDSP6_ARCH__", "2");
3552    }
3553  }
3554  else if(CPU == "hexagonv3") {
3555    Builder.defineMacro("__HEXAGON_V3__");
3556    Builder.defineMacro("__HEXAGON_ARCH__", "3");
3557    if(Opts.HexagonQdsp6Compat) {
3558      Builder.defineMacro("__QDSP6_V3__");
3559      Builder.defineMacro("__QDSP6_ARCH__", "3");
3560    }
3561  }
3562  else if(CPU == "hexagonv4") {
3563    Builder.defineMacro("__HEXAGON_V4__");
3564    Builder.defineMacro("__HEXAGON_ARCH__", "4");
3565    if(Opts.HexagonQdsp6Compat) {
3566      Builder.defineMacro("__QDSP6_V4__");
3567      Builder.defineMacro("__QDSP6_ARCH__", "4");
3568    }
3569  }
3570  else if(CPU == "hexagonv5") {
3571    Builder.defineMacro("__HEXAGON_V5__");
3572    Builder.defineMacro("__HEXAGON_ARCH__", "5");
3573    if(Opts.HexagonQdsp6Compat) {
3574      Builder.defineMacro("__QDSP6_V5__");
3575      Builder.defineMacro("__QDSP6_ARCH__", "5");
3576    }
3577  }
3578}
3579
3580const char * const HexagonTargetInfo::GCCRegNames[] = {
3581  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3582  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3583  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3584  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
3585  "p0", "p1", "p2", "p3",
3586  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
3587};
3588
3589void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
3590                                   unsigned &NumNames) const {
3591  Names = GCCRegNames;
3592  NumNames = llvm::array_lengthof(GCCRegNames);
3593}
3594
3595
3596const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
3597  { { "sp" }, "r29" },
3598  { { "fp" }, "r30" },
3599  { { "lr" }, "r31" },
3600 };
3601
3602void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3603                                     unsigned &NumAliases) const {
3604  Aliases = GCCRegAliases;
3605  NumAliases = llvm::array_lengthof(GCCRegAliases);
3606}
3607
3608
3609const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
3610#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3611#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3612                                              ALL_LANGUAGES },
3613#include "clang/Basic/BuiltinsHexagon.def"
3614};
3615}
3616
3617
3618namespace {
3619class SparcV8TargetInfo : public TargetInfo {
3620  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3621  static const char * const GCCRegNames[];
3622  bool SoftFloat;
3623public:
3624  SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) {
3625    // FIXME: Support Sparc quad-precision long double?
3626    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3627                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32";
3628  }
3629  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3630                                 StringRef Name,
3631                                 bool Enabled) const {
3632    if (Name == "soft-float")
3633      Features[Name] = Enabled;
3634    else
3635      return false;
3636
3637    return true;
3638  }
3639  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3640    SoftFloat = false;
3641    for (unsigned i = 0, e = Features.size(); i != e; ++i)
3642      if (Features[i] == "+soft-float")
3643        SoftFloat = true;
3644  }
3645  virtual void getTargetDefines(const LangOptions &Opts,
3646                                MacroBuilder &Builder) const {
3647    DefineStd(Builder, "sparc", Opts);
3648    Builder.defineMacro("__sparcv8");
3649    Builder.defineMacro("__REGISTER_PREFIX__", "");
3650
3651    if (SoftFloat)
3652      Builder.defineMacro("SOFT_FLOAT", "1");
3653  }
3654
3655  virtual bool hasFeature(StringRef Feature) const {
3656    return llvm::StringSwitch<bool>(Feature)
3657             .Case("softfloat", SoftFloat)
3658             .Case("sparc", true)
3659             .Default(false);
3660  }
3661
3662  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3663                                 unsigned &NumRecords) const {
3664    // FIXME: Implement!
3665  }
3666  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3667    return TargetInfo::VoidPtrBuiltinVaList;
3668  }
3669  virtual void getGCCRegNames(const char * const *&Names,
3670                              unsigned &NumNames) const;
3671  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3672                                unsigned &NumAliases) const;
3673  virtual bool validateAsmConstraint(const char *&Name,
3674                                     TargetInfo::ConstraintInfo &info) const {
3675    // FIXME: Implement!
3676    return false;
3677  }
3678  virtual const char *getClobbers() const {
3679    // FIXME: Implement!
3680    return "";
3681  }
3682};
3683
3684const char * const SparcV8TargetInfo::GCCRegNames[] = {
3685  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3686  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3687  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3688  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3689};
3690
3691void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names,
3692                                       unsigned &NumNames) const {
3693  Names = GCCRegNames;
3694  NumNames = llvm::array_lengthof(GCCRegNames);
3695}
3696
3697const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = {
3698  { { "g0" }, "r0" },
3699  { { "g1" }, "r1" },
3700  { { "g2" }, "r2" },
3701  { { "g3" }, "r3" },
3702  { { "g4" }, "r4" },
3703  { { "g5" }, "r5" },
3704  { { "g6" }, "r6" },
3705  { { "g7" }, "r7" },
3706  { { "o0" }, "r8" },
3707  { { "o1" }, "r9" },
3708  { { "o2" }, "r10" },
3709  { { "o3" }, "r11" },
3710  { { "o4" }, "r12" },
3711  { { "o5" }, "r13" },
3712  { { "o6", "sp" }, "r14" },
3713  { { "o7" }, "r15" },
3714  { { "l0" }, "r16" },
3715  { { "l1" }, "r17" },
3716  { { "l2" }, "r18" },
3717  { { "l3" }, "r19" },
3718  { { "l4" }, "r20" },
3719  { { "l5" }, "r21" },
3720  { { "l6" }, "r22" },
3721  { { "l7" }, "r23" },
3722  { { "i0" }, "r24" },
3723  { { "i1" }, "r25" },
3724  { { "i2" }, "r26" },
3725  { { "i3" }, "r27" },
3726  { { "i4" }, "r28" },
3727  { { "i5" }, "r29" },
3728  { { "i6", "fp" }, "r30" },
3729  { { "i7" }, "r31" },
3730};
3731
3732void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3733                                         unsigned &NumAliases) const {
3734  Aliases = GCCRegAliases;
3735  NumAliases = llvm::array_lengthof(GCCRegAliases);
3736}
3737} // end anonymous namespace.
3738
3739namespace {
3740class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
3741public:
3742  AuroraUXSparcV8TargetInfo(const std::string& triple) :
3743      AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
3744    SizeType = UnsignedInt;
3745    PtrDiffType = SignedInt;
3746  }
3747};
3748class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
3749public:
3750  SolarisSparcV8TargetInfo(const std::string& triple) :
3751      SolarisTargetInfo<SparcV8TargetInfo>(triple) {
3752    SizeType = UnsignedInt;
3753    PtrDiffType = SignedInt;
3754  }
3755};
3756} // end anonymous namespace.
3757
3758namespace {
3759  class MSP430TargetInfo : public TargetInfo {
3760    static const char * const GCCRegNames[];
3761  public:
3762    MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
3763      BigEndian = false;
3764      TLSSupported = false;
3765      IntWidth = 16; IntAlign = 16;
3766      LongWidth = 32; LongLongWidth = 64;
3767      LongAlign = LongLongAlign = 16;
3768      PointerWidth = 16; PointerAlign = 16;
3769      SuitableAlign = 16;
3770      SizeType = UnsignedInt;
3771      IntMaxType = SignedLong;
3772      UIntMaxType = UnsignedLong;
3773      IntPtrType = SignedShort;
3774      PtrDiffType = SignedInt;
3775      SigAtomicType = SignedLong;
3776      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
3777   }
3778    virtual void getTargetDefines(const LangOptions &Opts,
3779                                  MacroBuilder &Builder) const {
3780      Builder.defineMacro("MSP430");
3781      Builder.defineMacro("__MSP430__");
3782      // FIXME: defines for different 'flavours' of MCU
3783    }
3784    virtual void getTargetBuiltins(const Builtin::Info *&Records,
3785                                   unsigned &NumRecords) const {
3786     // FIXME: Implement.
3787      Records = 0;
3788      NumRecords = 0;
3789    }
3790    virtual bool hasFeature(StringRef Feature) const {
3791      return Feature == "msp430";
3792    }
3793    virtual void getGCCRegNames(const char * const *&Names,
3794                                unsigned &NumNames) const;
3795    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3796                                  unsigned &NumAliases) const {
3797      // No aliases.
3798      Aliases = 0;
3799      NumAliases = 0;
3800    }
3801    virtual bool validateAsmConstraint(const char *&Name,
3802                                       TargetInfo::ConstraintInfo &info) const {
3803      // No target constraints for now.
3804      return false;
3805    }
3806    virtual const char *getClobbers() const {
3807      // FIXME: Is this really right?
3808      return "";
3809    }
3810    virtual BuiltinVaListKind getBuiltinVaListKind() const {
3811      // FIXME: implement
3812      return TargetInfo::CharPtrBuiltinVaList;
3813   }
3814  };
3815
3816  const char * const MSP430TargetInfo::GCCRegNames[] = {
3817    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3818    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3819  };
3820
3821  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
3822                                        unsigned &NumNames) const {
3823    Names = GCCRegNames;
3824    NumNames = llvm::array_lengthof(GCCRegNames);
3825  }
3826}
3827
3828namespace {
3829
3830  // LLVM and Clang cannot be used directly to output native binaries for
3831  // target, but is used to compile C code to llvm bitcode with correct
3832  // type and alignment information.
3833  //
3834  // TCE uses the llvm bitcode as input and uses it for generating customized
3835  // target processor and program binary. TCE co-design environment is
3836  // publicly available in http://tce.cs.tut.fi
3837
3838  static const unsigned TCEOpenCLAddrSpaceMap[] = {
3839      3, // opencl_global
3840      4, // opencl_local
3841      5, // opencl_constant
3842      0, // cuda_device
3843      0, // cuda_constant
3844      0  // cuda_shared
3845  };
3846
3847  class TCETargetInfo : public TargetInfo{
3848  public:
3849    TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
3850      TLSSupported = false;
3851      IntWidth = 32;
3852      LongWidth = LongLongWidth = 32;
3853      PointerWidth = 32;
3854      IntAlign = 32;
3855      LongAlign = LongLongAlign = 32;
3856      PointerAlign = 32;
3857      SuitableAlign = 32;
3858      SizeType = UnsignedInt;
3859      IntMaxType = SignedLong;
3860      UIntMaxType = UnsignedLong;
3861      IntPtrType = SignedInt;
3862      PtrDiffType = SignedInt;
3863      FloatWidth = 32;
3864      FloatAlign = 32;
3865      DoubleWidth = 32;
3866      DoubleAlign = 32;
3867      LongDoubleWidth = 32;
3868      LongDoubleAlign = 32;
3869      FloatFormat = &llvm::APFloat::IEEEsingle;
3870      DoubleFormat = &llvm::APFloat::IEEEsingle;
3871      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
3872      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
3873                          "i16:16:32-i32:32:32-i64:32:32-"
3874                          "f32:32:32-f64:32:32-v64:32:32-"
3875                          "v128:32:32-a0:0:32-n32";
3876      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
3877    }
3878
3879    virtual void getTargetDefines(const LangOptions &Opts,
3880                                  MacroBuilder &Builder) const {
3881      DefineStd(Builder, "tce", Opts);
3882      Builder.defineMacro("__TCE__");
3883      Builder.defineMacro("__TCE_V1__");
3884    }
3885    virtual bool hasFeature(StringRef Feature) const {
3886      return Feature == "tce";
3887    }
3888
3889    virtual void getTargetBuiltins(const Builtin::Info *&Records,
3890                                   unsigned &NumRecords) const {}
3891    virtual const char *getClobbers() const {
3892      return "";
3893    }
3894    virtual BuiltinVaListKind getBuiltinVaListKind() const {
3895      return TargetInfo::VoidPtrBuiltinVaList;
3896    }
3897    virtual void getGCCRegNames(const char * const *&Names,
3898                                unsigned &NumNames) const {}
3899    virtual bool validateAsmConstraint(const char *&Name,
3900                                       TargetInfo::ConstraintInfo &info) const {
3901      return true;
3902    }
3903    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3904                                  unsigned &NumAliases) const {}
3905  };
3906}
3907
3908namespace {
3909class MipsTargetInfoBase : public TargetInfo {
3910  static const Builtin::Info BuiltinInfo[];
3911  std::string CPU;
3912  bool IsMips16;
3913  enum MipsFloatABI {
3914    HardFloat, SingleFloat, SoftFloat
3915  } FloatABI;
3916  enum DspRevEnum {
3917    NoDSP, DSP1, DSP2
3918  } DspRev;
3919
3920protected:
3921  std::string ABI;
3922
3923public:
3924  MipsTargetInfoBase(const std::string& triple,
3925                     const std::string& ABIStr,
3926                     const std::string& CPUStr)
3927    : TargetInfo(triple),
3928      CPU(CPUStr),
3929      IsMips16(false),
3930      FloatABI(HardFloat),
3931      DspRev(NoDSP),
3932      ABI(ABIStr)
3933  {}
3934
3935  virtual const char *getABI() const { return ABI.c_str(); }
3936  virtual bool setABI(const std::string &Name) = 0;
3937  virtual bool setCPU(const std::string &Name) {
3938    CPU = Name;
3939    return true;
3940  }
3941  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3942    Features[ABI] = true;
3943    Features[CPU] = true;
3944  }
3945
3946  virtual void getTargetDefines(const LangOptions &Opts,
3947                                MacroBuilder &Builder) const {
3948    DefineStd(Builder, "mips", Opts);
3949    Builder.defineMacro("_mips");
3950    Builder.defineMacro("__REGISTER_PREFIX__", "");
3951
3952    switch (FloatABI) {
3953    case HardFloat:
3954      Builder.defineMacro("__mips_hard_float", Twine(1));
3955      break;
3956    case SingleFloat:
3957      Builder.defineMacro("__mips_hard_float", Twine(1));
3958      Builder.defineMacro("__mips_single_float", Twine(1));
3959      break;
3960    case SoftFloat:
3961      Builder.defineMacro("__mips_soft_float", Twine(1));
3962      break;
3963    }
3964
3965    if (IsMips16)
3966      Builder.defineMacro("__mips16", Twine(1));
3967
3968    switch (DspRev) {
3969    default:
3970      break;
3971    case DSP1:
3972      Builder.defineMacro("__mips_dsp_rev", Twine(1));
3973      Builder.defineMacro("__mips_dsp", Twine(1));
3974      break;
3975    case DSP2:
3976      Builder.defineMacro("__mips_dsp_rev", Twine(2));
3977      Builder.defineMacro("__mips_dspr2", Twine(1));
3978      Builder.defineMacro("__mips_dsp", Twine(1));
3979      break;
3980    }
3981
3982    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
3983    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
3984    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
3985
3986    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
3987    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
3988  }
3989
3990  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3991                                 unsigned &NumRecords) const {
3992    Records = BuiltinInfo;
3993    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
3994  }
3995  virtual bool hasFeature(StringRef Feature) const {
3996    return Feature == "mips";
3997  }
3998  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3999    return TargetInfo::VoidPtrBuiltinVaList;
4000  }
4001  virtual void getGCCRegNames(const char * const *&Names,
4002                              unsigned &NumNames) const {
4003    static const char * const GCCRegNames[] = {
4004      // CPU register names
4005      // Must match second column of GCCRegAliases
4006      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4007      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4008      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4009      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4010      // Floating point register names
4011      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4012      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4013      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4014      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4015      // Hi/lo and condition register names
4016      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4017      "$fcc5","$fcc6","$fcc7"
4018    };
4019    Names = GCCRegNames;
4020    NumNames = llvm::array_lengthof(GCCRegNames);
4021  }
4022  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4023                                unsigned &NumAliases) const = 0;
4024  virtual bool validateAsmConstraint(const char *&Name,
4025                                     TargetInfo::ConstraintInfo &Info) const {
4026    switch (*Name) {
4027    default:
4028      return false;
4029
4030    case 'r': // CPU registers.
4031    case 'd': // Equivalent to "r" unless generating MIPS16 code.
4032    case 'y': // Equivalent to "r", backwards compatibility only.
4033    case 'f': // floating-point registers.
4034    case 'c': // $25 for indirect jumps
4035    case 'l': // lo register
4036    case 'x': // hilo register pair
4037      Info.setAllowsRegister();
4038      return true;
4039    }
4040  }
4041
4042  virtual const char *getClobbers() const {
4043    // FIXME: Implement!
4044    return "";
4045  }
4046
4047  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4048                                 StringRef Name,
4049                                 bool Enabled) const {
4050    if (Name == "soft-float" || Name == "single-float" ||
4051        Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4052        Name == "mips32" || Name == "mips32r2" ||
4053        Name == "mips64" || Name == "mips64r2" ||
4054        Name == "mips16" || Name == "dsp" || Name == "dspr2") {
4055      Features[Name] = Enabled;
4056      return true;
4057    }
4058    return false;
4059  }
4060
4061  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4062    IsMips16 = false;
4063    FloatABI = HardFloat;
4064    DspRev = NoDSP;
4065
4066    for (std::vector<std::string>::iterator it = Features.begin(),
4067         ie = Features.end(); it != ie; ++it) {
4068      if (*it == "+single-float")
4069        FloatABI = SingleFloat;
4070      else if (*it == "+soft-float")
4071        FloatABI = SoftFloat;
4072      else if (*it == "+mips16")
4073        IsMips16 = true;
4074      else if (*it == "+dsp")
4075        DspRev = std::max(DspRev, DSP1);
4076      else if (*it == "+dspr2")
4077        DspRev = std::max(DspRev, DSP2);
4078    }
4079
4080    // Remove front-end specific option.
4081    std::vector<std::string>::iterator it =
4082      std::find(Features.begin(), Features.end(), "+soft-float");
4083    if (it != Features.end())
4084      Features.erase(it);
4085  }
4086};
4087
4088const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4089#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4090#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4091                                              ALL_LANGUAGES },
4092#include "clang/Basic/BuiltinsMips.def"
4093};
4094
4095class Mips32TargetInfoBase : public MipsTargetInfoBase {
4096public:
4097  Mips32TargetInfoBase(const std::string& triple) :
4098    MipsTargetInfoBase(triple, "o32", "mips32") {
4099    SizeType = UnsignedInt;
4100    PtrDiffType = SignedInt;
4101  }
4102  virtual bool setABI(const std::string &Name) {
4103    if ((Name == "o32") || (Name == "eabi")) {
4104      ABI = Name;
4105      return true;
4106    } else
4107      return false;
4108  }
4109  virtual void getTargetDefines(const LangOptions &Opts,
4110                                MacroBuilder &Builder) const {
4111    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4112
4113    if (ABI == "o32") {
4114      Builder.defineMacro("__mips_o32");
4115      Builder.defineMacro("_ABIO32", "1");
4116      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4117    }
4118    else if (ABI == "eabi")
4119      Builder.defineMacro("__mips_eabi");
4120    else
4121      llvm_unreachable("Invalid ABI for Mips32.");
4122  }
4123  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4124                                unsigned &NumAliases) const {
4125    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4126      { { "at" },  "$1" },
4127      { { "v0" },  "$2" },
4128      { { "v1" },  "$3" },
4129      { { "a0" },  "$4" },
4130      { { "a1" },  "$5" },
4131      { { "a2" },  "$6" },
4132      { { "a3" },  "$7" },
4133      { { "t0" },  "$8" },
4134      { { "t1" },  "$9" },
4135      { { "t2" }, "$10" },
4136      { { "t3" }, "$11" },
4137      { { "t4" }, "$12" },
4138      { { "t5" }, "$13" },
4139      { { "t6" }, "$14" },
4140      { { "t7" }, "$15" },
4141      { { "s0" }, "$16" },
4142      { { "s1" }, "$17" },
4143      { { "s2" }, "$18" },
4144      { { "s3" }, "$19" },
4145      { { "s4" }, "$20" },
4146      { { "s5" }, "$21" },
4147      { { "s6" }, "$22" },
4148      { { "s7" }, "$23" },
4149      { { "t8" }, "$24" },
4150      { { "t9" }, "$25" },
4151      { { "k0" }, "$26" },
4152      { { "k1" }, "$27" },
4153      { { "gp" }, "$28" },
4154      { { "sp","$sp" }, "$29" },
4155      { { "fp","$fp" }, "$30" },
4156      { { "ra" }, "$31" }
4157    };
4158    Aliases = GCCRegAliases;
4159    NumAliases = llvm::array_lengthof(GCCRegAliases);
4160  }
4161};
4162
4163class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4164public:
4165  Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4166    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4167                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32";
4168  }
4169  virtual void getTargetDefines(const LangOptions &Opts,
4170                                MacroBuilder &Builder) const {
4171    DefineStd(Builder, "MIPSEB", Opts);
4172    Builder.defineMacro("_MIPSEB");
4173    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4174  }
4175};
4176
4177class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4178public:
4179  Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4180    BigEndian = false;
4181    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4182                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32";
4183  }
4184  virtual void getTargetDefines(const LangOptions &Opts,
4185                                MacroBuilder &Builder) const {
4186    DefineStd(Builder, "MIPSEL", Opts);
4187    Builder.defineMacro("_MIPSEL");
4188    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4189  }
4190};
4191
4192class Mips64TargetInfoBase : public MipsTargetInfoBase {
4193  virtual void SetDescriptionString(const std::string &Name) = 0;
4194public:
4195  Mips64TargetInfoBase(const std::string& triple) :
4196    MipsTargetInfoBase(triple, "n64", "mips64") {
4197    LongWidth = LongAlign = 64;
4198    PointerWidth = PointerAlign = 64;
4199    LongDoubleWidth = LongDoubleAlign = 128;
4200    LongDoubleFormat = &llvm::APFloat::IEEEquad;
4201    SuitableAlign = 128;
4202  }
4203  virtual bool setABI(const std::string &Name) {
4204    SetDescriptionString(Name);
4205
4206    if (Name != "n32" && Name != "n64")
4207      return false;
4208
4209    ABI = Name;
4210
4211    if (Name == "n32") {
4212      LongWidth = LongAlign = 32;
4213      PointerWidth = PointerAlign = 32;
4214    }
4215
4216    return true;
4217  }
4218  virtual void getTargetDefines(const LangOptions &Opts,
4219                                MacroBuilder &Builder) const {
4220    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4221
4222    Builder.defineMacro("__mips64");
4223    Builder.defineMacro("__mips64__");
4224
4225    if (ABI == "n32") {
4226      Builder.defineMacro("__mips_n32");
4227      Builder.defineMacro("_ABIN32", "2");
4228      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4229    }
4230    else if (ABI == "n64") {
4231      Builder.defineMacro("__mips_n64");
4232      Builder.defineMacro("_ABI64", "3");
4233      Builder.defineMacro("_MIPS_SIM", "_ABI64");
4234    }
4235    else
4236      llvm_unreachable("Invalid ABI for Mips64.");
4237  }
4238  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4239                                unsigned &NumAliases) const {
4240    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4241      { { "at" },  "$1" },
4242      { { "v0" },  "$2" },
4243      { { "v1" },  "$3" },
4244      { { "a0" },  "$4" },
4245      { { "a1" },  "$5" },
4246      { { "a2" },  "$6" },
4247      { { "a3" },  "$7" },
4248      { { "a4" },  "$8" },
4249      { { "a5" },  "$9" },
4250      { { "a6" }, "$10" },
4251      { { "a7" }, "$11" },
4252      { { "t0" }, "$12" },
4253      { { "t1" }, "$13" },
4254      { { "t2" }, "$14" },
4255      { { "t3" }, "$15" },
4256      { { "s0" }, "$16" },
4257      { { "s1" }, "$17" },
4258      { { "s2" }, "$18" },
4259      { { "s3" }, "$19" },
4260      { { "s4" }, "$20" },
4261      { { "s5" }, "$21" },
4262      { { "s6" }, "$22" },
4263      { { "s7" }, "$23" },
4264      { { "t8" }, "$24" },
4265      { { "t9" }, "$25" },
4266      { { "k0" }, "$26" },
4267      { { "k1" }, "$27" },
4268      { { "gp" }, "$28" },
4269      { { "sp","$sp" }, "$29" },
4270      { { "fp","$fp" }, "$30" },
4271      { { "ra" }, "$31" }
4272    };
4273    Aliases = GCCRegAliases;
4274    NumAliases = llvm::array_lengthof(GCCRegAliases);
4275  }
4276};
4277
4278class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4279  virtual void SetDescriptionString(const std::string &Name) {
4280    // Change DescriptionString only if ABI is n32.
4281    if (Name == "n32")
4282      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4283                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4284                          "v64:64:64-n32";
4285  }
4286public:
4287  Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4288    // Default ABI is n64.
4289    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4290                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4291                        "v64:64:64-n32";
4292  }
4293  virtual void getTargetDefines(const LangOptions &Opts,
4294                                MacroBuilder &Builder) const {
4295    DefineStd(Builder, "MIPSEB", Opts);
4296    Builder.defineMacro("_MIPSEB");
4297    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4298  }
4299};
4300
4301class Mips64ELTargetInfo : public Mips64TargetInfoBase {
4302  virtual void SetDescriptionString(const std::string &Name) {
4303    // Change DescriptionString only if ABI is n32.
4304    if (Name == "n32")
4305      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4306                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
4307                          "-v64:64:64-n32";
4308  }
4309public:
4310  Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4311    // Default ABI is n64.
4312    BigEndian = false;
4313    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4314                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4315                        "v64:64:64-n32";
4316  }
4317  virtual void getTargetDefines(const LangOptions &Opts,
4318                                MacroBuilder &Builder) const {
4319    DefineStd(Builder, "MIPSEL", Opts);
4320    Builder.defineMacro("_MIPSEL");
4321    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4322  }
4323};
4324} // end anonymous namespace.
4325
4326namespace {
4327class PNaClTargetInfo : public TargetInfo {
4328public:
4329  PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
4330    BigEndian = false;
4331    this->UserLabelPrefix = "";
4332    this->LongAlign = 32;
4333    this->LongWidth = 32;
4334    this->PointerAlign = 32;
4335    this->PointerWidth = 32;
4336    this->IntMaxType = TargetInfo::SignedLongLong;
4337    this->UIntMaxType = TargetInfo::UnsignedLongLong;
4338    this->Int64Type = TargetInfo::SignedLongLong;
4339    this->DoubleAlign = 64;
4340    this->LongDoubleWidth = 64;
4341    this->LongDoubleAlign = 64;
4342    this->SizeType = TargetInfo::UnsignedInt;
4343    this->PtrDiffType = TargetInfo::SignedInt;
4344    this->IntPtrType = TargetInfo::SignedInt;
4345    this->RegParmMax = 2;
4346    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4347                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
4348  }
4349
4350  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4351  }
4352  virtual void getArchDefines(const LangOptions &Opts,
4353                              MacroBuilder &Builder) const {
4354    Builder.defineMacro("__le32__");
4355    Builder.defineMacro("__pnacl__");
4356  }
4357  virtual void getTargetDefines(const LangOptions &Opts,
4358                                MacroBuilder &Builder) const {
4359    Builder.defineMacro("__LITTLE_ENDIAN__");
4360    getArchDefines(Opts, Builder);
4361  }
4362  virtual bool hasFeature(StringRef Feature) const {
4363    return Feature == "pnacl";
4364  }
4365  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4366                                 unsigned &NumRecords) const {
4367  }
4368  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4369    return TargetInfo::PNaClABIBuiltinVaList;
4370  }
4371  virtual void getGCCRegNames(const char * const *&Names,
4372                              unsigned &NumNames) const;
4373  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4374                                unsigned &NumAliases) const;
4375  virtual bool validateAsmConstraint(const char *&Name,
4376                                     TargetInfo::ConstraintInfo &Info) const {
4377    return false;
4378  }
4379
4380  virtual const char *getClobbers() const {
4381    return "";
4382  }
4383};
4384
4385void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
4386                                     unsigned &NumNames) const {
4387  Names = NULL;
4388  NumNames = 0;
4389}
4390
4391void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4392                                       unsigned &NumAliases) const {
4393  Aliases = NULL;
4394  NumAliases = 0;
4395}
4396} // end anonymous namespace.
4397
4398
4399//===----------------------------------------------------------------------===//
4400// Driver code
4401//===----------------------------------------------------------------------===//
4402
4403static TargetInfo *AllocateTarget(const std::string &T) {
4404  llvm::Triple Triple(T);
4405  llvm::Triple::OSType os = Triple.getOS();
4406
4407  switch (Triple.getArch()) {
4408  default:
4409    return NULL;
4410
4411  case llvm::Triple::hexagon:
4412    return new HexagonTargetInfo(T);
4413
4414  case llvm::Triple::arm:
4415  case llvm::Triple::thumb:
4416    if (Triple.isOSDarwin())
4417      return new DarwinARMTargetInfo(T);
4418
4419    switch (os) {
4420    case llvm::Triple::Linux:
4421      return new LinuxTargetInfo<ARMTargetInfo>(T);
4422    case llvm::Triple::FreeBSD:
4423      return new FreeBSDTargetInfo<ARMTargetInfo>(T);
4424    case llvm::Triple::NetBSD:
4425      return new NetBSDTargetInfo<ARMTargetInfo>(T);
4426    case llvm::Triple::OpenBSD:
4427      return new OpenBSDTargetInfo<ARMTargetInfo>(T);
4428    case llvm::Triple::Bitrig:
4429      return new BitrigTargetInfo<ARMTargetInfo>(T);
4430    case llvm::Triple::RTEMS:
4431      return new RTEMSTargetInfo<ARMTargetInfo>(T);
4432    case llvm::Triple::NativeClient:
4433      return new NaClTargetInfo<ARMTargetInfo>(T);
4434    default:
4435      return new ARMTargetInfo(T);
4436    }
4437
4438  case llvm::Triple::msp430:
4439    return new MSP430TargetInfo(T);
4440
4441  case llvm::Triple::mips:
4442    switch (os) {
4443    case llvm::Triple::Linux:
4444      return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
4445    case llvm::Triple::RTEMS:
4446      return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
4447    case llvm::Triple::FreeBSD:
4448      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
4449    case llvm::Triple::NetBSD:
4450      return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
4451    default:
4452      return new Mips32EBTargetInfo(T);
4453    }
4454
4455  case llvm::Triple::mipsel:
4456    switch (os) {
4457    case llvm::Triple::Linux:
4458      return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
4459    case llvm::Triple::RTEMS:
4460      return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
4461    case llvm::Triple::FreeBSD:
4462      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
4463    case llvm::Triple::NetBSD:
4464      return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
4465    default:
4466      return new Mips32ELTargetInfo(T);
4467    }
4468
4469  case llvm::Triple::mips64:
4470    switch (os) {
4471    case llvm::Triple::Linux:
4472      return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
4473    case llvm::Triple::RTEMS:
4474      return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
4475    case llvm::Triple::FreeBSD:
4476      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
4477    case llvm::Triple::NetBSD:
4478      return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
4479    case llvm::Triple::OpenBSD:
4480      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
4481    default:
4482      return new Mips64EBTargetInfo(T);
4483    }
4484
4485  case llvm::Triple::mips64el:
4486    switch (os) {
4487    case llvm::Triple::Linux:
4488      return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
4489    case llvm::Triple::RTEMS:
4490      return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
4491    case llvm::Triple::FreeBSD:
4492      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
4493    case llvm::Triple::NetBSD:
4494      return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
4495    case llvm::Triple::OpenBSD:
4496      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
4497    default:
4498      return new Mips64ELTargetInfo(T);
4499    }
4500
4501  case llvm::Triple::le32:
4502    switch (os) {
4503      case llvm::Triple::NativeClient:
4504        return new NaClTargetInfo<PNaClTargetInfo>(T);
4505      default:
4506        return NULL;
4507    }
4508
4509  case llvm::Triple::ppc:
4510    if (Triple.isOSDarwin())
4511      return new DarwinPPC32TargetInfo(T);
4512    switch (os) {
4513    case llvm::Triple::Linux:
4514      return new LinuxTargetInfo<PPC32TargetInfo>(T);
4515    case llvm::Triple::FreeBSD:
4516      return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
4517    case llvm::Triple::NetBSD:
4518      return new NetBSDTargetInfo<PPC32TargetInfo>(T);
4519    case llvm::Triple::OpenBSD:
4520      return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
4521    case llvm::Triple::RTEMS:
4522      return new RTEMSTargetInfo<PPC32TargetInfo>(T);
4523    default:
4524      return new PPC32TargetInfo(T);
4525    }
4526
4527  case llvm::Triple::ppc64:
4528    if (Triple.isOSDarwin())
4529      return new DarwinPPC64TargetInfo(T);
4530    switch (os) {
4531    case llvm::Triple::Linux:
4532      return new LinuxTargetInfo<PPC64TargetInfo>(T);
4533    case llvm::Triple::Lv2:
4534      return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
4535    case llvm::Triple::FreeBSD:
4536      return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
4537    case llvm::Triple::NetBSD:
4538      return new NetBSDTargetInfo<PPC64TargetInfo>(T);
4539    default:
4540      return new PPC64TargetInfo(T);
4541    }
4542
4543  case llvm::Triple::nvptx:
4544    return new NVPTX32TargetInfo(T);
4545  case llvm::Triple::nvptx64:
4546    return new NVPTX64TargetInfo(T);
4547
4548  case llvm::Triple::mblaze:
4549    return new MBlazeTargetInfo(T);
4550
4551  case llvm::Triple::r600:
4552    return new R600TargetInfo(T);
4553
4554  case llvm::Triple::sparc:
4555    switch (os) {
4556    case llvm::Triple::Linux:
4557      return new LinuxTargetInfo<SparcV8TargetInfo>(T);
4558    case llvm::Triple::AuroraUX:
4559      return new AuroraUXSparcV8TargetInfo(T);
4560    case llvm::Triple::Solaris:
4561      return new SolarisSparcV8TargetInfo(T);
4562    case llvm::Triple::NetBSD:
4563      return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
4564    case llvm::Triple::OpenBSD:
4565      return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
4566    case llvm::Triple::RTEMS:
4567      return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
4568    default:
4569      return new SparcV8TargetInfo(T);
4570    }
4571
4572  case llvm::Triple::tce:
4573    return new TCETargetInfo(T);
4574
4575  case llvm::Triple::x86:
4576    if (Triple.isOSDarwin())
4577      return new DarwinI386TargetInfo(T);
4578
4579    switch (os) {
4580    case llvm::Triple::AuroraUX:
4581      return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
4582    case llvm::Triple::Linux:
4583      return new LinuxTargetInfo<X86_32TargetInfo>(T);
4584    case llvm::Triple::DragonFly:
4585      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
4586    case llvm::Triple::NetBSD:
4587      return new NetBSDI386TargetInfo(T);
4588    case llvm::Triple::OpenBSD:
4589      return new OpenBSDI386TargetInfo(T);
4590    case llvm::Triple::Bitrig:
4591      return new BitrigI386TargetInfo(T);
4592    case llvm::Triple::FreeBSD:
4593      return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
4594    case llvm::Triple::Minix:
4595      return new MinixTargetInfo<X86_32TargetInfo>(T);
4596    case llvm::Triple::Solaris:
4597      return new SolarisTargetInfo<X86_32TargetInfo>(T);
4598    case llvm::Triple::Cygwin:
4599      return new CygwinX86_32TargetInfo(T);
4600    case llvm::Triple::MinGW32:
4601      return new MinGWX86_32TargetInfo(T);
4602    case llvm::Triple::Win32:
4603      return new VisualStudioWindowsX86_32TargetInfo(T);
4604    case llvm::Triple::Haiku:
4605      return new HaikuX86_32TargetInfo(T);
4606    case llvm::Triple::RTEMS:
4607      return new RTEMSX86_32TargetInfo(T);
4608    case llvm::Triple::NativeClient:
4609      return new NaClTargetInfo<X86_32TargetInfo>(T);
4610    default:
4611      return new X86_32TargetInfo(T);
4612    }
4613
4614  case llvm::Triple::x86_64:
4615    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
4616      return new DarwinX86_64TargetInfo(T);
4617
4618    switch (os) {
4619    case llvm::Triple::AuroraUX:
4620      return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
4621    case llvm::Triple::Linux:
4622      return new LinuxTargetInfo<X86_64TargetInfo>(T);
4623    case llvm::Triple::DragonFly:
4624      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
4625    case llvm::Triple::NetBSD:
4626      return new NetBSDTargetInfo<X86_64TargetInfo>(T);
4627    case llvm::Triple::OpenBSD:
4628      return new OpenBSDX86_64TargetInfo(T);
4629    case llvm::Triple::Bitrig:
4630      return new BitrigX86_64TargetInfo(T);
4631    case llvm::Triple::FreeBSD:
4632      return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
4633    case llvm::Triple::Solaris:
4634      return new SolarisTargetInfo<X86_64TargetInfo>(T);
4635    case llvm::Triple::MinGW32:
4636      return new MinGWX86_64TargetInfo(T);
4637    case llvm::Triple::Win32:   // This is what Triple.h supports now.
4638      return new VisualStudioWindowsX86_64TargetInfo(T);
4639    case llvm::Triple::NativeClient:
4640      return new NaClTargetInfo<X86_64TargetInfo>(T);
4641    default:
4642      return new X86_64TargetInfo(T);
4643    }
4644  }
4645}
4646
4647/// CreateTargetInfo - Return the target info object for the specified target
4648/// triple.
4649TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
4650                                         TargetOptions *Opts) {
4651  llvm::Triple Triple(Opts->Triple);
4652
4653  // Construct the target
4654  OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
4655  if (!Target) {
4656    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
4657    return 0;
4658  }
4659  Target->setTargetOpts(Opts);
4660
4661  // Set the target CPU if specified.
4662  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
4663    Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
4664    return 0;
4665  }
4666
4667  // Set the target ABI if specified.
4668  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
4669    Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
4670    return 0;
4671  }
4672
4673  // Set the target C++ ABI.
4674  if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
4675    Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
4676    return 0;
4677  }
4678
4679  // Compute the default target features, we need the target to handle this
4680  // because features may have dependencies on one another.
4681  llvm::StringMap<bool> Features;
4682  Target->getDefaultFeatures(Features);
4683
4684  // Apply the user specified deltas.
4685  // First the enables.
4686  for (std::vector<std::string>::const_iterator
4687         it = Opts->FeaturesAsWritten.begin(),
4688         ie = Opts->FeaturesAsWritten.end();
4689       it != ie; ++it) {
4690    const char *Name = it->c_str();
4691
4692    if (Name[0] != '+')
4693      continue;
4694
4695    // Apply the feature via the target.
4696    if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
4697      Diags.Report(diag::err_target_invalid_feature) << Name;
4698      return 0;
4699    }
4700  }
4701
4702  // Then the disables.
4703  for (std::vector<std::string>::const_iterator
4704         it = Opts->FeaturesAsWritten.begin(),
4705         ie = Opts->FeaturesAsWritten.end();
4706       it != ie; ++it) {
4707    const char *Name = it->c_str();
4708
4709    if (Name[0] == '+')
4710      continue;
4711
4712    // Apply the feature via the target.
4713    if (Name[0] != '-' ||
4714        !Target->setFeatureEnabled(Features, Name + 1, false)) {
4715      Diags.Report(diag::err_target_invalid_feature) << Name;
4716      return 0;
4717    }
4718  }
4719
4720  // Add the features to the compile options.
4721  //
4722  // FIXME: If we are completely confident that we have the right set, we only
4723  // need to pass the minuses.
4724  Opts->Features.clear();
4725  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
4726         ie = Features.end(); it != ie; ++it)
4727    Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
4728  Target->HandleTargetFeatures(Opts->Features);
4729
4730  return Target.take();
4731}
4732