Targets.cpp revision 7185d6272b8dc75d5492a6ea0ed43d7631554b61 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "5621");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.getOS() == llvm::Triple::IOS) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else {
153    // Note that the Driver allows versions which aren't representable in the
154    // define (because we only get a single digit for the minor and micro
155    // revision numbers). So, we limit them to the maximum representable
156    // version.
157    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159    char Str[5];
160    Str[0] = '0' + (Maj / 10);
161    Str[1] = '0' + (Maj % 10);
162    Str[2] = '0' + std::min(Min, 9U);
163    Str[3] = '0' + std::min(Rev, 9U);
164    Str[4] = '\0';
165    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166  }
167
168  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169}
170
171namespace {
172template<typename Target>
173class DarwinTargetInfo : public OSTargetInfo<Target> {
174protected:
175  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                            MacroBuilder &Builder) const {
177    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                     this->PlatformMinVersion);
179  }
180
181public:
182  DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
183    this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
184    this->MCountName = "\01mcount";
185  }
186
187  virtual std::string isValidSectionSpecifier(StringRef SR) const {
188    // Let MCSectionMachO validate this.
189    StringRef Segment, Section;
190    unsigned TAA, StubSize;
191    bool HasTAA;
192    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
193                                                       TAA, HasTAA, StubSize);
194  }
195
196  virtual const char *getStaticInitSectionSpecifier() const {
197    // FIXME: We should return 0 when building kexts.
198    return "__TEXT,__StaticInit,regular,pure_instructions";
199  }
200
201  /// Darwin does not support protected visibility.  Darwin's "default"
202  /// is very similar to ELF's "protected";  Darwin requires a "weak"
203  /// attribute on declarations that can be dynamically replaced.
204  virtual bool hasProtectedVisibility() const {
205    return false;
206  }
207};
208
209
210// DragonFlyBSD Target
211template<typename Target>
212class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
213protected:
214  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
215                            MacroBuilder &Builder) const {
216    // DragonFly defines; list based off of gcc output
217    Builder.defineMacro("__DragonFly__");
218    Builder.defineMacro("__DragonFly_cc_version", "100001");
219    Builder.defineMacro("__ELF__");
220    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
221    Builder.defineMacro("__tune_i386__");
222    DefineStd(Builder, "unix", Opts);
223  }
224public:
225  DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
226      : OSTargetInfo<Target>(Triple) {
227    this->UserLabelPrefix = "";
228
229    switch (Triple.getArch()) {
230    default:
231    case llvm::Triple::x86:
232    case llvm::Triple::x86_64:
233      this->MCountName = ".mcount";
234      break;
235    }
236  }
237};
238
239// FreeBSD Target
240template<typename Target>
241class FreeBSDTargetInfo : public OSTargetInfo<Target> {
242protected:
243  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
244                            MacroBuilder &Builder) const {
245    // FreeBSD defines; list based off of gcc output
246
247    unsigned Release = Triple.getOSMajorVersion();
248    if (Release == 0U)
249      Release = 8;
250
251    Builder.defineMacro("__FreeBSD__", Twine(Release));
252    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
253    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
254    DefineStd(Builder, "unix", Opts);
255    Builder.defineMacro("__ELF__");
256  }
257public:
258  FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
259    this->UserLabelPrefix = "";
260
261    switch (Triple.getArch()) {
262    default:
263    case llvm::Triple::x86:
264    case llvm::Triple::x86_64:
265      this->MCountName = ".mcount";
266      break;
267    case llvm::Triple::mips:
268    case llvm::Triple::mipsel:
269    case llvm::Triple::ppc:
270    case llvm::Triple::ppc64:
271      this->MCountName = "_mcount";
272      break;
273    case llvm::Triple::arm:
274      this->MCountName = "__mcount";
275      break;
276    }
277  }
278};
279
280// Minix Target
281template<typename Target>
282class MinixTargetInfo : public OSTargetInfo<Target> {
283protected:
284  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
285                            MacroBuilder &Builder) const {
286    // Minix defines
287
288    Builder.defineMacro("__minix", "3");
289    Builder.defineMacro("_EM_WSIZE", "4");
290    Builder.defineMacro("_EM_PSIZE", "4");
291    Builder.defineMacro("_EM_SSIZE", "2");
292    Builder.defineMacro("_EM_LSIZE", "4");
293    Builder.defineMacro("_EM_FSIZE", "4");
294    Builder.defineMacro("_EM_DSIZE", "8");
295    Builder.defineMacro("__ELF__");
296    DefineStd(Builder, "unix", Opts);
297  }
298public:
299  MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
300    this->UserLabelPrefix = "";
301  }
302};
303
304// Linux target
305template<typename Target>
306class LinuxTargetInfo : public OSTargetInfo<Target> {
307protected:
308  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
309                            MacroBuilder &Builder) const {
310    // Linux defines; list based off of gcc output
311    DefineStd(Builder, "unix", Opts);
312    DefineStd(Builder, "linux", Opts);
313    Builder.defineMacro("__gnu_linux__");
314    Builder.defineMacro("__ELF__");
315    if (Triple.getEnvironment() == llvm::Triple::Android)
316      Builder.defineMacro("__ANDROID__", "1");
317    if (Opts.POSIXThreads)
318      Builder.defineMacro("_REENTRANT");
319    if (Opts.CPlusPlus)
320      Builder.defineMacro("_GNU_SOURCE");
321  }
322public:
323  LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
324    this->UserLabelPrefix = "";
325    this->WIntType = TargetInfo::UnsignedInt;
326  }
327
328  virtual const char *getStaticInitSectionSpecifier() const {
329    return ".text.startup";
330  }
331};
332
333// NetBSD Target
334template<typename Target>
335class NetBSDTargetInfo : public OSTargetInfo<Target> {
336protected:
337  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
338                            MacroBuilder &Builder) const {
339    // NetBSD defines; list based off of gcc output
340    Builder.defineMacro("__NetBSD__");
341    Builder.defineMacro("__unix__");
342    Builder.defineMacro("__ELF__");
343    if (Opts.POSIXThreads)
344      Builder.defineMacro("_POSIX_THREADS");
345  }
346public:
347  NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
348    this->UserLabelPrefix = "";
349  }
350};
351
352// OpenBSD Target
353template<typename Target>
354class OpenBSDTargetInfo : public OSTargetInfo<Target> {
355protected:
356  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
357                            MacroBuilder &Builder) const {
358    // OpenBSD defines; list based off of gcc output
359
360    Builder.defineMacro("__OpenBSD__");
361    DefineStd(Builder, "unix", Opts);
362    Builder.defineMacro("__ELF__");
363    if (Opts.POSIXThreads)
364      Builder.defineMacro("_REENTRANT");
365  }
366public:
367  OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
368    this->UserLabelPrefix = "";
369    this->TLSSupported = false;
370
371      switch (Triple.getArch()) {
372        default:
373        case llvm::Triple::x86:
374        case llvm::Triple::x86_64:
375        case llvm::Triple::arm:
376        case llvm::Triple::sparc:
377          this->MCountName = "__mcount";
378          break;
379        case llvm::Triple::mips64:
380        case llvm::Triple::mips64el:
381        case llvm::Triple::ppc:
382        case llvm::Triple::sparcv9:
383          this->MCountName = "_mcount";
384          break;
385      }
386  }
387};
388
389// Bitrig Target
390template<typename Target>
391class BitrigTargetInfo : public OSTargetInfo<Target> {
392protected:
393  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
394                            MacroBuilder &Builder) const {
395    // Bitrig defines; list based off of gcc output
396
397    Builder.defineMacro("__Bitrig__");
398    DefineStd(Builder, "unix", Opts);
399    Builder.defineMacro("__ELF__");
400    if (Opts.POSIXThreads)
401      Builder.defineMacro("_REENTRANT");
402  }
403public:
404  BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
405    this->UserLabelPrefix = "";
406    this->TLSSupported = false;
407    this->MCountName = "__mcount";
408  }
409};
410
411// PSP Target
412template<typename Target>
413class PSPTargetInfo : public OSTargetInfo<Target> {
414protected:
415  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
416                            MacroBuilder &Builder) const {
417    // PSP defines; list based on the output of the pspdev gcc toolchain.
418    Builder.defineMacro("PSP");
419    Builder.defineMacro("_PSP");
420    Builder.defineMacro("__psp__");
421    Builder.defineMacro("__ELF__");
422  }
423public:
424  PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
425    this->UserLabelPrefix = "";
426  }
427};
428
429// PS3 PPU Target
430template<typename Target>
431class PS3PPUTargetInfo : public OSTargetInfo<Target> {
432protected:
433  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
434                            MacroBuilder &Builder) const {
435    // PS3 PPU defines.
436    Builder.defineMacro("__PPC__");
437    Builder.defineMacro("__PPU__");
438    Builder.defineMacro("__CELLOS_LV2__");
439    Builder.defineMacro("__ELF__");
440    Builder.defineMacro("__LP32__");
441    Builder.defineMacro("_ARCH_PPC64");
442    Builder.defineMacro("__powerpc64__");
443  }
444public:
445  PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
446    this->UserLabelPrefix = "";
447    this->LongWidth = this->LongAlign = 32;
448    this->PointerWidth = this->PointerAlign = 32;
449    this->IntMaxType = TargetInfo::SignedLongLong;
450    this->UIntMaxType = TargetInfo::UnsignedLongLong;
451    this->Int64Type = TargetInfo::SignedLongLong;
452    this->SizeType = TargetInfo::UnsignedInt;
453    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
454                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
455  }
456};
457
458// FIXME: Need a real SPU target.
459// PS3 SPU Target
460template<typename Target>
461class PS3SPUTargetInfo : public OSTargetInfo<Target> {
462protected:
463  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
464                            MacroBuilder &Builder) const {
465    // PS3 PPU defines.
466    Builder.defineMacro("__SPU__");
467    Builder.defineMacro("__ELF__");
468  }
469public:
470  PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
471    this->UserLabelPrefix = "";
472  }
473};
474
475// AuroraUX target
476template<typename Target>
477class AuroraUXTargetInfo : public OSTargetInfo<Target> {
478protected:
479  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
480                            MacroBuilder &Builder) const {
481    DefineStd(Builder, "sun", Opts);
482    DefineStd(Builder, "unix", Opts);
483    Builder.defineMacro("__ELF__");
484    Builder.defineMacro("__svr4__");
485    Builder.defineMacro("__SVR4");
486  }
487public:
488  AuroraUXTargetInfo(const llvm::Triple &Triple)
489      : OSTargetInfo<Target>(Triple) {
490    this->UserLabelPrefix = "";
491    this->WCharType = this->SignedLong;
492    // FIXME: WIntType should be SignedLong
493  }
494};
495
496// Solaris target
497template<typename Target>
498class SolarisTargetInfo : public OSTargetInfo<Target> {
499protected:
500  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
501                            MacroBuilder &Builder) const {
502    DefineStd(Builder, "sun", Opts);
503    DefineStd(Builder, "unix", Opts);
504    Builder.defineMacro("__ELF__");
505    Builder.defineMacro("__svr4__");
506    Builder.defineMacro("__SVR4");
507    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
508    // newer, but to 500 for everything else.  feature_test.h has a check to
509    // ensure that you are not using C99 with an old version of X/Open or C89
510    // with a new version.
511    if (Opts.C99 || Opts.C11)
512      Builder.defineMacro("_XOPEN_SOURCE", "600");
513    else
514      Builder.defineMacro("_XOPEN_SOURCE", "500");
515    if (Opts.CPlusPlus)
516      Builder.defineMacro("__C99FEATURES__");
517    Builder.defineMacro("_LARGEFILE_SOURCE");
518    Builder.defineMacro("_LARGEFILE64_SOURCE");
519    Builder.defineMacro("__EXTENSIONS__");
520    Builder.defineMacro("_REENTRANT");
521  }
522public:
523  SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
524    this->UserLabelPrefix = "";
525    this->WCharType = this->SignedInt;
526    // FIXME: WIntType should be SignedLong
527  }
528};
529
530// Windows target
531template<typename Target>
532class WindowsTargetInfo : public OSTargetInfo<Target> {
533protected:
534  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
535                            MacroBuilder &Builder) const {
536    Builder.defineMacro("_WIN32");
537  }
538  void getVisualStudioDefines(const LangOptions &Opts,
539                              MacroBuilder &Builder) const {
540    if (Opts.CPlusPlus) {
541      if (Opts.RTTI)
542        Builder.defineMacro("_CPPRTTI");
543
544      if (Opts.Exceptions)
545        Builder.defineMacro("_CPPUNWIND");
546    }
547
548    if (!Opts.CharIsSigned)
549      Builder.defineMacro("_CHAR_UNSIGNED");
550
551    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
552    //        but it works for now.
553    if (Opts.POSIXThreads)
554      Builder.defineMacro("_MT");
555
556    if (Opts.MSCVersion != 0)
557      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
558
559    if (Opts.MicrosoftExt) {
560      Builder.defineMacro("_MSC_EXTENSIONS");
561
562      if (Opts.CPlusPlus11) {
563        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
564        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
565        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
566      }
567    }
568
569    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
570  }
571
572public:
573  WindowsTargetInfo(const llvm::Triple &Triple)
574      : OSTargetInfo<Target>(Triple) {}
575};
576
577template <typename Target>
578class NaClTargetInfo : public OSTargetInfo<Target> {
579protected:
580  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
581                            MacroBuilder &Builder) const {
582    if (Opts.POSIXThreads)
583      Builder.defineMacro("_REENTRANT");
584    if (Opts.CPlusPlus)
585      Builder.defineMacro("_GNU_SOURCE");
586
587    DefineStd(Builder, "unix", Opts);
588    Builder.defineMacro("__ELF__");
589    Builder.defineMacro("__native_client__");
590  }
591
592public:
593  NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
594    this->UserLabelPrefix = "";
595    this->LongAlign = 32;
596    this->LongWidth = 32;
597    this->PointerAlign = 32;
598    this->PointerWidth = 32;
599    this->IntMaxType = TargetInfo::SignedLongLong;
600    this->UIntMaxType = TargetInfo::UnsignedLongLong;
601    this->Int64Type = TargetInfo::SignedLongLong;
602    this->DoubleAlign = 64;
603    this->LongDoubleWidth = 64;
604    this->LongDoubleAlign = 64;
605    this->SizeType = TargetInfo::UnsignedInt;
606    this->PtrDiffType = TargetInfo::SignedInt;
607    this->IntPtrType = TargetInfo::SignedInt;
608    // RegParmMax is inherited from the underlying architecture
609    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
610    this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
611                              "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
612  }
613  virtual typename Target::CallingConvCheckResult checkCallingConvention(
614      CallingConv CC) const {
615    return CC == CC_PnaclCall ? Target::CCCR_OK :
616        Target::checkCallingConvention(CC);
617  }
618};
619} // end anonymous namespace.
620
621//===----------------------------------------------------------------------===//
622// Specific target implementations.
623//===----------------------------------------------------------------------===//
624
625namespace {
626// PPC abstract base class
627class PPCTargetInfo : public TargetInfo {
628  static const Builtin::Info BuiltinInfo[];
629  static const char * const GCCRegNames[];
630  static const TargetInfo::GCCRegAlias GCCRegAliases[];
631  std::string CPU;
632public:
633  PPCTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
634    LongDoubleWidth = LongDoubleAlign = 128;
635    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
636  }
637
638  /// \brief Flags for architecture specific defines.
639  typedef enum {
640    ArchDefineNone  = 0,
641    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
642    ArchDefinePpcgr = 1 << 1,
643    ArchDefinePpcsq = 1 << 2,
644    ArchDefine440   = 1 << 3,
645    ArchDefine603   = 1 << 4,
646    ArchDefine604   = 1 << 5,
647    ArchDefinePwr4  = 1 << 6,
648    ArchDefinePwr5  = 1 << 7,
649    ArchDefinePwr5x = 1 << 8,
650    ArchDefinePwr6  = 1 << 9,
651    ArchDefinePwr6x = 1 << 10,
652    ArchDefinePwr7  = 1 << 11,
653    ArchDefineA2    = 1 << 12,
654    ArchDefineA2q   = 1 << 13
655  } ArchDefineTypes;
656
657  // Note: GCC recognizes the following additional cpus:
658  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
659  //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
660  //  titan, rs64.
661  virtual bool setCPU(const std::string &Name) {
662    bool CPUKnown = llvm::StringSwitch<bool>(Name)
663      .Case("generic", true)
664      .Case("440", true)
665      .Case("450", true)
666      .Case("601", true)
667      .Case("602", true)
668      .Case("603", true)
669      .Case("603e", true)
670      .Case("603ev", true)
671      .Case("604", true)
672      .Case("604e", true)
673      .Case("620", true)
674      .Case("630", true)
675      .Case("g3", true)
676      .Case("7400", true)
677      .Case("g4", true)
678      .Case("7450", true)
679      .Case("g4+", true)
680      .Case("750", true)
681      .Case("970", true)
682      .Case("g5", true)
683      .Case("a2", true)
684      .Case("a2q", true)
685      .Case("e500mc", true)
686      .Case("e5500", true)
687      .Case("power3", true)
688      .Case("pwr3", true)
689      .Case("power4", true)
690      .Case("pwr4", true)
691      .Case("power5", true)
692      .Case("pwr5", true)
693      .Case("power5x", true)
694      .Case("pwr5x", true)
695      .Case("power6", true)
696      .Case("pwr6", true)
697      .Case("power6x", true)
698      .Case("pwr6x", true)
699      .Case("power7", true)
700      .Case("pwr7", true)
701      .Case("powerpc", true)
702      .Case("ppc", true)
703      .Case("powerpc64", true)
704      .Case("ppc64", true)
705      .Default(false);
706
707    if (CPUKnown)
708      CPU = Name;
709
710    return CPUKnown;
711  }
712
713  virtual void getTargetBuiltins(const Builtin::Info *&Records,
714                                 unsigned &NumRecords) const {
715    Records = BuiltinInfo;
716    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
717  }
718
719  virtual bool isCLZForZeroUndef() const { return false; }
720
721  virtual void getTargetDefines(const LangOptions &Opts,
722                                MacroBuilder &Builder) const;
723
724  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
725
726  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
727                                 StringRef Name,
728                                 bool Enabled) const;
729
730  virtual bool hasFeature(StringRef Feature) const;
731
732  virtual void getGCCRegNames(const char * const *&Names,
733                              unsigned &NumNames) const;
734  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
735                                unsigned &NumAliases) const;
736  virtual bool validateAsmConstraint(const char *&Name,
737                                     TargetInfo::ConstraintInfo &Info) const {
738    switch (*Name) {
739    default: return false;
740    case 'O': // Zero
741      break;
742    case 'b': // Base register
743    case 'f': // Floating point register
744      Info.setAllowsRegister();
745      break;
746    // FIXME: The following are added to allow parsing.
747    // I just took a guess at what the actions should be.
748    // Also, is more specific checking needed?  I.e. specific registers?
749    case 'd': // Floating point register (containing 64-bit value)
750    case 'v': // Altivec vector register
751      Info.setAllowsRegister();
752      break;
753    case 'w':
754      switch (Name[1]) {
755        case 'd':// VSX vector register to hold vector double data
756        case 'f':// VSX vector register to hold vector float data
757        case 's':// VSX vector register to hold scalar float data
758        case 'a':// Any VSX register
759          break;
760        default:
761          return false;
762      }
763      Info.setAllowsRegister();
764      Name++; // Skip over 'w'.
765      break;
766    case 'h': // `MQ', `CTR', or `LINK' register
767    case 'q': // `MQ' register
768    case 'c': // `CTR' register
769    case 'l': // `LINK' register
770    case 'x': // `CR' register (condition register) number 0
771    case 'y': // `CR' register (condition register)
772    case 'z': // `XER[CA]' carry bit (part of the XER register)
773      Info.setAllowsRegister();
774      break;
775    case 'I': // Signed 16-bit constant
776    case 'J': // Unsigned 16-bit constant shifted left 16 bits
777              //  (use `L' instead for SImode constants)
778    case 'K': // Unsigned 16-bit constant
779    case 'L': // Signed 16-bit constant shifted left 16 bits
780    case 'M': // Constant larger than 31
781    case 'N': // Exact power of 2
782    case 'P': // Constant whose negation is a signed 16-bit constant
783    case 'G': // Floating point constant that can be loaded into a
784              // register with one instruction per word
785    case 'H': // Integer/Floating point constant that can be loaded
786              // into a register using three instructions
787      break;
788    case 'm': // Memory operand. Note that on PowerPC targets, m can
789              // include addresses that update the base register. It
790              // is therefore only safe to use `m' in an asm statement
791              // if that asm statement accesses the operand exactly once.
792              // The asm statement must also use `%U<opno>' as a
793              // placeholder for the "update" flag in the corresponding
794              // load or store instruction. For example:
795              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
796              // is correct but:
797              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
798              // is not. Use es rather than m if you don't want the base
799              // register to be updated.
800    case 'e':
801      if (Name[1] != 's')
802          return false;
803              // es: A "stable" memory operand; that is, one which does not
804              // include any automodification of the base register. Unlike
805              // `m', this constraint can be used in asm statements that
806              // might access the operand several times, or that might not
807              // access it at all.
808      Info.setAllowsMemory();
809      Name++; // Skip over 'e'.
810      break;
811    case 'Q': // Memory operand that is an offset from a register (it is
812              // usually better to use `m' or `es' in asm statements)
813    case 'Z': // Memory operand that is an indexed or indirect from a
814              // register (it is usually better to use `m' or `es' in
815              // asm statements)
816      Info.setAllowsMemory();
817      Info.setAllowsRegister();
818      break;
819    case 'R': // AIX TOC entry
820    case 'a': // Address operand that is an indexed or indirect from a
821              // register (`p' is preferable for asm statements)
822    case 'S': // Constant suitable as a 64-bit mask operand
823    case 'T': // Constant suitable as a 32-bit mask operand
824    case 'U': // System V Release 4 small data area reference
825    case 't': // AND masks that can be performed by two rldic{l, r}
826              // instructions
827    case 'W': // Vector constant that does not require memory
828    case 'j': // Vector constant that is all zeros.
829      break;
830    // End FIXME.
831    }
832    return true;
833  }
834  virtual const char *getClobbers() const {
835    return "";
836  }
837  int getEHDataRegisterNumber(unsigned RegNo) const {
838    if (RegNo == 0) return 3;
839    if (RegNo == 1) return 4;
840    return -1;
841  }
842};
843
844const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
845#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
846#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
847                                              ALL_LANGUAGES },
848#include "clang/Basic/BuiltinsPPC.def"
849};
850
851
852/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
853/// #defines that are not tied to a specific subtarget.
854void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
855                                     MacroBuilder &Builder) const {
856  // Target identification.
857  Builder.defineMacro("__ppc__");
858  Builder.defineMacro("__PPC__");
859  Builder.defineMacro("_ARCH_PPC");
860  Builder.defineMacro("__powerpc__");
861  Builder.defineMacro("__POWERPC__");
862  if (PointerWidth == 64) {
863    Builder.defineMacro("_ARCH_PPC64");
864    Builder.defineMacro("__powerpc64__");
865    Builder.defineMacro("__ppc64__");
866    Builder.defineMacro("__PPC64__");
867  }
868
869  // Target properties.
870  if (getTriple().getOS() != llvm::Triple::NetBSD &&
871      getTriple().getOS() != llvm::Triple::OpenBSD)
872    Builder.defineMacro("_BIG_ENDIAN");
873  Builder.defineMacro("__BIG_ENDIAN__");
874
875  // Subtarget options.
876  Builder.defineMacro("__NATURAL_ALIGNMENT__");
877  Builder.defineMacro("__REGISTER_PREFIX__", "");
878
879  // FIXME: Should be controlled by command line option.
880  if (LongDoubleWidth == 128)
881    Builder.defineMacro("__LONG_DOUBLE_128__");
882
883  if (Opts.AltiVec) {
884    Builder.defineMacro("__VEC__", "10206");
885    Builder.defineMacro("__ALTIVEC__");
886  }
887
888  // CPU identification.
889  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
890    .Case("440",   ArchDefineName)
891    .Case("450",   ArchDefineName | ArchDefine440)
892    .Case("601",   ArchDefineName)
893    .Case("602",   ArchDefineName | ArchDefinePpcgr)
894    .Case("603",   ArchDefineName | ArchDefinePpcgr)
895    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
896    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
897    .Case("604",   ArchDefineName | ArchDefinePpcgr)
898    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
899    .Case("620",   ArchDefineName | ArchDefinePpcgr)
900    .Case("630",   ArchDefineName | ArchDefinePpcgr)
901    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
902    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
903    .Case("750",   ArchDefineName | ArchDefinePpcgr)
904    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
905                     | ArchDefinePpcsq)
906    .Case("a2",    ArchDefineA2)
907    .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
908    .Case("pwr3",  ArchDefinePpcgr)
909    .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
910    .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
911                     | ArchDefinePpcsq)
912    .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
913                     | ArchDefinePpcgr | ArchDefinePpcsq)
914    .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
915                     | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
916    .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
917                     | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
918                     | ArchDefinePpcsq)
919    .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
920                     | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
921                     | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
922    .Case("power3",  ArchDefinePpcgr)
923    .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
924    .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
925                       | ArchDefinePpcsq)
926    .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
927                       | ArchDefinePpcgr | ArchDefinePpcsq)
928    .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
929                       | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
930    .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
931                       | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
932                       | ArchDefinePpcsq)
933    .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
934                       | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
935                       | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
936    .Default(ArchDefineNone);
937
938  if (defs & ArchDefineName)
939    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
940  if (defs & ArchDefinePpcgr)
941    Builder.defineMacro("_ARCH_PPCGR");
942  if (defs & ArchDefinePpcsq)
943    Builder.defineMacro("_ARCH_PPCSQ");
944  if (defs & ArchDefine440)
945    Builder.defineMacro("_ARCH_440");
946  if (defs & ArchDefine603)
947    Builder.defineMacro("_ARCH_603");
948  if (defs & ArchDefine604)
949    Builder.defineMacro("_ARCH_604");
950  if (defs & ArchDefinePwr4)
951    Builder.defineMacro("_ARCH_PWR4");
952  if (defs & ArchDefinePwr5)
953    Builder.defineMacro("_ARCH_PWR5");
954  if (defs & ArchDefinePwr5x)
955    Builder.defineMacro("_ARCH_PWR5X");
956  if (defs & ArchDefinePwr6)
957    Builder.defineMacro("_ARCH_PWR6");
958  if (defs & ArchDefinePwr6x)
959    Builder.defineMacro("_ARCH_PWR6X");
960  if (defs & ArchDefinePwr7)
961    Builder.defineMacro("_ARCH_PWR7");
962  if (defs & ArchDefineA2)
963    Builder.defineMacro("_ARCH_A2");
964  if (defs & ArchDefineA2q) {
965    Builder.defineMacro("_ARCH_A2Q");
966    Builder.defineMacro("_ARCH_QP");
967  }
968
969  if (getTriple().getVendor() == llvm::Triple::BGQ) {
970    Builder.defineMacro("__bg__");
971    Builder.defineMacro("__THW_BLUEGENE__");
972    Builder.defineMacro("__bgq__");
973    Builder.defineMacro("__TOS_BGQ__");
974  }
975
976  // FIXME: The following are not yet generated here by Clang, but are
977  //        generated by GCC:
978  //
979  //   _SOFT_FLOAT_
980  //   __RECIP_PRECISION__
981  //   __APPLE_ALTIVEC__
982  //   __VSX__
983  //   __RECIP__
984  //   __RECIPF__
985  //   __RSQRTE__
986  //   __RSQRTEF__
987  //   _SOFT_DOUBLE_
988  //   __NO_LWSYNC__
989  //   __HAVE_BSWAP__
990  //   __LONGDOUBLE128
991  //   __CMODEL_MEDIUM__
992  //   __CMODEL_LARGE__
993  //   _CALL_SYSV
994  //   _CALL_DARWIN
995  //   __NO_FPRS__
996}
997
998void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
999  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1000    .Case("7400", true)
1001    .Case("g4", true)
1002    .Case("7450", true)
1003    .Case("g4+", true)
1004    .Case("970", true)
1005    .Case("g5", true)
1006    .Case("pwr6", true)
1007    .Case("pwr7", true)
1008    .Case("ppc64", true)
1009    .Default(false);
1010
1011  Features["qpx"] = (CPU == "a2q");
1012}
1013
1014bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1015                                         StringRef Name,
1016                                         bool Enabled) const {
1017  if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1018      Name == "popcntd" || Name == "qpx") {
1019    Features[Name] = Enabled;
1020    return true;
1021  }
1022
1023  return false;
1024}
1025
1026bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1027  return Feature == "powerpc";
1028}
1029
1030
1031const char * const PPCTargetInfo::GCCRegNames[] = {
1032  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1033  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1034  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1035  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1036  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1037  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1038  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1039  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1040  "mq", "lr", "ctr", "ap",
1041  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1042  "xer",
1043  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1044  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1045  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1046  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1047  "vrsave", "vscr",
1048  "spe_acc", "spefscr",
1049  "sfp"
1050};
1051
1052void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1053                                   unsigned &NumNames) const {
1054  Names = GCCRegNames;
1055  NumNames = llvm::array_lengthof(GCCRegNames);
1056}
1057
1058const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1059  // While some of these aliases do map to different registers
1060  // they still share the same register name.
1061  { { "0" }, "r0" },
1062  { { "1"}, "r1" },
1063  { { "2" }, "r2" },
1064  { { "3" }, "r3" },
1065  { { "4" }, "r4" },
1066  { { "5" }, "r5" },
1067  { { "6" }, "r6" },
1068  { { "7" }, "r7" },
1069  { { "8" }, "r8" },
1070  { { "9" }, "r9" },
1071  { { "10" }, "r10" },
1072  { { "11" }, "r11" },
1073  { { "12" }, "r12" },
1074  { { "13" }, "r13" },
1075  { { "14" }, "r14" },
1076  { { "15" }, "r15" },
1077  { { "16" }, "r16" },
1078  { { "17" }, "r17" },
1079  { { "18" }, "r18" },
1080  { { "19" }, "r19" },
1081  { { "20" }, "r20" },
1082  { { "21" }, "r21" },
1083  { { "22" }, "r22" },
1084  { { "23" }, "r23" },
1085  { { "24" }, "r24" },
1086  { { "25" }, "r25" },
1087  { { "26" }, "r26" },
1088  { { "27" }, "r27" },
1089  { { "28" }, "r28" },
1090  { { "29" }, "r29" },
1091  { { "30" }, "r30" },
1092  { { "31" }, "r31" },
1093  { { "fr0" }, "f0" },
1094  { { "fr1" }, "f1" },
1095  { { "fr2" }, "f2" },
1096  { { "fr3" }, "f3" },
1097  { { "fr4" }, "f4" },
1098  { { "fr5" }, "f5" },
1099  { { "fr6" }, "f6" },
1100  { { "fr7" }, "f7" },
1101  { { "fr8" }, "f8" },
1102  { { "fr9" }, "f9" },
1103  { { "fr10" }, "f10" },
1104  { { "fr11" }, "f11" },
1105  { { "fr12" }, "f12" },
1106  { { "fr13" }, "f13" },
1107  { { "fr14" }, "f14" },
1108  { { "fr15" }, "f15" },
1109  { { "fr16" }, "f16" },
1110  { { "fr17" }, "f17" },
1111  { { "fr18" }, "f18" },
1112  { { "fr19" }, "f19" },
1113  { { "fr20" }, "f20" },
1114  { { "fr21" }, "f21" },
1115  { { "fr22" }, "f22" },
1116  { { "fr23" }, "f23" },
1117  { { "fr24" }, "f24" },
1118  { { "fr25" }, "f25" },
1119  { { "fr26" }, "f26" },
1120  { { "fr27" }, "f27" },
1121  { { "fr28" }, "f28" },
1122  { { "fr29" }, "f29" },
1123  { { "fr30" }, "f30" },
1124  { { "fr31" }, "f31" },
1125  { { "cc" }, "cr0" },
1126};
1127
1128void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1129                                     unsigned &NumAliases) const {
1130  Aliases = GCCRegAliases;
1131  NumAliases = llvm::array_lengthof(GCCRegAliases);
1132}
1133} // end anonymous namespace.
1134
1135namespace {
1136class PPC32TargetInfo : public PPCTargetInfo {
1137public:
1138  PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1139    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1140                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1141
1142    switch (getTriple().getOS()) {
1143    case llvm::Triple::Linux:
1144    case llvm::Triple::FreeBSD:
1145    case llvm::Triple::NetBSD:
1146      SizeType = UnsignedInt;
1147      PtrDiffType = SignedInt;
1148      IntPtrType = SignedInt;
1149      break;
1150    default:
1151      break;
1152    }
1153
1154    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1155      LongDoubleWidth = LongDoubleAlign = 64;
1156      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1157    }
1158
1159    // PPC32 supports atomics up to 4 bytes.
1160    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1161  }
1162
1163  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1164    // This is the ELF definition, and is overridden by the Darwin sub-target
1165    return TargetInfo::PowerABIBuiltinVaList;
1166  }
1167};
1168} // end anonymous namespace.
1169
1170namespace {
1171class PPC64TargetInfo : public PPCTargetInfo {
1172public:
1173  PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1174    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1175    IntMaxType = SignedLong;
1176    UIntMaxType = UnsignedLong;
1177    Int64Type = SignedLong;
1178
1179    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1180      LongDoubleWidth = LongDoubleAlign = 64;
1181      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1182      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1183                          "i64:64:64-f32:32:32-f64:64:64-"
1184                          "v128:128:128-n32:64";
1185    } else
1186      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1187                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1188                          "v128:128:128-n32:64";
1189
1190    // PPC64 supports atomics up to 8 bytes.
1191    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1192  }
1193  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1194    return TargetInfo::CharPtrBuiltinVaList;
1195  }
1196};
1197} // end anonymous namespace.
1198
1199
1200namespace {
1201class DarwinPPC32TargetInfo :
1202  public DarwinTargetInfo<PPC32TargetInfo> {
1203public:
1204  DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1205      : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1206    HasAlignMac68kSupport = true;
1207    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1208    PtrDiffType = SignedInt;	// for http://llvm.org/bugs/show_bug.cgi?id=15726
1209    LongLongAlign = 32;
1210    SuitableAlign = 128;
1211    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1212                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1213  }
1214  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1215    return TargetInfo::CharPtrBuiltinVaList;
1216  }
1217};
1218
1219class DarwinPPC64TargetInfo :
1220  public DarwinTargetInfo<PPC64TargetInfo> {
1221public:
1222  DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1223      : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1224    HasAlignMac68kSupport = true;
1225    SuitableAlign = 128;
1226    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1227                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1228  }
1229};
1230} // end anonymous namespace.
1231
1232namespace {
1233  static const unsigned NVPTXAddrSpaceMap[] = {
1234    1,    // opencl_global
1235    3,    // opencl_local
1236    4,    // opencl_constant
1237    1,    // cuda_device
1238    4,    // cuda_constant
1239    3,    // cuda_shared
1240  };
1241  class NVPTXTargetInfo : public TargetInfo {
1242    static const char * const GCCRegNames[];
1243    static const Builtin::Info BuiltinInfo[];
1244    std::vector<StringRef> AvailableFeatures;
1245  public:
1246    NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1247      BigEndian = false;
1248      TLSSupported = false;
1249      LongWidth = LongAlign = 64;
1250      AddrSpaceMap = &NVPTXAddrSpaceMap;
1251      // Define available target features
1252      // These must be defined in sorted order!
1253      NoAsmVariants = true;
1254    }
1255    virtual void getTargetDefines(const LangOptions &Opts,
1256                                  MacroBuilder &Builder) const {
1257      Builder.defineMacro("__PTX__");
1258      Builder.defineMacro("__NVPTX__");
1259    }
1260    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1261                                   unsigned &NumRecords) const {
1262      Records = BuiltinInfo;
1263      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1264    }
1265    virtual bool hasFeature(StringRef Feature) const {
1266      return Feature == "ptx" || Feature == "nvptx";
1267    }
1268
1269    virtual void getGCCRegNames(const char * const *&Names,
1270                                unsigned &NumNames) const;
1271    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1272                                  unsigned &NumAliases) const {
1273      // No aliases.
1274      Aliases = 0;
1275      NumAliases = 0;
1276    }
1277    virtual bool validateAsmConstraint(const char *&Name,
1278                                       TargetInfo::ConstraintInfo &Info) const {
1279      switch (*Name) {
1280      default: return false;
1281      case 'c':
1282      case 'h':
1283      case 'r':
1284      case 'l':
1285      case 'f':
1286      case 'd':
1287        Info.setAllowsRegister();
1288        return true;
1289      }
1290    }
1291    virtual const char *getClobbers() const {
1292      // FIXME: Is this really right?
1293      return "";
1294    }
1295    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1296      // FIXME: implement
1297      return TargetInfo::CharPtrBuiltinVaList;
1298    }
1299    virtual bool setCPU(const std::string &Name) {
1300      bool Valid = llvm::StringSwitch<bool>(Name)
1301        .Case("sm_20", true)
1302        .Case("sm_21", true)
1303        .Case("sm_30", true)
1304        .Case("sm_35", true)
1305        .Default(false);
1306
1307      return Valid;
1308    }
1309    virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1310                                   StringRef Name,
1311                                   bool Enabled) const;
1312  };
1313
1314  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1315#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1316#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1317                                              ALL_LANGUAGES },
1318#include "clang/Basic/BuiltinsNVPTX.def"
1319  };
1320
1321  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1322    "r0"
1323  };
1324
1325  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1326                                     unsigned &NumNames) const {
1327    Names = GCCRegNames;
1328    NumNames = llvm::array_lengthof(GCCRegNames);
1329  }
1330
1331  bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1332                                          StringRef Name,
1333                                          bool Enabled) const {
1334    if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1335                          Name)) {
1336      Features[Name] = Enabled;
1337      return true;
1338    } else {
1339      return false;
1340    }
1341  }
1342
1343  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1344  public:
1345    NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1346      PointerWidth = PointerAlign = 32;
1347      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1348      DescriptionString
1349        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1350          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1351          "n16:32:64";
1352  }
1353  };
1354
1355  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1356  public:
1357    NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1358      PointerWidth = PointerAlign = 64;
1359      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1360      DescriptionString
1361        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1362          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1363          "n16:32:64";
1364  }
1365  };
1366}
1367
1368namespace {
1369
1370static const unsigned R600AddrSpaceMap[] = {
1371  1,    // opencl_global
1372  3,    // opencl_local
1373  2,    // opencl_constant
1374  1,    // cuda_device
1375  2,    // cuda_constant
1376  3     // cuda_shared
1377};
1378
1379static const char *DescriptionStringR600 =
1380  "e"
1381  "-p:32:32:32"
1382  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1383  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1384  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1385  "-n32:64";
1386
1387static const char *DescriptionStringR600DoubleOps =
1388  "e"
1389  "-p:32:32:32"
1390  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1391  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1392  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1393  "-n32:64";
1394
1395static const char *DescriptionStringSI =
1396  "e"
1397  "-p:64:64:64"
1398  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1399  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1400  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1401  "-n32:64";
1402
1403class R600TargetInfo : public TargetInfo {
1404  /// \brief The GPU profiles supported by the R600 target.
1405  enum GPUKind {
1406    GK_NONE,
1407    GK_R600,
1408    GK_R600_DOUBLE_OPS,
1409    GK_R700,
1410    GK_R700_DOUBLE_OPS,
1411    GK_EVERGREEN,
1412    GK_EVERGREEN_DOUBLE_OPS,
1413    GK_NORTHERN_ISLANDS,
1414    GK_CAYMAN,
1415    GK_SOUTHERN_ISLANDS
1416  } GPU;
1417
1418public:
1419  R600TargetInfo(const llvm::Triple &Triple)
1420      : TargetInfo(Triple), GPU(GK_R600) {
1421    DescriptionString = DescriptionStringR600;
1422    AddrSpaceMap = &R600AddrSpaceMap;
1423  }
1424
1425  virtual const char * getClobbers() const {
1426    return "";
1427  }
1428
1429  virtual void getGCCRegNames(const char * const *&Names,
1430                              unsigned &numNames) const  {
1431    Names = NULL;
1432    numNames = 0;
1433  }
1434
1435  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1436                                unsigned &NumAliases) const {
1437    Aliases = NULL;
1438    NumAliases = 0;
1439  }
1440
1441  virtual bool validateAsmConstraint(const char *&Name,
1442                                     TargetInfo::ConstraintInfo &info) const {
1443    return true;
1444  }
1445
1446  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1447                                 unsigned &NumRecords) const {
1448    Records = NULL;
1449    NumRecords = 0;
1450  }
1451
1452
1453  virtual void getTargetDefines(const LangOptions &Opts,
1454                                MacroBuilder &Builder) const {
1455    Builder.defineMacro("__R600__");
1456  }
1457
1458  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1459    return TargetInfo::CharPtrBuiltinVaList;
1460  }
1461
1462  virtual bool setCPU(const std::string &Name) {
1463    GPU = llvm::StringSwitch<GPUKind>(Name)
1464      .Case("r600" ,    GK_R600)
1465      .Case("rv610",    GK_R600)
1466      .Case("rv620",    GK_R600)
1467      .Case("rv630",    GK_R600)
1468      .Case("rv635",    GK_R600)
1469      .Case("rs780",    GK_R600)
1470      .Case("rs880",    GK_R600)
1471      .Case("rv670",    GK_R600_DOUBLE_OPS)
1472      .Case("rv710",    GK_R700)
1473      .Case("rv730",    GK_R700)
1474      .Case("rv740",    GK_R700_DOUBLE_OPS)
1475      .Case("rv770",    GK_R700_DOUBLE_OPS)
1476      .Case("palm",     GK_EVERGREEN)
1477      .Case("cedar",    GK_EVERGREEN)
1478      .Case("sumo",     GK_EVERGREEN)
1479      .Case("sumo2",    GK_EVERGREEN)
1480      .Case("redwood",  GK_EVERGREEN)
1481      .Case("juniper",  GK_EVERGREEN)
1482      .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1483      .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1484      .Case("barts",    GK_NORTHERN_ISLANDS)
1485      .Case("turks",    GK_NORTHERN_ISLANDS)
1486      .Case("caicos",   GK_NORTHERN_ISLANDS)
1487      .Case("cayman",   GK_CAYMAN)
1488      .Case("aruba",    GK_CAYMAN)
1489      .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1490      .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1491      .Case("verde",    GK_SOUTHERN_ISLANDS)
1492      .Case("oland",    GK_SOUTHERN_ISLANDS)
1493      .Default(GK_NONE);
1494
1495    if (GPU == GK_NONE) {
1496      return false;
1497    }
1498
1499    // Set the correct data layout
1500    switch (GPU) {
1501    case GK_NONE:
1502    case GK_R600:
1503    case GK_R700:
1504    case GK_EVERGREEN:
1505    case GK_NORTHERN_ISLANDS:
1506      DescriptionString = DescriptionStringR600;
1507      break;
1508    case GK_R600_DOUBLE_OPS:
1509    case GK_R700_DOUBLE_OPS:
1510    case GK_EVERGREEN_DOUBLE_OPS:
1511    case GK_CAYMAN:
1512      DescriptionString = DescriptionStringR600DoubleOps;
1513      break;
1514    case GK_SOUTHERN_ISLANDS:
1515      DescriptionString = DescriptionStringSI;
1516      break;
1517    }
1518
1519    return true;
1520  }
1521};
1522
1523} // end anonymous namespace
1524
1525namespace {
1526// Namespace for x86 abstract base class
1527const Builtin::Info BuiltinInfo[] = {
1528#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1529#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1530                                              ALL_LANGUAGES },
1531#include "clang/Basic/BuiltinsX86.def"
1532};
1533
1534static const char* const GCCRegNames[] = {
1535  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1536  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1537  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1538  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1539  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1540  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1541  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1542  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1543  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1544};
1545
1546const TargetInfo::AddlRegName AddlRegNames[] = {
1547  { { "al", "ah", "eax", "rax" }, 0 },
1548  { { "bl", "bh", "ebx", "rbx" }, 3 },
1549  { { "cl", "ch", "ecx", "rcx" }, 2 },
1550  { { "dl", "dh", "edx", "rdx" }, 1 },
1551  { { "esi", "rsi" }, 4 },
1552  { { "edi", "rdi" }, 5 },
1553  { { "esp", "rsp" }, 7 },
1554  { { "ebp", "rbp" }, 6 },
1555};
1556
1557// X86 target abstract base class; x86-32 and x86-64 are very close, so
1558// most of the implementation can be shared.
1559class X86TargetInfo : public TargetInfo {
1560  enum X86SSEEnum {
1561    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1562  } SSELevel;
1563  enum MMX3DNowEnum {
1564    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1565  } MMX3DNowLevel;
1566
1567  bool HasAES;
1568  bool HasPCLMUL;
1569  bool HasLZCNT;
1570  bool HasRDRND;
1571  bool HasBMI;
1572  bool HasBMI2;
1573  bool HasPOPCNT;
1574  bool HasRTM;
1575  bool HasPRFCHW;
1576  bool HasRDSEED;
1577  bool HasSSE4a;
1578  bool HasFMA4;
1579  bool HasFMA;
1580  bool HasXOP;
1581  bool HasF16C;
1582
1583  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1584  ///
1585  /// Each enumeration represents a particular CPU supported by Clang. These
1586  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1587  enum CPUKind {
1588    CK_Generic,
1589
1590    /// \name i386
1591    /// i386-generation processors.
1592    //@{
1593    CK_i386,
1594    //@}
1595
1596    /// \name i486
1597    /// i486-generation processors.
1598    //@{
1599    CK_i486,
1600    CK_WinChipC6,
1601    CK_WinChip2,
1602    CK_C3,
1603    //@}
1604
1605    /// \name i586
1606    /// i586-generation processors, P5 microarchitecture based.
1607    //@{
1608    CK_i586,
1609    CK_Pentium,
1610    CK_PentiumMMX,
1611    //@}
1612
1613    /// \name i686
1614    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1615    //@{
1616    CK_i686,
1617    CK_PentiumPro,
1618    CK_Pentium2,
1619    CK_Pentium3,
1620    CK_Pentium3M,
1621    CK_PentiumM,
1622    CK_C3_2,
1623
1624    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1625    /// Clang however has some logic to suport this.
1626    // FIXME: Warn, deprecate, and potentially remove this.
1627    CK_Yonah,
1628    //@}
1629
1630    /// \name Netburst
1631    /// Netburst microarchitecture based processors.
1632    //@{
1633    CK_Pentium4,
1634    CK_Pentium4M,
1635    CK_Prescott,
1636    CK_Nocona,
1637    //@}
1638
1639    /// \name Core
1640    /// Core microarchitecture based processors.
1641    //@{
1642    CK_Core2,
1643
1644    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1645    /// codename which GCC no longer accepts as an option to -march, but Clang
1646    /// has some logic for recognizing it.
1647    // FIXME: Warn, deprecate, and potentially remove this.
1648    CK_Penryn,
1649    //@}
1650
1651    /// \name Atom
1652    /// Atom processors
1653    //@{
1654    CK_Atom,
1655    //@}
1656
1657    /// \name Nehalem
1658    /// Nehalem microarchitecture based processors.
1659    //@{
1660    CK_Corei7,
1661    CK_Corei7AVX,
1662    CK_CoreAVXi,
1663    CK_CoreAVX2,
1664    //@}
1665
1666    /// \name K6
1667    /// K6 architecture processors.
1668    //@{
1669    CK_K6,
1670    CK_K6_2,
1671    CK_K6_3,
1672    //@}
1673
1674    /// \name K7
1675    /// K7 architecture processors.
1676    //@{
1677    CK_Athlon,
1678    CK_AthlonThunderbird,
1679    CK_Athlon4,
1680    CK_AthlonXP,
1681    CK_AthlonMP,
1682    //@}
1683
1684    /// \name K8
1685    /// K8 architecture processors.
1686    //@{
1687    CK_Athlon64,
1688    CK_Athlon64SSE3,
1689    CK_AthlonFX,
1690    CK_K8,
1691    CK_K8SSE3,
1692    CK_Opteron,
1693    CK_OpteronSSE3,
1694    CK_AMDFAM10,
1695    //@}
1696
1697    /// \name Bobcat
1698    /// Bobcat architecture processors.
1699    //@{
1700    CK_BTVER1,
1701    CK_BTVER2,
1702    //@}
1703
1704    /// \name Bulldozer
1705    /// Bulldozer architecture processors.
1706    //@{
1707    CK_BDVER1,
1708    CK_BDVER2,
1709    //@}
1710
1711    /// This specification is deprecated and will be removed in the future.
1712    /// Users should prefer \see CK_K8.
1713    // FIXME: Warn on this when the CPU is set to it.
1714    CK_x86_64,
1715    //@}
1716
1717    /// \name Geode
1718    /// Geode processors.
1719    //@{
1720    CK_Geode
1721    //@}
1722  } CPU;
1723
1724public:
1725  X86TargetInfo(const llvm::Triple &Triple)
1726      : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1727        HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1728        HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1729        HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1730        HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1731    BigEndian = false;
1732    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1733  }
1734  virtual unsigned getFloatEvalMethod() const {
1735    // X87 evaluates with 80 bits "long double" precision.
1736    return SSELevel == NoSSE ? 2 : 0;
1737  }
1738  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1739                                 unsigned &NumRecords) const {
1740    Records = BuiltinInfo;
1741    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1742  }
1743  virtual void getGCCRegNames(const char * const *&Names,
1744                              unsigned &NumNames) const {
1745    Names = GCCRegNames;
1746    NumNames = llvm::array_lengthof(GCCRegNames);
1747  }
1748  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1749                                unsigned &NumAliases) const {
1750    Aliases = 0;
1751    NumAliases = 0;
1752  }
1753  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1754                                  unsigned &NumNames) const {
1755    Names = AddlRegNames;
1756    NumNames = llvm::array_lengthof(AddlRegNames);
1757  }
1758  virtual bool validateAsmConstraint(const char *&Name,
1759                                     TargetInfo::ConstraintInfo &info) const;
1760  virtual std::string convertConstraint(const char *&Constraint) const;
1761  virtual const char *getClobbers() const {
1762    return "~{dirflag},~{fpsr},~{flags}";
1763  }
1764  virtual void getTargetDefines(const LangOptions &Opts,
1765                                MacroBuilder &Builder) const;
1766  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1767                                 StringRef Name,
1768                                 bool Enabled) const;
1769  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1770  virtual bool hasFeature(StringRef Feature) const;
1771  virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1772  virtual const char* getABI() const {
1773    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1774      return "avx";
1775    else if (getTriple().getArch() == llvm::Triple::x86 &&
1776             MMX3DNowLevel == NoMMX3DNow)
1777      return "no-mmx";
1778    return "";
1779  }
1780  virtual bool setCPU(const std::string &Name) {
1781    CPU = llvm::StringSwitch<CPUKind>(Name)
1782      .Case("i386", CK_i386)
1783      .Case("i486", CK_i486)
1784      .Case("winchip-c6", CK_WinChipC6)
1785      .Case("winchip2", CK_WinChip2)
1786      .Case("c3", CK_C3)
1787      .Case("i586", CK_i586)
1788      .Case("pentium", CK_Pentium)
1789      .Case("pentium-mmx", CK_PentiumMMX)
1790      .Case("i686", CK_i686)
1791      .Case("pentiumpro", CK_PentiumPro)
1792      .Case("pentium2", CK_Pentium2)
1793      .Case("pentium3", CK_Pentium3)
1794      .Case("pentium3m", CK_Pentium3M)
1795      .Case("pentium-m", CK_PentiumM)
1796      .Case("c3-2", CK_C3_2)
1797      .Case("yonah", CK_Yonah)
1798      .Case("pentium4", CK_Pentium4)
1799      .Case("pentium4m", CK_Pentium4M)
1800      .Case("prescott", CK_Prescott)
1801      .Case("nocona", CK_Nocona)
1802      .Case("core2", CK_Core2)
1803      .Case("penryn", CK_Penryn)
1804      .Case("atom", CK_Atom)
1805      .Case("corei7", CK_Corei7)
1806      .Case("corei7-avx", CK_Corei7AVX)
1807      .Case("core-avx-i", CK_CoreAVXi)
1808      .Case("core-avx2", CK_CoreAVX2)
1809      .Case("k6", CK_K6)
1810      .Case("k6-2", CK_K6_2)
1811      .Case("k6-3", CK_K6_3)
1812      .Case("athlon", CK_Athlon)
1813      .Case("athlon-tbird", CK_AthlonThunderbird)
1814      .Case("athlon-4", CK_Athlon4)
1815      .Case("athlon-xp", CK_AthlonXP)
1816      .Case("athlon-mp", CK_AthlonMP)
1817      .Case("athlon64", CK_Athlon64)
1818      .Case("athlon64-sse3", CK_Athlon64SSE3)
1819      .Case("athlon-fx", CK_AthlonFX)
1820      .Case("k8", CK_K8)
1821      .Case("k8-sse3", CK_K8SSE3)
1822      .Case("opteron", CK_Opteron)
1823      .Case("opteron-sse3", CK_OpteronSSE3)
1824      .Case("amdfam10", CK_AMDFAM10)
1825      .Case("btver1", CK_BTVER1)
1826      .Case("btver2", CK_BTVER2)
1827      .Case("bdver1", CK_BDVER1)
1828      .Case("bdver2", CK_BDVER2)
1829      .Case("x86-64", CK_x86_64)
1830      .Case("geode", CK_Geode)
1831      .Default(CK_Generic);
1832
1833    // Perform any per-CPU checks necessary to determine if this CPU is
1834    // acceptable.
1835    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1836    // invalid without explaining *why*.
1837    switch (CPU) {
1838    case CK_Generic:
1839      // No processor selected!
1840      return false;
1841
1842    case CK_i386:
1843    case CK_i486:
1844    case CK_WinChipC6:
1845    case CK_WinChip2:
1846    case CK_C3:
1847    case CK_i586:
1848    case CK_Pentium:
1849    case CK_PentiumMMX:
1850    case CK_i686:
1851    case CK_PentiumPro:
1852    case CK_Pentium2:
1853    case CK_Pentium3:
1854    case CK_Pentium3M:
1855    case CK_PentiumM:
1856    case CK_Yonah:
1857    case CK_C3_2:
1858    case CK_Pentium4:
1859    case CK_Pentium4M:
1860    case CK_Prescott:
1861    case CK_K6:
1862    case CK_K6_2:
1863    case CK_K6_3:
1864    case CK_Athlon:
1865    case CK_AthlonThunderbird:
1866    case CK_Athlon4:
1867    case CK_AthlonXP:
1868    case CK_AthlonMP:
1869    case CK_Geode:
1870      // Only accept certain architectures when compiling in 32-bit mode.
1871      if (getTriple().getArch() != llvm::Triple::x86)
1872        return false;
1873
1874      // Fallthrough
1875    case CK_Nocona:
1876    case CK_Core2:
1877    case CK_Penryn:
1878    case CK_Atom:
1879    case CK_Corei7:
1880    case CK_Corei7AVX:
1881    case CK_CoreAVXi:
1882    case CK_CoreAVX2:
1883    case CK_Athlon64:
1884    case CK_Athlon64SSE3:
1885    case CK_AthlonFX:
1886    case CK_K8:
1887    case CK_K8SSE3:
1888    case CK_Opteron:
1889    case CK_OpteronSSE3:
1890    case CK_AMDFAM10:
1891    case CK_BTVER1:
1892    case CK_BTVER2:
1893    case CK_BDVER1:
1894    case CK_BDVER2:
1895    case CK_x86_64:
1896      return true;
1897    }
1898    llvm_unreachable("Unhandled CPU kind");
1899  }
1900
1901  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
1902    // We accept all non-ARM calling conventions
1903    return (CC == CC_X86ThisCall ||
1904            CC == CC_X86FastCall ||
1905            CC == CC_X86StdCall ||
1906            CC == CC_C ||
1907            CC == CC_X86Pascal ||
1908            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
1909  }
1910
1911  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
1912    return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
1913  }
1914};
1915
1916void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1917  // FIXME: This should not be here.
1918  Features["3dnow"] = false;
1919  Features["3dnowa"] = false;
1920  Features["mmx"] = false;
1921  Features["sse"] = false;
1922  Features["sse2"] = false;
1923  Features["sse3"] = false;
1924  Features["ssse3"] = false;
1925  Features["sse41"] = false;
1926  Features["sse42"] = false;
1927  Features["sse4a"] = false;
1928  Features["aes"] = false;
1929  Features["pclmul"] = false;
1930  Features["avx"] = false;
1931  Features["avx2"] = false;
1932  Features["lzcnt"] = false;
1933  Features["rdrand"] = false;
1934  Features["bmi"] = false;
1935  Features["bmi2"] = false;
1936  Features["popcnt"] = false;
1937  Features["rtm"] = false;
1938  Features["prfchw"] = false;
1939  Features["rdseed"] = false;
1940  Features["fma4"] = false;
1941  Features["fma"] = false;
1942  Features["xop"] = false;
1943  Features["f16c"] = false;
1944
1945  // FIXME: This *really* should not be here.
1946
1947  // X86_64 always has SSE2.
1948  if (getTriple().getArch() == llvm::Triple::x86_64)
1949    setFeatureEnabled(Features, "sse2", true);
1950
1951  switch (CPU) {
1952  case CK_Generic:
1953  case CK_i386:
1954  case CK_i486:
1955  case CK_i586:
1956  case CK_Pentium:
1957  case CK_i686:
1958  case CK_PentiumPro:
1959    break;
1960  case CK_PentiumMMX:
1961  case CK_Pentium2:
1962    setFeatureEnabled(Features, "mmx", true);
1963    break;
1964  case CK_Pentium3:
1965  case CK_Pentium3M:
1966    setFeatureEnabled(Features, "sse", true);
1967    break;
1968  case CK_PentiumM:
1969  case CK_Pentium4:
1970  case CK_Pentium4M:
1971  case CK_x86_64:
1972    setFeatureEnabled(Features, "sse2", true);
1973    break;
1974  case CK_Yonah:
1975  case CK_Prescott:
1976  case CK_Nocona:
1977    setFeatureEnabled(Features, "sse3", true);
1978    break;
1979  case CK_Core2:
1980    setFeatureEnabled(Features, "ssse3", true);
1981    break;
1982  case CK_Penryn:
1983    setFeatureEnabled(Features, "sse4.1", true);
1984    break;
1985  case CK_Atom:
1986    setFeatureEnabled(Features, "ssse3", true);
1987    break;
1988  case CK_Corei7:
1989    setFeatureEnabled(Features, "sse4", true);
1990    break;
1991  case CK_Corei7AVX:
1992    setFeatureEnabled(Features, "avx", true);
1993    setFeatureEnabled(Features, "aes", true);
1994    setFeatureEnabled(Features, "pclmul", true);
1995    break;
1996  case CK_CoreAVXi:
1997    setFeatureEnabled(Features, "avx", true);
1998    setFeatureEnabled(Features, "aes", true);
1999    setFeatureEnabled(Features, "pclmul", true);
2000    setFeatureEnabled(Features, "rdrnd", true);
2001    setFeatureEnabled(Features, "f16c", true);
2002    break;
2003  case CK_CoreAVX2:
2004    setFeatureEnabled(Features, "avx2", true);
2005    setFeatureEnabled(Features, "aes", true);
2006    setFeatureEnabled(Features, "pclmul", true);
2007    setFeatureEnabled(Features, "lzcnt", true);
2008    setFeatureEnabled(Features, "rdrnd", true);
2009    setFeatureEnabled(Features, "f16c", true);
2010    setFeatureEnabled(Features, "bmi", true);
2011    setFeatureEnabled(Features, "bmi2", true);
2012    setFeatureEnabled(Features, "rtm", true);
2013    setFeatureEnabled(Features, "fma", true);
2014    break;
2015  case CK_K6:
2016  case CK_WinChipC6:
2017    setFeatureEnabled(Features, "mmx", true);
2018    break;
2019  case CK_K6_2:
2020  case CK_K6_3:
2021  case CK_WinChip2:
2022  case CK_C3:
2023    setFeatureEnabled(Features, "3dnow", true);
2024    break;
2025  case CK_Athlon:
2026  case CK_AthlonThunderbird:
2027  case CK_Geode:
2028    setFeatureEnabled(Features, "3dnowa", true);
2029    break;
2030  case CK_Athlon4:
2031  case CK_AthlonXP:
2032  case CK_AthlonMP:
2033    setFeatureEnabled(Features, "sse", true);
2034    setFeatureEnabled(Features, "3dnowa", true);
2035    break;
2036  case CK_K8:
2037  case CK_Opteron:
2038  case CK_Athlon64:
2039  case CK_AthlonFX:
2040    setFeatureEnabled(Features, "sse2", true);
2041    setFeatureEnabled(Features, "3dnowa", true);
2042    break;
2043  case CK_K8SSE3:
2044  case CK_OpteronSSE3:
2045  case CK_Athlon64SSE3:
2046    setFeatureEnabled(Features, "sse3", true);
2047    setFeatureEnabled(Features, "3dnowa", true);
2048    break;
2049  case CK_AMDFAM10:
2050    setFeatureEnabled(Features, "sse3", true);
2051    setFeatureEnabled(Features, "sse4a", true);
2052    setFeatureEnabled(Features, "3dnowa", true);
2053    setFeatureEnabled(Features, "lzcnt", true);
2054    setFeatureEnabled(Features, "popcnt", true);
2055    break;
2056  case CK_BTVER1:
2057    setFeatureEnabled(Features, "ssse3", true);
2058    setFeatureEnabled(Features, "sse4a", true);
2059    setFeatureEnabled(Features, "lzcnt", true);
2060    setFeatureEnabled(Features, "popcnt", true);
2061    break;
2062  case CK_BTVER2:
2063    setFeatureEnabled(Features, "avx", true);
2064    setFeatureEnabled(Features, "sse4a", true);
2065    setFeatureEnabled(Features, "lzcnt", true);
2066    setFeatureEnabled(Features, "aes", true);
2067    setFeatureEnabled(Features, "pclmul", true);
2068    setFeatureEnabled(Features, "bmi", true);
2069    setFeatureEnabled(Features, "f16c", true);
2070    break;
2071  case CK_BDVER1:
2072    setFeatureEnabled(Features, "xop", true);
2073    setFeatureEnabled(Features, "lzcnt", true);
2074    setFeatureEnabled(Features, "aes", true);
2075    setFeatureEnabled(Features, "pclmul", true);
2076    break;
2077  case CK_BDVER2:
2078    setFeatureEnabled(Features, "xop", true);
2079    setFeatureEnabled(Features, "lzcnt", true);
2080    setFeatureEnabled(Features, "aes", true);
2081    setFeatureEnabled(Features, "pclmul", true);
2082    setFeatureEnabled(Features, "bmi", true);
2083    setFeatureEnabled(Features, "fma", true);
2084    setFeatureEnabled(Features, "f16c", true);
2085    break;
2086  case CK_C3_2:
2087    setFeatureEnabled(Features, "sse", true);
2088    break;
2089  }
2090}
2091
2092bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2093                                      StringRef Name,
2094                                      bool Enabled) const {
2095  // FIXME: This *really* should not be here.  We need some way of translating
2096  // options into llvm subtarget features.
2097  if (!Features.count(Name) &&
2098      (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2099       Name != "rdrnd"))
2100    return false;
2101
2102  // FIXME: this should probably use a switch with fall through.
2103
2104  if (Enabled) {
2105    if (Name == "mmx")
2106      Features["mmx"] = true;
2107    else if (Name == "sse")
2108      Features["mmx"] = Features["sse"] = true;
2109    else if (Name == "sse2")
2110      Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2111    else if (Name == "sse3")
2112      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2113        true;
2114    else if (Name == "ssse3")
2115      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2116        Features["ssse3"] = true;
2117    else if (Name == "sse4" || Name == "sse4.2")
2118      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2119        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2120        Features["popcnt"] = true;
2121    else if (Name == "sse4.1")
2122      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2123        Features["ssse3"] = Features["sse41"] = true;
2124    else if (Name == "3dnow")
2125      Features["mmx"] = Features["3dnow"] = true;
2126    else if (Name == "3dnowa")
2127      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2128    else if (Name == "aes")
2129      Features["sse"] = Features["sse2"] = Features["aes"] = true;
2130    else if (Name == "pclmul")
2131      Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2132    else if (Name == "avx")
2133      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2134        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2135        Features["popcnt"] = Features["avx"] = true;
2136    else if (Name == "avx2")
2137      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2138        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2139        Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2140    else if (Name == "fma")
2141      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2142        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2143        Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2144    else if (Name == "fma4")
2145      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2146        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2147        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2148        Features["fma4"] = true;
2149    else if (Name == "xop")
2150      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2151        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2152        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2153        Features["fma4"] = Features["xop"] = true;
2154    else if (Name == "sse4a")
2155      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2156        Features["sse4a"] = true;
2157    else if (Name == "lzcnt")
2158      Features["lzcnt"] = true;
2159    else if (Name == "rdrnd")
2160      Features["rdrand"] = true;
2161    else if (Name == "bmi")
2162      Features["bmi"] = true;
2163    else if (Name == "bmi2")
2164      Features["bmi2"] = true;
2165    else if (Name == "popcnt")
2166      Features["popcnt"] = true;
2167    else if (Name == "f16c")
2168      Features["f16c"] = true;
2169    else if (Name == "rtm")
2170      Features["rtm"] = true;
2171    else if (Name == "prfchw")
2172      Features["prfchw"] = true;
2173    else if (Name == "rdseed")
2174      Features["rdseed"] = true;
2175  } else {
2176    if (Name == "mmx")
2177      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2178    else if (Name == "sse")
2179      Features["sse"] = Features["sse2"] = Features["sse3"] =
2180        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2181        Features["sse4a"] = Features["avx"] = Features["avx2"] =
2182        Features["fma"] = Features["fma4"] = Features["aes"] =
2183        Features["pclmul"] = Features["xop"] = false;
2184    else if (Name == "sse2")
2185      Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2186        Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2187        Features["avx"] = Features["avx2"] = Features["fma"] =
2188        Features["fma4"] = Features["aes"] = Features["pclmul"] =
2189        Features["xop"] = false;
2190    else if (Name == "sse3")
2191      Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2192        Features["sse42"] = Features["sse4a"] = Features["avx"] =
2193        Features["avx2"] = Features["fma"] = Features["fma4"] =
2194        Features["xop"] = false;
2195    else if (Name == "ssse3")
2196      Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2197        Features["avx"] = Features["avx2"] = Features["fma"] = false;
2198    else if (Name == "sse4" || Name == "sse4.1")
2199      Features["sse41"] = Features["sse42"] = Features["avx"] =
2200        Features["avx2"] = Features["fma"] = false;
2201    else if (Name == "sse4.2")
2202      Features["sse42"] = Features["avx"] = Features["avx2"] =
2203        Features["fma"] = false;
2204    else if (Name == "3dnow")
2205      Features["3dnow"] = Features["3dnowa"] = false;
2206    else if (Name == "3dnowa")
2207      Features["3dnowa"] = false;
2208    else if (Name == "aes")
2209      Features["aes"] = false;
2210    else if (Name == "pclmul")
2211      Features["pclmul"] = false;
2212    else if (Name == "avx")
2213      Features["avx"] = Features["avx2"] = Features["fma"] =
2214        Features["fma4"] = Features["xop"] = false;
2215    else if (Name == "avx2")
2216      Features["avx2"] = false;
2217    else if (Name == "fma")
2218      Features["fma"] = false;
2219    else if (Name == "sse4a")
2220      Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2221    else if (Name == "lzcnt")
2222      Features["lzcnt"] = false;
2223    else if (Name == "rdrnd")
2224      Features["rdrand"] = false;
2225    else if (Name == "bmi")
2226      Features["bmi"] = false;
2227    else if (Name == "bmi2")
2228      Features["bmi2"] = false;
2229    else if (Name == "popcnt")
2230      Features["popcnt"] = false;
2231    else if (Name == "fma4")
2232      Features["fma4"] = Features["xop"] = false;
2233    else if (Name == "xop")
2234      Features["xop"] = false;
2235    else if (Name == "f16c")
2236      Features["f16c"] = false;
2237    else if (Name == "rtm")
2238      Features["rtm"] = false;
2239    else if (Name == "prfchw")
2240      Features["prfchw"] = false;
2241    else if (Name == "rdseed")
2242      Features["rdseed"] = false;
2243  }
2244
2245  return true;
2246}
2247
2248/// HandleTargetOptions - Perform initialization based on the user
2249/// configured set of features.
2250void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2251  // Remember the maximum enabled sselevel.
2252  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2253    // Ignore disabled features.
2254    if (Features[i][0] == '-')
2255      continue;
2256
2257    StringRef Feature = StringRef(Features[i]).substr(1);
2258
2259    if (Feature == "aes") {
2260      HasAES = true;
2261      continue;
2262    }
2263
2264    if (Feature == "pclmul") {
2265      HasPCLMUL = true;
2266      continue;
2267    }
2268
2269    if (Feature == "lzcnt") {
2270      HasLZCNT = true;
2271      continue;
2272    }
2273
2274    if (Feature == "rdrand") {
2275      HasRDRND = true;
2276      continue;
2277    }
2278
2279    if (Feature == "bmi") {
2280      HasBMI = true;
2281      continue;
2282    }
2283
2284    if (Feature == "bmi2") {
2285      HasBMI2 = true;
2286      continue;
2287    }
2288
2289    if (Feature == "popcnt") {
2290      HasPOPCNT = true;
2291      continue;
2292    }
2293
2294    if (Feature == "rtm") {
2295      HasRTM = true;
2296      continue;
2297    }
2298
2299    if (Feature == "prfchw") {
2300      HasPRFCHW = true;
2301      continue;
2302    }
2303
2304    if (Feature == "rdseed") {
2305      HasRDSEED = true;
2306      continue;
2307    }
2308
2309    if (Feature == "sse4a") {
2310      HasSSE4a = true;
2311      continue;
2312    }
2313
2314    if (Feature == "fma4") {
2315      HasFMA4 = true;
2316      continue;
2317    }
2318
2319    if (Feature == "fma") {
2320      HasFMA = true;
2321      continue;
2322    }
2323
2324    if (Feature == "xop") {
2325      HasXOP = true;
2326      continue;
2327    }
2328
2329    if (Feature == "f16c") {
2330      HasF16C = true;
2331      continue;
2332    }
2333
2334    assert(Features[i][0] == '+' && "Invalid target feature!");
2335    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2336      .Case("avx2", AVX2)
2337      .Case("avx", AVX)
2338      .Case("sse42", SSE42)
2339      .Case("sse41", SSE41)
2340      .Case("ssse3", SSSE3)
2341      .Case("sse3", SSE3)
2342      .Case("sse2", SSE2)
2343      .Case("sse", SSE1)
2344      .Default(NoSSE);
2345    SSELevel = std::max(SSELevel, Level);
2346
2347    MMX3DNowEnum ThreeDNowLevel =
2348      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2349        .Case("3dnowa", AMD3DNowAthlon)
2350        .Case("3dnow", AMD3DNow)
2351        .Case("mmx", MMX)
2352        .Default(NoMMX3DNow);
2353
2354    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2355  }
2356
2357  // Don't tell the backend if we're turning off mmx; it will end up disabling
2358  // SSE, which we don't want.
2359  std::vector<std::string>::iterator it;
2360  it = std::find(Features.begin(), Features.end(), "-mmx");
2361  if (it != Features.end())
2362    Features.erase(it);
2363}
2364
2365/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2366/// definitions for this particular subtarget.
2367void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2368                                     MacroBuilder &Builder) const {
2369  // Target identification.
2370  if (getTriple().getArch() == llvm::Triple::x86_64) {
2371    Builder.defineMacro("__amd64__");
2372    Builder.defineMacro("__amd64");
2373    Builder.defineMacro("__x86_64");
2374    Builder.defineMacro("__x86_64__");
2375  } else {
2376    DefineStd(Builder, "i386", Opts);
2377  }
2378
2379  // Subtarget options.
2380  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2381  // truly should be based on -mtune options.
2382  switch (CPU) {
2383  case CK_Generic:
2384    break;
2385  case CK_i386:
2386    // The rest are coming from the i386 define above.
2387    Builder.defineMacro("__tune_i386__");
2388    break;
2389  case CK_i486:
2390  case CK_WinChipC6:
2391  case CK_WinChip2:
2392  case CK_C3:
2393    defineCPUMacros(Builder, "i486");
2394    break;
2395  case CK_PentiumMMX:
2396    Builder.defineMacro("__pentium_mmx__");
2397    Builder.defineMacro("__tune_pentium_mmx__");
2398    // Fallthrough
2399  case CK_i586:
2400  case CK_Pentium:
2401    defineCPUMacros(Builder, "i586");
2402    defineCPUMacros(Builder, "pentium");
2403    break;
2404  case CK_Pentium3:
2405  case CK_Pentium3M:
2406  case CK_PentiumM:
2407    Builder.defineMacro("__tune_pentium3__");
2408    // Fallthrough
2409  case CK_Pentium2:
2410  case CK_C3_2:
2411    Builder.defineMacro("__tune_pentium2__");
2412    // Fallthrough
2413  case CK_PentiumPro:
2414    Builder.defineMacro("__tune_i686__");
2415    Builder.defineMacro("__tune_pentiumpro__");
2416    // Fallthrough
2417  case CK_i686:
2418    Builder.defineMacro("__i686");
2419    Builder.defineMacro("__i686__");
2420    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2421    Builder.defineMacro("__pentiumpro");
2422    Builder.defineMacro("__pentiumpro__");
2423    break;
2424  case CK_Pentium4:
2425  case CK_Pentium4M:
2426    defineCPUMacros(Builder, "pentium4");
2427    break;
2428  case CK_Yonah:
2429  case CK_Prescott:
2430  case CK_Nocona:
2431    defineCPUMacros(Builder, "nocona");
2432    break;
2433  case CK_Core2:
2434  case CK_Penryn:
2435    defineCPUMacros(Builder, "core2");
2436    break;
2437  case CK_Atom:
2438    defineCPUMacros(Builder, "atom");
2439    break;
2440  case CK_Corei7:
2441  case CK_Corei7AVX:
2442  case CK_CoreAVXi:
2443  case CK_CoreAVX2:
2444    defineCPUMacros(Builder, "corei7");
2445    break;
2446  case CK_K6_2:
2447    Builder.defineMacro("__k6_2__");
2448    Builder.defineMacro("__tune_k6_2__");
2449    // Fallthrough
2450  case CK_K6_3:
2451    if (CPU != CK_K6_2) {  // In case of fallthrough
2452      // FIXME: GCC may be enabling these in cases where some other k6
2453      // architecture is specified but -m3dnow is explicitly provided. The
2454      // exact semantics need to be determined and emulated here.
2455      Builder.defineMacro("__k6_3__");
2456      Builder.defineMacro("__tune_k6_3__");
2457    }
2458    // Fallthrough
2459  case CK_K6:
2460    defineCPUMacros(Builder, "k6");
2461    break;
2462  case CK_Athlon:
2463  case CK_AthlonThunderbird:
2464  case CK_Athlon4:
2465  case CK_AthlonXP:
2466  case CK_AthlonMP:
2467    defineCPUMacros(Builder, "athlon");
2468    if (SSELevel != NoSSE) {
2469      Builder.defineMacro("__athlon_sse__");
2470      Builder.defineMacro("__tune_athlon_sse__");
2471    }
2472    break;
2473  case CK_K8:
2474  case CK_K8SSE3:
2475  case CK_x86_64:
2476  case CK_Opteron:
2477  case CK_OpteronSSE3:
2478  case CK_Athlon64:
2479  case CK_Athlon64SSE3:
2480  case CK_AthlonFX:
2481    defineCPUMacros(Builder, "k8");
2482    break;
2483  case CK_AMDFAM10:
2484    defineCPUMacros(Builder, "amdfam10");
2485    break;
2486  case CK_BTVER1:
2487    defineCPUMacros(Builder, "btver1");
2488    break;
2489  case CK_BTVER2:
2490    defineCPUMacros(Builder, "btver2");
2491    break;
2492  case CK_BDVER1:
2493    defineCPUMacros(Builder, "bdver1");
2494    break;
2495  case CK_BDVER2:
2496    defineCPUMacros(Builder, "bdver2");
2497    break;
2498  case CK_Geode:
2499    defineCPUMacros(Builder, "geode");
2500    break;
2501  }
2502
2503  // Target properties.
2504  Builder.defineMacro("__LITTLE_ENDIAN__");
2505  Builder.defineMacro("__REGISTER_PREFIX__", "");
2506
2507  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2508  // functions in glibc header files that use FP Stack inline asm which the
2509  // backend can't deal with (PR879).
2510  Builder.defineMacro("__NO_MATH_INLINES");
2511
2512  if (HasAES)
2513    Builder.defineMacro("__AES__");
2514
2515  if (HasPCLMUL)
2516    Builder.defineMacro("__PCLMUL__");
2517
2518  if (HasLZCNT)
2519    Builder.defineMacro("__LZCNT__");
2520
2521  if (HasRDRND)
2522    Builder.defineMacro("__RDRND__");
2523
2524  if (HasBMI)
2525    Builder.defineMacro("__BMI__");
2526
2527  if (HasBMI2)
2528    Builder.defineMacro("__BMI2__");
2529
2530  if (HasPOPCNT)
2531    Builder.defineMacro("__POPCNT__");
2532
2533  if (HasRTM)
2534    Builder.defineMacro("__RTM__");
2535
2536  if (HasPRFCHW)
2537    Builder.defineMacro("__PRFCHW__");
2538
2539  if (HasRDSEED)
2540    Builder.defineMacro("__RDSEED__");
2541
2542  if (HasSSE4a)
2543    Builder.defineMacro("__SSE4A__");
2544
2545  if (HasFMA4)
2546    Builder.defineMacro("__FMA4__");
2547
2548  if (HasFMA)
2549    Builder.defineMacro("__FMA__");
2550
2551  if (HasXOP)
2552    Builder.defineMacro("__XOP__");
2553
2554  if (HasF16C)
2555    Builder.defineMacro("__F16C__");
2556
2557  // Each case falls through to the previous one here.
2558  switch (SSELevel) {
2559  case AVX2:
2560    Builder.defineMacro("__AVX2__");
2561  case AVX:
2562    Builder.defineMacro("__AVX__");
2563  case SSE42:
2564    Builder.defineMacro("__SSE4_2__");
2565  case SSE41:
2566    Builder.defineMacro("__SSE4_1__");
2567  case SSSE3:
2568    Builder.defineMacro("__SSSE3__");
2569  case SSE3:
2570    Builder.defineMacro("__SSE3__");
2571  case SSE2:
2572    Builder.defineMacro("__SSE2__");
2573    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2574  case SSE1:
2575    Builder.defineMacro("__SSE__");
2576    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2577  case NoSSE:
2578    break;
2579  }
2580
2581  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2582    switch (SSELevel) {
2583    case AVX2:
2584    case AVX:
2585    case SSE42:
2586    case SSE41:
2587    case SSSE3:
2588    case SSE3:
2589    case SSE2:
2590      Builder.defineMacro("_M_IX86_FP", Twine(2));
2591      break;
2592    case SSE1:
2593      Builder.defineMacro("_M_IX86_FP", Twine(1));
2594      break;
2595    default:
2596      Builder.defineMacro("_M_IX86_FP", Twine(0));
2597    }
2598  }
2599
2600  // Each case falls through to the previous one here.
2601  switch (MMX3DNowLevel) {
2602  case AMD3DNowAthlon:
2603    Builder.defineMacro("__3dNOW_A__");
2604  case AMD3DNow:
2605    Builder.defineMacro("__3dNOW__");
2606  case MMX:
2607    Builder.defineMacro("__MMX__");
2608  case NoMMX3DNow:
2609    break;
2610  }
2611
2612  if (CPU >= CK_i486) {
2613    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2614    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2615    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2616  }
2617  if (CPU >= CK_i586)
2618    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2619}
2620
2621bool X86TargetInfo::hasFeature(StringRef Feature) const {
2622  return llvm::StringSwitch<bool>(Feature)
2623      .Case("aes", HasAES)
2624      .Case("avx", SSELevel >= AVX)
2625      .Case("avx2", SSELevel >= AVX2)
2626      .Case("bmi", HasBMI)
2627      .Case("bmi2", HasBMI2)
2628      .Case("fma", HasFMA)
2629      .Case("fma4", HasFMA4)
2630      .Case("lzcnt", HasLZCNT)
2631      .Case("rdrnd", HasRDRND)
2632      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2633      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2634      .Case("mmx", MMX3DNowLevel >= MMX)
2635      .Case("pclmul", HasPCLMUL)
2636      .Case("popcnt", HasPOPCNT)
2637      .Case("rtm", HasRTM)
2638      .Case("prfchw", HasPRFCHW)
2639      .Case("rdseed", HasRDSEED)
2640      .Case("sse", SSELevel >= SSE1)
2641      .Case("sse2", SSELevel >= SSE2)
2642      .Case("sse3", SSELevel >= SSE3)
2643      .Case("ssse3", SSELevel >= SSSE3)
2644      .Case("sse41", SSELevel >= SSE41)
2645      .Case("sse42", SSELevel >= SSE42)
2646      .Case("sse4a", HasSSE4a)
2647      .Case("x86", true)
2648      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2649      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2650      .Case("xop", HasXOP)
2651      .Case("f16c", HasF16C)
2652      .Default(false);
2653}
2654
2655bool
2656X86TargetInfo::validateAsmConstraint(const char *&Name,
2657                                     TargetInfo::ConstraintInfo &Info) const {
2658  switch (*Name) {
2659  default: return false;
2660  case 'Y': // first letter of a pair:
2661    switch (*(Name+1)) {
2662    default: return false;
2663    case '0':  // First SSE register.
2664    case 't':  // Any SSE register, when SSE2 is enabled.
2665    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2666    case 'm':  // any MMX register, when inter-unit moves enabled.
2667      break;   // falls through to setAllowsRegister.
2668  }
2669  case 'a': // eax.
2670  case 'b': // ebx.
2671  case 'c': // ecx.
2672  case 'd': // edx.
2673  case 'S': // esi.
2674  case 'D': // edi.
2675  case 'A': // edx:eax.
2676  case 'f': // any x87 floating point stack register.
2677  case 't': // top of floating point stack.
2678  case 'u': // second from top of floating point stack.
2679  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2680  case 'y': // Any MMX register.
2681  case 'x': // Any SSE register.
2682  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2683  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2684  case 'l': // "Index" registers: any general register that can be used as an
2685            // index in a base+index memory access.
2686    Info.setAllowsRegister();
2687    return true;
2688  case 'C': // SSE floating point constant.
2689  case 'G': // x87 floating point constant.
2690  case 'e': // 32-bit signed integer constant for use with zero-extending
2691            // x86_64 instructions.
2692  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2693            // x86_64 instructions.
2694    return true;
2695  }
2696}
2697
2698
2699std::string
2700X86TargetInfo::convertConstraint(const char *&Constraint) const {
2701  switch (*Constraint) {
2702  case 'a': return std::string("{ax}");
2703  case 'b': return std::string("{bx}");
2704  case 'c': return std::string("{cx}");
2705  case 'd': return std::string("{dx}");
2706  case 'S': return std::string("{si}");
2707  case 'D': return std::string("{di}");
2708  case 'p': // address
2709    return std::string("im");
2710  case 't': // top of floating point stack.
2711    return std::string("{st}");
2712  case 'u': // second from top of floating point stack.
2713    return std::string("{st(1)}"); // second from top of floating point stack.
2714  default:
2715    return std::string(1, *Constraint);
2716  }
2717}
2718} // end anonymous namespace
2719
2720namespace {
2721// X86-32 generic target
2722class X86_32TargetInfo : public X86TargetInfo {
2723public:
2724  X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
2725    DoubleAlign = LongLongAlign = 32;
2726    LongDoubleWidth = 96;
2727    LongDoubleAlign = 32;
2728    SuitableAlign = 128;
2729    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2730                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2731                        "a0:0:64-f80:32:32-n8:16:32-S128";
2732    SizeType = UnsignedInt;
2733    PtrDiffType = SignedInt;
2734    IntPtrType = SignedInt;
2735    RegParmMax = 3;
2736
2737    // Use fpret for all types.
2738    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2739                             (1 << TargetInfo::Double) |
2740                             (1 << TargetInfo::LongDouble));
2741
2742    // x86-32 has atomics up to 8 bytes
2743    // FIXME: Check that we actually have cmpxchg8b before setting
2744    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2745    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2746  }
2747  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2748    return TargetInfo::CharPtrBuiltinVaList;
2749  }
2750
2751  int getEHDataRegisterNumber(unsigned RegNo) const {
2752    if (RegNo == 0) return 0;
2753    if (RegNo == 1) return 2;
2754    return -1;
2755  }
2756  virtual bool validateInputSize(StringRef Constraint,
2757                                 unsigned Size) const {
2758    switch (Constraint[0]) {
2759    default: break;
2760    case 'a':
2761    case 'b':
2762    case 'c':
2763    case 'd':
2764      return Size <= 32;
2765    }
2766
2767    return true;
2768  }
2769};
2770} // end anonymous namespace
2771
2772namespace {
2773class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2774public:
2775  NetBSDI386TargetInfo(const llvm::Triple &Triple)
2776      : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
2777
2778  virtual unsigned getFloatEvalMethod() const {
2779    // NetBSD defaults to "double" rounding
2780    return 1;
2781  }
2782};
2783} // end anonymous namespace
2784
2785namespace {
2786class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2787public:
2788  OpenBSDI386TargetInfo(const llvm::Triple &Triple)
2789      : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
2790    SizeType = UnsignedLong;
2791    IntPtrType = SignedLong;
2792    PtrDiffType = SignedLong;
2793  }
2794};
2795} // end anonymous namespace
2796
2797namespace {
2798class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2799public:
2800  BitrigI386TargetInfo(const llvm::Triple &Triple)
2801      : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
2802    SizeType = UnsignedLong;
2803    IntPtrType = SignedLong;
2804    PtrDiffType = SignedLong;
2805  }
2806};
2807} // end anonymous namespace
2808
2809namespace {
2810class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2811public:
2812  DarwinI386TargetInfo(const llvm::Triple &Triple)
2813      : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
2814    LongDoubleWidth = 128;
2815    LongDoubleAlign = 128;
2816    SuitableAlign = 128;
2817    MaxVectorAlign = 256;
2818    SizeType = UnsignedLong;
2819    IntPtrType = SignedLong;
2820    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2821                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2822                        "a0:0:64-f80:128:128-n8:16:32-S128";
2823    HasAlignMac68kSupport = true;
2824  }
2825
2826};
2827} // end anonymous namespace
2828
2829namespace {
2830// x86-32 Windows target
2831class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2832public:
2833  WindowsX86_32TargetInfo(const llvm::Triple &Triple)
2834      : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
2835    TLSSupported = false;
2836    WCharType = UnsignedShort;
2837    DoubleAlign = LongLongAlign = 64;
2838    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2839                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2840                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2841  }
2842  virtual void getTargetDefines(const LangOptions &Opts,
2843                                MacroBuilder &Builder) const {
2844    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2845  }
2846};
2847} // end anonymous namespace
2848
2849namespace {
2850
2851// x86-32 Windows Visual Studio target
2852class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2853public:
2854  VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple)
2855      : WindowsX86_32TargetInfo(Triple) {
2856    LongDoubleWidth = LongDoubleAlign = 64;
2857    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2858  }
2859  virtual void getTargetDefines(const LangOptions &Opts,
2860                                MacroBuilder &Builder) const {
2861    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2862    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2863    // The value of the following reflects processor type.
2864    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2865    // We lost the original triple, so we use the default.
2866    Builder.defineMacro("_M_IX86", "600");
2867  }
2868};
2869} // end anonymous namespace
2870
2871namespace {
2872// x86-32 MinGW target
2873class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
2874public:
2875  MinGWX86_32TargetInfo(const llvm::Triple &Triple)
2876      : WindowsX86_32TargetInfo(Triple) {}
2877  virtual void getTargetDefines(const LangOptions &Opts,
2878                                MacroBuilder &Builder) const {
2879    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2880    DefineStd(Builder, "WIN32", Opts);
2881    DefineStd(Builder, "WINNT", Opts);
2882    Builder.defineMacro("_X86_");
2883    Builder.defineMacro("__MSVCRT__");
2884    Builder.defineMacro("__MINGW32__");
2885
2886    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
2887    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
2888    if (Opts.MicrosoftExt)
2889      // Provide "as-is" __declspec.
2890      Builder.defineMacro("__declspec", "__declspec");
2891    else
2892      // Provide alias of __attribute__ like mingw32-gcc.
2893      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
2894  }
2895};
2896} // end anonymous namespace
2897
2898namespace {
2899// x86-32 Cygwin target
2900class CygwinX86_32TargetInfo : public X86_32TargetInfo {
2901public:
2902  CygwinX86_32TargetInfo(const llvm::Triple &Triple)
2903      : X86_32TargetInfo(Triple) {
2904    TLSSupported = false;
2905    WCharType = UnsignedShort;
2906    DoubleAlign = LongLongAlign = 64;
2907    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2908                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
2909                        "a0:0:64-f80:32:32-n8:16:32-S32";
2910  }
2911  virtual void getTargetDefines(const LangOptions &Opts,
2912                                MacroBuilder &Builder) const {
2913    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2914    Builder.defineMacro("_X86_");
2915    Builder.defineMacro("__CYGWIN__");
2916    Builder.defineMacro("__CYGWIN32__");
2917    DefineStd(Builder, "unix", Opts);
2918    if (Opts.CPlusPlus)
2919      Builder.defineMacro("_GNU_SOURCE");
2920  }
2921};
2922} // end anonymous namespace
2923
2924namespace {
2925// x86-32 Haiku target
2926class HaikuX86_32TargetInfo : public X86_32TargetInfo {
2927public:
2928  HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
2929    SizeType = UnsignedLong;
2930    IntPtrType = SignedLong;
2931    PtrDiffType = SignedLong;
2932    ProcessIDType = SignedLong;
2933    this->UserLabelPrefix = "";
2934    this->TLSSupported = false;
2935  }
2936  virtual void getTargetDefines(const LangOptions &Opts,
2937                                MacroBuilder &Builder) const {
2938    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2939    Builder.defineMacro("__INTEL__");
2940    Builder.defineMacro("__HAIKU__");
2941  }
2942};
2943} // end anonymous namespace
2944
2945// RTEMS Target
2946template<typename Target>
2947class RTEMSTargetInfo : public OSTargetInfo<Target> {
2948protected:
2949  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
2950                            MacroBuilder &Builder) const {
2951    // RTEMS defines; list based off of gcc output
2952
2953    Builder.defineMacro("__rtems__");
2954    Builder.defineMacro("__ELF__");
2955  }
2956
2957public:
2958  RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
2959    this->UserLabelPrefix = "";
2960
2961    switch (Triple.getArch()) {
2962    default:
2963    case llvm::Triple::x86:
2964      // this->MCountName = ".mcount";
2965      break;
2966    case llvm::Triple::mips:
2967    case llvm::Triple::mipsel:
2968    case llvm::Triple::ppc:
2969    case llvm::Triple::ppc64:
2970      // this->MCountName = "_mcount";
2971      break;
2972    case llvm::Triple::arm:
2973      // this->MCountName = "__mcount";
2974      break;
2975    }
2976  }
2977};
2978
2979namespace {
2980// x86-32 RTEMS target
2981class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
2982public:
2983  RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
2984    SizeType = UnsignedLong;
2985    IntPtrType = SignedLong;
2986    PtrDiffType = SignedLong;
2987    this->UserLabelPrefix = "";
2988  }
2989  virtual void getTargetDefines(const LangOptions &Opts,
2990                                MacroBuilder &Builder) const {
2991    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2992    Builder.defineMacro("__INTEL__");
2993    Builder.defineMacro("__rtems__");
2994  }
2995};
2996} // end anonymous namespace
2997
2998namespace {
2999// x86-64 generic target
3000class X86_64TargetInfo : public X86TargetInfo {
3001public:
3002  X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3003    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3004    LongDoubleWidth = 128;
3005    LongDoubleAlign = 128;
3006    LargeArrayMinWidth = 128;
3007    LargeArrayAlign = 128;
3008    SuitableAlign = 128;
3009    IntMaxType = SignedLong;
3010    UIntMaxType = UnsignedLong;
3011    Int64Type = SignedLong;
3012    RegParmMax = 6;
3013
3014    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3015                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3016                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3017
3018    // Use fpret only for long double.
3019    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3020
3021    // Use fp2ret for _Complex long double.
3022    ComplexLongDoubleUsesFP2Ret = true;
3023
3024    // x86-64 has atomics up to 16 bytes.
3025    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3026    // on CPUs with cmpxchg16b
3027    MaxAtomicPromoteWidth = 128;
3028    MaxAtomicInlineWidth = 64;
3029  }
3030  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3031    return TargetInfo::X86_64ABIBuiltinVaList;
3032  }
3033
3034  int getEHDataRegisterNumber(unsigned RegNo) const {
3035    if (RegNo == 0) return 0;
3036    if (RegNo == 1) return 1;
3037    return -1;
3038  }
3039
3040  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3041    return (CC == CC_Default ||
3042            CC == CC_C ||
3043            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3044  }
3045
3046  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3047    return CC_C;
3048  }
3049
3050};
3051} // end anonymous namespace
3052
3053namespace {
3054// x86-64 Windows target
3055class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3056public:
3057  WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3058      : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3059    TLSSupported = false;
3060    WCharType = UnsignedShort;
3061    LongWidth = LongAlign = 32;
3062    DoubleAlign = LongLongAlign = 64;
3063    IntMaxType = SignedLongLong;
3064    UIntMaxType = UnsignedLongLong;
3065    Int64Type = SignedLongLong;
3066    SizeType = UnsignedLongLong;
3067    PtrDiffType = SignedLongLong;
3068    IntPtrType = SignedLongLong;
3069    this->UserLabelPrefix = "";
3070  }
3071  virtual void getTargetDefines(const LangOptions &Opts,
3072                                MacroBuilder &Builder) const {
3073    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3074    Builder.defineMacro("_WIN64");
3075  }
3076  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3077    return TargetInfo::CharPtrBuiltinVaList;
3078  }
3079};
3080} // end anonymous namespace
3081
3082namespace {
3083// x86-64 Windows Visual Studio target
3084class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3085public:
3086  VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple)
3087      : WindowsX86_64TargetInfo(Triple) {
3088    LongDoubleWidth = LongDoubleAlign = 64;
3089    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3090  }
3091  virtual void getTargetDefines(const LangOptions &Opts,
3092                                MacroBuilder &Builder) const {
3093    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3094    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3095    Builder.defineMacro("_M_X64");
3096    Builder.defineMacro("_M_AMD64");
3097  }
3098};
3099} // end anonymous namespace
3100
3101namespace {
3102// x86-64 MinGW target
3103class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3104public:
3105  MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3106      : WindowsX86_64TargetInfo(Triple) {}
3107  virtual void getTargetDefines(const LangOptions &Opts,
3108                                MacroBuilder &Builder) const {
3109    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3110    DefineStd(Builder, "WIN64", Opts);
3111    Builder.defineMacro("__MSVCRT__");
3112    Builder.defineMacro("__MINGW32__");
3113    Builder.defineMacro("__MINGW64__");
3114
3115    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3116    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3117    if (Opts.MicrosoftExt)
3118      // Provide "as-is" __declspec.
3119      Builder.defineMacro("__declspec", "__declspec");
3120    else
3121      // Provide alias of __attribute__ like mingw32-gcc.
3122      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3123  }
3124};
3125} // end anonymous namespace
3126
3127namespace {
3128class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3129public:
3130  DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3131      : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3132    Int64Type = SignedLongLong;
3133    MaxVectorAlign = 256;
3134  }
3135};
3136} // end anonymous namespace
3137
3138namespace {
3139class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3140public:
3141  OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3142      : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3143    IntMaxType = SignedLongLong;
3144    UIntMaxType = UnsignedLongLong;
3145    Int64Type = SignedLongLong;
3146  }
3147};
3148} // end anonymous namespace
3149
3150namespace {
3151class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3152public:
3153  BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3154      : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3155    IntMaxType = SignedLongLong;
3156    UIntMaxType = UnsignedLongLong;
3157    Int64Type = SignedLongLong;
3158  }
3159};
3160}
3161
3162namespace {
3163class AArch64TargetInfo : public TargetInfo {
3164  static const char * const GCCRegNames[];
3165  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3166
3167  static const Builtin::Info BuiltinInfo[];
3168public:
3169  AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
3170    BigEndian = false;
3171    LongWidth = LongAlign = 64;
3172    LongDoubleWidth = LongDoubleAlign = 128;
3173    PointerWidth = PointerAlign = 64;
3174    SuitableAlign = 128;
3175    DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3176                        "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3177                        "f128:128:128-n32:64-S128";
3178
3179    WCharType = UnsignedInt;
3180    LongDoubleFormat = &llvm::APFloat::IEEEquad;
3181
3182    // AArch64 backend supports 64-bit operations at the moment. In principle
3183    // 128-bit is possible if register-pairs are used.
3184    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3185
3186    TheCXXABI.set(TargetCXXABI::GenericAArch64);
3187  }
3188  virtual void getTargetDefines(const LangOptions &Opts,
3189                                MacroBuilder &Builder) const {
3190    // GCC defines theses currently
3191    Builder.defineMacro("__aarch64__");
3192    Builder.defineMacro("__AARCH64EL__");
3193
3194    // ACLE predefines. Many can only have one possible value on v8 AArch64.
3195
3196    // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3197    // which was intended to be compatible with a 64-bit implementation. They
3198    // will need updating when a real 64-bit ACLE exists. Particularly pressing
3199    // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3200    Builder.defineMacro("__ARM_ACLE",         "101");
3201    Builder.defineMacro("__ARM_ARCH",         "8");
3202    Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3203
3204    Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3205    Builder.defineMacro("__ARM_FEATURE_CLZ");
3206    Builder.defineMacro("__ARM_FEATURE_FMA");
3207
3208    // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3209    // 128-bit LDXP present, at which point this becomes 0x1f.
3210    Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3211
3212    // 0xe implies support for half, single and double precision operations.
3213    Builder.defineMacro("__ARM_FP", "0xe");
3214
3215    // PCS specifies this for SysV variants, which is all we support. Other ABIs
3216    // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3217    Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3218
3219    if (Opts.FastMath || Opts.FiniteMathOnly)
3220      Builder.defineMacro("__ARM_FP_FAST");
3221
3222    if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3223      Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3224
3225    Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3226                        Opts.ShortWChar ? "2" : "4");
3227
3228    Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3229                        Opts.ShortEnums ? "1" : "4");
3230
3231    if (BigEndian)
3232      Builder.defineMacro("__ARM_BIG_ENDIAN");
3233  }
3234  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3235                                 unsigned &NumRecords) const {
3236    Records = BuiltinInfo;
3237    NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3238  }
3239  virtual bool hasFeature(StringRef Feature) const {
3240    return Feature == "aarch64";
3241  }
3242  virtual void getGCCRegNames(const char * const *&Names,
3243                              unsigned &NumNames) const;
3244  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3245                                unsigned &NumAliases) const;
3246
3247  virtual bool isCLZForZeroUndef() const { return false; }
3248
3249  virtual bool validateAsmConstraint(const char *&Name,
3250                                     TargetInfo::ConstraintInfo &Info) const {
3251    switch (*Name) {
3252    default: return false;
3253    case 'w': // An FP/SIMD vector register
3254      Info.setAllowsRegister();
3255      return true;
3256    case 'I': // Constant that can be used with an ADD instruction
3257    case 'J': // Constant that can be used with a SUB instruction
3258    case 'K': // Constant that can be used with a 32-bit logical instruction
3259    case 'L': // Constant that can be used with a 64-bit logical instruction
3260    case 'M': // Constant that can be used as a 32-bit MOV immediate
3261    case 'N': // Constant that can be used as a 64-bit MOV immediate
3262    case 'Y': // Floating point constant zero
3263    case 'Z': // Integer constant zero
3264      return true;
3265    case 'Q': // A memory reference with base register and no offset
3266      Info.setAllowsMemory();
3267      return true;
3268    case 'S': // A symbolic address
3269      Info.setAllowsRegister();
3270      return true;
3271    case 'U':
3272      // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3273      // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3274      // Usa: An absolute symbolic address
3275      // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3276      llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3277    }
3278  }
3279
3280  virtual const char *getClobbers() const {
3281    // There are no AArch64 clobbers shared by all asm statements.
3282    return "";
3283  }
3284
3285  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3286    return TargetInfo::AArch64ABIBuiltinVaList;
3287  }
3288};
3289
3290const char * const AArch64TargetInfo::GCCRegNames[] = {
3291  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3292  "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3293  "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3294  "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3295
3296  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3297  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3298  "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3299  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3300
3301  "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3302  "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3303  "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3304  "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3305
3306  "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3307  "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3308  "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3309  "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3310
3311  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3312  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3313  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3314  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3315
3316  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3317  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3318  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3319  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3320
3321  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3322  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3323  "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3324  "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3325};
3326
3327void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3328                                       unsigned &NumNames) const {
3329  Names = GCCRegNames;
3330  NumNames = llvm::array_lengthof(GCCRegNames);
3331}
3332
3333const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3334  { { "x16" }, "ip0"},
3335  { { "x17" }, "ip1"},
3336  { { "x29" }, "fp" },
3337  { { "x30" }, "lr" }
3338};
3339
3340void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3341                                         unsigned &NumAliases) const {
3342  Aliases = GCCRegAliases;
3343  NumAliases = llvm::array_lengthof(GCCRegAliases);
3344
3345}
3346
3347const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3348#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3349#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3350                                              ALL_LANGUAGES },
3351#include "clang/Basic/BuiltinsAArch64.def"
3352};
3353
3354} // end anonymous namespace
3355
3356namespace {
3357class ARMTargetInfo : public TargetInfo {
3358  // Possible FPU choices.
3359  enum FPUMode {
3360    VFP2FPU = (1 << 0),
3361    VFP3FPU = (1 << 1),
3362    VFP4FPU = (1 << 2),
3363    NeonFPU = (1 << 3)
3364  };
3365
3366  static bool FPUModeIsVFP(FPUMode Mode) {
3367    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3368  }
3369
3370  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3371  static const char * const GCCRegNames[];
3372
3373  std::string ABI, CPU;
3374
3375  unsigned FPU : 4;
3376
3377  unsigned IsAAPCS : 1;
3378  unsigned IsThumb : 1;
3379
3380  // Initialized via features.
3381  unsigned SoftFloat : 1;
3382  unsigned SoftFloatABI : 1;
3383
3384  static const Builtin::Info BuiltinInfo[];
3385
3386  static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3387    // On linux, binaries targeting old cpus call functions in libgcc to
3388    // perform atomic operations. The implementation in libgcc then calls into
3389    // the kernel which on armv6 and newer uses ldrex and strex. The net result
3390    // is that if we assume the kernel is at least as recent as the hardware,
3391    // it is safe to use atomic instructions on armv6 and newer.
3392    if (T.getOS() != llvm::Triple::Linux &&
3393        T.getOS() != llvm::Triple::FreeBSD &&
3394        T.getOS() != llvm::Triple::Bitrig)
3395      return false;
3396    StringRef ArchName = T.getArchName();
3397    if (T.getArch() == llvm::Triple::arm) {
3398      if (!ArchName.startswith("armv"))
3399        return false;
3400      StringRef VersionStr = ArchName.substr(4);
3401      unsigned Version;
3402      if (VersionStr.getAsInteger(10, Version))
3403        return false;
3404      return Version >= 6;
3405    }
3406    assert(T.getArch() == llvm::Triple::thumb);
3407    if (!ArchName.startswith("thumbv"))
3408      return false;
3409    StringRef VersionStr = ArchName.substr(6);
3410    unsigned Version;
3411    if (VersionStr.getAsInteger(10, Version))
3412      return false;
3413    return Version >= 7;
3414  }
3415
3416public:
3417  ARMTargetInfo(const llvm::Triple &Triple)
3418      : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"),
3419        IsAAPCS(true) {
3420    BigEndian = false;
3421    SizeType = UnsignedInt;
3422    PtrDiffType = SignedInt;
3423    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3424    WCharType = UnsignedInt;
3425
3426    // {} in inline assembly are neon specifiers, not assembly variant
3427    // specifiers.
3428    NoAsmVariants = true;
3429
3430    // FIXME: Should we just treat this as a feature?
3431    IsThumb = getTriple().getArchName().startswith("thumb");
3432    if (IsThumb) {
3433      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3434      // so set preferred for small types to 32.
3435      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3436                           "i64:64:64-f32:32:32-f64:64:64-"
3437                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3438    } else {
3439      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3440                           "i64:64:64-f32:32:32-f64:64:64-"
3441                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3442    }
3443
3444    // ARM targets default to using the ARM C++ ABI.
3445    TheCXXABI.set(TargetCXXABI::GenericARM);
3446
3447    // ARM has atomics up to 8 bytes
3448    MaxAtomicPromoteWidth = 64;
3449    if (shouldUseInlineAtomic(getTriple()))
3450      MaxAtomicInlineWidth = 64;
3451
3452    // Do force alignment of members that follow zero length bitfields.  If
3453    // the alignment of the zero-length bitfield is greater than the member
3454    // that follows it, `bar', `bar' will be aligned as the  type of the
3455    // zero length bitfield.
3456    UseZeroLengthBitfieldAlignment = true;
3457  }
3458  virtual const char *getABI() const { return ABI.c_str(); }
3459  virtual bool setABI(const std::string &Name) {
3460    ABI = Name;
3461
3462    // The defaults (above) are for AAPCS, check if we need to change them.
3463    //
3464    // FIXME: We need support for -meabi... we could just mangle it into the
3465    // name.
3466    if (Name == "apcs-gnu") {
3467      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3468      // size_t is unsigned int on FreeBSD.
3469      if (getTriple().getOS() != llvm::Triple::FreeBSD)
3470        SizeType = UnsignedLong;
3471
3472      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3473      WCharType = SignedInt;
3474
3475      // Do not respect the alignment of bit-field types when laying out
3476      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3477      UseBitFieldTypeAlignment = false;
3478
3479      /// gcc forces the alignment to 4 bytes, regardless of the type of the
3480      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3481      /// gcc.
3482      ZeroLengthBitfieldBoundary = 32;
3483
3484      IsAAPCS = false;
3485
3486      if (IsThumb) {
3487        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3488        // so set preferred for small types to 32.
3489        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3490                             "i64:32:64-f32:32:32-f64:32:64-"
3491                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3492      } else {
3493        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3494                             "i64:32:64-f32:32:32-f64:32:64-"
3495                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3496      }
3497
3498      // FIXME: Override "preferred align" for double and long long.
3499    } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3500      // size_t is unsigned long on Darwin.
3501      if (getTriple().isOSDarwin())
3502        SizeType = UnsignedLong;
3503      IsAAPCS = true;
3504      // FIXME: Enumerated types are variable width in straight AAPCS.
3505    } else if (Name == "aapcs-linux") {
3506      IsAAPCS = true;
3507    } else
3508      return false;
3509
3510    return true;
3511  }
3512
3513  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3514    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3515      Features["vfp2"] = true;
3516    else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3517             CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3518      Features["neon"] = true;
3519    else if (CPU == "swift" || CPU == "cortex-a7") {
3520      Features["vfp4"] = true;
3521      Features["neon"] = true;
3522    }
3523  }
3524
3525  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3526                                 StringRef Name,
3527                                 bool Enabled) const {
3528    if (Name == "soft-float" || Name == "soft-float-abi" ||
3529        Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3530        Name == "d16" || Name == "neonfp" || Name == "v8fp") {
3531      Features[Name] = Enabled;
3532    } else
3533      return false;
3534
3535    return true;
3536  }
3537
3538  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3539    FPU = 0;
3540    SoftFloat = SoftFloatABI = false;
3541    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3542      if (Features[i] == "+soft-float")
3543        SoftFloat = true;
3544      else if (Features[i] == "+soft-float-abi")
3545        SoftFloatABI = true;
3546      else if (Features[i] == "+vfp2")
3547        FPU |= VFP2FPU;
3548      else if (Features[i] == "+vfp3")
3549        FPU |= VFP3FPU;
3550      else if (Features[i] == "+vfp4")
3551        FPU |= VFP4FPU;
3552      else if (Features[i] == "+neon")
3553        FPU |= NeonFPU;
3554    }
3555
3556    // Remove front-end specific options which the backend handles differently.
3557    std::vector<std::string>::iterator it;
3558    it = std::find(Features.begin(), Features.end(), "+soft-float");
3559    if (it != Features.end())
3560      Features.erase(it);
3561    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3562    if (it != Features.end())
3563      Features.erase(it);
3564  }
3565
3566  virtual bool hasFeature(StringRef Feature) const {
3567    return llvm::StringSwitch<bool>(Feature)
3568        .Case("arm", true)
3569        .Case("softfloat", SoftFloat)
3570        .Case("thumb", IsThumb)
3571        .Case("neon", FPU == NeonFPU && !SoftFloat &&
3572              StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3573        .Default(false);
3574  }
3575  // FIXME: Should we actually have some table instead of these switches?
3576  static const char *getCPUDefineSuffix(StringRef Name) {
3577    return llvm::StringSwitch<const char*>(Name)
3578      .Cases("arm8", "arm810", "4")
3579      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3580      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3581      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3582      .Case("ep9312", "4T")
3583      .Cases("arm10tdmi", "arm1020t", "5T")
3584      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3585      .Case("arm926ej-s", "5TEJ")
3586      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3587      .Cases("xscale", "iwmmxt", "5TE")
3588      .Case("arm1136j-s", "6J")
3589      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3590      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3591      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3592      .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3593      .Cases("cortex-a9", "cortex-a15", "7A")
3594      .Case("cortex-r5", "7R")
3595      .Case("cortex-a9-mp", "7F")
3596      .Case("swift", "7S")
3597      .Cases("cortex-m3", "cortex-m4", "7M")
3598      .Case("cortex-m0", "6M")
3599      .Case("cortex-a53", "8A")
3600      .Default(0);
3601  }
3602  static const char *getCPUProfile(StringRef Name) {
3603    return llvm::StringSwitch<const char*>(Name)
3604      .Cases("cortex-a8", "cortex-a9", "A")
3605      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3606      .Case("cortex-r5", "R")
3607      .Default("");
3608  }
3609  virtual bool setCPU(const std::string &Name) {
3610    if (!getCPUDefineSuffix(Name))
3611      return false;
3612
3613    CPU = Name;
3614    return true;
3615  }
3616  virtual void getTargetDefines(const LangOptions &Opts,
3617                                MacroBuilder &Builder) const {
3618    // Target identification.
3619    Builder.defineMacro("__arm");
3620    Builder.defineMacro("__arm__");
3621
3622    // Target properties.
3623    Builder.defineMacro("__ARMEL__");
3624    Builder.defineMacro("__LITTLE_ENDIAN__");
3625    Builder.defineMacro("__REGISTER_PREFIX__", "");
3626
3627    StringRef CPUArch = getCPUDefineSuffix(CPU);
3628    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3629    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3630    StringRef CPUProfile = getCPUProfile(CPU);
3631    if (!CPUProfile.empty())
3632      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3633
3634    // Subtarget options.
3635
3636    // FIXME: It's more complicated than this and we don't really support
3637    // interworking.
3638    if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3639      Builder.defineMacro("__THUMB_INTERWORK__");
3640
3641    if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3642      // M-class CPUs on Darwin follow AAPCS, but not EABI.
3643      if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3644        Builder.defineMacro("__ARM_EABI__");
3645      Builder.defineMacro("__ARM_PCS", "1");
3646
3647      if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3648        Builder.defineMacro("__ARM_PCS_VFP", "1");
3649    }
3650
3651    if (SoftFloat)
3652      Builder.defineMacro("__SOFTFP__");
3653
3654    if (CPU == "xscale")
3655      Builder.defineMacro("__XSCALE__");
3656
3657    bool IsARMv7 = CPUArch.startswith("7");
3658    if (IsThumb) {
3659      Builder.defineMacro("__THUMBEL__");
3660      Builder.defineMacro("__thumb__");
3661      if (CPUArch == "6T2" || IsARMv7)
3662        Builder.defineMacro("__thumb2__");
3663    }
3664
3665    // Note, this is always on in gcc, even though it doesn't make sense.
3666    Builder.defineMacro("__APCS_32__");
3667
3668    if (FPUModeIsVFP((FPUMode) FPU)) {
3669      Builder.defineMacro("__VFP_FP__");
3670      if (FPU & VFP2FPU)
3671        Builder.defineMacro("__ARM_VFPV2__");
3672      if (FPU & VFP3FPU)
3673        Builder.defineMacro("__ARM_VFPV3__");
3674      if (FPU & VFP4FPU)
3675        Builder.defineMacro("__ARM_VFPV4__");
3676    }
3677
3678    // This only gets set when Neon instructions are actually available, unlike
3679    // the VFP define, hence the soft float and arch check. This is subtly
3680    // different from gcc, we follow the intent which was that it should be set
3681    // when Neon instructions are actually available.
3682    if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3683      Builder.defineMacro("__ARM_NEON__");
3684  }
3685  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3686                                 unsigned &NumRecords) const {
3687    Records = BuiltinInfo;
3688    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3689  }
3690  virtual bool isCLZForZeroUndef() const { return false; }
3691  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3692    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3693  }
3694  virtual void getGCCRegNames(const char * const *&Names,
3695                              unsigned &NumNames) const;
3696  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3697                                unsigned &NumAliases) const;
3698  virtual bool validateAsmConstraint(const char *&Name,
3699                                     TargetInfo::ConstraintInfo &Info) const {
3700    switch (*Name) {
3701    default: break;
3702    case 'l': // r0-r7
3703    case 'h': // r8-r15
3704    case 'w': // VFP Floating point register single precision
3705    case 'P': // VFP Floating point register double precision
3706      Info.setAllowsRegister();
3707      return true;
3708    case 'Q': // A memory address that is a single base register.
3709      Info.setAllowsMemory();
3710      return true;
3711    case 'U': // a memory reference...
3712      switch (Name[1]) {
3713      case 'q': // ...ARMV4 ldrsb
3714      case 'v': // ...VFP load/store (reg+constant offset)
3715      case 'y': // ...iWMMXt load/store
3716      case 't': // address valid for load/store opaque types wider
3717                // than 128-bits
3718      case 'n': // valid address for Neon doubleword vector load/store
3719      case 'm': // valid address for Neon element and structure load/store
3720      case 's': // valid address for non-offset loads/stores of quad-word
3721                // values in four ARM registers
3722        Info.setAllowsMemory();
3723        Name++;
3724        return true;
3725      }
3726    }
3727    return false;
3728  }
3729  virtual std::string convertConstraint(const char *&Constraint) const {
3730    std::string R;
3731    switch (*Constraint) {
3732    case 'U':   // Two-character constraint; add "^" hint for later parsing.
3733      R = std::string("^") + std::string(Constraint, 2);
3734      Constraint++;
3735      break;
3736    case 'p': // 'p' should be translated to 'r' by default.
3737      R = std::string("r");
3738      break;
3739    default:
3740      return std::string(1, *Constraint);
3741    }
3742    return R;
3743  }
3744  virtual bool validateConstraintModifier(StringRef Constraint,
3745                                          const char Modifier,
3746                                          unsigned Size) const {
3747    bool isOutput = (Constraint[0] == '=');
3748    bool isInOut = (Constraint[0] == '+');
3749
3750    // Strip off constraint modifiers.
3751    while (Constraint[0] == '=' ||
3752           Constraint[0] == '+' ||
3753           Constraint[0] == '&')
3754      Constraint = Constraint.substr(1);
3755
3756    switch (Constraint[0]) {
3757    default: break;
3758    case 'r': {
3759      switch (Modifier) {
3760      default:
3761        return (isInOut || isOutput || Size <= 32);
3762      case 'q':
3763        // A register of size 32 cannot fit a vector type.
3764        return false;
3765      }
3766    }
3767    }
3768
3769    return true;
3770  }
3771  virtual const char *getClobbers() const {
3772    // FIXME: Is this really right?
3773    return "";
3774  }
3775
3776  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3777    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3778  }
3779
3780  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3781    if (RegNo == 0) return 0;
3782    if (RegNo == 1) return 1;
3783    return -1;
3784  }
3785};
3786
3787const char * const ARMTargetInfo::GCCRegNames[] = {
3788  // Integer registers
3789  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3790  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3791
3792  // Float registers
3793  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3794  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3795  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3796  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3797
3798  // Double registers
3799  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3800  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3801  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3802  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3803
3804  // Quad registers
3805  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3806  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3807};
3808
3809void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3810                                   unsigned &NumNames) const {
3811  Names = GCCRegNames;
3812  NumNames = llvm::array_lengthof(GCCRegNames);
3813}
3814
3815const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3816  { { "a1" }, "r0" },
3817  { { "a2" }, "r1" },
3818  { { "a3" }, "r2" },
3819  { { "a4" }, "r3" },
3820  { { "v1" }, "r4" },
3821  { { "v2" }, "r5" },
3822  { { "v3" }, "r6" },
3823  { { "v4" }, "r7" },
3824  { { "v5" }, "r8" },
3825  { { "v6", "rfp" }, "r9" },
3826  { { "sl" }, "r10" },
3827  { { "fp" }, "r11" },
3828  { { "ip" }, "r12" },
3829  { { "r13" }, "sp" },
3830  { { "r14" }, "lr" },
3831  { { "r15" }, "pc" },
3832  // The S, D and Q registers overlap, but aren't really aliases; we
3833  // don't want to substitute one of these for a different-sized one.
3834};
3835
3836void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3837                                       unsigned &NumAliases) const {
3838  Aliases = GCCRegAliases;
3839  NumAliases = llvm::array_lengthof(GCCRegAliases);
3840}
3841
3842const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3843#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3844#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3845                                              ALL_LANGUAGES },
3846#include "clang/Basic/BuiltinsARM.def"
3847};
3848} // end anonymous namespace.
3849
3850namespace {
3851class DarwinARMTargetInfo :
3852  public DarwinTargetInfo<ARMTargetInfo> {
3853protected:
3854  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3855                            MacroBuilder &Builder) const {
3856    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3857  }
3858
3859public:
3860  DarwinARMTargetInfo(const llvm::Triple &Triple)
3861      : DarwinTargetInfo<ARMTargetInfo>(Triple) {
3862    HasAlignMac68kSupport = true;
3863    // iOS always has 64-bit atomic instructions.
3864    // FIXME: This should be based off of the target features in ARMTargetInfo.
3865    MaxAtomicInlineWidth = 64;
3866
3867    // Darwin on iOS uses a variant of the ARM C++ ABI.
3868    TheCXXABI.set(TargetCXXABI::iOS);
3869  }
3870};
3871} // end anonymous namespace.
3872
3873
3874namespace {
3875// Hexagon abstract base class
3876class HexagonTargetInfo : public TargetInfo {
3877  static const Builtin::Info BuiltinInfo[];
3878  static const char * const GCCRegNames[];
3879  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3880  std::string CPU;
3881public:
3882  HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
3883    BigEndian = false;
3884    DescriptionString = ("e-p:32:32:32-"
3885                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
3886                         "f64:64:64-f32:32:32-a0:0-n32");
3887
3888    // {} in inline assembly are packet specifiers, not assembly variant
3889    // specifiers.
3890    NoAsmVariants = true;
3891  }
3892
3893  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3894                                 unsigned &NumRecords) const {
3895    Records = BuiltinInfo;
3896    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
3897  }
3898
3899  virtual bool validateAsmConstraint(const char *&Name,
3900                                     TargetInfo::ConstraintInfo &Info) const {
3901    return true;
3902  }
3903
3904  virtual void getTargetDefines(const LangOptions &Opts,
3905                                MacroBuilder &Builder) const;
3906
3907  virtual bool hasFeature(StringRef Feature) const {
3908    return Feature == "hexagon";
3909  }
3910
3911  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3912    return TargetInfo::CharPtrBuiltinVaList;
3913  }
3914  virtual void getGCCRegNames(const char * const *&Names,
3915                              unsigned &NumNames) const;
3916  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3917                                unsigned &NumAliases) const;
3918  virtual const char *getClobbers() const {
3919    return "";
3920  }
3921
3922  static const char *getHexagonCPUSuffix(StringRef Name) {
3923    return llvm::StringSwitch<const char*>(Name)
3924      .Case("hexagonv4", "4")
3925      .Case("hexagonv5", "5")
3926      .Default(0);
3927  }
3928
3929  virtual bool setCPU(const std::string &Name) {
3930    if (!getHexagonCPUSuffix(Name))
3931      return false;
3932
3933    CPU = Name;
3934    return true;
3935  }
3936};
3937
3938void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
3939                                MacroBuilder &Builder) const {
3940  Builder.defineMacro("qdsp6");
3941  Builder.defineMacro("__qdsp6", "1");
3942  Builder.defineMacro("__qdsp6__", "1");
3943
3944  Builder.defineMacro("hexagon");
3945  Builder.defineMacro("__hexagon", "1");
3946  Builder.defineMacro("__hexagon__", "1");
3947
3948  if(CPU == "hexagonv1") {
3949    Builder.defineMacro("__HEXAGON_V1__");
3950    Builder.defineMacro("__HEXAGON_ARCH__", "1");
3951    if(Opts.HexagonQdsp6Compat) {
3952      Builder.defineMacro("__QDSP6_V1__");
3953      Builder.defineMacro("__QDSP6_ARCH__", "1");
3954    }
3955  }
3956  else if(CPU == "hexagonv2") {
3957    Builder.defineMacro("__HEXAGON_V2__");
3958    Builder.defineMacro("__HEXAGON_ARCH__", "2");
3959    if(Opts.HexagonQdsp6Compat) {
3960      Builder.defineMacro("__QDSP6_V2__");
3961      Builder.defineMacro("__QDSP6_ARCH__", "2");
3962    }
3963  }
3964  else if(CPU == "hexagonv3") {
3965    Builder.defineMacro("__HEXAGON_V3__");
3966    Builder.defineMacro("__HEXAGON_ARCH__", "3");
3967    if(Opts.HexagonQdsp6Compat) {
3968      Builder.defineMacro("__QDSP6_V3__");
3969      Builder.defineMacro("__QDSP6_ARCH__", "3");
3970    }
3971  }
3972  else if(CPU == "hexagonv4") {
3973    Builder.defineMacro("__HEXAGON_V4__");
3974    Builder.defineMacro("__HEXAGON_ARCH__", "4");
3975    if(Opts.HexagonQdsp6Compat) {
3976      Builder.defineMacro("__QDSP6_V4__");
3977      Builder.defineMacro("__QDSP6_ARCH__", "4");
3978    }
3979  }
3980  else if(CPU == "hexagonv5") {
3981    Builder.defineMacro("__HEXAGON_V5__");
3982    Builder.defineMacro("__HEXAGON_ARCH__", "5");
3983    if(Opts.HexagonQdsp6Compat) {
3984      Builder.defineMacro("__QDSP6_V5__");
3985      Builder.defineMacro("__QDSP6_ARCH__", "5");
3986    }
3987  }
3988}
3989
3990const char * const HexagonTargetInfo::GCCRegNames[] = {
3991  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3992  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3993  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3994  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
3995  "p0", "p1", "p2", "p3",
3996  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
3997};
3998
3999void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4000                                   unsigned &NumNames) const {
4001  Names = GCCRegNames;
4002  NumNames = llvm::array_lengthof(GCCRegNames);
4003}
4004
4005
4006const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4007  { { "sp" }, "r29" },
4008  { { "fp" }, "r30" },
4009  { { "lr" }, "r31" },
4010 };
4011
4012void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4013                                     unsigned &NumAliases) const {
4014  Aliases = GCCRegAliases;
4015  NumAliases = llvm::array_lengthof(GCCRegAliases);
4016}
4017
4018
4019const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4020#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4021#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4022                                              ALL_LANGUAGES },
4023#include "clang/Basic/BuiltinsHexagon.def"
4024};
4025}
4026
4027
4028namespace {
4029// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4030class SparcTargetInfo : public TargetInfo {
4031  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4032  static const char * const GCCRegNames[];
4033  bool SoftFloat;
4034public:
4035  SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
4036
4037  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4038                                 StringRef Name,
4039                                 bool Enabled) const {
4040    if (Name == "soft-float")
4041      Features[Name] = Enabled;
4042    else
4043      return false;
4044
4045    return true;
4046  }
4047  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4048    SoftFloat = false;
4049    for (unsigned i = 0, e = Features.size(); i != e; ++i)
4050      if (Features[i] == "+soft-float")
4051        SoftFloat = true;
4052  }
4053  virtual void getTargetDefines(const LangOptions &Opts,
4054                                MacroBuilder &Builder) const {
4055    DefineStd(Builder, "sparc", Opts);
4056    Builder.defineMacro("__REGISTER_PREFIX__", "");
4057
4058    if (SoftFloat)
4059      Builder.defineMacro("SOFT_FLOAT", "1");
4060  }
4061
4062  virtual bool hasFeature(StringRef Feature) const {
4063    return llvm::StringSwitch<bool>(Feature)
4064             .Case("softfloat", SoftFloat)
4065             .Case("sparc", true)
4066             .Default(false);
4067  }
4068
4069  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4070                                 unsigned &NumRecords) const {
4071    // FIXME: Implement!
4072  }
4073  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4074    return TargetInfo::VoidPtrBuiltinVaList;
4075  }
4076  virtual void getGCCRegNames(const char * const *&Names,
4077                              unsigned &NumNames) const;
4078  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4079                                unsigned &NumAliases) const;
4080  virtual bool validateAsmConstraint(const char *&Name,
4081                                     TargetInfo::ConstraintInfo &info) const {
4082    // FIXME: Implement!
4083    return false;
4084  }
4085  virtual const char *getClobbers() const {
4086    // FIXME: Implement!
4087    return "";
4088  }
4089};
4090
4091const char * const SparcTargetInfo::GCCRegNames[] = {
4092  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4093  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4094  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4095  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4096};
4097
4098void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4099                                     unsigned &NumNames) const {
4100  Names = GCCRegNames;
4101  NumNames = llvm::array_lengthof(GCCRegNames);
4102}
4103
4104const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4105  { { "g0" }, "r0" },
4106  { { "g1" }, "r1" },
4107  { { "g2" }, "r2" },
4108  { { "g3" }, "r3" },
4109  { { "g4" }, "r4" },
4110  { { "g5" }, "r5" },
4111  { { "g6" }, "r6" },
4112  { { "g7" }, "r7" },
4113  { { "o0" }, "r8" },
4114  { { "o1" }, "r9" },
4115  { { "o2" }, "r10" },
4116  { { "o3" }, "r11" },
4117  { { "o4" }, "r12" },
4118  { { "o5" }, "r13" },
4119  { { "o6", "sp" }, "r14" },
4120  { { "o7" }, "r15" },
4121  { { "l0" }, "r16" },
4122  { { "l1" }, "r17" },
4123  { { "l2" }, "r18" },
4124  { { "l3" }, "r19" },
4125  { { "l4" }, "r20" },
4126  { { "l5" }, "r21" },
4127  { { "l6" }, "r22" },
4128  { { "l7" }, "r23" },
4129  { { "i0" }, "r24" },
4130  { { "i1" }, "r25" },
4131  { { "i2" }, "r26" },
4132  { { "i3" }, "r27" },
4133  { { "i4" }, "r28" },
4134  { { "i5" }, "r29" },
4135  { { "i6", "fp" }, "r30" },
4136  { { "i7" }, "r31" },
4137};
4138
4139void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4140                                       unsigned &NumAliases) const {
4141  Aliases = GCCRegAliases;
4142  NumAliases = llvm::array_lengthof(GCCRegAliases);
4143}
4144
4145// SPARC v8 is the 32-bit mode selected by Triple::sparc.
4146class SparcV8TargetInfo : public SparcTargetInfo {
4147public:
4148  SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4149    // FIXME: Support Sparc quad-precision long double?
4150    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4151                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4152  }
4153
4154  virtual void getTargetDefines(const LangOptions &Opts,
4155                                MacroBuilder &Builder) const {
4156    SparcTargetInfo::getTargetDefines(Opts, Builder);
4157    Builder.defineMacro("__sparcv8");
4158  }
4159};
4160
4161// SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4162class SparcV9TargetInfo : public SparcTargetInfo {
4163public:
4164  SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4165    // FIXME: Support Sparc quad-precision long double?
4166    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4167                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4168    // This is an LP64 platform.
4169    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4170
4171    // OpenBSD uses long long for int64_t and intmax_t.
4172    if (getTriple().getOS() == llvm::Triple::OpenBSD) {
4173      IntMaxType = SignedLongLong;
4174      UIntMaxType = UnsignedLongLong;
4175    } else {
4176      IntMaxType = SignedLong;
4177      UIntMaxType = UnsignedLong;
4178    }
4179    Int64Type = IntMaxType;
4180  }
4181
4182  virtual void getTargetDefines(const LangOptions &Opts,
4183                                MacroBuilder &Builder) const {
4184    SparcTargetInfo::getTargetDefines(Opts, Builder);
4185    Builder.defineMacro("__sparcv9");
4186    Builder.defineMacro("__arch64__");
4187    // Solaris and its derivative AuroraUX don't need these variants, but the
4188    // BSDs do.
4189    if (getTriple().getOS() != llvm::Triple::Solaris &&
4190        getTriple().getOS() != llvm::Triple::AuroraUX) {
4191      Builder.defineMacro("__sparc64__");
4192      Builder.defineMacro("__sparc_v9__");
4193      Builder.defineMacro("__sparcv9__");
4194    }
4195  }
4196};
4197
4198} // end anonymous namespace.
4199
4200namespace {
4201class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4202public:
4203  AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
4204      : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
4205    SizeType = UnsignedInt;
4206    PtrDiffType = SignedInt;
4207  }
4208};
4209class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4210public:
4211  SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
4212      : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
4213    SizeType = UnsignedInt;
4214    PtrDiffType = SignedInt;
4215  }
4216};
4217} // end anonymous namespace.
4218
4219namespace {
4220  class SystemZTargetInfo : public TargetInfo {
4221    static const char *const GCCRegNames[];
4222
4223  public:
4224    SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4225      TLSSupported = true;
4226      IntWidth = IntAlign = 32;
4227      LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4228      PointerWidth = PointerAlign = 64;
4229      LongDoubleWidth = 128;
4230      LongDoubleAlign = 64;
4231      LongDoubleFormat = &llvm::APFloat::IEEEquad;
4232      MinGlobalAlign = 16;
4233      DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4234       "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4235      MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4236    }
4237    virtual void getTargetDefines(const LangOptions &Opts,
4238                                  MacroBuilder &Builder) const {
4239      Builder.defineMacro("__s390__");
4240      Builder.defineMacro("__s390x__");
4241      Builder.defineMacro("__zarch__");
4242      Builder.defineMacro("__LONG_DOUBLE_128__");
4243    }
4244    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4245                                   unsigned &NumRecords) const {
4246      // FIXME: Implement.
4247      Records = 0;
4248      NumRecords = 0;
4249    }
4250
4251    virtual void getGCCRegNames(const char *const *&Names,
4252                                unsigned &NumNames) const;
4253    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4254                                  unsigned &NumAliases) const {
4255      // No aliases.
4256      Aliases = 0;
4257      NumAliases = 0;
4258    }
4259    virtual bool validateAsmConstraint(const char *&Name,
4260                                       TargetInfo::ConstraintInfo &info) const;
4261    virtual const char *getClobbers() const {
4262      // FIXME: Is this really right?
4263      return "";
4264    }
4265    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4266      return TargetInfo::SystemZBuiltinVaList;
4267    }
4268    virtual bool setCPU(const std::string &Name) {
4269      bool CPUKnown = llvm::StringSwitch<bool>(Name)
4270        .Case("z10", true)
4271        .Case("z196", true)
4272        .Case("zEC12", true)
4273        .Default(false);
4274
4275      // No need to store the CPU yet.  There aren't any CPU-specific
4276      // macros to define.
4277      return CPUKnown;
4278    }
4279  };
4280
4281  const char *const SystemZTargetInfo::GCCRegNames[] = {
4282    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
4283    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
4284    "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
4285    "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
4286  };
4287
4288  void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4289                                         unsigned &NumNames) const {
4290    Names = GCCRegNames;
4291    NumNames = llvm::array_lengthof(GCCRegNames);
4292  }
4293
4294  bool SystemZTargetInfo::
4295  validateAsmConstraint(const char *&Name,
4296                        TargetInfo::ConstraintInfo &Info) const {
4297    switch (*Name) {
4298    default:
4299      return false;
4300
4301    case 'a': // Address register
4302    case 'd': // Data register (equivalent to 'r')
4303    case 'f': // Floating-point register
4304      Info.setAllowsRegister();
4305      return true;
4306
4307    case 'I': // Unsigned 8-bit constant
4308    case 'J': // Unsigned 12-bit constant
4309    case 'K': // Signed 16-bit constant
4310    case 'L': // Signed 20-bit displacement (on all targets we support)
4311    case 'M': // 0x7fffffff
4312      return true;
4313
4314    case 'Q': // Memory with base and unsigned 12-bit displacement
4315    case 'R': // Likewise, plus an index
4316    case 'S': // Memory with base and signed 20-bit displacement
4317    case 'T': // Likewise, plus an index
4318      Info.setAllowsMemory();
4319      return true;
4320    }
4321  }
4322}
4323
4324namespace {
4325  class MSP430TargetInfo : public TargetInfo {
4326    static const char * const GCCRegNames[];
4327  public:
4328    MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4329      BigEndian = false;
4330      TLSSupported = false;
4331      IntWidth = 16; IntAlign = 16;
4332      LongWidth = 32; LongLongWidth = 64;
4333      LongAlign = LongLongAlign = 16;
4334      PointerWidth = 16; PointerAlign = 16;
4335      SuitableAlign = 16;
4336      SizeType = UnsignedInt;
4337      IntMaxType = SignedLongLong;
4338      UIntMaxType = UnsignedLongLong;
4339      IntPtrType = SignedInt;
4340      PtrDiffType = SignedInt;
4341      SigAtomicType = SignedLong;
4342      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4343   }
4344    virtual void getTargetDefines(const LangOptions &Opts,
4345                                  MacroBuilder &Builder) const {
4346      Builder.defineMacro("MSP430");
4347      Builder.defineMacro("__MSP430__");
4348      // FIXME: defines for different 'flavours' of MCU
4349    }
4350    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4351                                   unsigned &NumRecords) const {
4352     // FIXME: Implement.
4353      Records = 0;
4354      NumRecords = 0;
4355    }
4356    virtual bool hasFeature(StringRef Feature) const {
4357      return Feature == "msp430";
4358    }
4359    virtual void getGCCRegNames(const char * const *&Names,
4360                                unsigned &NumNames) const;
4361    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4362                                  unsigned &NumAliases) const {
4363      // No aliases.
4364      Aliases = 0;
4365      NumAliases = 0;
4366    }
4367    virtual bool validateAsmConstraint(const char *&Name,
4368                                       TargetInfo::ConstraintInfo &info) const {
4369      // No target constraints for now.
4370      return false;
4371    }
4372    virtual const char *getClobbers() const {
4373      // FIXME: Is this really right?
4374      return "";
4375    }
4376    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4377      // FIXME: implement
4378      return TargetInfo::CharPtrBuiltinVaList;
4379   }
4380  };
4381
4382  const char * const MSP430TargetInfo::GCCRegNames[] = {
4383    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4384    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4385  };
4386
4387  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4388                                        unsigned &NumNames) const {
4389    Names = GCCRegNames;
4390    NumNames = llvm::array_lengthof(GCCRegNames);
4391  }
4392}
4393
4394namespace {
4395
4396  // LLVM and Clang cannot be used directly to output native binaries for
4397  // target, but is used to compile C code to llvm bitcode with correct
4398  // type and alignment information.
4399  //
4400  // TCE uses the llvm bitcode as input and uses it for generating customized
4401  // target processor and program binary. TCE co-design environment is
4402  // publicly available in http://tce.cs.tut.fi
4403
4404  static const unsigned TCEOpenCLAddrSpaceMap[] = {
4405      3, // opencl_global
4406      4, // opencl_local
4407      5, // opencl_constant
4408      0, // cuda_device
4409      0, // cuda_constant
4410      0  // cuda_shared
4411  };
4412
4413  class TCETargetInfo : public TargetInfo{
4414  public:
4415    TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4416      TLSSupported = false;
4417      IntWidth = 32;
4418      LongWidth = LongLongWidth = 32;
4419      PointerWidth = 32;
4420      IntAlign = 32;
4421      LongAlign = LongLongAlign = 32;
4422      PointerAlign = 32;
4423      SuitableAlign = 32;
4424      SizeType = UnsignedInt;
4425      IntMaxType = SignedLong;
4426      UIntMaxType = UnsignedLong;
4427      IntPtrType = SignedInt;
4428      PtrDiffType = SignedInt;
4429      FloatWidth = 32;
4430      FloatAlign = 32;
4431      DoubleWidth = 32;
4432      DoubleAlign = 32;
4433      LongDoubleWidth = 32;
4434      LongDoubleAlign = 32;
4435      FloatFormat = &llvm::APFloat::IEEEsingle;
4436      DoubleFormat = &llvm::APFloat::IEEEsingle;
4437      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4438      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4439                          "i16:16:32-i32:32:32-i64:32:32-"
4440                          "f32:32:32-f64:32:32-v64:32:32-"
4441                          "v128:32:32-a0:0:32-n32";
4442      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4443    }
4444
4445    virtual void getTargetDefines(const LangOptions &Opts,
4446                                  MacroBuilder &Builder) const {
4447      DefineStd(Builder, "tce", Opts);
4448      Builder.defineMacro("__TCE__");
4449      Builder.defineMacro("__TCE_V1__");
4450    }
4451    virtual bool hasFeature(StringRef Feature) const {
4452      return Feature == "tce";
4453    }
4454
4455    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4456                                   unsigned &NumRecords) const {}
4457    virtual const char *getClobbers() const {
4458      return "";
4459    }
4460    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4461      return TargetInfo::VoidPtrBuiltinVaList;
4462    }
4463    virtual void getGCCRegNames(const char * const *&Names,
4464                                unsigned &NumNames) const {}
4465    virtual bool validateAsmConstraint(const char *&Name,
4466                                       TargetInfo::ConstraintInfo &info) const {
4467      return true;
4468    }
4469    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4470                                  unsigned &NumAliases) const {}
4471  };
4472}
4473
4474namespace {
4475class MipsTargetInfoBase : public TargetInfo {
4476  static const Builtin::Info BuiltinInfo[];
4477  std::string CPU;
4478  bool IsMips16;
4479  bool IsMicromips;
4480  bool IsSingleFloat;
4481  enum MipsFloatABI {
4482    HardFloat, SoftFloat
4483  } FloatABI;
4484  enum DspRevEnum {
4485    NoDSP, DSP1, DSP2
4486  } DspRev;
4487
4488protected:
4489  std::string ABI;
4490
4491public:
4492  MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
4493                     const std::string &CPUStr)
4494      : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
4495        IsSingleFloat(false), FloatABI(HardFloat), DspRev(NoDSP), ABI(ABIStr) {}
4496
4497  virtual const char *getABI() const { return ABI.c_str(); }
4498  virtual bool setABI(const std::string &Name) = 0;
4499  virtual bool setCPU(const std::string &Name) {
4500    CPU = Name;
4501    return true;
4502  }
4503  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4504    Features[ABI] = true;
4505    Features[CPU] = true;
4506  }
4507
4508  virtual void getTargetDefines(const LangOptions &Opts,
4509                                MacroBuilder &Builder) const {
4510    DefineStd(Builder, "mips", Opts);
4511    Builder.defineMacro("_mips");
4512    Builder.defineMacro("__REGISTER_PREFIX__", "");
4513
4514    switch (FloatABI) {
4515    case HardFloat:
4516      Builder.defineMacro("__mips_hard_float", Twine(1));
4517      break;
4518    case SoftFloat:
4519      Builder.defineMacro("__mips_soft_float", Twine(1));
4520      break;
4521    }
4522
4523    if (IsSingleFloat)
4524      Builder.defineMacro("__mips_single_float", Twine(1));
4525
4526    if (IsMips16)
4527      Builder.defineMacro("__mips16", Twine(1));
4528
4529    if (IsMicromips)
4530      Builder.defineMacro("__mips_micromips", Twine(1));
4531
4532    switch (DspRev) {
4533    default:
4534      break;
4535    case DSP1:
4536      Builder.defineMacro("__mips_dsp_rev", Twine(1));
4537      Builder.defineMacro("__mips_dsp", Twine(1));
4538      break;
4539    case DSP2:
4540      Builder.defineMacro("__mips_dsp_rev", Twine(2));
4541      Builder.defineMacro("__mips_dspr2", Twine(1));
4542      Builder.defineMacro("__mips_dsp", Twine(1));
4543      break;
4544    }
4545
4546    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4547    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4548    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4549
4550    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4551    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4552  }
4553
4554  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4555                                 unsigned &NumRecords) const {
4556    Records = BuiltinInfo;
4557    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4558  }
4559  virtual bool hasFeature(StringRef Feature) const {
4560    return Feature == "mips";
4561  }
4562  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4563    return TargetInfo::VoidPtrBuiltinVaList;
4564  }
4565  virtual void getGCCRegNames(const char * const *&Names,
4566                              unsigned &NumNames) const {
4567    static const char * const GCCRegNames[] = {
4568      // CPU register names
4569      // Must match second column of GCCRegAliases
4570      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4571      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4572      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4573      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4574      // Floating point register names
4575      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4576      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4577      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4578      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4579      // Hi/lo and condition register names
4580      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4581      "$fcc5","$fcc6","$fcc7"
4582    };
4583    Names = GCCRegNames;
4584    NumNames = llvm::array_lengthof(GCCRegNames);
4585  }
4586  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4587                                unsigned &NumAliases) const = 0;
4588  virtual bool validateAsmConstraint(const char *&Name,
4589                                     TargetInfo::ConstraintInfo &Info) const {
4590    switch (*Name) {
4591    default:
4592      return false;
4593
4594    case 'r': // CPU registers.
4595    case 'd': // Equivalent to "r" unless generating MIPS16 code.
4596    case 'y': // Equivalent to "r", backwards compatibility only.
4597    case 'f': // floating-point registers.
4598    case 'c': // $25 for indirect jumps
4599    case 'l': // lo register
4600    case 'x': // hilo register pair
4601      Info.setAllowsRegister();
4602      return true;
4603    case 'R': // An address that can be used in a non-macro load or store
4604      Info.setAllowsMemory();
4605      return true;
4606    }
4607  }
4608
4609  virtual const char *getClobbers() const {
4610    // FIXME: Implement!
4611    return "";
4612  }
4613
4614  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4615                                 StringRef Name,
4616                                 bool Enabled) const {
4617    if (Name == "soft-float" || Name == "single-float" ||
4618        Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4619        Name == "mips32" || Name == "mips32r2" ||
4620        Name == "mips64" || Name == "mips64r2" ||
4621        Name == "mips16" || Name == "micromips" ||
4622        Name == "dsp" || Name == "dspr2") {
4623      Features[Name] = Enabled;
4624      return true;
4625    } else if (Name == "32") {
4626      Features["o32"] = Enabled;
4627      return true;
4628    } else if (Name == "64") {
4629      Features["n64"] = Enabled;
4630      return true;
4631    }
4632    return false;
4633  }
4634
4635  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4636    IsMips16 = false;
4637    IsMicromips = false;
4638    IsSingleFloat = false;
4639    FloatABI = HardFloat;
4640    DspRev = NoDSP;
4641
4642    for (std::vector<std::string>::iterator it = Features.begin(),
4643         ie = Features.end(); it != ie; ++it) {
4644      if (*it == "+single-float")
4645        IsSingleFloat = true;
4646      else if (*it == "+soft-float")
4647        FloatABI = SoftFloat;
4648      else if (*it == "+mips16")
4649        IsMips16 = true;
4650      else if (*it == "+micromips")
4651        IsMicromips = true;
4652      else if (*it == "+dsp")
4653        DspRev = std::max(DspRev, DSP1);
4654      else if (*it == "+dspr2")
4655        DspRev = std::max(DspRev, DSP2);
4656    }
4657
4658    // Remove front-end specific option.
4659    std::vector<std::string>::iterator it =
4660      std::find(Features.begin(), Features.end(), "+soft-float");
4661    if (it != Features.end())
4662      Features.erase(it);
4663  }
4664
4665  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4666    if (RegNo == 0) return 4;
4667    if (RegNo == 1) return 5;
4668    return -1;
4669  }
4670};
4671
4672const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4673#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4674#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4675                                              ALL_LANGUAGES },
4676#include "clang/Basic/BuiltinsMips.def"
4677};
4678
4679class Mips32TargetInfoBase : public MipsTargetInfoBase {
4680public:
4681  Mips32TargetInfoBase(const llvm::Triple &Triple)
4682      : MipsTargetInfoBase(Triple, "o32", "mips32") {
4683    SizeType = UnsignedInt;
4684    PtrDiffType = SignedInt;
4685    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4686  }
4687  virtual bool setABI(const std::string &Name) {
4688    if ((Name == "o32") || (Name == "eabi")) {
4689      ABI = Name;
4690      return true;
4691    } else if (Name == "32") {
4692      ABI = "o32";
4693      return true;
4694    } else
4695      return false;
4696  }
4697  virtual void getTargetDefines(const LangOptions &Opts,
4698                                MacroBuilder &Builder) const {
4699    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4700
4701    if (ABI == "o32") {
4702      Builder.defineMacro("__mips_o32");
4703      Builder.defineMacro("_ABIO32", "1");
4704      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4705    }
4706    else if (ABI == "eabi")
4707      Builder.defineMacro("__mips_eabi");
4708    else
4709      llvm_unreachable("Invalid ABI for Mips32.");
4710  }
4711  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4712                                unsigned &NumAliases) const {
4713    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4714      { { "at" },  "$1" },
4715      { { "v0" },  "$2" },
4716      { { "v1" },  "$3" },
4717      { { "a0" },  "$4" },
4718      { { "a1" },  "$5" },
4719      { { "a2" },  "$6" },
4720      { { "a3" },  "$7" },
4721      { { "t0" },  "$8" },
4722      { { "t1" },  "$9" },
4723      { { "t2" }, "$10" },
4724      { { "t3" }, "$11" },
4725      { { "t4" }, "$12" },
4726      { { "t5" }, "$13" },
4727      { { "t6" }, "$14" },
4728      { { "t7" }, "$15" },
4729      { { "s0" }, "$16" },
4730      { { "s1" }, "$17" },
4731      { { "s2" }, "$18" },
4732      { { "s3" }, "$19" },
4733      { { "s4" }, "$20" },
4734      { { "s5" }, "$21" },
4735      { { "s6" }, "$22" },
4736      { { "s7" }, "$23" },
4737      { { "t8" }, "$24" },
4738      { { "t9" }, "$25" },
4739      { { "k0" }, "$26" },
4740      { { "k1" }, "$27" },
4741      { { "gp" }, "$28" },
4742      { { "sp","$sp" }, "$29" },
4743      { { "fp","$fp" }, "$30" },
4744      { { "ra" }, "$31" }
4745    };
4746    Aliases = GCCRegAliases;
4747    NumAliases = llvm::array_lengthof(GCCRegAliases);
4748  }
4749};
4750
4751class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4752public:
4753  Mips32EBTargetInfo(const llvm::Triple &Triple)
4754      : Mips32TargetInfoBase(Triple) {
4755    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4756                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4757  }
4758  virtual void getTargetDefines(const LangOptions &Opts,
4759                                MacroBuilder &Builder) const {
4760    DefineStd(Builder, "MIPSEB", Opts);
4761    Builder.defineMacro("_MIPSEB");
4762    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4763  }
4764};
4765
4766class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4767public:
4768  Mips32ELTargetInfo(const llvm::Triple &Triple)
4769      : Mips32TargetInfoBase(Triple) {
4770    BigEndian = false;
4771    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4772                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4773  }
4774  virtual void getTargetDefines(const LangOptions &Opts,
4775                                MacroBuilder &Builder) const {
4776    DefineStd(Builder, "MIPSEL", Opts);
4777    Builder.defineMacro("_MIPSEL");
4778    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4779  }
4780};
4781
4782class Mips64TargetInfoBase : public MipsTargetInfoBase {
4783  virtual void SetDescriptionString(const std::string &Name) = 0;
4784public:
4785  Mips64TargetInfoBase(const llvm::Triple &Triple)
4786      : MipsTargetInfoBase(Triple, "n64", "mips64") {
4787    LongWidth = LongAlign = 64;
4788    PointerWidth = PointerAlign = 64;
4789    LongDoubleWidth = LongDoubleAlign = 128;
4790    LongDoubleFormat = &llvm::APFloat::IEEEquad;
4791    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4792      LongDoubleWidth = LongDoubleAlign = 64;
4793      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4794    }
4795    SuitableAlign = 128;
4796    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4797  }
4798  virtual bool setABI(const std::string &Name) {
4799    SetDescriptionString(Name);
4800    if (Name == "n32") {
4801      LongWidth = LongAlign = 32;
4802      PointerWidth = PointerAlign = 32;
4803      ABI = Name;
4804      return true;
4805    } else if (Name == "n64") {
4806      ABI = Name;
4807      return true;
4808    } else if (Name == "64") {
4809      ABI = "n64";
4810      return true;
4811    } else
4812      return false;
4813  }
4814  virtual void getTargetDefines(const LangOptions &Opts,
4815                                MacroBuilder &Builder) const {
4816    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4817
4818    Builder.defineMacro("__mips64");
4819    Builder.defineMacro("__mips64__");
4820
4821    if (ABI == "n32") {
4822      Builder.defineMacro("__mips_n32");
4823      Builder.defineMacro("_ABIN32", "2");
4824      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4825    }
4826    else if (ABI == "n64") {
4827      Builder.defineMacro("__mips_n64");
4828      Builder.defineMacro("_ABI64", "3");
4829      Builder.defineMacro("_MIPS_SIM", "_ABI64");
4830    }
4831    else
4832      llvm_unreachable("Invalid ABI for Mips64.");
4833  }
4834  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4835                                unsigned &NumAliases) const {
4836    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4837      { { "at" },  "$1" },
4838      { { "v0" },  "$2" },
4839      { { "v1" },  "$3" },
4840      { { "a0" },  "$4" },
4841      { { "a1" },  "$5" },
4842      { { "a2" },  "$6" },
4843      { { "a3" },  "$7" },
4844      { { "a4" },  "$8" },
4845      { { "a5" },  "$9" },
4846      { { "a6" }, "$10" },
4847      { { "a7" }, "$11" },
4848      { { "t0" }, "$12" },
4849      { { "t1" }, "$13" },
4850      { { "t2" }, "$14" },
4851      { { "t3" }, "$15" },
4852      { { "s0" }, "$16" },
4853      { { "s1" }, "$17" },
4854      { { "s2" }, "$18" },
4855      { { "s3" }, "$19" },
4856      { { "s4" }, "$20" },
4857      { { "s5" }, "$21" },
4858      { { "s6" }, "$22" },
4859      { { "s7" }, "$23" },
4860      { { "t8" }, "$24" },
4861      { { "t9" }, "$25" },
4862      { { "k0" }, "$26" },
4863      { { "k1" }, "$27" },
4864      { { "gp" }, "$28" },
4865      { { "sp","$sp" }, "$29" },
4866      { { "fp","$fp" }, "$30" },
4867      { { "ra" }, "$31" }
4868    };
4869    Aliases = GCCRegAliases;
4870    NumAliases = llvm::array_lengthof(GCCRegAliases);
4871  }
4872};
4873
4874class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4875  virtual void SetDescriptionString(const std::string &Name) {
4876    // Change DescriptionString only if ABI is n32.
4877    if (Name == "n32")
4878      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4879                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4880                          "v64:64:64-n32:64-S128";
4881  }
4882public:
4883  Mips64EBTargetInfo(const llvm::Triple &Triple)
4884      : Mips64TargetInfoBase(Triple) {
4885    // Default ABI is n64.
4886    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4887                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4888                        "v64:64:64-n32:64-S128";
4889  }
4890  virtual void getTargetDefines(const LangOptions &Opts,
4891                                MacroBuilder &Builder) const {
4892    DefineStd(Builder, "MIPSEB", Opts);
4893    Builder.defineMacro("_MIPSEB");
4894    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4895  }
4896};
4897
4898class Mips64ELTargetInfo : public Mips64TargetInfoBase {
4899  virtual void SetDescriptionString(const std::string &Name) {
4900    // Change DescriptionString only if ABI is n32.
4901    if (Name == "n32")
4902      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4903                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
4904                          "-v64:64:64-n32:64-S128";
4905  }
4906public:
4907  Mips64ELTargetInfo(const llvm::Triple &Triple)
4908      : Mips64TargetInfoBase(Triple) {
4909    // Default ABI is n64.
4910    BigEndian = false;
4911    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4912                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4913                        "v64:64:64-n32:64-S128";
4914  }
4915  virtual void getTargetDefines(const LangOptions &Opts,
4916                                MacroBuilder &Builder) const {
4917    DefineStd(Builder, "MIPSEL", Opts);
4918    Builder.defineMacro("_MIPSEL");
4919    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4920  }
4921};
4922} // end anonymous namespace.
4923
4924namespace {
4925class PNaClTargetInfo : public TargetInfo {
4926public:
4927  PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4928    BigEndian = false;
4929    this->UserLabelPrefix = "";
4930    this->LongAlign = 32;
4931    this->LongWidth = 32;
4932    this->PointerAlign = 32;
4933    this->PointerWidth = 32;
4934    this->IntMaxType = TargetInfo::SignedLongLong;
4935    this->UIntMaxType = TargetInfo::UnsignedLongLong;
4936    this->Int64Type = TargetInfo::SignedLongLong;
4937    this->DoubleAlign = 64;
4938    this->LongDoubleWidth = 64;
4939    this->LongDoubleAlign = 64;
4940    this->SizeType = TargetInfo::UnsignedInt;
4941    this->PtrDiffType = TargetInfo::SignedInt;
4942    this->IntPtrType = TargetInfo::SignedInt;
4943    this->RegParmMax = 0; // Disallow regparm
4944    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4945                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
4946  }
4947
4948  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4949  }
4950  virtual void getArchDefines(const LangOptions &Opts,
4951                              MacroBuilder &Builder) const {
4952    Builder.defineMacro("__le32__");
4953    Builder.defineMacro("__pnacl__");
4954  }
4955  virtual void getTargetDefines(const LangOptions &Opts,
4956                                MacroBuilder &Builder) const {
4957    Builder.defineMacro("__LITTLE_ENDIAN__");
4958    getArchDefines(Opts, Builder);
4959  }
4960  virtual bool hasFeature(StringRef Feature) const {
4961    return Feature == "pnacl";
4962  }
4963  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4964                                 unsigned &NumRecords) const {
4965  }
4966  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4967    return TargetInfo::PNaClABIBuiltinVaList;
4968  }
4969  virtual void getGCCRegNames(const char * const *&Names,
4970                              unsigned &NumNames) const;
4971  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4972                                unsigned &NumAliases) const;
4973  virtual bool validateAsmConstraint(const char *&Name,
4974                                     TargetInfo::ConstraintInfo &Info) const {
4975    return false;
4976  }
4977
4978  virtual const char *getClobbers() const {
4979    return "";
4980  }
4981};
4982
4983void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
4984                                     unsigned &NumNames) const {
4985  Names = NULL;
4986  NumNames = 0;
4987}
4988
4989void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4990                                       unsigned &NumAliases) const {
4991  Aliases = NULL;
4992  NumAliases = 0;
4993}
4994} // end anonymous namespace.
4995
4996namespace {
4997  static const unsigned SPIRAddrSpaceMap[] = {
4998    1,    // opencl_global
4999    3,    // opencl_local
5000    2,    // opencl_constant
5001    0,    // cuda_device
5002    0,    // cuda_constant
5003    0     // cuda_shared
5004  };
5005  class SPIRTargetInfo : public TargetInfo {
5006    static const char * const GCCRegNames[];
5007    static const Builtin::Info BuiltinInfo[];
5008    std::vector<StringRef> AvailableFeatures;
5009  public:
5010    SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5011      assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5012        "SPIR target must use unknown OS");
5013      assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5014        "SPIR target must use unknown environment type");
5015      BigEndian = false;
5016      TLSSupported = false;
5017      LongWidth = LongAlign = 64;
5018      AddrSpaceMap = &SPIRAddrSpaceMap;
5019      // Define available target features
5020      // These must be defined in sorted order!
5021      NoAsmVariants = true;
5022    }
5023    virtual void getTargetDefines(const LangOptions &Opts,
5024                                  MacroBuilder &Builder) const {
5025      DefineStd(Builder, "SPIR", Opts);
5026    }
5027    virtual bool hasFeature(StringRef Feature) const {
5028      return Feature == "spir";
5029    }
5030
5031    virtual void getTargetBuiltins(const Builtin::Info *&Records,
5032                                   unsigned &NumRecords) const {}
5033    virtual const char *getClobbers() const {
5034      return "";
5035    }
5036    virtual void getGCCRegNames(const char * const *&Names,
5037                                unsigned &NumNames) const {}
5038    virtual bool validateAsmConstraint(const char *&Name,
5039                                       TargetInfo::ConstraintInfo &info) const {
5040      return true;
5041    }
5042    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5043                                  unsigned &NumAliases) const {}
5044    virtual BuiltinVaListKind getBuiltinVaListKind() const {
5045      return TargetInfo::VoidPtrBuiltinVaList;
5046    }
5047  };
5048
5049
5050  class SPIR32TargetInfo : public SPIRTargetInfo {
5051  public:
5052    SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5053      PointerWidth = PointerAlign = 32;
5054      SizeType     = TargetInfo::UnsignedInt;
5055      PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5056      DescriptionString
5057        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5058          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5059          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5060          "v512:512:512-v1024:1024:1024";
5061    }
5062    virtual void getTargetDefines(const LangOptions &Opts,
5063                                  MacroBuilder &Builder) const {
5064      DefineStd(Builder, "SPIR32", Opts);
5065    }
5066  };
5067
5068  class SPIR64TargetInfo : public SPIRTargetInfo {
5069  public:
5070    SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5071      PointerWidth = PointerAlign = 64;
5072      SizeType     = TargetInfo::UnsignedLong;
5073      PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5074      DescriptionString
5075        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5076          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5077          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5078          "v512:512:512-v1024:1024:1024";
5079    }
5080    virtual void getTargetDefines(const LangOptions &Opts,
5081                                  MacroBuilder &Builder) const {
5082      DefineStd(Builder, "SPIR64", Opts);
5083    }
5084  };
5085}
5086
5087
5088//===----------------------------------------------------------------------===//
5089// Driver code
5090//===----------------------------------------------------------------------===//
5091
5092static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
5093  llvm::Triple::OSType os = Triple.getOS();
5094
5095  switch (Triple.getArch()) {
5096  default:
5097    return NULL;
5098
5099  case llvm::Triple::hexagon:
5100    return new HexagonTargetInfo(Triple);
5101
5102  case llvm::Triple::aarch64:
5103    switch (os) {
5104    case llvm::Triple::Linux:
5105      return new LinuxTargetInfo<AArch64TargetInfo>(Triple);
5106    default:
5107      return new AArch64TargetInfo(Triple);
5108    }
5109
5110  case llvm::Triple::arm:
5111  case llvm::Triple::thumb:
5112    if (Triple.isOSDarwin())
5113      return new DarwinARMTargetInfo(Triple);
5114
5115    switch (os) {
5116    case llvm::Triple::Linux:
5117      return new LinuxTargetInfo<ARMTargetInfo>(Triple);
5118    case llvm::Triple::FreeBSD:
5119      return new FreeBSDTargetInfo<ARMTargetInfo>(Triple);
5120    case llvm::Triple::NetBSD:
5121      return new NetBSDTargetInfo<ARMTargetInfo>(Triple);
5122    case llvm::Triple::OpenBSD:
5123      return new OpenBSDTargetInfo<ARMTargetInfo>(Triple);
5124    case llvm::Triple::Bitrig:
5125      return new BitrigTargetInfo<ARMTargetInfo>(Triple);
5126    case llvm::Triple::RTEMS:
5127      return new RTEMSTargetInfo<ARMTargetInfo>(Triple);
5128    case llvm::Triple::NaCl:
5129      return new NaClTargetInfo<ARMTargetInfo>(Triple);
5130    default:
5131      return new ARMTargetInfo(Triple);
5132    }
5133
5134  case llvm::Triple::msp430:
5135    return new MSP430TargetInfo(Triple);
5136
5137  case llvm::Triple::mips:
5138    switch (os) {
5139    case llvm::Triple::Linux:
5140      return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
5141    case llvm::Triple::RTEMS:
5142      return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
5143    case llvm::Triple::FreeBSD:
5144      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5145    case llvm::Triple::NetBSD:
5146      return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5147    default:
5148      return new Mips32EBTargetInfo(Triple);
5149    }
5150
5151  case llvm::Triple::mipsel:
5152    switch (os) {
5153    case llvm::Triple::Linux:
5154      return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
5155    case llvm::Triple::RTEMS:
5156      return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
5157    case llvm::Triple::FreeBSD:
5158      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5159    case llvm::Triple::NetBSD:
5160      return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5161    default:
5162      return new Mips32ELTargetInfo(Triple);
5163    }
5164
5165  case llvm::Triple::mips64:
5166    switch (os) {
5167    case llvm::Triple::Linux:
5168      return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
5169    case llvm::Triple::RTEMS:
5170      return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
5171    case llvm::Triple::FreeBSD:
5172      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5173    case llvm::Triple::NetBSD:
5174      return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5175    case llvm::Triple::OpenBSD:
5176      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5177    default:
5178      return new Mips64EBTargetInfo(Triple);
5179    }
5180
5181  case llvm::Triple::mips64el:
5182    switch (os) {
5183    case llvm::Triple::Linux:
5184      return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
5185    case llvm::Triple::RTEMS:
5186      return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
5187    case llvm::Triple::FreeBSD:
5188      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5189    case llvm::Triple::NetBSD:
5190      return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5191    case llvm::Triple::OpenBSD:
5192      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5193    default:
5194      return new Mips64ELTargetInfo(Triple);
5195    }
5196
5197  case llvm::Triple::le32:
5198    switch (os) {
5199      case llvm::Triple::NaCl:
5200        return new NaClTargetInfo<PNaClTargetInfo>(Triple);
5201      default:
5202        return NULL;
5203    }
5204
5205  case llvm::Triple::ppc:
5206    if (Triple.isOSDarwin())
5207      return new DarwinPPC32TargetInfo(Triple);
5208    switch (os) {
5209    case llvm::Triple::Linux:
5210      return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
5211    case llvm::Triple::FreeBSD:
5212      return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
5213    case llvm::Triple::NetBSD:
5214      return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
5215    case llvm::Triple::OpenBSD:
5216      return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
5217    case llvm::Triple::RTEMS:
5218      return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
5219    default:
5220      return new PPC32TargetInfo(Triple);
5221    }
5222
5223  case llvm::Triple::ppc64:
5224    if (Triple.isOSDarwin())
5225      return new DarwinPPC64TargetInfo(Triple);
5226    switch (os) {
5227    case llvm::Triple::Linux:
5228      return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
5229    case llvm::Triple::Lv2:
5230      return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
5231    case llvm::Triple::FreeBSD:
5232      return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
5233    case llvm::Triple::NetBSD:
5234      return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
5235    default:
5236      return new PPC64TargetInfo(Triple);
5237    }
5238
5239  case llvm::Triple::nvptx:
5240    return new NVPTX32TargetInfo(Triple);
5241  case llvm::Triple::nvptx64:
5242    return new NVPTX64TargetInfo(Triple);
5243
5244  case llvm::Triple::r600:
5245    return new R600TargetInfo(Triple);
5246
5247  case llvm::Triple::sparc:
5248    switch (os) {
5249    case llvm::Triple::Linux:
5250      return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
5251    case llvm::Triple::AuroraUX:
5252      return new AuroraUXSparcV8TargetInfo(Triple);
5253    case llvm::Triple::Solaris:
5254      return new SolarisSparcV8TargetInfo(Triple);
5255    case llvm::Triple::NetBSD:
5256      return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
5257    case llvm::Triple::OpenBSD:
5258      return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
5259    case llvm::Triple::RTEMS:
5260      return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
5261    default:
5262      return new SparcV8TargetInfo(Triple);
5263    }
5264
5265  case llvm::Triple::sparcv9:
5266    switch (os) {
5267    case llvm::Triple::Linux:
5268      return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
5269    case llvm::Triple::AuroraUX:
5270      return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple);
5271    case llvm::Triple::Solaris:
5272      return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
5273    case llvm::Triple::NetBSD:
5274      return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
5275    case llvm::Triple::OpenBSD:
5276      return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
5277    case llvm::Triple::FreeBSD:
5278      return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
5279    default:
5280      return new SparcV9TargetInfo(Triple);
5281    }
5282
5283  case llvm::Triple::systemz:
5284    switch (os) {
5285    case llvm::Triple::Linux:
5286      return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
5287    default:
5288      return new SystemZTargetInfo(Triple);
5289    }
5290
5291  case llvm::Triple::tce:
5292    return new TCETargetInfo(Triple);
5293
5294  case llvm::Triple::x86:
5295    if (Triple.isOSDarwin())
5296      return new DarwinI386TargetInfo(Triple);
5297
5298    switch (os) {
5299    case llvm::Triple::AuroraUX:
5300      return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple);
5301    case llvm::Triple::Linux:
5302      return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
5303    case llvm::Triple::DragonFly:
5304      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
5305    case llvm::Triple::NetBSD:
5306      return new NetBSDI386TargetInfo(Triple);
5307    case llvm::Triple::OpenBSD:
5308      return new OpenBSDI386TargetInfo(Triple);
5309    case llvm::Triple::Bitrig:
5310      return new BitrigI386TargetInfo(Triple);
5311    case llvm::Triple::FreeBSD:
5312      return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
5313    case llvm::Triple::Minix:
5314      return new MinixTargetInfo<X86_32TargetInfo>(Triple);
5315    case llvm::Triple::Solaris:
5316      return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
5317    case llvm::Triple::Cygwin:
5318      return new CygwinX86_32TargetInfo(Triple);
5319    case llvm::Triple::MinGW32:
5320      return new MinGWX86_32TargetInfo(Triple);
5321    case llvm::Triple::Win32:
5322      return new VisualStudioWindowsX86_32TargetInfo(Triple);
5323    case llvm::Triple::Haiku:
5324      return new HaikuX86_32TargetInfo(Triple);
5325    case llvm::Triple::RTEMS:
5326      return new RTEMSX86_32TargetInfo(Triple);
5327    case llvm::Triple::NaCl:
5328      return new NaClTargetInfo<X86_32TargetInfo>(Triple);
5329    default:
5330      return new X86_32TargetInfo(Triple);
5331    }
5332
5333  case llvm::Triple::x86_64:
5334    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5335      return new DarwinX86_64TargetInfo(Triple);
5336
5337    switch (os) {
5338    case llvm::Triple::AuroraUX:
5339      return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple);
5340    case llvm::Triple::Linux:
5341      return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
5342    case llvm::Triple::DragonFly:
5343      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
5344    case llvm::Triple::NetBSD:
5345      return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
5346    case llvm::Triple::OpenBSD:
5347      return new OpenBSDX86_64TargetInfo(Triple);
5348    case llvm::Triple::Bitrig:
5349      return new BitrigX86_64TargetInfo(Triple);
5350    case llvm::Triple::FreeBSD:
5351      return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
5352    case llvm::Triple::Solaris:
5353      return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
5354    case llvm::Triple::MinGW32:
5355      return new MinGWX86_64TargetInfo(Triple);
5356    case llvm::Triple::Win32:   // This is what Triple.h supports now.
5357      return new VisualStudioWindowsX86_64TargetInfo(Triple);
5358    case llvm::Triple::NaCl:
5359      return new NaClTargetInfo<X86_64TargetInfo>(Triple);
5360    default:
5361      return new X86_64TargetInfo(Triple);
5362    }
5363
5364    case llvm::Triple::spir: {
5365      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5366          Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5367        return NULL;
5368      return new SPIR32TargetInfo(Triple);
5369    }
5370    case llvm::Triple::spir64: {
5371      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5372          Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5373        return NULL;
5374      return new SPIR64TargetInfo(Triple);
5375    }
5376  }
5377}
5378
5379/// CreateTargetInfo - Return the target info object for the specified target
5380/// triple.
5381TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5382                                         TargetOptions *Opts) {
5383  llvm::Triple Triple(Opts->Triple);
5384
5385  // Construct the target
5386  OwningPtr<TargetInfo> Target(AllocateTarget(Triple));
5387  if (!Target) {
5388    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5389    return 0;
5390  }
5391  Target->setTargetOpts(Opts);
5392
5393  // Set the target CPU if specified.
5394  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5395    Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5396    return 0;
5397  }
5398
5399  // Set the target ABI if specified.
5400  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5401    Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5402    return 0;
5403  }
5404
5405  // Set the target C++ ABI.
5406  if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5407    Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5408    return 0;
5409  }
5410
5411  // Compute the default target features, we need the target to handle this
5412  // because features may have dependencies on one another.
5413  llvm::StringMap<bool> Features;
5414  Target->getDefaultFeatures(Features);
5415
5416  // Apply the user specified deltas.
5417  // First the enables.
5418  for (std::vector<std::string>::const_iterator
5419         it = Opts->FeaturesAsWritten.begin(),
5420         ie = Opts->FeaturesAsWritten.end();
5421       it != ie; ++it) {
5422    const char *Name = it->c_str();
5423
5424    if (Name[0] != '+')
5425      continue;
5426
5427    // Apply the feature via the target.
5428    if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5429      Diags.Report(diag::err_target_invalid_feature) << Name;
5430      return 0;
5431    }
5432  }
5433
5434  // Then the disables.
5435  for (std::vector<std::string>::const_iterator
5436         it = Opts->FeaturesAsWritten.begin(),
5437         ie = Opts->FeaturesAsWritten.end();
5438       it != ie; ++it) {
5439    const char *Name = it->c_str();
5440
5441    if (Name[0] == '+')
5442      continue;
5443
5444    // Apply the feature via the target.
5445    if (Name[0] != '-' ||
5446        !Target->setFeatureEnabled(Features, Name + 1, false)) {
5447      Diags.Report(diag::err_target_invalid_feature) << Name;
5448      return 0;
5449    }
5450  }
5451
5452  // Add the features to the compile options.
5453  //
5454  // FIXME: If we are completely confident that we have the right set, we only
5455  // need to pass the minuses.
5456  Opts->Features.clear();
5457  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5458         ie = Features.end(); it != ie; ++it)
5459    Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5460  Target->HandleTargetFeatures(Opts->Features);
5461
5462  return Target.take();
5463}
5464