Targets.cpp revision 9df0823a4b82794f573e333115ad4dfff3ab0a34 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "5621");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.getOS() == llvm::Triple::IOS) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else {
153    // Note that the Driver allows versions which aren't representable in the
154    // define (because we only get a single digit for the minor and micro
155    // revision numbers). So, we limit them to the maximum representable
156    // version.
157    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159    char Str[5];
160    Str[0] = '0' + (Maj / 10);
161    Str[1] = '0' + (Maj % 10);
162    Str[2] = '0' + std::min(Min, 9U);
163    Str[3] = '0' + std::min(Rev, 9U);
164    Str[4] = '\0';
165    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166  }
167
168  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169}
170
171namespace {
172template<typename Target>
173class DarwinTargetInfo : public OSTargetInfo<Target> {
174protected:
175  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                            MacroBuilder &Builder) const {
177    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                     this->PlatformMinVersion);
179  }
180
181public:
182  DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
183    this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
184    this->MCountName = "\01mcount";
185  }
186
187  virtual std::string isValidSectionSpecifier(StringRef SR) const {
188    // Let MCSectionMachO validate this.
189    StringRef Segment, Section;
190    unsigned TAA, StubSize;
191    bool HasTAA;
192    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
193                                                       TAA, HasTAA, StubSize);
194  }
195
196  virtual const char *getStaticInitSectionSpecifier() const {
197    // FIXME: We should return 0 when building kexts.
198    return "__TEXT,__StaticInit,regular,pure_instructions";
199  }
200
201  /// Darwin does not support protected visibility.  Darwin's "default"
202  /// is very similar to ELF's "protected";  Darwin requires a "weak"
203  /// attribute on declarations that can be dynamically replaced.
204  virtual bool hasProtectedVisibility() const {
205    return false;
206  }
207};
208
209
210// DragonFlyBSD Target
211template<typename Target>
212class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
213protected:
214  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
215                            MacroBuilder &Builder) const {
216    // DragonFly defines; list based off of gcc output
217    Builder.defineMacro("__DragonFly__");
218    Builder.defineMacro("__DragonFly_cc_version", "100001");
219    Builder.defineMacro("__ELF__");
220    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
221    Builder.defineMacro("__tune_i386__");
222    DefineStd(Builder, "unix", Opts);
223  }
224public:
225  DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
226      : OSTargetInfo<Target>(Triple) {
227    this->UserLabelPrefix = "";
228
229    switch (Triple.getArch()) {
230    default:
231    case llvm::Triple::x86:
232    case llvm::Triple::x86_64:
233      this->MCountName = ".mcount";
234      break;
235    }
236  }
237};
238
239// FreeBSD Target
240template<typename Target>
241class FreeBSDTargetInfo : public OSTargetInfo<Target> {
242protected:
243  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
244                            MacroBuilder &Builder) const {
245    // FreeBSD defines; list based off of gcc output
246
247    unsigned Release = Triple.getOSMajorVersion();
248    if (Release == 0U)
249      Release = 8;
250
251    Builder.defineMacro("__FreeBSD__", Twine(Release));
252    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
253    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
254    DefineStd(Builder, "unix", Opts);
255    Builder.defineMacro("__ELF__");
256  }
257public:
258  FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
259    this->UserLabelPrefix = "";
260
261    switch (Triple.getArch()) {
262    default:
263    case llvm::Triple::x86:
264    case llvm::Triple::x86_64:
265      this->MCountName = ".mcount";
266      break;
267    case llvm::Triple::mips:
268    case llvm::Triple::mipsel:
269    case llvm::Triple::ppc:
270    case llvm::Triple::ppc64:
271      this->MCountName = "_mcount";
272      break;
273    case llvm::Triple::arm:
274      this->MCountName = "__mcount";
275      break;
276    }
277  }
278};
279
280// Minix Target
281template<typename Target>
282class MinixTargetInfo : public OSTargetInfo<Target> {
283protected:
284  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
285                            MacroBuilder &Builder) const {
286    // Minix defines
287
288    Builder.defineMacro("__minix", "3");
289    Builder.defineMacro("_EM_WSIZE", "4");
290    Builder.defineMacro("_EM_PSIZE", "4");
291    Builder.defineMacro("_EM_SSIZE", "2");
292    Builder.defineMacro("_EM_LSIZE", "4");
293    Builder.defineMacro("_EM_FSIZE", "4");
294    Builder.defineMacro("_EM_DSIZE", "8");
295    Builder.defineMacro("__ELF__");
296    DefineStd(Builder, "unix", Opts);
297  }
298public:
299  MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
300    this->UserLabelPrefix = "";
301  }
302};
303
304// Linux target
305template<typename Target>
306class LinuxTargetInfo : public OSTargetInfo<Target> {
307protected:
308  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
309                            MacroBuilder &Builder) const {
310    // Linux defines; list based off of gcc output
311    DefineStd(Builder, "unix", Opts);
312    DefineStd(Builder, "linux", Opts);
313    Builder.defineMacro("__gnu_linux__");
314    Builder.defineMacro("__ELF__");
315    if (Triple.getEnvironment() == llvm::Triple::Android)
316      Builder.defineMacro("__ANDROID__", "1");
317    if (Opts.POSIXThreads)
318      Builder.defineMacro("_REENTRANT");
319    if (Opts.CPlusPlus)
320      Builder.defineMacro("_GNU_SOURCE");
321  }
322public:
323  LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
324    this->UserLabelPrefix = "";
325    this->WIntType = TargetInfo::UnsignedInt;
326  }
327
328  virtual const char *getStaticInitSectionSpecifier() const {
329    return ".text.startup";
330  }
331};
332
333// NetBSD Target
334template<typename Target>
335class NetBSDTargetInfo : public OSTargetInfo<Target> {
336protected:
337  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
338                            MacroBuilder &Builder) const {
339    // NetBSD defines; list based off of gcc output
340    Builder.defineMacro("__NetBSD__");
341    Builder.defineMacro("__unix__");
342    Builder.defineMacro("__ELF__");
343    if (Opts.POSIXThreads)
344      Builder.defineMacro("_POSIX_THREADS");
345  }
346public:
347  NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
348    this->UserLabelPrefix = "";
349  }
350};
351
352// OpenBSD Target
353template<typename Target>
354class OpenBSDTargetInfo : public OSTargetInfo<Target> {
355protected:
356  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
357                            MacroBuilder &Builder) const {
358    // OpenBSD defines; list based off of gcc output
359
360    Builder.defineMacro("__OpenBSD__");
361    DefineStd(Builder, "unix", Opts);
362    Builder.defineMacro("__ELF__");
363    if (Opts.POSIXThreads)
364      Builder.defineMacro("_REENTRANT");
365  }
366public:
367  OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
368    this->UserLabelPrefix = "";
369    this->TLSSupported = false;
370
371      switch (Triple.getArch()) {
372        default:
373        case llvm::Triple::x86:
374        case llvm::Triple::x86_64:
375        case llvm::Triple::arm:
376        case llvm::Triple::sparc:
377          this->MCountName = "__mcount";
378          break;
379        case llvm::Triple::mips64:
380        case llvm::Triple::mips64el:
381        case llvm::Triple::ppc:
382        case llvm::Triple::sparcv9:
383          this->MCountName = "_mcount";
384          break;
385      }
386  }
387};
388
389// Bitrig Target
390template<typename Target>
391class BitrigTargetInfo : public OSTargetInfo<Target> {
392protected:
393  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
394                            MacroBuilder &Builder) const {
395    // Bitrig defines; list based off of gcc output
396
397    Builder.defineMacro("__Bitrig__");
398    DefineStd(Builder, "unix", Opts);
399    Builder.defineMacro("__ELF__");
400    if (Opts.POSIXThreads)
401      Builder.defineMacro("_REENTRANT");
402  }
403public:
404  BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
405    this->UserLabelPrefix = "";
406    this->TLSSupported = false;
407    this->MCountName = "__mcount";
408  }
409};
410
411// PSP Target
412template<typename Target>
413class PSPTargetInfo : public OSTargetInfo<Target> {
414protected:
415  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
416                            MacroBuilder &Builder) const {
417    // PSP defines; list based on the output of the pspdev gcc toolchain.
418    Builder.defineMacro("PSP");
419    Builder.defineMacro("_PSP");
420    Builder.defineMacro("__psp__");
421    Builder.defineMacro("__ELF__");
422  }
423public:
424  PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
425    this->UserLabelPrefix = "";
426  }
427};
428
429// PS3 PPU Target
430template<typename Target>
431class PS3PPUTargetInfo : public OSTargetInfo<Target> {
432protected:
433  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
434                            MacroBuilder &Builder) const {
435    // PS3 PPU defines.
436    Builder.defineMacro("__PPC__");
437    Builder.defineMacro("__PPU__");
438    Builder.defineMacro("__CELLOS_LV2__");
439    Builder.defineMacro("__ELF__");
440    Builder.defineMacro("__LP32__");
441    Builder.defineMacro("_ARCH_PPC64");
442    Builder.defineMacro("__powerpc64__");
443  }
444public:
445  PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
446    this->UserLabelPrefix = "";
447    this->LongWidth = this->LongAlign = 32;
448    this->PointerWidth = this->PointerAlign = 32;
449    this->IntMaxType = TargetInfo::SignedLongLong;
450    this->UIntMaxType = TargetInfo::UnsignedLongLong;
451    this->Int64Type = TargetInfo::SignedLongLong;
452    this->SizeType = TargetInfo::UnsignedInt;
453    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
454                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
455  }
456};
457
458// FIXME: Need a real SPU target.
459// PS3 SPU Target
460template<typename Target>
461class PS3SPUTargetInfo : public OSTargetInfo<Target> {
462protected:
463  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
464                            MacroBuilder &Builder) const {
465    // PS3 PPU defines.
466    Builder.defineMacro("__SPU__");
467    Builder.defineMacro("__ELF__");
468  }
469public:
470  PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
471    this->UserLabelPrefix = "";
472  }
473};
474
475// AuroraUX target
476template<typename Target>
477class AuroraUXTargetInfo : public OSTargetInfo<Target> {
478protected:
479  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
480                            MacroBuilder &Builder) const {
481    DefineStd(Builder, "sun", Opts);
482    DefineStd(Builder, "unix", Opts);
483    Builder.defineMacro("__ELF__");
484    Builder.defineMacro("__svr4__");
485    Builder.defineMacro("__SVR4");
486  }
487public:
488  AuroraUXTargetInfo(const llvm::Triple &Triple)
489      : OSTargetInfo<Target>(Triple) {
490    this->UserLabelPrefix = "";
491    this->WCharType = this->SignedLong;
492    // FIXME: WIntType should be SignedLong
493  }
494};
495
496// Solaris target
497template<typename Target>
498class SolarisTargetInfo : public OSTargetInfo<Target> {
499protected:
500  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
501                            MacroBuilder &Builder) const {
502    DefineStd(Builder, "sun", Opts);
503    DefineStd(Builder, "unix", Opts);
504    Builder.defineMacro("__ELF__");
505    Builder.defineMacro("__svr4__");
506    Builder.defineMacro("__SVR4");
507    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
508    // newer, but to 500 for everything else.  feature_test.h has a check to
509    // ensure that you are not using C99 with an old version of X/Open or C89
510    // with a new version.
511    if (Opts.C99 || Opts.C11)
512      Builder.defineMacro("_XOPEN_SOURCE", "600");
513    else
514      Builder.defineMacro("_XOPEN_SOURCE", "500");
515    if (Opts.CPlusPlus)
516      Builder.defineMacro("__C99FEATURES__");
517    Builder.defineMacro("_LARGEFILE_SOURCE");
518    Builder.defineMacro("_LARGEFILE64_SOURCE");
519    Builder.defineMacro("__EXTENSIONS__");
520    Builder.defineMacro("_REENTRANT");
521  }
522public:
523  SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
524    this->UserLabelPrefix = "";
525    this->WCharType = this->SignedInt;
526    // FIXME: WIntType should be SignedLong
527  }
528};
529
530// Windows target
531template<typename Target>
532class WindowsTargetInfo : public OSTargetInfo<Target> {
533protected:
534  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
535                            MacroBuilder &Builder) const {
536    Builder.defineMacro("_WIN32");
537  }
538  void getVisualStudioDefines(const LangOptions &Opts,
539                              MacroBuilder &Builder) const {
540    if (Opts.CPlusPlus) {
541      if (Opts.RTTI)
542        Builder.defineMacro("_CPPRTTI");
543
544      if (Opts.Exceptions)
545        Builder.defineMacro("_CPPUNWIND");
546    }
547
548    if (!Opts.CharIsSigned)
549      Builder.defineMacro("_CHAR_UNSIGNED");
550
551    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
552    //        but it works for now.
553    if (Opts.POSIXThreads)
554      Builder.defineMacro("_MT");
555
556    if (Opts.MSCVersion != 0)
557      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
558
559    if (Opts.MicrosoftExt) {
560      Builder.defineMacro("_MSC_EXTENSIONS");
561
562      if (Opts.CPlusPlus11) {
563        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
564        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
565        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
566      }
567    }
568
569    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
570  }
571
572public:
573  WindowsTargetInfo(const llvm::Triple &Triple)
574      : OSTargetInfo<Target>(Triple) {}
575};
576
577template <typename Target>
578class NaClTargetInfo : public OSTargetInfo<Target> {
579protected:
580  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
581                            MacroBuilder &Builder) const {
582    if (Opts.POSIXThreads)
583      Builder.defineMacro("_REENTRANT");
584    if (Opts.CPlusPlus)
585      Builder.defineMacro("_GNU_SOURCE");
586
587    DefineStd(Builder, "unix", Opts);
588    Builder.defineMacro("__ELF__");
589    Builder.defineMacro("__native_client__");
590  }
591
592public:
593  NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
594    this->UserLabelPrefix = "";
595    this->LongAlign = 32;
596    this->LongWidth = 32;
597    this->PointerAlign = 32;
598    this->PointerWidth = 32;
599    this->IntMaxType = TargetInfo::SignedLongLong;
600    this->UIntMaxType = TargetInfo::UnsignedLongLong;
601    this->Int64Type = TargetInfo::SignedLongLong;
602    this->DoubleAlign = 64;
603    this->LongDoubleWidth = 64;
604    this->LongDoubleAlign = 64;
605    this->SizeType = TargetInfo::UnsignedInt;
606    this->PtrDiffType = TargetInfo::SignedInt;
607    this->IntPtrType = TargetInfo::SignedInt;
608    // RegParmMax is inherited from the underlying architecture
609    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
610    this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
611                              "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
612  }
613  virtual typename Target::CallingConvCheckResult checkCallingConvention(
614      CallingConv CC) const {
615    return CC == CC_PnaclCall ? Target::CCCR_OK :
616        Target::checkCallingConvention(CC);
617  }
618};
619} // end anonymous namespace.
620
621//===----------------------------------------------------------------------===//
622// Specific target implementations.
623//===----------------------------------------------------------------------===//
624
625namespace {
626// PPC abstract base class
627class PPCTargetInfo : public TargetInfo {
628  static const Builtin::Info BuiltinInfo[];
629  static const char * const GCCRegNames[];
630  static const TargetInfo::GCCRegAlias GCCRegAliases[];
631  std::string CPU;
632public:
633  PPCTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
634    LongDoubleWidth = LongDoubleAlign = 128;
635    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
636  }
637
638  /// \brief Flags for architecture specific defines.
639  typedef enum {
640    ArchDefineNone  = 0,
641    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
642    ArchDefinePpcgr = 1 << 1,
643    ArchDefinePpcsq = 1 << 2,
644    ArchDefine440   = 1 << 3,
645    ArchDefine603   = 1 << 4,
646    ArchDefine604   = 1 << 5,
647    ArchDefinePwr4  = 1 << 6,
648    ArchDefinePwr5  = 1 << 7,
649    ArchDefinePwr5x = 1 << 8,
650    ArchDefinePwr6  = 1 << 9,
651    ArchDefinePwr6x = 1 << 10,
652    ArchDefinePwr7  = 1 << 11,
653    ArchDefineA2    = 1 << 12,
654    ArchDefineA2q   = 1 << 13
655  } ArchDefineTypes;
656
657  // Note: GCC recognizes the following additional cpus:
658  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
659  //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
660  //  titan, rs64.
661  virtual bool setCPU(const std::string &Name) {
662    bool CPUKnown = llvm::StringSwitch<bool>(Name)
663      .Case("generic", true)
664      .Case("440", true)
665      .Case("450", true)
666      .Case("601", true)
667      .Case("602", true)
668      .Case("603", true)
669      .Case("603e", true)
670      .Case("603ev", true)
671      .Case("604", true)
672      .Case("604e", true)
673      .Case("620", true)
674      .Case("630", true)
675      .Case("g3", true)
676      .Case("7400", true)
677      .Case("g4", true)
678      .Case("7450", true)
679      .Case("g4+", true)
680      .Case("750", true)
681      .Case("970", true)
682      .Case("g5", true)
683      .Case("a2", true)
684      .Case("a2q", true)
685      .Case("e500mc", true)
686      .Case("e5500", true)
687      .Case("power3", true)
688      .Case("pwr3", true)
689      .Case("power4", true)
690      .Case("pwr4", true)
691      .Case("power5", true)
692      .Case("pwr5", true)
693      .Case("power5x", true)
694      .Case("pwr5x", true)
695      .Case("power6", true)
696      .Case("pwr6", true)
697      .Case("power6x", true)
698      .Case("pwr6x", true)
699      .Case("power7", true)
700      .Case("pwr7", true)
701      .Case("powerpc", true)
702      .Case("ppc", true)
703      .Case("powerpc64", true)
704      .Case("ppc64", true)
705      .Default(false);
706
707    if (CPUKnown)
708      CPU = Name;
709
710    return CPUKnown;
711  }
712
713  virtual void getTargetBuiltins(const Builtin::Info *&Records,
714                                 unsigned &NumRecords) const {
715    Records = BuiltinInfo;
716    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
717  }
718
719  virtual bool isCLZForZeroUndef() const { return false; }
720
721  virtual void getTargetDefines(const LangOptions &Opts,
722                                MacroBuilder &Builder) const;
723
724  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
725
726  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
727                                 StringRef Name,
728                                 bool Enabled) const;
729
730  virtual bool hasFeature(StringRef Feature) const;
731
732  virtual void getGCCRegNames(const char * const *&Names,
733                              unsigned &NumNames) const;
734  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
735                                unsigned &NumAliases) const;
736  virtual bool validateAsmConstraint(const char *&Name,
737                                     TargetInfo::ConstraintInfo &Info) const {
738    switch (*Name) {
739    default: return false;
740    case 'O': // Zero
741      break;
742    case 'b': // Base register
743    case 'f': // Floating point register
744      Info.setAllowsRegister();
745      break;
746    // FIXME: The following are added to allow parsing.
747    // I just took a guess at what the actions should be.
748    // Also, is more specific checking needed?  I.e. specific registers?
749    case 'd': // Floating point register (containing 64-bit value)
750    case 'v': // Altivec vector register
751      Info.setAllowsRegister();
752      break;
753    case 'w':
754      switch (Name[1]) {
755        case 'd':// VSX vector register to hold vector double data
756        case 'f':// VSX vector register to hold vector float data
757        case 's':// VSX vector register to hold scalar float data
758        case 'a':// Any VSX register
759          break;
760        default:
761          return false;
762      }
763      Info.setAllowsRegister();
764      Name++; // Skip over 'w'.
765      break;
766    case 'h': // `MQ', `CTR', or `LINK' register
767    case 'q': // `MQ' register
768    case 'c': // `CTR' register
769    case 'l': // `LINK' register
770    case 'x': // `CR' register (condition register) number 0
771    case 'y': // `CR' register (condition register)
772    case 'z': // `XER[CA]' carry bit (part of the XER register)
773      Info.setAllowsRegister();
774      break;
775    case 'I': // Signed 16-bit constant
776    case 'J': // Unsigned 16-bit constant shifted left 16 bits
777              //  (use `L' instead for SImode constants)
778    case 'K': // Unsigned 16-bit constant
779    case 'L': // Signed 16-bit constant shifted left 16 bits
780    case 'M': // Constant larger than 31
781    case 'N': // Exact power of 2
782    case 'P': // Constant whose negation is a signed 16-bit constant
783    case 'G': // Floating point constant that can be loaded into a
784              // register with one instruction per word
785    case 'H': // Integer/Floating point constant that can be loaded
786              // into a register using three instructions
787      break;
788    case 'm': // Memory operand. Note that on PowerPC targets, m can
789              // include addresses that update the base register. It
790              // is therefore only safe to use `m' in an asm statement
791              // if that asm statement accesses the operand exactly once.
792              // The asm statement must also use `%U<opno>' as a
793              // placeholder for the "update" flag in the corresponding
794              // load or store instruction. For example:
795              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
796              // is correct but:
797              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
798              // is not. Use es rather than m if you don't want the base
799              // register to be updated.
800    case 'e':
801      if (Name[1] != 's')
802          return false;
803              // es: A "stable" memory operand; that is, one which does not
804              // include any automodification of the base register. Unlike
805              // `m', this constraint can be used in asm statements that
806              // might access the operand several times, or that might not
807              // access it at all.
808      Info.setAllowsMemory();
809      Name++; // Skip over 'e'.
810      break;
811    case 'Q': // Memory operand that is an offset from a register (it is
812              // usually better to use `m' or `es' in asm statements)
813    case 'Z': // Memory operand that is an indexed or indirect from a
814              // register (it is usually better to use `m' or `es' in
815              // asm statements)
816      Info.setAllowsMemory();
817      Info.setAllowsRegister();
818      break;
819    case 'R': // AIX TOC entry
820    case 'a': // Address operand that is an indexed or indirect from a
821              // register (`p' is preferable for asm statements)
822    case 'S': // Constant suitable as a 64-bit mask operand
823    case 'T': // Constant suitable as a 32-bit mask operand
824    case 'U': // System V Release 4 small data area reference
825    case 't': // AND masks that can be performed by two rldic{l, r}
826              // instructions
827    case 'W': // Vector constant that does not require memory
828    case 'j': // Vector constant that is all zeros.
829      break;
830    // End FIXME.
831    }
832    return true;
833  }
834  virtual const char *getClobbers() const {
835    return "";
836  }
837  int getEHDataRegisterNumber(unsigned RegNo) const {
838    if (RegNo == 0) return 3;
839    if (RegNo == 1) return 4;
840    return -1;
841  }
842};
843
844const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
845#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
846#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
847                                              ALL_LANGUAGES },
848#include "clang/Basic/BuiltinsPPC.def"
849};
850
851
852/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
853/// #defines that are not tied to a specific subtarget.
854void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
855                                     MacroBuilder &Builder) const {
856  // Target identification.
857  Builder.defineMacro("__ppc__");
858  Builder.defineMacro("__PPC__");
859  Builder.defineMacro("_ARCH_PPC");
860  Builder.defineMacro("__powerpc__");
861  Builder.defineMacro("__POWERPC__");
862  if (PointerWidth == 64) {
863    Builder.defineMacro("_ARCH_PPC64");
864    Builder.defineMacro("__powerpc64__");
865    Builder.defineMacro("__ppc64__");
866    Builder.defineMacro("__PPC64__");
867  }
868
869  // Target properties.
870  if (getTriple().getOS() != llvm::Triple::NetBSD &&
871      getTriple().getOS() != llvm::Triple::OpenBSD)
872    Builder.defineMacro("_BIG_ENDIAN");
873  Builder.defineMacro("__BIG_ENDIAN__");
874
875  // Subtarget options.
876  Builder.defineMacro("__NATURAL_ALIGNMENT__");
877  Builder.defineMacro("__REGISTER_PREFIX__", "");
878
879  // FIXME: Should be controlled by command line option.
880  Builder.defineMacro("__LONG_DOUBLE_128__");
881
882  if (Opts.AltiVec) {
883    Builder.defineMacro("__VEC__", "10206");
884    Builder.defineMacro("__ALTIVEC__");
885  }
886
887  // CPU identification.
888  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
889    .Case("440",   ArchDefineName)
890    .Case("450",   ArchDefineName | ArchDefine440)
891    .Case("601",   ArchDefineName)
892    .Case("602",   ArchDefineName | ArchDefinePpcgr)
893    .Case("603",   ArchDefineName | ArchDefinePpcgr)
894    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
895    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
896    .Case("604",   ArchDefineName | ArchDefinePpcgr)
897    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
898    .Case("620",   ArchDefineName | ArchDefinePpcgr)
899    .Case("630",   ArchDefineName | ArchDefinePpcgr)
900    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
901    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
902    .Case("750",   ArchDefineName | ArchDefinePpcgr)
903    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
904                     | ArchDefinePpcsq)
905    .Case("a2",    ArchDefineA2)
906    .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
907    .Case("pwr3",  ArchDefinePpcgr)
908    .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
909    .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
910                     | ArchDefinePpcsq)
911    .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
912                     | ArchDefinePpcgr | ArchDefinePpcsq)
913    .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
914                     | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
915    .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
916                     | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
917                     | ArchDefinePpcsq)
918    .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
919                     | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
920                     | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
921    .Case("power3",  ArchDefinePpcgr)
922    .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
923    .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
924                       | ArchDefinePpcsq)
925    .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
926                       | ArchDefinePpcgr | ArchDefinePpcsq)
927    .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
928                       | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
929    .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
930                       | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
931                       | ArchDefinePpcsq)
932    .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
933                       | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
934                       | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
935    .Default(ArchDefineNone);
936
937  if (defs & ArchDefineName)
938    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
939  if (defs & ArchDefinePpcgr)
940    Builder.defineMacro("_ARCH_PPCGR");
941  if (defs & ArchDefinePpcsq)
942    Builder.defineMacro("_ARCH_PPCSQ");
943  if (defs & ArchDefine440)
944    Builder.defineMacro("_ARCH_440");
945  if (defs & ArchDefine603)
946    Builder.defineMacro("_ARCH_603");
947  if (defs & ArchDefine604)
948    Builder.defineMacro("_ARCH_604");
949  if (defs & ArchDefinePwr4)
950    Builder.defineMacro("_ARCH_PWR4");
951  if (defs & ArchDefinePwr5)
952    Builder.defineMacro("_ARCH_PWR5");
953  if (defs & ArchDefinePwr5x)
954    Builder.defineMacro("_ARCH_PWR5X");
955  if (defs & ArchDefinePwr6)
956    Builder.defineMacro("_ARCH_PWR6");
957  if (defs & ArchDefinePwr6x)
958    Builder.defineMacro("_ARCH_PWR6X");
959  if (defs & ArchDefinePwr7)
960    Builder.defineMacro("_ARCH_PWR7");
961  if (defs & ArchDefineA2)
962    Builder.defineMacro("_ARCH_A2");
963  if (defs & ArchDefineA2q) {
964    Builder.defineMacro("_ARCH_A2Q");
965    Builder.defineMacro("_ARCH_QP");
966  }
967
968  if (getTriple().getVendor() == llvm::Triple::BGQ) {
969    Builder.defineMacro("__bg__");
970    Builder.defineMacro("__THW_BLUEGENE__");
971    Builder.defineMacro("__bgq__");
972    Builder.defineMacro("__TOS_BGQ__");
973  }
974
975  // FIXME: The following are not yet generated here by Clang, but are
976  //        generated by GCC:
977  //
978  //   _SOFT_FLOAT_
979  //   __RECIP_PRECISION__
980  //   __APPLE_ALTIVEC__
981  //   __VSX__
982  //   __RECIP__
983  //   __RECIPF__
984  //   __RSQRTE__
985  //   __RSQRTEF__
986  //   _SOFT_DOUBLE_
987  //   __NO_LWSYNC__
988  //   __HAVE_BSWAP__
989  //   __LONGDOUBLE128
990  //   __CMODEL_MEDIUM__
991  //   __CMODEL_LARGE__
992  //   _CALL_SYSV
993  //   _CALL_DARWIN
994  //   __NO_FPRS__
995}
996
997void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
998  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
999    .Case("7400", true)
1000    .Case("g4", true)
1001    .Case("7450", true)
1002    .Case("g4+", true)
1003    .Case("970", true)
1004    .Case("g5", true)
1005    .Case("pwr6", true)
1006    .Case("pwr7", true)
1007    .Case("ppc64", true)
1008    .Default(false);
1009
1010  Features["qpx"] = (CPU == "a2q");
1011}
1012
1013bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1014                                         StringRef Name,
1015                                         bool Enabled) const {
1016  if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1017      Name == "popcntd" || Name == "qpx") {
1018    Features[Name] = Enabled;
1019    return true;
1020  }
1021
1022  return false;
1023}
1024
1025bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1026  return Feature == "powerpc";
1027}
1028
1029
1030const char * const PPCTargetInfo::GCCRegNames[] = {
1031  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1032  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1033  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1034  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1035  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1036  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1037  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1038  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1039  "mq", "lr", "ctr", "ap",
1040  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1041  "xer",
1042  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1043  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1044  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1045  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1046  "vrsave", "vscr",
1047  "spe_acc", "spefscr",
1048  "sfp"
1049};
1050
1051void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1052                                   unsigned &NumNames) const {
1053  Names = GCCRegNames;
1054  NumNames = llvm::array_lengthof(GCCRegNames);
1055}
1056
1057const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1058  // While some of these aliases do map to different registers
1059  // they still share the same register name.
1060  { { "0" }, "r0" },
1061  { { "1"}, "r1" },
1062  { { "2" }, "r2" },
1063  { { "3" }, "r3" },
1064  { { "4" }, "r4" },
1065  { { "5" }, "r5" },
1066  { { "6" }, "r6" },
1067  { { "7" }, "r7" },
1068  { { "8" }, "r8" },
1069  { { "9" }, "r9" },
1070  { { "10" }, "r10" },
1071  { { "11" }, "r11" },
1072  { { "12" }, "r12" },
1073  { { "13" }, "r13" },
1074  { { "14" }, "r14" },
1075  { { "15" }, "r15" },
1076  { { "16" }, "r16" },
1077  { { "17" }, "r17" },
1078  { { "18" }, "r18" },
1079  { { "19" }, "r19" },
1080  { { "20" }, "r20" },
1081  { { "21" }, "r21" },
1082  { { "22" }, "r22" },
1083  { { "23" }, "r23" },
1084  { { "24" }, "r24" },
1085  { { "25" }, "r25" },
1086  { { "26" }, "r26" },
1087  { { "27" }, "r27" },
1088  { { "28" }, "r28" },
1089  { { "29" }, "r29" },
1090  { { "30" }, "r30" },
1091  { { "31" }, "r31" },
1092  { { "fr0" }, "f0" },
1093  { { "fr1" }, "f1" },
1094  { { "fr2" }, "f2" },
1095  { { "fr3" }, "f3" },
1096  { { "fr4" }, "f4" },
1097  { { "fr5" }, "f5" },
1098  { { "fr6" }, "f6" },
1099  { { "fr7" }, "f7" },
1100  { { "fr8" }, "f8" },
1101  { { "fr9" }, "f9" },
1102  { { "fr10" }, "f10" },
1103  { { "fr11" }, "f11" },
1104  { { "fr12" }, "f12" },
1105  { { "fr13" }, "f13" },
1106  { { "fr14" }, "f14" },
1107  { { "fr15" }, "f15" },
1108  { { "fr16" }, "f16" },
1109  { { "fr17" }, "f17" },
1110  { { "fr18" }, "f18" },
1111  { { "fr19" }, "f19" },
1112  { { "fr20" }, "f20" },
1113  { { "fr21" }, "f21" },
1114  { { "fr22" }, "f22" },
1115  { { "fr23" }, "f23" },
1116  { { "fr24" }, "f24" },
1117  { { "fr25" }, "f25" },
1118  { { "fr26" }, "f26" },
1119  { { "fr27" }, "f27" },
1120  { { "fr28" }, "f28" },
1121  { { "fr29" }, "f29" },
1122  { { "fr30" }, "f30" },
1123  { { "fr31" }, "f31" },
1124  { { "cc" }, "cr0" },
1125};
1126
1127void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1128                                     unsigned &NumAliases) const {
1129  Aliases = GCCRegAliases;
1130  NumAliases = llvm::array_lengthof(GCCRegAliases);
1131}
1132} // end anonymous namespace.
1133
1134namespace {
1135class PPC32TargetInfo : public PPCTargetInfo {
1136public:
1137  PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1138    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1139                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1140
1141    switch (getTriple().getOS()) {
1142    case llvm::Triple::Linux:
1143    case llvm::Triple::FreeBSD:
1144    case llvm::Triple::NetBSD:
1145      SizeType = UnsignedInt;
1146      PtrDiffType = SignedInt;
1147      IntPtrType = SignedInt;
1148      break;
1149    default:
1150      break;
1151    }
1152
1153    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1154      LongDoubleWidth = LongDoubleAlign = 64;
1155      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1156    }
1157
1158    // PPC32 supports atomics up to 4 bytes.
1159    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1160  }
1161
1162  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1163    // This is the ELF definition, and is overridden by the Darwin sub-target
1164    return TargetInfo::PowerABIBuiltinVaList;
1165  }
1166};
1167} // end anonymous namespace.
1168
1169namespace {
1170class PPC64TargetInfo : public PPCTargetInfo {
1171public:
1172  PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1173    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1174    IntMaxType = SignedLong;
1175    UIntMaxType = UnsignedLong;
1176    Int64Type = SignedLong;
1177
1178    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1179      LongDoubleWidth = LongDoubleAlign = 64;
1180      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1181      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1182                          "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1183                          "v128:128:128-n32:64";
1184    } else
1185      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1186                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1187                          "v128:128:128-n32:64";
1188
1189    // PPC64 supports atomics up to 8 bytes.
1190    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1191  }
1192  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1193    return TargetInfo::CharPtrBuiltinVaList;
1194  }
1195};
1196} // end anonymous namespace.
1197
1198
1199namespace {
1200class DarwinPPC32TargetInfo :
1201  public DarwinTargetInfo<PPC32TargetInfo> {
1202public:
1203  DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1204      : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1205    HasAlignMac68kSupport = true;
1206    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1207    PtrDiffType = SignedInt;	// for http://llvm.org/bugs/show_bug.cgi?id=15726
1208    LongLongAlign = 32;
1209    SuitableAlign = 128;
1210    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1211                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1212  }
1213  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1214    return TargetInfo::CharPtrBuiltinVaList;
1215  }
1216};
1217
1218class DarwinPPC64TargetInfo :
1219  public DarwinTargetInfo<PPC64TargetInfo> {
1220public:
1221  DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1222      : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1223    HasAlignMac68kSupport = true;
1224    SuitableAlign = 128;
1225    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1226                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1227  }
1228};
1229} // end anonymous namespace.
1230
1231namespace {
1232  static const unsigned NVPTXAddrSpaceMap[] = {
1233    1,    // opencl_global
1234    3,    // opencl_local
1235    4,    // opencl_constant
1236    1,    // cuda_device
1237    4,    // cuda_constant
1238    3,    // cuda_shared
1239  };
1240  class NVPTXTargetInfo : public TargetInfo {
1241    static const char * const GCCRegNames[];
1242    static const Builtin::Info BuiltinInfo[];
1243    std::vector<StringRef> AvailableFeatures;
1244  public:
1245    NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1246      BigEndian = false;
1247      TLSSupported = false;
1248      LongWidth = LongAlign = 64;
1249      AddrSpaceMap = &NVPTXAddrSpaceMap;
1250      // Define available target features
1251      // These must be defined in sorted order!
1252      NoAsmVariants = true;
1253    }
1254    virtual void getTargetDefines(const LangOptions &Opts,
1255                                  MacroBuilder &Builder) const {
1256      Builder.defineMacro("__PTX__");
1257      Builder.defineMacro("__NVPTX__");
1258    }
1259    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1260                                   unsigned &NumRecords) const {
1261      Records = BuiltinInfo;
1262      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1263    }
1264    virtual bool hasFeature(StringRef Feature) const {
1265      return Feature == "ptx" || Feature == "nvptx";
1266    }
1267
1268    virtual void getGCCRegNames(const char * const *&Names,
1269                                unsigned &NumNames) const;
1270    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1271                                  unsigned &NumAliases) const {
1272      // No aliases.
1273      Aliases = 0;
1274      NumAliases = 0;
1275    }
1276    virtual bool validateAsmConstraint(const char *&Name,
1277                                       TargetInfo::ConstraintInfo &Info) const {
1278      switch (*Name) {
1279      default: return false;
1280      case 'c':
1281      case 'h':
1282      case 'r':
1283      case 'l':
1284      case 'f':
1285      case 'd':
1286        Info.setAllowsRegister();
1287        return true;
1288      }
1289    }
1290    virtual const char *getClobbers() const {
1291      // FIXME: Is this really right?
1292      return "";
1293    }
1294    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1295      // FIXME: implement
1296      return TargetInfo::CharPtrBuiltinVaList;
1297    }
1298    virtual bool setCPU(const std::string &Name) {
1299      bool Valid = llvm::StringSwitch<bool>(Name)
1300        .Case("sm_20", true)
1301        .Case("sm_21", true)
1302        .Case("sm_30", true)
1303        .Case("sm_35", true)
1304        .Default(false);
1305
1306      return Valid;
1307    }
1308    virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1309                                   StringRef Name,
1310                                   bool Enabled) const;
1311  };
1312
1313  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1314#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1315#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1316                                              ALL_LANGUAGES },
1317#include "clang/Basic/BuiltinsNVPTX.def"
1318  };
1319
1320  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1321    "r0"
1322  };
1323
1324  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1325                                     unsigned &NumNames) const {
1326    Names = GCCRegNames;
1327    NumNames = llvm::array_lengthof(GCCRegNames);
1328  }
1329
1330  bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1331                                          StringRef Name,
1332                                          bool Enabled) const {
1333    if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1334                          Name)) {
1335      Features[Name] = Enabled;
1336      return true;
1337    } else {
1338      return false;
1339    }
1340  }
1341
1342  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1343  public:
1344    NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1345      PointerWidth = PointerAlign = 32;
1346      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1347      DescriptionString
1348        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1349          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1350          "n16:32:64";
1351  }
1352  };
1353
1354  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1355  public:
1356    NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1357      PointerWidth = PointerAlign = 64;
1358      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1359      DescriptionString
1360        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1361          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1362          "n16:32:64";
1363  }
1364  };
1365}
1366
1367namespace {
1368
1369static const unsigned R600AddrSpaceMap[] = {
1370  1,    // opencl_global
1371  3,    // opencl_local
1372  2,    // opencl_constant
1373  1,    // cuda_device
1374  2,    // cuda_constant
1375  3     // cuda_shared
1376};
1377
1378static const char *DescriptionStringR600 =
1379  "e"
1380  "-p:32:32:32"
1381  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1382  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1383  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1384  "-n32:64";
1385
1386static const char *DescriptionStringR600DoubleOps =
1387  "e"
1388  "-p:32:32:32"
1389  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1390  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1391  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1392  "-n32:64";
1393
1394static const char *DescriptionStringSI =
1395  "e"
1396  "-p:64:64:64"
1397  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1398  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1399  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1400  "-n32:64";
1401
1402class R600TargetInfo : public TargetInfo {
1403  /// \brief The GPU profiles supported by the R600 target.
1404  enum GPUKind {
1405    GK_NONE,
1406    GK_R600,
1407    GK_R600_DOUBLE_OPS,
1408    GK_R700,
1409    GK_R700_DOUBLE_OPS,
1410    GK_EVERGREEN,
1411    GK_EVERGREEN_DOUBLE_OPS,
1412    GK_NORTHERN_ISLANDS,
1413    GK_CAYMAN,
1414    GK_SOUTHERN_ISLANDS
1415  } GPU;
1416
1417public:
1418  R600TargetInfo(const llvm::Triple &Triple)
1419      : TargetInfo(Triple), GPU(GK_R600) {
1420    DescriptionString = DescriptionStringR600;
1421    AddrSpaceMap = &R600AddrSpaceMap;
1422  }
1423
1424  virtual const char * getClobbers() const {
1425    return "";
1426  }
1427
1428  virtual void getGCCRegNames(const char * const *&Names,
1429                              unsigned &numNames) const  {
1430    Names = NULL;
1431    numNames = 0;
1432  }
1433
1434  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1435                                unsigned &NumAliases) const {
1436    Aliases = NULL;
1437    NumAliases = 0;
1438  }
1439
1440  virtual bool validateAsmConstraint(const char *&Name,
1441                                     TargetInfo::ConstraintInfo &info) const {
1442    return true;
1443  }
1444
1445  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1446                                 unsigned &NumRecords) const {
1447    Records = NULL;
1448    NumRecords = 0;
1449  }
1450
1451
1452  virtual void getTargetDefines(const LangOptions &Opts,
1453                                MacroBuilder &Builder) const {
1454    Builder.defineMacro("__R600__");
1455  }
1456
1457  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1458    return TargetInfo::CharPtrBuiltinVaList;
1459  }
1460
1461  virtual bool setCPU(const std::string &Name) {
1462    GPU = llvm::StringSwitch<GPUKind>(Name)
1463      .Case("r600" ,    GK_R600)
1464      .Case("rv610",    GK_R600)
1465      .Case("rv620",    GK_R600)
1466      .Case("rv630",    GK_R600)
1467      .Case("rv635",    GK_R600)
1468      .Case("rs780",    GK_R600)
1469      .Case("rs880",    GK_R600)
1470      .Case("rv670",    GK_R600_DOUBLE_OPS)
1471      .Case("rv710",    GK_R700)
1472      .Case("rv730",    GK_R700)
1473      .Case("rv740",    GK_R700_DOUBLE_OPS)
1474      .Case("rv770",    GK_R700_DOUBLE_OPS)
1475      .Case("palm",     GK_EVERGREEN)
1476      .Case("cedar",    GK_EVERGREEN)
1477      .Case("sumo",     GK_EVERGREEN)
1478      .Case("sumo2",    GK_EVERGREEN)
1479      .Case("redwood",  GK_EVERGREEN)
1480      .Case("juniper",  GK_EVERGREEN)
1481      .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1482      .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1483      .Case("barts",    GK_NORTHERN_ISLANDS)
1484      .Case("turks",    GK_NORTHERN_ISLANDS)
1485      .Case("caicos",   GK_NORTHERN_ISLANDS)
1486      .Case("cayman",   GK_CAYMAN)
1487      .Case("aruba",    GK_CAYMAN)
1488      .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1489      .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1490      .Case("verde",    GK_SOUTHERN_ISLANDS)
1491      .Case("oland",    GK_SOUTHERN_ISLANDS)
1492      .Default(GK_NONE);
1493
1494    if (GPU == GK_NONE) {
1495      return false;
1496    }
1497
1498    // Set the correct data layout
1499    switch (GPU) {
1500    case GK_NONE:
1501    case GK_R600:
1502    case GK_R700:
1503    case GK_EVERGREEN:
1504    case GK_NORTHERN_ISLANDS:
1505      DescriptionString = DescriptionStringR600;
1506      break;
1507    case GK_R600_DOUBLE_OPS:
1508    case GK_R700_DOUBLE_OPS:
1509    case GK_EVERGREEN_DOUBLE_OPS:
1510    case GK_CAYMAN:
1511      DescriptionString = DescriptionStringR600DoubleOps;
1512      break;
1513    case GK_SOUTHERN_ISLANDS:
1514      DescriptionString = DescriptionStringSI;
1515      break;
1516    }
1517
1518    return true;
1519  }
1520};
1521
1522} // end anonymous namespace
1523
1524namespace {
1525// MBlaze abstract base class
1526class MBlazeTargetInfo : public TargetInfo {
1527  static const char * const GCCRegNames[];
1528  static const TargetInfo::GCCRegAlias GCCRegAliases[];
1529
1530public:
1531  MBlazeTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1532    DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1533  }
1534
1535  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1536                                 unsigned &NumRecords) const {
1537    // FIXME: Implement.
1538    Records = 0;
1539    NumRecords = 0;
1540  }
1541
1542  virtual void getTargetDefines(const LangOptions &Opts,
1543                                MacroBuilder &Builder) const;
1544
1545  virtual bool hasFeature(StringRef Feature) const {
1546    return Feature == "mblaze";
1547  }
1548
1549  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1550    return TargetInfo::CharPtrBuiltinVaList;
1551  }
1552  virtual const char *getTargetPrefix() const {
1553    return "mblaze";
1554  }
1555  virtual void getGCCRegNames(const char * const *&Names,
1556                              unsigned &NumNames) const;
1557  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1558                                unsigned &NumAliases) const;
1559  virtual bool validateAsmConstraint(const char *&Name,
1560                                     TargetInfo::ConstraintInfo &Info) const {
1561    switch (*Name) {
1562    default: return false;
1563    case 'O': // Zero
1564      return true;
1565    case 'b': // Base register
1566    case 'f': // Floating point register
1567      Info.setAllowsRegister();
1568      return true;
1569    }
1570  }
1571  virtual const char *getClobbers() const {
1572    return "";
1573  }
1574};
1575
1576/// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1577/// #defines that are not tied to a specific subtarget.
1578void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1579                                     MacroBuilder &Builder) const {
1580  // Target identification.
1581  Builder.defineMacro("__microblaze__");
1582  Builder.defineMacro("_ARCH_MICROBLAZE");
1583  Builder.defineMacro("__MICROBLAZE__");
1584
1585  // Target properties.
1586  Builder.defineMacro("_BIG_ENDIAN");
1587  Builder.defineMacro("__BIG_ENDIAN__");
1588
1589  // Subtarget options.
1590  Builder.defineMacro("__REGISTER_PREFIX__", "");
1591}
1592
1593
1594const char * const MBlazeTargetInfo::GCCRegNames[] = {
1595  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1596  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1597  "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1598  "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1599  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1600  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1601  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1602  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1603  "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1604  "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1605};
1606
1607void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1608                                   unsigned &NumNames) const {
1609  Names = GCCRegNames;
1610  NumNames = llvm::array_lengthof(GCCRegNames);
1611}
1612
1613const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1614  { {"f0"},  "r0" },
1615  { {"f1"},  "r1" },
1616  { {"f2"},  "r2" },
1617  { {"f3"},  "r3" },
1618  { {"f4"},  "r4" },
1619  { {"f5"},  "r5" },
1620  { {"f6"},  "r6" },
1621  { {"f7"},  "r7" },
1622  { {"f8"},  "r8" },
1623  { {"f9"},  "r9" },
1624  { {"f10"}, "r10" },
1625  { {"f11"}, "r11" },
1626  { {"f12"}, "r12" },
1627  { {"f13"}, "r13" },
1628  { {"f14"}, "r14" },
1629  { {"f15"}, "r15" },
1630  { {"f16"}, "r16" },
1631  { {"f17"}, "r17" },
1632  { {"f18"}, "r18" },
1633  { {"f19"}, "r19" },
1634  { {"f20"}, "r20" },
1635  { {"f21"}, "r21" },
1636  { {"f22"}, "r22" },
1637  { {"f23"}, "r23" },
1638  { {"f24"}, "r24" },
1639  { {"f25"}, "r25" },
1640  { {"f26"}, "r26" },
1641  { {"f27"}, "r27" },
1642  { {"f28"}, "r28" },
1643  { {"f29"}, "r29" },
1644  { {"f30"}, "r30" },
1645  { {"f31"}, "r31" },
1646};
1647
1648void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1649                                     unsigned &NumAliases) const {
1650  Aliases = GCCRegAliases;
1651  NumAliases = llvm::array_lengthof(GCCRegAliases);
1652}
1653} // end anonymous namespace.
1654
1655namespace {
1656// Namespace for x86 abstract base class
1657const Builtin::Info BuiltinInfo[] = {
1658#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1659#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1660                                              ALL_LANGUAGES },
1661#include "clang/Basic/BuiltinsX86.def"
1662};
1663
1664static const char* const GCCRegNames[] = {
1665  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1666  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1667  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1668  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1669  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1670  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1671  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1672  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1673  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1674};
1675
1676const TargetInfo::AddlRegName AddlRegNames[] = {
1677  { { "al", "ah", "eax", "rax" }, 0 },
1678  { { "bl", "bh", "ebx", "rbx" }, 3 },
1679  { { "cl", "ch", "ecx", "rcx" }, 2 },
1680  { { "dl", "dh", "edx", "rdx" }, 1 },
1681  { { "esi", "rsi" }, 4 },
1682  { { "edi", "rdi" }, 5 },
1683  { { "esp", "rsp" }, 7 },
1684  { { "ebp", "rbp" }, 6 },
1685};
1686
1687// X86 target abstract base class; x86-32 and x86-64 are very close, so
1688// most of the implementation can be shared.
1689class X86TargetInfo : public TargetInfo {
1690  enum X86SSEEnum {
1691    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1692  } SSELevel;
1693  enum MMX3DNowEnum {
1694    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1695  } MMX3DNowLevel;
1696
1697  bool HasAES;
1698  bool HasPCLMUL;
1699  bool HasLZCNT;
1700  bool HasRDRND;
1701  bool HasBMI;
1702  bool HasBMI2;
1703  bool HasPOPCNT;
1704  bool HasRTM;
1705  bool HasPRFCHW;
1706  bool HasRDSEED;
1707  bool HasSSE4a;
1708  bool HasFMA4;
1709  bool HasFMA;
1710  bool HasXOP;
1711  bool HasF16C;
1712
1713  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1714  ///
1715  /// Each enumeration represents a particular CPU supported by Clang. These
1716  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1717  enum CPUKind {
1718    CK_Generic,
1719
1720    /// \name i386
1721    /// i386-generation processors.
1722    //@{
1723    CK_i386,
1724    //@}
1725
1726    /// \name i486
1727    /// i486-generation processors.
1728    //@{
1729    CK_i486,
1730    CK_WinChipC6,
1731    CK_WinChip2,
1732    CK_C3,
1733    //@}
1734
1735    /// \name i586
1736    /// i586-generation processors, P5 microarchitecture based.
1737    //@{
1738    CK_i586,
1739    CK_Pentium,
1740    CK_PentiumMMX,
1741    //@}
1742
1743    /// \name i686
1744    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1745    //@{
1746    CK_i686,
1747    CK_PentiumPro,
1748    CK_Pentium2,
1749    CK_Pentium3,
1750    CK_Pentium3M,
1751    CK_PentiumM,
1752    CK_C3_2,
1753
1754    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1755    /// Clang however has some logic to suport this.
1756    // FIXME: Warn, deprecate, and potentially remove this.
1757    CK_Yonah,
1758    //@}
1759
1760    /// \name Netburst
1761    /// Netburst microarchitecture based processors.
1762    //@{
1763    CK_Pentium4,
1764    CK_Pentium4M,
1765    CK_Prescott,
1766    CK_Nocona,
1767    //@}
1768
1769    /// \name Core
1770    /// Core microarchitecture based processors.
1771    //@{
1772    CK_Core2,
1773
1774    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1775    /// codename which GCC no longer accepts as an option to -march, but Clang
1776    /// has some logic for recognizing it.
1777    // FIXME: Warn, deprecate, and potentially remove this.
1778    CK_Penryn,
1779    //@}
1780
1781    /// \name Atom
1782    /// Atom processors
1783    //@{
1784    CK_Atom,
1785    //@}
1786
1787    /// \name Nehalem
1788    /// Nehalem microarchitecture based processors.
1789    //@{
1790    CK_Corei7,
1791    CK_Corei7AVX,
1792    CK_CoreAVXi,
1793    CK_CoreAVX2,
1794    //@}
1795
1796    /// \name K6
1797    /// K6 architecture processors.
1798    //@{
1799    CK_K6,
1800    CK_K6_2,
1801    CK_K6_3,
1802    //@}
1803
1804    /// \name K7
1805    /// K7 architecture processors.
1806    //@{
1807    CK_Athlon,
1808    CK_AthlonThunderbird,
1809    CK_Athlon4,
1810    CK_AthlonXP,
1811    CK_AthlonMP,
1812    //@}
1813
1814    /// \name K8
1815    /// K8 architecture processors.
1816    //@{
1817    CK_Athlon64,
1818    CK_Athlon64SSE3,
1819    CK_AthlonFX,
1820    CK_K8,
1821    CK_K8SSE3,
1822    CK_Opteron,
1823    CK_OpteronSSE3,
1824    CK_AMDFAM10,
1825    //@}
1826
1827    /// \name Bobcat
1828    /// Bobcat architecture processors.
1829    //@{
1830    CK_BTVER1,
1831    CK_BTVER2,
1832    //@}
1833
1834    /// \name Bulldozer
1835    /// Bulldozer architecture processors.
1836    //@{
1837    CK_BDVER1,
1838    CK_BDVER2,
1839    //@}
1840
1841    /// This specification is deprecated and will be removed in the future.
1842    /// Users should prefer \see CK_K8.
1843    // FIXME: Warn on this when the CPU is set to it.
1844    CK_x86_64,
1845    //@}
1846
1847    /// \name Geode
1848    /// Geode processors.
1849    //@{
1850    CK_Geode
1851    //@}
1852  } CPU;
1853
1854public:
1855  X86TargetInfo(const llvm::Triple &Triple)
1856      : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1857        HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1858        HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1859        HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1860        HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1861    BigEndian = false;
1862    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1863  }
1864  virtual unsigned getFloatEvalMethod() const {
1865    // X87 evaluates with 80 bits "long double" precision.
1866    return SSELevel == NoSSE ? 2 : 0;
1867  }
1868  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1869                                 unsigned &NumRecords) const {
1870    Records = BuiltinInfo;
1871    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1872  }
1873  virtual void getGCCRegNames(const char * const *&Names,
1874                              unsigned &NumNames) const {
1875    Names = GCCRegNames;
1876    NumNames = llvm::array_lengthof(GCCRegNames);
1877  }
1878  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1879                                unsigned &NumAliases) const {
1880    Aliases = 0;
1881    NumAliases = 0;
1882  }
1883  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1884                                  unsigned &NumNames) const {
1885    Names = AddlRegNames;
1886    NumNames = llvm::array_lengthof(AddlRegNames);
1887  }
1888  virtual bool validateAsmConstraint(const char *&Name,
1889                                     TargetInfo::ConstraintInfo &info) const;
1890  virtual std::string convertConstraint(const char *&Constraint) const;
1891  virtual const char *getClobbers() const {
1892    return "~{dirflag},~{fpsr},~{flags}";
1893  }
1894  virtual void getTargetDefines(const LangOptions &Opts,
1895                                MacroBuilder &Builder) const;
1896  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1897                                 StringRef Name,
1898                                 bool Enabled) const;
1899  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1900  virtual bool hasFeature(StringRef Feature) const;
1901  virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1902  virtual const char* getABI() const {
1903    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1904      return "avx";
1905    else if (getTriple().getArch() == llvm::Triple::x86 &&
1906             MMX3DNowLevel == NoMMX3DNow)
1907      return "no-mmx";
1908    return "";
1909  }
1910  virtual bool setCPU(const std::string &Name) {
1911    CPU = llvm::StringSwitch<CPUKind>(Name)
1912      .Case("i386", CK_i386)
1913      .Case("i486", CK_i486)
1914      .Case("winchip-c6", CK_WinChipC6)
1915      .Case("winchip2", CK_WinChip2)
1916      .Case("c3", CK_C3)
1917      .Case("i586", CK_i586)
1918      .Case("pentium", CK_Pentium)
1919      .Case("pentium-mmx", CK_PentiumMMX)
1920      .Case("i686", CK_i686)
1921      .Case("pentiumpro", CK_PentiumPro)
1922      .Case("pentium2", CK_Pentium2)
1923      .Case("pentium3", CK_Pentium3)
1924      .Case("pentium3m", CK_Pentium3M)
1925      .Case("pentium-m", CK_PentiumM)
1926      .Case("c3-2", CK_C3_2)
1927      .Case("yonah", CK_Yonah)
1928      .Case("pentium4", CK_Pentium4)
1929      .Case("pentium4m", CK_Pentium4M)
1930      .Case("prescott", CK_Prescott)
1931      .Case("nocona", CK_Nocona)
1932      .Case("core2", CK_Core2)
1933      .Case("penryn", CK_Penryn)
1934      .Case("atom", CK_Atom)
1935      .Case("corei7", CK_Corei7)
1936      .Case("corei7-avx", CK_Corei7AVX)
1937      .Case("core-avx-i", CK_CoreAVXi)
1938      .Case("core-avx2", CK_CoreAVX2)
1939      .Case("k6", CK_K6)
1940      .Case("k6-2", CK_K6_2)
1941      .Case("k6-3", CK_K6_3)
1942      .Case("athlon", CK_Athlon)
1943      .Case("athlon-tbird", CK_AthlonThunderbird)
1944      .Case("athlon-4", CK_Athlon4)
1945      .Case("athlon-xp", CK_AthlonXP)
1946      .Case("athlon-mp", CK_AthlonMP)
1947      .Case("athlon64", CK_Athlon64)
1948      .Case("athlon64-sse3", CK_Athlon64SSE3)
1949      .Case("athlon-fx", CK_AthlonFX)
1950      .Case("k8", CK_K8)
1951      .Case("k8-sse3", CK_K8SSE3)
1952      .Case("opteron", CK_Opteron)
1953      .Case("opteron-sse3", CK_OpteronSSE3)
1954      .Case("amdfam10", CK_AMDFAM10)
1955      .Case("btver1", CK_BTVER1)
1956      .Case("btver2", CK_BTVER2)
1957      .Case("bdver1", CK_BDVER1)
1958      .Case("bdver2", CK_BDVER2)
1959      .Case("x86-64", CK_x86_64)
1960      .Case("geode", CK_Geode)
1961      .Default(CK_Generic);
1962
1963    // Perform any per-CPU checks necessary to determine if this CPU is
1964    // acceptable.
1965    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1966    // invalid without explaining *why*.
1967    switch (CPU) {
1968    case CK_Generic:
1969      // No processor selected!
1970      return false;
1971
1972    case CK_i386:
1973    case CK_i486:
1974    case CK_WinChipC6:
1975    case CK_WinChip2:
1976    case CK_C3:
1977    case CK_i586:
1978    case CK_Pentium:
1979    case CK_PentiumMMX:
1980    case CK_i686:
1981    case CK_PentiumPro:
1982    case CK_Pentium2:
1983    case CK_Pentium3:
1984    case CK_Pentium3M:
1985    case CK_PentiumM:
1986    case CK_Yonah:
1987    case CK_C3_2:
1988    case CK_Pentium4:
1989    case CK_Pentium4M:
1990    case CK_Prescott:
1991    case CK_K6:
1992    case CK_K6_2:
1993    case CK_K6_3:
1994    case CK_Athlon:
1995    case CK_AthlonThunderbird:
1996    case CK_Athlon4:
1997    case CK_AthlonXP:
1998    case CK_AthlonMP:
1999    case CK_Geode:
2000      // Only accept certain architectures when compiling in 32-bit mode.
2001      if (getTriple().getArch() != llvm::Triple::x86)
2002        return false;
2003
2004      // Fallthrough
2005    case CK_Nocona:
2006    case CK_Core2:
2007    case CK_Penryn:
2008    case CK_Atom:
2009    case CK_Corei7:
2010    case CK_Corei7AVX:
2011    case CK_CoreAVXi:
2012    case CK_CoreAVX2:
2013    case CK_Athlon64:
2014    case CK_Athlon64SSE3:
2015    case CK_AthlonFX:
2016    case CK_K8:
2017    case CK_K8SSE3:
2018    case CK_Opteron:
2019    case CK_OpteronSSE3:
2020    case CK_AMDFAM10:
2021    case CK_BTVER1:
2022    case CK_BTVER2:
2023    case CK_BDVER1:
2024    case CK_BDVER2:
2025    case CK_x86_64:
2026      return true;
2027    }
2028    llvm_unreachable("Unhandled CPU kind");
2029  }
2030
2031  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2032    // We accept all non-ARM calling conventions
2033    return (CC == CC_X86ThisCall ||
2034            CC == CC_X86FastCall ||
2035            CC == CC_X86StdCall ||
2036            CC == CC_C ||
2037            CC == CC_X86Pascal ||
2038            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2039  }
2040
2041  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2042    return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2043  }
2044};
2045
2046void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2047  // FIXME: This should not be here.
2048  Features["3dnow"] = false;
2049  Features["3dnowa"] = false;
2050  Features["mmx"] = false;
2051  Features["sse"] = false;
2052  Features["sse2"] = false;
2053  Features["sse3"] = false;
2054  Features["ssse3"] = false;
2055  Features["sse41"] = false;
2056  Features["sse42"] = false;
2057  Features["sse4a"] = false;
2058  Features["aes"] = false;
2059  Features["pclmul"] = false;
2060  Features["avx"] = false;
2061  Features["avx2"] = false;
2062  Features["lzcnt"] = false;
2063  Features["rdrand"] = false;
2064  Features["bmi"] = false;
2065  Features["bmi2"] = false;
2066  Features["popcnt"] = false;
2067  Features["rtm"] = false;
2068  Features["prfchw"] = false;
2069  Features["rdseed"] = false;
2070  Features["fma4"] = false;
2071  Features["fma"] = false;
2072  Features["xop"] = false;
2073  Features["f16c"] = false;
2074
2075  // FIXME: This *really* should not be here.
2076
2077  // X86_64 always has SSE2.
2078  if (getTriple().getArch() == llvm::Triple::x86_64)
2079    setFeatureEnabled(Features, "sse2", true);
2080
2081  switch (CPU) {
2082  case CK_Generic:
2083  case CK_i386:
2084  case CK_i486:
2085  case CK_i586:
2086  case CK_Pentium:
2087  case CK_i686:
2088  case CK_PentiumPro:
2089    break;
2090  case CK_PentiumMMX:
2091  case CK_Pentium2:
2092    setFeatureEnabled(Features, "mmx", true);
2093    break;
2094  case CK_Pentium3:
2095  case CK_Pentium3M:
2096    setFeatureEnabled(Features, "sse", true);
2097    break;
2098  case CK_PentiumM:
2099  case CK_Pentium4:
2100  case CK_Pentium4M:
2101  case CK_x86_64:
2102    setFeatureEnabled(Features, "sse2", true);
2103    break;
2104  case CK_Yonah:
2105  case CK_Prescott:
2106  case CK_Nocona:
2107    setFeatureEnabled(Features, "sse3", true);
2108    break;
2109  case CK_Core2:
2110    setFeatureEnabled(Features, "ssse3", true);
2111    break;
2112  case CK_Penryn:
2113    setFeatureEnabled(Features, "sse4.1", true);
2114    break;
2115  case CK_Atom:
2116    setFeatureEnabled(Features, "ssse3", true);
2117    break;
2118  case CK_Corei7:
2119    setFeatureEnabled(Features, "sse4", true);
2120    break;
2121  case CK_Corei7AVX:
2122    setFeatureEnabled(Features, "avx", true);
2123    setFeatureEnabled(Features, "aes", true);
2124    setFeatureEnabled(Features, "pclmul", true);
2125    break;
2126  case CK_CoreAVXi:
2127    setFeatureEnabled(Features, "avx", true);
2128    setFeatureEnabled(Features, "aes", true);
2129    setFeatureEnabled(Features, "pclmul", true);
2130    setFeatureEnabled(Features, "rdrnd", true);
2131    setFeatureEnabled(Features, "f16c", true);
2132    break;
2133  case CK_CoreAVX2:
2134    setFeatureEnabled(Features, "avx2", true);
2135    setFeatureEnabled(Features, "aes", true);
2136    setFeatureEnabled(Features, "pclmul", true);
2137    setFeatureEnabled(Features, "lzcnt", true);
2138    setFeatureEnabled(Features, "rdrnd", true);
2139    setFeatureEnabled(Features, "f16c", true);
2140    setFeatureEnabled(Features, "bmi", true);
2141    setFeatureEnabled(Features, "bmi2", true);
2142    setFeatureEnabled(Features, "rtm", true);
2143    setFeatureEnabled(Features, "fma", true);
2144    break;
2145  case CK_K6:
2146  case CK_WinChipC6:
2147    setFeatureEnabled(Features, "mmx", true);
2148    break;
2149  case CK_K6_2:
2150  case CK_K6_3:
2151  case CK_WinChip2:
2152  case CK_C3:
2153    setFeatureEnabled(Features, "3dnow", true);
2154    break;
2155  case CK_Athlon:
2156  case CK_AthlonThunderbird:
2157  case CK_Geode:
2158    setFeatureEnabled(Features, "3dnowa", true);
2159    break;
2160  case CK_Athlon4:
2161  case CK_AthlonXP:
2162  case CK_AthlonMP:
2163    setFeatureEnabled(Features, "sse", true);
2164    setFeatureEnabled(Features, "3dnowa", true);
2165    break;
2166  case CK_K8:
2167  case CK_Opteron:
2168  case CK_Athlon64:
2169  case CK_AthlonFX:
2170    setFeatureEnabled(Features, "sse2", true);
2171    setFeatureEnabled(Features, "3dnowa", true);
2172    break;
2173  case CK_K8SSE3:
2174  case CK_OpteronSSE3:
2175  case CK_Athlon64SSE3:
2176    setFeatureEnabled(Features, "sse3", true);
2177    setFeatureEnabled(Features, "3dnowa", true);
2178    break;
2179  case CK_AMDFAM10:
2180    setFeatureEnabled(Features, "sse3", true);
2181    setFeatureEnabled(Features, "sse4a", true);
2182    setFeatureEnabled(Features, "3dnowa", true);
2183    setFeatureEnabled(Features, "lzcnt", true);
2184    setFeatureEnabled(Features, "popcnt", true);
2185    break;
2186  case CK_BTVER1:
2187    setFeatureEnabled(Features, "ssse3", true);
2188    setFeatureEnabled(Features, "sse4a", true);
2189    setFeatureEnabled(Features, "lzcnt", true);
2190    setFeatureEnabled(Features, "popcnt", true);
2191    break;
2192  case CK_BTVER2:
2193    setFeatureEnabled(Features, "avx", true);
2194    setFeatureEnabled(Features, "sse4a", true);
2195    setFeatureEnabled(Features, "lzcnt", true);
2196    setFeatureEnabled(Features, "aes", true);
2197    setFeatureEnabled(Features, "pclmul", true);
2198    setFeatureEnabled(Features, "bmi", true);
2199    setFeatureEnabled(Features, "f16c", true);
2200    break;
2201  case CK_BDVER1:
2202    setFeatureEnabled(Features, "xop", true);
2203    setFeatureEnabled(Features, "lzcnt", true);
2204    setFeatureEnabled(Features, "aes", true);
2205    setFeatureEnabled(Features, "pclmul", true);
2206    break;
2207  case CK_BDVER2:
2208    setFeatureEnabled(Features, "xop", true);
2209    setFeatureEnabled(Features, "lzcnt", true);
2210    setFeatureEnabled(Features, "aes", true);
2211    setFeatureEnabled(Features, "pclmul", true);
2212    setFeatureEnabled(Features, "bmi", true);
2213    setFeatureEnabled(Features, "fma", true);
2214    setFeatureEnabled(Features, "f16c", true);
2215    break;
2216  case CK_C3_2:
2217    setFeatureEnabled(Features, "sse", true);
2218    break;
2219  }
2220}
2221
2222bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2223                                      StringRef Name,
2224                                      bool Enabled) const {
2225  // FIXME: This *really* should not be here.  We need some way of translating
2226  // options into llvm subtarget features.
2227  if (!Features.count(Name) &&
2228      (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2229       Name != "rdrnd"))
2230    return false;
2231
2232  // FIXME: this should probably use a switch with fall through.
2233
2234  if (Enabled) {
2235    if (Name == "mmx")
2236      Features["mmx"] = true;
2237    else if (Name == "sse")
2238      Features["mmx"] = Features["sse"] = true;
2239    else if (Name == "sse2")
2240      Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2241    else if (Name == "sse3")
2242      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2243        true;
2244    else if (Name == "ssse3")
2245      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2246        Features["ssse3"] = true;
2247    else if (Name == "sse4" || Name == "sse4.2")
2248      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2249        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2250        Features["popcnt"] = true;
2251    else if (Name == "sse4.1")
2252      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2253        Features["ssse3"] = Features["sse41"] = true;
2254    else if (Name == "3dnow")
2255      Features["mmx"] = Features["3dnow"] = true;
2256    else if (Name == "3dnowa")
2257      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2258    else if (Name == "aes")
2259      Features["sse"] = Features["sse2"] = Features["aes"] = true;
2260    else if (Name == "pclmul")
2261      Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2262    else if (Name == "avx")
2263      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2264        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2265        Features["popcnt"] = Features["avx"] = true;
2266    else if (Name == "avx2")
2267      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2268        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2269        Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2270    else if (Name == "fma")
2271      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2272        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2273        Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2274    else if (Name == "fma4")
2275      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2276        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2277        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2278        Features["fma4"] = true;
2279    else if (Name == "xop")
2280      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2281        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2282        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2283        Features["fma4"] = Features["xop"] = true;
2284    else if (Name == "sse4a")
2285      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2286        Features["sse4a"] = true;
2287    else if (Name == "lzcnt")
2288      Features["lzcnt"] = true;
2289    else if (Name == "rdrnd")
2290      Features["rdrand"] = true;
2291    else if (Name == "bmi")
2292      Features["bmi"] = true;
2293    else if (Name == "bmi2")
2294      Features["bmi2"] = true;
2295    else if (Name == "popcnt")
2296      Features["popcnt"] = true;
2297    else if (Name == "f16c")
2298      Features["f16c"] = true;
2299    else if (Name == "rtm")
2300      Features["rtm"] = true;
2301    else if (Name == "prfchw")
2302      Features["prfchw"] = true;
2303    else if (Name == "rdseed")
2304      Features["rdseed"] = true;
2305  } else {
2306    if (Name == "mmx")
2307      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2308    else if (Name == "sse")
2309      Features["sse"] = Features["sse2"] = Features["sse3"] =
2310        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2311        Features["sse4a"] = Features["avx"] = Features["avx2"] =
2312        Features["fma"] = Features["fma4"] = Features["aes"] =
2313        Features["pclmul"] = Features["xop"] = false;
2314    else if (Name == "sse2")
2315      Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2316        Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2317        Features["avx"] = Features["avx2"] = Features["fma"] =
2318        Features["fma4"] = Features["aes"] = Features["pclmul"] =
2319        Features["xop"] = false;
2320    else if (Name == "sse3")
2321      Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2322        Features["sse42"] = Features["sse4a"] = Features["avx"] =
2323        Features["avx2"] = Features["fma"] = Features["fma4"] =
2324        Features["xop"] = false;
2325    else if (Name == "ssse3")
2326      Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2327        Features["avx"] = Features["avx2"] = Features["fma"] = false;
2328    else if (Name == "sse4" || Name == "sse4.1")
2329      Features["sse41"] = Features["sse42"] = Features["avx"] =
2330        Features["avx2"] = Features["fma"] = false;
2331    else if (Name == "sse4.2")
2332      Features["sse42"] = Features["avx"] = Features["avx2"] =
2333        Features["fma"] = false;
2334    else if (Name == "3dnow")
2335      Features["3dnow"] = Features["3dnowa"] = false;
2336    else if (Name == "3dnowa")
2337      Features["3dnowa"] = false;
2338    else if (Name == "aes")
2339      Features["aes"] = false;
2340    else if (Name == "pclmul")
2341      Features["pclmul"] = false;
2342    else if (Name == "avx")
2343      Features["avx"] = Features["avx2"] = Features["fma"] =
2344        Features["fma4"] = Features["xop"] = false;
2345    else if (Name == "avx2")
2346      Features["avx2"] = false;
2347    else if (Name == "fma")
2348      Features["fma"] = false;
2349    else if (Name == "sse4a")
2350      Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2351    else if (Name == "lzcnt")
2352      Features["lzcnt"] = false;
2353    else if (Name == "rdrnd")
2354      Features["rdrand"] = false;
2355    else if (Name == "bmi")
2356      Features["bmi"] = false;
2357    else if (Name == "bmi2")
2358      Features["bmi2"] = false;
2359    else if (Name == "popcnt")
2360      Features["popcnt"] = false;
2361    else if (Name == "fma4")
2362      Features["fma4"] = Features["xop"] = false;
2363    else if (Name == "xop")
2364      Features["xop"] = false;
2365    else if (Name == "f16c")
2366      Features["f16c"] = false;
2367    else if (Name == "rtm")
2368      Features["rtm"] = false;
2369    else if (Name == "prfchw")
2370      Features["prfchw"] = false;
2371    else if (Name == "rdseed")
2372      Features["rdseed"] = false;
2373  }
2374
2375  return true;
2376}
2377
2378/// HandleTargetOptions - Perform initialization based on the user
2379/// configured set of features.
2380void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2381  // Remember the maximum enabled sselevel.
2382  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2383    // Ignore disabled features.
2384    if (Features[i][0] == '-')
2385      continue;
2386
2387    StringRef Feature = StringRef(Features[i]).substr(1);
2388
2389    if (Feature == "aes") {
2390      HasAES = true;
2391      continue;
2392    }
2393
2394    if (Feature == "pclmul") {
2395      HasPCLMUL = true;
2396      continue;
2397    }
2398
2399    if (Feature == "lzcnt") {
2400      HasLZCNT = true;
2401      continue;
2402    }
2403
2404    if (Feature == "rdrand") {
2405      HasRDRND = true;
2406      continue;
2407    }
2408
2409    if (Feature == "bmi") {
2410      HasBMI = true;
2411      continue;
2412    }
2413
2414    if (Feature == "bmi2") {
2415      HasBMI2 = true;
2416      continue;
2417    }
2418
2419    if (Feature == "popcnt") {
2420      HasPOPCNT = true;
2421      continue;
2422    }
2423
2424    if (Feature == "rtm") {
2425      HasRTM = true;
2426      continue;
2427    }
2428
2429    if (Feature == "prfchw") {
2430      HasPRFCHW = true;
2431      continue;
2432    }
2433
2434    if (Feature == "rdseed") {
2435      HasRDSEED = true;
2436      continue;
2437    }
2438
2439    if (Feature == "sse4a") {
2440      HasSSE4a = true;
2441      continue;
2442    }
2443
2444    if (Feature == "fma4") {
2445      HasFMA4 = true;
2446      continue;
2447    }
2448
2449    if (Feature == "fma") {
2450      HasFMA = true;
2451      continue;
2452    }
2453
2454    if (Feature == "xop") {
2455      HasXOP = true;
2456      continue;
2457    }
2458
2459    if (Feature == "f16c") {
2460      HasF16C = true;
2461      continue;
2462    }
2463
2464    assert(Features[i][0] == '+' && "Invalid target feature!");
2465    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2466      .Case("avx2", AVX2)
2467      .Case("avx", AVX)
2468      .Case("sse42", SSE42)
2469      .Case("sse41", SSE41)
2470      .Case("ssse3", SSSE3)
2471      .Case("sse3", SSE3)
2472      .Case("sse2", SSE2)
2473      .Case("sse", SSE1)
2474      .Default(NoSSE);
2475    SSELevel = std::max(SSELevel, Level);
2476
2477    MMX3DNowEnum ThreeDNowLevel =
2478      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2479        .Case("3dnowa", AMD3DNowAthlon)
2480        .Case("3dnow", AMD3DNow)
2481        .Case("mmx", MMX)
2482        .Default(NoMMX3DNow);
2483
2484    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2485  }
2486
2487  // Don't tell the backend if we're turning off mmx; it will end up disabling
2488  // SSE, which we don't want.
2489  std::vector<std::string>::iterator it;
2490  it = std::find(Features.begin(), Features.end(), "-mmx");
2491  if (it != Features.end())
2492    Features.erase(it);
2493}
2494
2495/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2496/// definitions for this particular subtarget.
2497void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2498                                     MacroBuilder &Builder) const {
2499  // Target identification.
2500  if (getTriple().getArch() == llvm::Triple::x86_64) {
2501    Builder.defineMacro("__amd64__");
2502    Builder.defineMacro("__amd64");
2503    Builder.defineMacro("__x86_64");
2504    Builder.defineMacro("__x86_64__");
2505  } else {
2506    DefineStd(Builder, "i386", Opts);
2507  }
2508
2509  // Subtarget options.
2510  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2511  // truly should be based on -mtune options.
2512  switch (CPU) {
2513  case CK_Generic:
2514    break;
2515  case CK_i386:
2516    // The rest are coming from the i386 define above.
2517    Builder.defineMacro("__tune_i386__");
2518    break;
2519  case CK_i486:
2520  case CK_WinChipC6:
2521  case CK_WinChip2:
2522  case CK_C3:
2523    defineCPUMacros(Builder, "i486");
2524    break;
2525  case CK_PentiumMMX:
2526    Builder.defineMacro("__pentium_mmx__");
2527    Builder.defineMacro("__tune_pentium_mmx__");
2528    // Fallthrough
2529  case CK_i586:
2530  case CK_Pentium:
2531    defineCPUMacros(Builder, "i586");
2532    defineCPUMacros(Builder, "pentium");
2533    break;
2534  case CK_Pentium3:
2535  case CK_Pentium3M:
2536  case CK_PentiumM:
2537    Builder.defineMacro("__tune_pentium3__");
2538    // Fallthrough
2539  case CK_Pentium2:
2540  case CK_C3_2:
2541    Builder.defineMacro("__tune_pentium2__");
2542    // Fallthrough
2543  case CK_PentiumPro:
2544    Builder.defineMacro("__tune_i686__");
2545    Builder.defineMacro("__tune_pentiumpro__");
2546    // Fallthrough
2547  case CK_i686:
2548    Builder.defineMacro("__i686");
2549    Builder.defineMacro("__i686__");
2550    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2551    Builder.defineMacro("__pentiumpro");
2552    Builder.defineMacro("__pentiumpro__");
2553    break;
2554  case CK_Pentium4:
2555  case CK_Pentium4M:
2556    defineCPUMacros(Builder, "pentium4");
2557    break;
2558  case CK_Yonah:
2559  case CK_Prescott:
2560  case CK_Nocona:
2561    defineCPUMacros(Builder, "nocona");
2562    break;
2563  case CK_Core2:
2564  case CK_Penryn:
2565    defineCPUMacros(Builder, "core2");
2566    break;
2567  case CK_Atom:
2568    defineCPUMacros(Builder, "atom");
2569    break;
2570  case CK_Corei7:
2571  case CK_Corei7AVX:
2572  case CK_CoreAVXi:
2573  case CK_CoreAVX2:
2574    defineCPUMacros(Builder, "corei7");
2575    break;
2576  case CK_K6_2:
2577    Builder.defineMacro("__k6_2__");
2578    Builder.defineMacro("__tune_k6_2__");
2579    // Fallthrough
2580  case CK_K6_3:
2581    if (CPU != CK_K6_2) {  // In case of fallthrough
2582      // FIXME: GCC may be enabling these in cases where some other k6
2583      // architecture is specified but -m3dnow is explicitly provided. The
2584      // exact semantics need to be determined and emulated here.
2585      Builder.defineMacro("__k6_3__");
2586      Builder.defineMacro("__tune_k6_3__");
2587    }
2588    // Fallthrough
2589  case CK_K6:
2590    defineCPUMacros(Builder, "k6");
2591    break;
2592  case CK_Athlon:
2593  case CK_AthlonThunderbird:
2594  case CK_Athlon4:
2595  case CK_AthlonXP:
2596  case CK_AthlonMP:
2597    defineCPUMacros(Builder, "athlon");
2598    if (SSELevel != NoSSE) {
2599      Builder.defineMacro("__athlon_sse__");
2600      Builder.defineMacro("__tune_athlon_sse__");
2601    }
2602    break;
2603  case CK_K8:
2604  case CK_K8SSE3:
2605  case CK_x86_64:
2606  case CK_Opteron:
2607  case CK_OpteronSSE3:
2608  case CK_Athlon64:
2609  case CK_Athlon64SSE3:
2610  case CK_AthlonFX:
2611    defineCPUMacros(Builder, "k8");
2612    break;
2613  case CK_AMDFAM10:
2614    defineCPUMacros(Builder, "amdfam10");
2615    break;
2616  case CK_BTVER1:
2617    defineCPUMacros(Builder, "btver1");
2618    break;
2619  case CK_BTVER2:
2620    defineCPUMacros(Builder, "btver2");
2621    break;
2622  case CK_BDVER1:
2623    defineCPUMacros(Builder, "bdver1");
2624    break;
2625  case CK_BDVER2:
2626    defineCPUMacros(Builder, "bdver2");
2627    break;
2628  case CK_Geode:
2629    defineCPUMacros(Builder, "geode");
2630    break;
2631  }
2632
2633  // Target properties.
2634  Builder.defineMacro("__LITTLE_ENDIAN__");
2635  Builder.defineMacro("__REGISTER_PREFIX__", "");
2636
2637  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2638  // functions in glibc header files that use FP Stack inline asm which the
2639  // backend can't deal with (PR879).
2640  Builder.defineMacro("__NO_MATH_INLINES");
2641
2642  if (HasAES)
2643    Builder.defineMacro("__AES__");
2644
2645  if (HasPCLMUL)
2646    Builder.defineMacro("__PCLMUL__");
2647
2648  if (HasLZCNT)
2649    Builder.defineMacro("__LZCNT__");
2650
2651  if (HasRDRND)
2652    Builder.defineMacro("__RDRND__");
2653
2654  if (HasBMI)
2655    Builder.defineMacro("__BMI__");
2656
2657  if (HasBMI2)
2658    Builder.defineMacro("__BMI2__");
2659
2660  if (HasPOPCNT)
2661    Builder.defineMacro("__POPCNT__");
2662
2663  if (HasRTM)
2664    Builder.defineMacro("__RTM__");
2665
2666  if (HasPRFCHW)
2667    Builder.defineMacro("__PRFCHW__");
2668
2669  if (HasRDSEED)
2670    Builder.defineMacro("__RDSEED__");
2671
2672  if (HasSSE4a)
2673    Builder.defineMacro("__SSE4A__");
2674
2675  if (HasFMA4)
2676    Builder.defineMacro("__FMA4__");
2677
2678  if (HasFMA)
2679    Builder.defineMacro("__FMA__");
2680
2681  if (HasXOP)
2682    Builder.defineMacro("__XOP__");
2683
2684  if (HasF16C)
2685    Builder.defineMacro("__F16C__");
2686
2687  // Each case falls through to the previous one here.
2688  switch (SSELevel) {
2689  case AVX2:
2690    Builder.defineMacro("__AVX2__");
2691  case AVX:
2692    Builder.defineMacro("__AVX__");
2693  case SSE42:
2694    Builder.defineMacro("__SSE4_2__");
2695  case SSE41:
2696    Builder.defineMacro("__SSE4_1__");
2697  case SSSE3:
2698    Builder.defineMacro("__SSSE3__");
2699  case SSE3:
2700    Builder.defineMacro("__SSE3__");
2701  case SSE2:
2702    Builder.defineMacro("__SSE2__");
2703    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2704  case SSE1:
2705    Builder.defineMacro("__SSE__");
2706    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2707  case NoSSE:
2708    break;
2709  }
2710
2711  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2712    switch (SSELevel) {
2713    case AVX2:
2714    case AVX:
2715    case SSE42:
2716    case SSE41:
2717    case SSSE3:
2718    case SSE3:
2719    case SSE2:
2720      Builder.defineMacro("_M_IX86_FP", Twine(2));
2721      break;
2722    case SSE1:
2723      Builder.defineMacro("_M_IX86_FP", Twine(1));
2724      break;
2725    default:
2726      Builder.defineMacro("_M_IX86_FP", Twine(0));
2727    }
2728  }
2729
2730  // Each case falls through to the previous one here.
2731  switch (MMX3DNowLevel) {
2732  case AMD3DNowAthlon:
2733    Builder.defineMacro("__3dNOW_A__");
2734  case AMD3DNow:
2735    Builder.defineMacro("__3dNOW__");
2736  case MMX:
2737    Builder.defineMacro("__MMX__");
2738  case NoMMX3DNow:
2739    break;
2740  }
2741
2742  if (CPU >= CK_i486) {
2743    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2744    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2745    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2746  }
2747  if (CPU >= CK_i586)
2748    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2749}
2750
2751bool X86TargetInfo::hasFeature(StringRef Feature) const {
2752  return llvm::StringSwitch<bool>(Feature)
2753      .Case("aes", HasAES)
2754      .Case("avx", SSELevel >= AVX)
2755      .Case("avx2", SSELevel >= AVX2)
2756      .Case("bmi", HasBMI)
2757      .Case("bmi2", HasBMI2)
2758      .Case("fma", HasFMA)
2759      .Case("fma4", HasFMA4)
2760      .Case("lzcnt", HasLZCNT)
2761      .Case("rdrnd", HasRDRND)
2762      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2763      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2764      .Case("mmx", MMX3DNowLevel >= MMX)
2765      .Case("pclmul", HasPCLMUL)
2766      .Case("popcnt", HasPOPCNT)
2767      .Case("rtm", HasRTM)
2768      .Case("prfchw", HasPRFCHW)
2769      .Case("rdseed", HasRDSEED)
2770      .Case("sse", SSELevel >= SSE1)
2771      .Case("sse2", SSELevel >= SSE2)
2772      .Case("sse3", SSELevel >= SSE3)
2773      .Case("ssse3", SSELevel >= SSSE3)
2774      .Case("sse41", SSELevel >= SSE41)
2775      .Case("sse42", SSELevel >= SSE42)
2776      .Case("sse4a", HasSSE4a)
2777      .Case("x86", true)
2778      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2779      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2780      .Case("xop", HasXOP)
2781      .Case("f16c", HasF16C)
2782      .Default(false);
2783}
2784
2785bool
2786X86TargetInfo::validateAsmConstraint(const char *&Name,
2787                                     TargetInfo::ConstraintInfo &Info) const {
2788  switch (*Name) {
2789  default: return false;
2790  case 'Y': // first letter of a pair:
2791    switch (*(Name+1)) {
2792    default: return false;
2793    case '0':  // First SSE register.
2794    case 't':  // Any SSE register, when SSE2 is enabled.
2795    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2796    case 'm':  // any MMX register, when inter-unit moves enabled.
2797      break;   // falls through to setAllowsRegister.
2798  }
2799  case 'a': // eax.
2800  case 'b': // ebx.
2801  case 'c': // ecx.
2802  case 'd': // edx.
2803  case 'S': // esi.
2804  case 'D': // edi.
2805  case 'A': // edx:eax.
2806  case 'f': // any x87 floating point stack register.
2807  case 't': // top of floating point stack.
2808  case 'u': // second from top of floating point stack.
2809  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2810  case 'y': // Any MMX register.
2811  case 'x': // Any SSE register.
2812  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2813  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2814  case 'l': // "Index" registers: any general register that can be used as an
2815            // index in a base+index memory access.
2816    Info.setAllowsRegister();
2817    return true;
2818  case 'C': // SSE floating point constant.
2819  case 'G': // x87 floating point constant.
2820  case 'e': // 32-bit signed integer constant for use with zero-extending
2821            // x86_64 instructions.
2822  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2823            // x86_64 instructions.
2824    return true;
2825  }
2826}
2827
2828
2829std::string
2830X86TargetInfo::convertConstraint(const char *&Constraint) const {
2831  switch (*Constraint) {
2832  case 'a': return std::string("{ax}");
2833  case 'b': return std::string("{bx}");
2834  case 'c': return std::string("{cx}");
2835  case 'd': return std::string("{dx}");
2836  case 'S': return std::string("{si}");
2837  case 'D': return std::string("{di}");
2838  case 'p': // address
2839    return std::string("im");
2840  case 't': // top of floating point stack.
2841    return std::string("{st}");
2842  case 'u': // second from top of floating point stack.
2843    return std::string("{st(1)}"); // second from top of floating point stack.
2844  default:
2845    return std::string(1, *Constraint);
2846  }
2847}
2848} // end anonymous namespace
2849
2850namespace {
2851// X86-32 generic target
2852class X86_32TargetInfo : public X86TargetInfo {
2853public:
2854  X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
2855    DoubleAlign = LongLongAlign = 32;
2856    LongDoubleWidth = 96;
2857    LongDoubleAlign = 32;
2858    SuitableAlign = 128;
2859    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2860                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2861                        "a0:0:64-f80:32:32-n8:16:32-S128";
2862    SizeType = UnsignedInt;
2863    PtrDiffType = SignedInt;
2864    IntPtrType = SignedInt;
2865    RegParmMax = 3;
2866
2867    // Use fpret for all types.
2868    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2869                             (1 << TargetInfo::Double) |
2870                             (1 << TargetInfo::LongDouble));
2871
2872    // x86-32 has atomics up to 8 bytes
2873    // FIXME: Check that we actually have cmpxchg8b before setting
2874    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2875    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2876  }
2877  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2878    return TargetInfo::CharPtrBuiltinVaList;
2879  }
2880
2881  int getEHDataRegisterNumber(unsigned RegNo) const {
2882    if (RegNo == 0) return 0;
2883    if (RegNo == 1) return 2;
2884    return -1;
2885  }
2886  virtual bool validateInputSize(StringRef Constraint,
2887                                 unsigned Size) const {
2888    switch (Constraint[0]) {
2889    default: break;
2890    case 'a':
2891    case 'b':
2892    case 'c':
2893    case 'd':
2894      return Size <= 32;
2895    }
2896
2897    return true;
2898  }
2899};
2900} // end anonymous namespace
2901
2902namespace {
2903class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2904public:
2905  NetBSDI386TargetInfo(const llvm::Triple &Triple)
2906      : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
2907
2908  virtual unsigned getFloatEvalMethod() const {
2909    // NetBSD defaults to "double" rounding
2910    return 1;
2911  }
2912};
2913} // end anonymous namespace
2914
2915namespace {
2916class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2917public:
2918  OpenBSDI386TargetInfo(const llvm::Triple &Triple)
2919      : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
2920    SizeType = UnsignedLong;
2921    IntPtrType = SignedLong;
2922    PtrDiffType = SignedLong;
2923  }
2924};
2925} // end anonymous namespace
2926
2927namespace {
2928class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2929public:
2930  BitrigI386TargetInfo(const llvm::Triple &Triple)
2931      : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
2932    SizeType = UnsignedLong;
2933    IntPtrType = SignedLong;
2934    PtrDiffType = SignedLong;
2935  }
2936};
2937} // end anonymous namespace
2938
2939namespace {
2940class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2941public:
2942  DarwinI386TargetInfo(const llvm::Triple &Triple)
2943      : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
2944    LongDoubleWidth = 128;
2945    LongDoubleAlign = 128;
2946    SuitableAlign = 128;
2947    MaxVectorAlign = 256;
2948    SizeType = UnsignedLong;
2949    IntPtrType = SignedLong;
2950    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2951                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2952                        "a0:0:64-f80:128:128-n8:16:32-S128";
2953    HasAlignMac68kSupport = true;
2954  }
2955
2956};
2957} // end anonymous namespace
2958
2959namespace {
2960// x86-32 Windows target
2961class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2962public:
2963  WindowsX86_32TargetInfo(const llvm::Triple &Triple)
2964      : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
2965    TLSSupported = false;
2966    WCharType = UnsignedShort;
2967    DoubleAlign = LongLongAlign = 64;
2968    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2969                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2970                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2971  }
2972  virtual void getTargetDefines(const LangOptions &Opts,
2973                                MacroBuilder &Builder) const {
2974    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2975  }
2976};
2977} // end anonymous namespace
2978
2979namespace {
2980
2981// x86-32 Windows Visual Studio target
2982class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2983public:
2984  VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple)
2985      : WindowsX86_32TargetInfo(Triple) {
2986    LongDoubleWidth = LongDoubleAlign = 64;
2987    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2988  }
2989  virtual void getTargetDefines(const LangOptions &Opts,
2990                                MacroBuilder &Builder) const {
2991    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2992    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2993    // The value of the following reflects processor type.
2994    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2995    // We lost the original triple, so we use the default.
2996    Builder.defineMacro("_M_IX86", "600");
2997  }
2998};
2999} // end anonymous namespace
3000
3001namespace {
3002// x86-32 MinGW target
3003class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3004public:
3005  MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3006      : WindowsX86_32TargetInfo(Triple) {}
3007  virtual void getTargetDefines(const LangOptions &Opts,
3008                                MacroBuilder &Builder) const {
3009    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3010    DefineStd(Builder, "WIN32", Opts);
3011    DefineStd(Builder, "WINNT", Opts);
3012    Builder.defineMacro("_X86_");
3013    Builder.defineMacro("__MSVCRT__");
3014    Builder.defineMacro("__MINGW32__");
3015
3016    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3017    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3018    if (Opts.MicrosoftExt)
3019      // Provide "as-is" __declspec.
3020      Builder.defineMacro("__declspec", "__declspec");
3021    else
3022      // Provide alias of __attribute__ like mingw32-gcc.
3023      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3024  }
3025};
3026} // end anonymous namespace
3027
3028namespace {
3029// x86-32 Cygwin target
3030class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3031public:
3032  CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3033      : X86_32TargetInfo(Triple) {
3034    TLSSupported = false;
3035    WCharType = UnsignedShort;
3036    DoubleAlign = LongLongAlign = 64;
3037    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3038                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3039                        "a0:0:64-f80:32:32-n8:16:32-S32";
3040  }
3041  virtual void getTargetDefines(const LangOptions &Opts,
3042                                MacroBuilder &Builder) const {
3043    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3044    Builder.defineMacro("_X86_");
3045    Builder.defineMacro("__CYGWIN__");
3046    Builder.defineMacro("__CYGWIN32__");
3047    DefineStd(Builder, "unix", Opts);
3048    if (Opts.CPlusPlus)
3049      Builder.defineMacro("_GNU_SOURCE");
3050  }
3051};
3052} // end anonymous namespace
3053
3054namespace {
3055// x86-32 Haiku target
3056class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3057public:
3058  HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3059    SizeType = UnsignedLong;
3060    IntPtrType = SignedLong;
3061    PtrDiffType = SignedLong;
3062    ProcessIDType = SignedLong;
3063    this->UserLabelPrefix = "";
3064    this->TLSSupported = false;
3065  }
3066  virtual void getTargetDefines(const LangOptions &Opts,
3067                                MacroBuilder &Builder) const {
3068    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3069    Builder.defineMacro("__INTEL__");
3070    Builder.defineMacro("__HAIKU__");
3071  }
3072};
3073} // end anonymous namespace
3074
3075// RTEMS Target
3076template<typename Target>
3077class RTEMSTargetInfo : public OSTargetInfo<Target> {
3078protected:
3079  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3080                            MacroBuilder &Builder) const {
3081    // RTEMS defines; list based off of gcc output
3082
3083    Builder.defineMacro("__rtems__");
3084    Builder.defineMacro("__ELF__");
3085  }
3086
3087public:
3088  RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3089    this->UserLabelPrefix = "";
3090
3091    switch (Triple.getArch()) {
3092    default:
3093    case llvm::Triple::x86:
3094      // this->MCountName = ".mcount";
3095      break;
3096    case llvm::Triple::mips:
3097    case llvm::Triple::mipsel:
3098    case llvm::Triple::ppc:
3099    case llvm::Triple::ppc64:
3100      // this->MCountName = "_mcount";
3101      break;
3102    case llvm::Triple::arm:
3103      // this->MCountName = "__mcount";
3104      break;
3105    }
3106  }
3107};
3108
3109namespace {
3110// x86-32 RTEMS target
3111class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3112public:
3113  RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3114    SizeType = UnsignedLong;
3115    IntPtrType = SignedLong;
3116    PtrDiffType = SignedLong;
3117    this->UserLabelPrefix = "";
3118  }
3119  virtual void getTargetDefines(const LangOptions &Opts,
3120                                MacroBuilder &Builder) const {
3121    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3122    Builder.defineMacro("__INTEL__");
3123    Builder.defineMacro("__rtems__");
3124  }
3125};
3126} // end anonymous namespace
3127
3128namespace {
3129// x86-64 generic target
3130class X86_64TargetInfo : public X86TargetInfo {
3131public:
3132  X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3133    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3134    LongDoubleWidth = 128;
3135    LongDoubleAlign = 128;
3136    LargeArrayMinWidth = 128;
3137    LargeArrayAlign = 128;
3138    SuitableAlign = 128;
3139    IntMaxType = SignedLong;
3140    UIntMaxType = UnsignedLong;
3141    Int64Type = SignedLong;
3142    RegParmMax = 6;
3143
3144    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3145                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3146                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3147
3148    // Use fpret only for long double.
3149    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3150
3151    // Use fp2ret for _Complex long double.
3152    ComplexLongDoubleUsesFP2Ret = true;
3153
3154    // x86-64 has atomics up to 16 bytes.
3155    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3156    // on CPUs with cmpxchg16b
3157    MaxAtomicPromoteWidth = 128;
3158    MaxAtomicInlineWidth = 64;
3159  }
3160  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3161    return TargetInfo::X86_64ABIBuiltinVaList;
3162  }
3163
3164  int getEHDataRegisterNumber(unsigned RegNo) const {
3165    if (RegNo == 0) return 0;
3166    if (RegNo == 1) return 1;
3167    return -1;
3168  }
3169
3170  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3171    return (CC == CC_Default ||
3172            CC == CC_C ||
3173            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3174  }
3175
3176  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3177    return CC_C;
3178  }
3179
3180};
3181} // end anonymous namespace
3182
3183namespace {
3184// x86-64 Windows target
3185class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3186public:
3187  WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3188      : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3189    TLSSupported = false;
3190    WCharType = UnsignedShort;
3191    LongWidth = LongAlign = 32;
3192    DoubleAlign = LongLongAlign = 64;
3193    IntMaxType = SignedLongLong;
3194    UIntMaxType = UnsignedLongLong;
3195    Int64Type = SignedLongLong;
3196    SizeType = UnsignedLongLong;
3197    PtrDiffType = SignedLongLong;
3198    IntPtrType = SignedLongLong;
3199    this->UserLabelPrefix = "";
3200  }
3201  virtual void getTargetDefines(const LangOptions &Opts,
3202                                MacroBuilder &Builder) const {
3203    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3204    Builder.defineMacro("_WIN64");
3205  }
3206  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3207    return TargetInfo::CharPtrBuiltinVaList;
3208  }
3209};
3210} // end anonymous namespace
3211
3212namespace {
3213// x86-64 Windows Visual Studio target
3214class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3215public:
3216  VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple)
3217      : WindowsX86_64TargetInfo(Triple) {
3218    LongDoubleWidth = LongDoubleAlign = 64;
3219    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3220  }
3221  virtual void getTargetDefines(const LangOptions &Opts,
3222                                MacroBuilder &Builder) const {
3223    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3224    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3225    Builder.defineMacro("_M_X64");
3226    Builder.defineMacro("_M_AMD64");
3227  }
3228};
3229} // end anonymous namespace
3230
3231namespace {
3232// x86-64 MinGW target
3233class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3234public:
3235  MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3236      : WindowsX86_64TargetInfo(Triple) {}
3237  virtual void getTargetDefines(const LangOptions &Opts,
3238                                MacroBuilder &Builder) const {
3239    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3240    DefineStd(Builder, "WIN64", Opts);
3241    Builder.defineMacro("__MSVCRT__");
3242    Builder.defineMacro("__MINGW32__");
3243    Builder.defineMacro("__MINGW64__");
3244
3245    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3246    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3247    if (Opts.MicrosoftExt)
3248      // Provide "as-is" __declspec.
3249      Builder.defineMacro("__declspec", "__declspec");
3250    else
3251      // Provide alias of __attribute__ like mingw32-gcc.
3252      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3253  }
3254};
3255} // end anonymous namespace
3256
3257namespace {
3258class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3259public:
3260  DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3261      : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3262    Int64Type = SignedLongLong;
3263    MaxVectorAlign = 256;
3264  }
3265};
3266} // end anonymous namespace
3267
3268namespace {
3269class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3270public:
3271  OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3272      : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3273    IntMaxType = SignedLongLong;
3274    UIntMaxType = UnsignedLongLong;
3275    Int64Type = SignedLongLong;
3276  }
3277};
3278} // end anonymous namespace
3279
3280namespace {
3281class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3282public:
3283  BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3284      : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3285    IntMaxType = SignedLongLong;
3286    UIntMaxType = UnsignedLongLong;
3287    Int64Type = SignedLongLong;
3288  }
3289};
3290}
3291
3292namespace {
3293class AArch64TargetInfo : public TargetInfo {
3294  static const char * const GCCRegNames[];
3295  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3296
3297  static const Builtin::Info BuiltinInfo[];
3298public:
3299  AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
3300    BigEndian = false;
3301    LongWidth = LongAlign = 64;
3302    LongDoubleWidth = LongDoubleAlign = 128;
3303    PointerWidth = PointerAlign = 64;
3304    SuitableAlign = 128;
3305    DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3306                        "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3307                        "f128:128:128-n32:64-S128";
3308
3309    WCharType = UnsignedInt;
3310    LongDoubleFormat = &llvm::APFloat::IEEEquad;
3311
3312    // AArch64 backend supports 64-bit operations at the moment. In principle
3313    // 128-bit is possible if register-pairs are used.
3314    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3315
3316    TheCXXABI.set(TargetCXXABI::GenericAArch64);
3317  }
3318  virtual void getTargetDefines(const LangOptions &Opts,
3319                                MacroBuilder &Builder) const {
3320    // GCC defines theses currently
3321    Builder.defineMacro("__aarch64__");
3322    Builder.defineMacro("__AARCH64EL__");
3323
3324    // ACLE predefines. Many can only have one possible value on v8 AArch64.
3325
3326    // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3327    // which was intended to be compatible with a 64-bit implementation. They
3328    // will need updating when a real 64-bit ACLE exists. Particularly pressing
3329    // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3330    Builder.defineMacro("__ARM_ACLE",         "101");
3331    Builder.defineMacro("__ARM_ARCH",         "8");
3332    Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3333
3334    Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3335    Builder.defineMacro("__ARM_FEATURE_CLZ");
3336    Builder.defineMacro("__ARM_FEATURE_FMA");
3337
3338    // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3339    // 128-bit LDXP present, at which point this becomes 0x1f.
3340    Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3341
3342    // 0xe implies support for half, single and double precision operations.
3343    Builder.defineMacro("__ARM_FP", "0xe");
3344
3345    // PCS specifies this for SysV variants, which is all we support. Other ABIs
3346    // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3347    Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3348
3349    if (Opts.FastMath || Opts.FiniteMathOnly)
3350      Builder.defineMacro("__ARM_FP_FAST");
3351
3352    if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3353      Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3354
3355    Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3356                        Opts.ShortWChar ? "2" : "4");
3357
3358    Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3359                        Opts.ShortEnums ? "1" : "4");
3360
3361    if (BigEndian)
3362      Builder.defineMacro("__ARM_BIG_ENDIAN");
3363  }
3364  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3365                                 unsigned &NumRecords) const {
3366    Records = BuiltinInfo;
3367    NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3368  }
3369  virtual bool hasFeature(StringRef Feature) const {
3370    return Feature == "aarch64";
3371  }
3372  virtual void getGCCRegNames(const char * const *&Names,
3373                              unsigned &NumNames) const;
3374  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3375                                unsigned &NumAliases) const;
3376
3377  virtual bool isCLZForZeroUndef() const { return false; }
3378
3379  virtual bool validateAsmConstraint(const char *&Name,
3380                                     TargetInfo::ConstraintInfo &Info) const {
3381    switch (*Name) {
3382    default: return false;
3383    case 'w': // An FP/SIMD vector register
3384      Info.setAllowsRegister();
3385      return true;
3386    case 'I': // Constant that can be used with an ADD instruction
3387    case 'J': // Constant that can be used with a SUB instruction
3388    case 'K': // Constant that can be used with a 32-bit logical instruction
3389    case 'L': // Constant that can be used with a 64-bit logical instruction
3390    case 'M': // Constant that can be used as a 32-bit MOV immediate
3391    case 'N': // Constant that can be used as a 64-bit MOV immediate
3392    case 'Y': // Floating point constant zero
3393    case 'Z': // Integer constant zero
3394      return true;
3395    case 'Q': // A memory reference with base register and no offset
3396      Info.setAllowsMemory();
3397      return true;
3398    case 'S': // A symbolic address
3399      Info.setAllowsRegister();
3400      return true;
3401    case 'U':
3402      // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3403      // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3404      // Usa: An absolute symbolic address
3405      // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3406      llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3407    }
3408  }
3409
3410  virtual const char *getClobbers() const {
3411    // There are no AArch64 clobbers shared by all asm statements.
3412    return "";
3413  }
3414
3415  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3416    return TargetInfo::AArch64ABIBuiltinVaList;
3417  }
3418};
3419
3420const char * const AArch64TargetInfo::GCCRegNames[] = {
3421  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3422  "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3423  "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3424  "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3425
3426  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3427  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3428  "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3429  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3430
3431  "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3432  "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3433  "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3434  "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3435
3436  "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3437  "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3438  "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3439  "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3440
3441  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3442  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3443  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3444  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3445
3446  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3447  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3448  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3449  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3450
3451  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3452  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3453  "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3454  "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3455};
3456
3457void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3458                                       unsigned &NumNames) const {
3459  Names = GCCRegNames;
3460  NumNames = llvm::array_lengthof(GCCRegNames);
3461}
3462
3463const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3464  { { "x16" }, "ip0"},
3465  { { "x17" }, "ip1"},
3466  { { "x29" }, "fp" },
3467  { { "x30" }, "lr" }
3468};
3469
3470void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3471                                         unsigned &NumAliases) const {
3472  Aliases = GCCRegAliases;
3473  NumAliases = llvm::array_lengthof(GCCRegAliases);
3474
3475}
3476
3477const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3478#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3479#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3480                                              ALL_LANGUAGES },
3481#include "clang/Basic/BuiltinsAArch64.def"
3482};
3483
3484} // end anonymous namespace
3485
3486namespace {
3487class ARMTargetInfo : public TargetInfo {
3488  // Possible FPU choices.
3489  enum FPUMode {
3490    VFP2FPU = (1 << 0),
3491    VFP3FPU = (1 << 1),
3492    VFP4FPU = (1 << 2),
3493    NeonFPU = (1 << 3)
3494  };
3495
3496  static bool FPUModeIsVFP(FPUMode Mode) {
3497    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3498  }
3499
3500  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3501  static const char * const GCCRegNames[];
3502
3503  std::string ABI, CPU;
3504
3505  unsigned FPU : 4;
3506
3507  unsigned IsAAPCS : 1;
3508  unsigned IsThumb : 1;
3509
3510  // Initialized via features.
3511  unsigned SoftFloat : 1;
3512  unsigned SoftFloatABI : 1;
3513
3514  static const Builtin::Info BuiltinInfo[];
3515
3516  static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3517    // On linux, binaries targeting old cpus call functions in libgcc to
3518    // perform atomic operations. The implementation in libgcc then calls into
3519    // the kernel which on armv6 and newer uses ldrex and strex. The net result
3520    // is that if we assume the kernel is at least as recent as the hardware,
3521    // it is safe to use atomic instructions on armv6 and newer.
3522    if (T.getOS() != llvm::Triple::Linux &&
3523        T.getOS() != llvm::Triple::FreeBSD &&
3524        T.getOS() != llvm::Triple::Bitrig)
3525      return false;
3526    StringRef ArchName = T.getArchName();
3527    if (T.getArch() == llvm::Triple::arm) {
3528      if (!ArchName.startswith("armv"))
3529        return false;
3530      StringRef VersionStr = ArchName.substr(4);
3531      unsigned Version;
3532      if (VersionStr.getAsInteger(10, Version))
3533        return false;
3534      return Version >= 6;
3535    }
3536    assert(T.getArch() == llvm::Triple::thumb);
3537    if (!ArchName.startswith("thumbv"))
3538      return false;
3539    StringRef VersionStr = ArchName.substr(6);
3540    unsigned Version;
3541    if (VersionStr.getAsInteger(10, Version))
3542      return false;
3543    return Version >= 7;
3544  }
3545
3546public:
3547  ARMTargetInfo(const llvm::Triple &Triple)
3548      : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"),
3549        IsAAPCS(true) {
3550    BigEndian = false;
3551    SizeType = UnsignedInt;
3552    PtrDiffType = SignedInt;
3553    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3554    WCharType = UnsignedInt;
3555
3556    // {} in inline assembly are neon specifiers, not assembly variant
3557    // specifiers.
3558    NoAsmVariants = true;
3559
3560    // FIXME: Should we just treat this as a feature?
3561    IsThumb = getTriple().getArchName().startswith("thumb");
3562    if (IsThumb) {
3563      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3564      // so set preferred for small types to 32.
3565      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3566                           "i64:64:64-f32:32:32-f64:64:64-"
3567                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3568    } else {
3569      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3570                           "i64:64:64-f32:32:32-f64:64:64-"
3571                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3572    }
3573
3574    // ARM targets default to using the ARM C++ ABI.
3575    TheCXXABI.set(TargetCXXABI::GenericARM);
3576
3577    // ARM has atomics up to 8 bytes
3578    MaxAtomicPromoteWidth = 64;
3579    if (shouldUseInlineAtomic(getTriple()))
3580      MaxAtomicInlineWidth = 64;
3581
3582    // Do force alignment of members that follow zero length bitfields.  If
3583    // the alignment of the zero-length bitfield is greater than the member
3584    // that follows it, `bar', `bar' will be aligned as the  type of the
3585    // zero length bitfield.
3586    UseZeroLengthBitfieldAlignment = true;
3587  }
3588  virtual const char *getABI() const { return ABI.c_str(); }
3589  virtual bool setABI(const std::string &Name) {
3590    ABI = Name;
3591
3592    // The defaults (above) are for AAPCS, check if we need to change them.
3593    //
3594    // FIXME: We need support for -meabi... we could just mangle it into the
3595    // name.
3596    if (Name == "apcs-gnu") {
3597      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3598      // size_t is unsigned int on FreeBSD.
3599      if (getTriple().getOS() != llvm::Triple::FreeBSD)
3600        SizeType = UnsignedLong;
3601
3602      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3603      WCharType = SignedInt;
3604
3605      // Do not respect the alignment of bit-field types when laying out
3606      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3607      UseBitFieldTypeAlignment = false;
3608
3609      /// gcc forces the alignment to 4 bytes, regardless of the type of the
3610      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3611      /// gcc.
3612      ZeroLengthBitfieldBoundary = 32;
3613
3614      IsAAPCS = false;
3615
3616      if (IsThumb) {
3617        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3618        // so set preferred for small types to 32.
3619        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3620                             "i64:32:64-f32:32:32-f64:32:64-"
3621                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3622      } else {
3623        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3624                             "i64:32:64-f32:32:32-f64:32:64-"
3625                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3626      }
3627
3628      // FIXME: Override "preferred align" for double and long long.
3629    } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3630      // size_t is unsigned long on Darwin.
3631      if (getTriple().isOSDarwin())
3632        SizeType = UnsignedLong;
3633      IsAAPCS = true;
3634      // FIXME: Enumerated types are variable width in straight AAPCS.
3635    } else if (Name == "aapcs-linux") {
3636      IsAAPCS = true;
3637    } else
3638      return false;
3639
3640    return true;
3641  }
3642
3643  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3644    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3645      Features["vfp2"] = true;
3646    else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3647             CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3648      Features["neon"] = true;
3649    else if (CPU == "swift" || CPU == "cortex-a7") {
3650      Features["vfp4"] = true;
3651      Features["neon"] = true;
3652    }
3653  }
3654
3655  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3656                                 StringRef Name,
3657                                 bool Enabled) const {
3658    if (Name == "soft-float" || Name == "soft-float-abi" ||
3659        Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3660        Name == "d16" || Name == "neonfp" || Name == "v8fp") {
3661      Features[Name] = Enabled;
3662    } else
3663      return false;
3664
3665    return true;
3666  }
3667
3668  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3669    FPU = 0;
3670    SoftFloat = SoftFloatABI = false;
3671    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3672      if (Features[i] == "+soft-float")
3673        SoftFloat = true;
3674      else if (Features[i] == "+soft-float-abi")
3675        SoftFloatABI = true;
3676      else if (Features[i] == "+vfp2")
3677        FPU |= VFP2FPU;
3678      else if (Features[i] == "+vfp3")
3679        FPU |= VFP3FPU;
3680      else if (Features[i] == "+vfp4")
3681        FPU |= VFP4FPU;
3682      else if (Features[i] == "+neon")
3683        FPU |= NeonFPU;
3684    }
3685
3686    // Remove front-end specific options which the backend handles differently.
3687    std::vector<std::string>::iterator it;
3688    it = std::find(Features.begin(), Features.end(), "+soft-float");
3689    if (it != Features.end())
3690      Features.erase(it);
3691    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3692    if (it != Features.end())
3693      Features.erase(it);
3694  }
3695
3696  virtual bool hasFeature(StringRef Feature) const {
3697    return llvm::StringSwitch<bool>(Feature)
3698        .Case("arm", true)
3699        .Case("softfloat", SoftFloat)
3700        .Case("thumb", IsThumb)
3701        .Case("neon", FPU == NeonFPU && !SoftFloat &&
3702              StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3703        .Default(false);
3704  }
3705  // FIXME: Should we actually have some table instead of these switches?
3706  static const char *getCPUDefineSuffix(StringRef Name) {
3707    return llvm::StringSwitch<const char*>(Name)
3708      .Cases("arm8", "arm810", "4")
3709      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3710      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3711      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3712      .Case("ep9312", "4T")
3713      .Cases("arm10tdmi", "arm1020t", "5T")
3714      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3715      .Case("arm926ej-s", "5TEJ")
3716      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3717      .Cases("xscale", "iwmmxt", "5TE")
3718      .Case("arm1136j-s", "6J")
3719      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3720      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3721      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3722      .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3723      .Cases("cortex-a9", "cortex-a15", "7A")
3724      .Case("cortex-r5", "7R")
3725      .Case("cortex-a9-mp", "7F")
3726      .Case("swift", "7S")
3727      .Cases("cortex-m3", "cortex-m4", "7M")
3728      .Case("cortex-m0", "6M")
3729      .Case("cortex-a53", "8A")
3730      .Default(0);
3731  }
3732  static const char *getCPUProfile(StringRef Name) {
3733    return llvm::StringSwitch<const char*>(Name)
3734      .Cases("cortex-a8", "cortex-a9", "A")
3735      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3736      .Case("cortex-r5", "R")
3737      .Default("");
3738  }
3739  virtual bool setCPU(const std::string &Name) {
3740    if (!getCPUDefineSuffix(Name))
3741      return false;
3742
3743    CPU = Name;
3744    return true;
3745  }
3746  virtual void getTargetDefines(const LangOptions &Opts,
3747                                MacroBuilder &Builder) const {
3748    // Target identification.
3749    Builder.defineMacro("__arm");
3750    Builder.defineMacro("__arm__");
3751
3752    // Target properties.
3753    Builder.defineMacro("__ARMEL__");
3754    Builder.defineMacro("__LITTLE_ENDIAN__");
3755    Builder.defineMacro("__REGISTER_PREFIX__", "");
3756
3757    StringRef CPUArch = getCPUDefineSuffix(CPU);
3758    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3759    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3760    StringRef CPUProfile = getCPUProfile(CPU);
3761    if (!CPUProfile.empty())
3762      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3763
3764    // Subtarget options.
3765
3766    // FIXME: It's more complicated than this and we don't really support
3767    // interworking.
3768    if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3769      Builder.defineMacro("__THUMB_INTERWORK__");
3770
3771    if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3772      // M-class CPUs on Darwin follow AAPCS, but not EABI.
3773      if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3774        Builder.defineMacro("__ARM_EABI__");
3775      Builder.defineMacro("__ARM_PCS", "1");
3776
3777      if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3778        Builder.defineMacro("__ARM_PCS_VFP", "1");
3779    }
3780
3781    if (SoftFloat)
3782      Builder.defineMacro("__SOFTFP__");
3783
3784    if (CPU == "xscale")
3785      Builder.defineMacro("__XSCALE__");
3786
3787    bool IsARMv7 = CPUArch.startswith("7");
3788    if (IsThumb) {
3789      Builder.defineMacro("__THUMBEL__");
3790      Builder.defineMacro("__thumb__");
3791      if (CPUArch == "6T2" || IsARMv7)
3792        Builder.defineMacro("__thumb2__");
3793    }
3794
3795    // Note, this is always on in gcc, even though it doesn't make sense.
3796    Builder.defineMacro("__APCS_32__");
3797
3798    if (FPUModeIsVFP((FPUMode) FPU)) {
3799      Builder.defineMacro("__VFP_FP__");
3800      if (FPU & VFP2FPU)
3801        Builder.defineMacro("__ARM_VFPV2__");
3802      if (FPU & VFP3FPU)
3803        Builder.defineMacro("__ARM_VFPV3__");
3804      if (FPU & VFP4FPU)
3805        Builder.defineMacro("__ARM_VFPV4__");
3806    }
3807
3808    // This only gets set when Neon instructions are actually available, unlike
3809    // the VFP define, hence the soft float and arch check. This is subtly
3810    // different from gcc, we follow the intent which was that it should be set
3811    // when Neon instructions are actually available.
3812    if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3813      Builder.defineMacro("__ARM_NEON__");
3814  }
3815  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3816                                 unsigned &NumRecords) const {
3817    Records = BuiltinInfo;
3818    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3819  }
3820  virtual bool isCLZForZeroUndef() const { return false; }
3821  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3822    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3823  }
3824  virtual void getGCCRegNames(const char * const *&Names,
3825                              unsigned &NumNames) const;
3826  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3827                                unsigned &NumAliases) const;
3828  virtual bool validateAsmConstraint(const char *&Name,
3829                                     TargetInfo::ConstraintInfo &Info) const {
3830    switch (*Name) {
3831    default: break;
3832    case 'l': // r0-r7
3833    case 'h': // r8-r15
3834    case 'w': // VFP Floating point register single precision
3835    case 'P': // VFP Floating point register double precision
3836      Info.setAllowsRegister();
3837      return true;
3838    case 'Q': // A memory address that is a single base register.
3839      Info.setAllowsMemory();
3840      return true;
3841    case 'U': // a memory reference...
3842      switch (Name[1]) {
3843      case 'q': // ...ARMV4 ldrsb
3844      case 'v': // ...VFP load/store (reg+constant offset)
3845      case 'y': // ...iWMMXt load/store
3846      case 't': // address valid for load/store opaque types wider
3847                // than 128-bits
3848      case 'n': // valid address for Neon doubleword vector load/store
3849      case 'm': // valid address for Neon element and structure load/store
3850      case 's': // valid address for non-offset loads/stores of quad-word
3851                // values in four ARM registers
3852        Info.setAllowsMemory();
3853        Name++;
3854        return true;
3855      }
3856    }
3857    return false;
3858  }
3859  virtual std::string convertConstraint(const char *&Constraint) const {
3860    std::string R;
3861    switch (*Constraint) {
3862    case 'U':   // Two-character constraint; add "^" hint for later parsing.
3863      R = std::string("^") + std::string(Constraint, 2);
3864      Constraint++;
3865      break;
3866    case 'p': // 'p' should be translated to 'r' by default.
3867      R = std::string("r");
3868      break;
3869    default:
3870      return std::string(1, *Constraint);
3871    }
3872    return R;
3873  }
3874  virtual bool validateConstraintModifier(StringRef Constraint,
3875                                          const char Modifier,
3876                                          unsigned Size) const {
3877    bool isOutput = (Constraint[0] == '=');
3878    bool isInOut = (Constraint[0] == '+');
3879
3880    // Strip off constraint modifiers.
3881    while (Constraint[0] == '=' ||
3882           Constraint[0] == '+' ||
3883           Constraint[0] == '&')
3884      Constraint = Constraint.substr(1);
3885
3886    switch (Constraint[0]) {
3887    default: break;
3888    case 'r': {
3889      switch (Modifier) {
3890      default:
3891        return (isInOut || isOutput || Size <= 32);
3892      case 'q':
3893        // A register of size 32 cannot fit a vector type.
3894        return false;
3895      }
3896    }
3897    }
3898
3899    return true;
3900  }
3901  virtual const char *getClobbers() const {
3902    // FIXME: Is this really right?
3903    return "";
3904  }
3905
3906  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3907    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3908  }
3909
3910  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3911    if (RegNo == 0) return 0;
3912    if (RegNo == 1) return 1;
3913    return -1;
3914  }
3915};
3916
3917const char * const ARMTargetInfo::GCCRegNames[] = {
3918  // Integer registers
3919  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3920  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3921
3922  // Float registers
3923  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3924  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3925  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3926  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3927
3928  // Double registers
3929  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3930  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3931  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3932  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3933
3934  // Quad registers
3935  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3936  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3937};
3938
3939void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3940                                   unsigned &NumNames) const {
3941  Names = GCCRegNames;
3942  NumNames = llvm::array_lengthof(GCCRegNames);
3943}
3944
3945const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3946  { { "a1" }, "r0" },
3947  { { "a2" }, "r1" },
3948  { { "a3" }, "r2" },
3949  { { "a4" }, "r3" },
3950  { { "v1" }, "r4" },
3951  { { "v2" }, "r5" },
3952  { { "v3" }, "r6" },
3953  { { "v4" }, "r7" },
3954  { { "v5" }, "r8" },
3955  { { "v6", "rfp" }, "r9" },
3956  { { "sl" }, "r10" },
3957  { { "fp" }, "r11" },
3958  { { "ip" }, "r12" },
3959  { { "r13" }, "sp" },
3960  { { "r14" }, "lr" },
3961  { { "r15" }, "pc" },
3962  // The S, D and Q registers overlap, but aren't really aliases; we
3963  // don't want to substitute one of these for a different-sized one.
3964};
3965
3966void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3967                                       unsigned &NumAliases) const {
3968  Aliases = GCCRegAliases;
3969  NumAliases = llvm::array_lengthof(GCCRegAliases);
3970}
3971
3972const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3973#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3974#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3975                                              ALL_LANGUAGES },
3976#include "clang/Basic/BuiltinsARM.def"
3977};
3978} // end anonymous namespace.
3979
3980namespace {
3981class DarwinARMTargetInfo :
3982  public DarwinTargetInfo<ARMTargetInfo> {
3983protected:
3984  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3985                            MacroBuilder &Builder) const {
3986    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3987  }
3988
3989public:
3990  DarwinARMTargetInfo(const llvm::Triple &Triple)
3991      : DarwinTargetInfo<ARMTargetInfo>(Triple) {
3992    HasAlignMac68kSupport = true;
3993    // iOS always has 64-bit atomic instructions.
3994    // FIXME: This should be based off of the target features in ARMTargetInfo.
3995    MaxAtomicInlineWidth = 64;
3996
3997    // Darwin on iOS uses a variant of the ARM C++ ABI.
3998    TheCXXABI.set(TargetCXXABI::iOS);
3999  }
4000};
4001} // end anonymous namespace.
4002
4003
4004namespace {
4005// Hexagon abstract base class
4006class HexagonTargetInfo : public TargetInfo {
4007  static const Builtin::Info BuiltinInfo[];
4008  static const char * const GCCRegNames[];
4009  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4010  std::string CPU;
4011public:
4012  HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4013    BigEndian = false;
4014    DescriptionString = ("e-p:32:32:32-"
4015                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
4016                         "f64:64:64-f32:32:32-a0:0-n32");
4017
4018    // {} in inline assembly are packet specifiers, not assembly variant
4019    // specifiers.
4020    NoAsmVariants = true;
4021  }
4022
4023  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4024                                 unsigned &NumRecords) const {
4025    Records = BuiltinInfo;
4026    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4027  }
4028
4029  virtual bool validateAsmConstraint(const char *&Name,
4030                                     TargetInfo::ConstraintInfo &Info) const {
4031    return true;
4032  }
4033
4034  virtual void getTargetDefines(const LangOptions &Opts,
4035                                MacroBuilder &Builder) const;
4036
4037  virtual bool hasFeature(StringRef Feature) const {
4038    return Feature == "hexagon";
4039  }
4040
4041  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4042    return TargetInfo::CharPtrBuiltinVaList;
4043  }
4044  virtual void getGCCRegNames(const char * const *&Names,
4045                              unsigned &NumNames) const;
4046  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4047                                unsigned &NumAliases) const;
4048  virtual const char *getClobbers() const {
4049    return "";
4050  }
4051
4052  static const char *getHexagonCPUSuffix(StringRef Name) {
4053    return llvm::StringSwitch<const char*>(Name)
4054      .Case("hexagonv4", "4")
4055      .Case("hexagonv5", "5")
4056      .Default(0);
4057  }
4058
4059  virtual bool setCPU(const std::string &Name) {
4060    if (!getHexagonCPUSuffix(Name))
4061      return false;
4062
4063    CPU = Name;
4064    return true;
4065  }
4066};
4067
4068void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4069                                MacroBuilder &Builder) const {
4070  Builder.defineMacro("qdsp6");
4071  Builder.defineMacro("__qdsp6", "1");
4072  Builder.defineMacro("__qdsp6__", "1");
4073
4074  Builder.defineMacro("hexagon");
4075  Builder.defineMacro("__hexagon", "1");
4076  Builder.defineMacro("__hexagon__", "1");
4077
4078  if(CPU == "hexagonv1") {
4079    Builder.defineMacro("__HEXAGON_V1__");
4080    Builder.defineMacro("__HEXAGON_ARCH__", "1");
4081    if(Opts.HexagonQdsp6Compat) {
4082      Builder.defineMacro("__QDSP6_V1__");
4083      Builder.defineMacro("__QDSP6_ARCH__", "1");
4084    }
4085  }
4086  else if(CPU == "hexagonv2") {
4087    Builder.defineMacro("__HEXAGON_V2__");
4088    Builder.defineMacro("__HEXAGON_ARCH__", "2");
4089    if(Opts.HexagonQdsp6Compat) {
4090      Builder.defineMacro("__QDSP6_V2__");
4091      Builder.defineMacro("__QDSP6_ARCH__", "2");
4092    }
4093  }
4094  else if(CPU == "hexagonv3") {
4095    Builder.defineMacro("__HEXAGON_V3__");
4096    Builder.defineMacro("__HEXAGON_ARCH__", "3");
4097    if(Opts.HexagonQdsp6Compat) {
4098      Builder.defineMacro("__QDSP6_V3__");
4099      Builder.defineMacro("__QDSP6_ARCH__", "3");
4100    }
4101  }
4102  else if(CPU == "hexagonv4") {
4103    Builder.defineMacro("__HEXAGON_V4__");
4104    Builder.defineMacro("__HEXAGON_ARCH__", "4");
4105    if(Opts.HexagonQdsp6Compat) {
4106      Builder.defineMacro("__QDSP6_V4__");
4107      Builder.defineMacro("__QDSP6_ARCH__", "4");
4108    }
4109  }
4110  else if(CPU == "hexagonv5") {
4111    Builder.defineMacro("__HEXAGON_V5__");
4112    Builder.defineMacro("__HEXAGON_ARCH__", "5");
4113    if(Opts.HexagonQdsp6Compat) {
4114      Builder.defineMacro("__QDSP6_V5__");
4115      Builder.defineMacro("__QDSP6_ARCH__", "5");
4116    }
4117  }
4118}
4119
4120const char * const HexagonTargetInfo::GCCRegNames[] = {
4121  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4122  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4123  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4124  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4125  "p0", "p1", "p2", "p3",
4126  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4127};
4128
4129void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4130                                   unsigned &NumNames) const {
4131  Names = GCCRegNames;
4132  NumNames = llvm::array_lengthof(GCCRegNames);
4133}
4134
4135
4136const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4137  { { "sp" }, "r29" },
4138  { { "fp" }, "r30" },
4139  { { "lr" }, "r31" },
4140 };
4141
4142void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4143                                     unsigned &NumAliases) const {
4144  Aliases = GCCRegAliases;
4145  NumAliases = llvm::array_lengthof(GCCRegAliases);
4146}
4147
4148
4149const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4150#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4151#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4152                                              ALL_LANGUAGES },
4153#include "clang/Basic/BuiltinsHexagon.def"
4154};
4155}
4156
4157
4158namespace {
4159// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4160class SparcTargetInfo : public TargetInfo {
4161  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4162  static const char * const GCCRegNames[];
4163  bool SoftFloat;
4164public:
4165  SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
4166
4167  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4168                                 StringRef Name,
4169                                 bool Enabled) const {
4170    if (Name == "soft-float")
4171      Features[Name] = Enabled;
4172    else
4173      return false;
4174
4175    return true;
4176  }
4177  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4178    SoftFloat = false;
4179    for (unsigned i = 0, e = Features.size(); i != e; ++i)
4180      if (Features[i] == "+soft-float")
4181        SoftFloat = true;
4182  }
4183  virtual void getTargetDefines(const LangOptions &Opts,
4184                                MacroBuilder &Builder) const {
4185    DefineStd(Builder, "sparc", Opts);
4186    Builder.defineMacro("__REGISTER_PREFIX__", "");
4187
4188    if (SoftFloat)
4189      Builder.defineMacro("SOFT_FLOAT", "1");
4190  }
4191
4192  virtual bool hasFeature(StringRef Feature) const {
4193    return llvm::StringSwitch<bool>(Feature)
4194             .Case("softfloat", SoftFloat)
4195             .Case("sparc", true)
4196             .Default(false);
4197  }
4198
4199  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4200                                 unsigned &NumRecords) const {
4201    // FIXME: Implement!
4202  }
4203  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4204    return TargetInfo::VoidPtrBuiltinVaList;
4205  }
4206  virtual void getGCCRegNames(const char * const *&Names,
4207                              unsigned &NumNames) const;
4208  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4209                                unsigned &NumAliases) const;
4210  virtual bool validateAsmConstraint(const char *&Name,
4211                                     TargetInfo::ConstraintInfo &info) const {
4212    // FIXME: Implement!
4213    return false;
4214  }
4215  virtual const char *getClobbers() const {
4216    // FIXME: Implement!
4217    return "";
4218  }
4219};
4220
4221const char * const SparcTargetInfo::GCCRegNames[] = {
4222  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4223  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4224  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4225  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4226};
4227
4228void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4229                                     unsigned &NumNames) const {
4230  Names = GCCRegNames;
4231  NumNames = llvm::array_lengthof(GCCRegNames);
4232}
4233
4234const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4235  { { "g0" }, "r0" },
4236  { { "g1" }, "r1" },
4237  { { "g2" }, "r2" },
4238  { { "g3" }, "r3" },
4239  { { "g4" }, "r4" },
4240  { { "g5" }, "r5" },
4241  { { "g6" }, "r6" },
4242  { { "g7" }, "r7" },
4243  { { "o0" }, "r8" },
4244  { { "o1" }, "r9" },
4245  { { "o2" }, "r10" },
4246  { { "o3" }, "r11" },
4247  { { "o4" }, "r12" },
4248  { { "o5" }, "r13" },
4249  { { "o6", "sp" }, "r14" },
4250  { { "o7" }, "r15" },
4251  { { "l0" }, "r16" },
4252  { { "l1" }, "r17" },
4253  { { "l2" }, "r18" },
4254  { { "l3" }, "r19" },
4255  { { "l4" }, "r20" },
4256  { { "l5" }, "r21" },
4257  { { "l6" }, "r22" },
4258  { { "l7" }, "r23" },
4259  { { "i0" }, "r24" },
4260  { { "i1" }, "r25" },
4261  { { "i2" }, "r26" },
4262  { { "i3" }, "r27" },
4263  { { "i4" }, "r28" },
4264  { { "i5" }, "r29" },
4265  { { "i6", "fp" }, "r30" },
4266  { { "i7" }, "r31" },
4267};
4268
4269void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4270                                       unsigned &NumAliases) const {
4271  Aliases = GCCRegAliases;
4272  NumAliases = llvm::array_lengthof(GCCRegAliases);
4273}
4274
4275// SPARC v8 is the 32-bit mode selected by Triple::sparc.
4276class SparcV8TargetInfo : public SparcTargetInfo {
4277public:
4278  SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4279    // FIXME: Support Sparc quad-precision long double?
4280    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4281                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4282  }
4283
4284  virtual void getTargetDefines(const LangOptions &Opts,
4285                                MacroBuilder &Builder) const {
4286    SparcTargetInfo::getTargetDefines(Opts, Builder);
4287    Builder.defineMacro("__sparcv8");
4288  }
4289};
4290
4291// SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4292class SparcV9TargetInfo : public SparcTargetInfo {
4293public:
4294  SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4295    // FIXME: Support Sparc quad-precision long double?
4296    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4297                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4298    // This is an LP64 platform.
4299    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4300
4301    // OpenBSD uses long long for int64_t and intmax_t.
4302    if (getTriple().getOS() == llvm::Triple::OpenBSD) {
4303      IntMaxType = SignedLongLong;
4304      UIntMaxType = UnsignedLongLong;
4305    } else {
4306      IntMaxType = SignedLong;
4307      UIntMaxType = UnsignedLong;
4308    }
4309    Int64Type = IntMaxType;
4310  }
4311
4312  virtual void getTargetDefines(const LangOptions &Opts,
4313                                MacroBuilder &Builder) const {
4314    SparcTargetInfo::getTargetDefines(Opts, Builder);
4315    Builder.defineMacro("__sparcv9");
4316    Builder.defineMacro("__arch64__");
4317    // Solaris and its derivative AuroraUX don't need these variants, but the
4318    // BSDs do.
4319    if (getTriple().getOS() != llvm::Triple::Solaris &&
4320        getTriple().getOS() != llvm::Triple::AuroraUX) {
4321      Builder.defineMacro("__sparc64__");
4322      Builder.defineMacro("__sparc_v9__");
4323      Builder.defineMacro("__sparcv9__");
4324    }
4325  }
4326};
4327
4328} // end anonymous namespace.
4329
4330namespace {
4331class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4332public:
4333  AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
4334      : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
4335    SizeType = UnsignedInt;
4336    PtrDiffType = SignedInt;
4337  }
4338};
4339class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4340public:
4341  SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
4342      : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
4343    SizeType = UnsignedInt;
4344    PtrDiffType = SignedInt;
4345  }
4346};
4347} // end anonymous namespace.
4348
4349namespace {
4350  class SystemZTargetInfo : public TargetInfo {
4351    static const char *const GCCRegNames[];
4352
4353  public:
4354    SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4355      TLSSupported = true;
4356      IntWidth = IntAlign = 32;
4357      LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4358      PointerWidth = PointerAlign = 64;
4359      LongDoubleWidth = 128;
4360      LongDoubleAlign = 64;
4361      LongDoubleFormat = &llvm::APFloat::IEEEquad;
4362      MinGlobalAlign = 16;
4363      DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4364       "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4365      MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4366    }
4367    virtual void getTargetDefines(const LangOptions &Opts,
4368                                  MacroBuilder &Builder) const {
4369      Builder.defineMacro("__s390__");
4370      Builder.defineMacro("__s390x__");
4371      Builder.defineMacro("__zarch__");
4372      Builder.defineMacro("__LONG_DOUBLE_128__");
4373    }
4374    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4375                                   unsigned &NumRecords) const {
4376      // FIXME: Implement.
4377      Records = 0;
4378      NumRecords = 0;
4379    }
4380
4381    virtual void getGCCRegNames(const char *const *&Names,
4382                                unsigned &NumNames) const;
4383    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4384                                  unsigned &NumAliases) const {
4385      // No aliases.
4386      Aliases = 0;
4387      NumAliases = 0;
4388    }
4389    virtual bool validateAsmConstraint(const char *&Name,
4390                                       TargetInfo::ConstraintInfo &info) const;
4391    virtual const char *getClobbers() const {
4392      // FIXME: Is this really right?
4393      return "";
4394    }
4395    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4396      return TargetInfo::SystemZBuiltinVaList;
4397    }
4398  };
4399
4400  const char *const SystemZTargetInfo::GCCRegNames[] = {
4401    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
4402    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
4403    "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
4404    "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
4405  };
4406
4407  void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4408                                         unsigned &NumNames) const {
4409    Names = GCCRegNames;
4410    NumNames = llvm::array_lengthof(GCCRegNames);
4411  }
4412
4413  bool SystemZTargetInfo::
4414  validateAsmConstraint(const char *&Name,
4415                        TargetInfo::ConstraintInfo &Info) const {
4416    switch (*Name) {
4417    default:
4418      return false;
4419
4420    case 'a': // Address register
4421    case 'd': // Data register (equivalent to 'r')
4422    case 'f': // Floating-point register
4423      Info.setAllowsRegister();
4424      return true;
4425
4426    case 'I': // Unsigned 8-bit constant
4427    case 'J': // Unsigned 12-bit constant
4428    case 'K': // Signed 16-bit constant
4429    case 'L': // Signed 20-bit displacement (on all targets we support)
4430    case 'M': // 0x7fffffff
4431      return true;
4432
4433    case 'Q': // Memory with base and unsigned 12-bit displacement
4434    case 'R': // Likewise, plus an index
4435    case 'S': // Memory with base and signed 20-bit displacement
4436    case 'T': // Likewise, plus an index
4437      Info.setAllowsMemory();
4438      return true;
4439    }
4440  }
4441}
4442
4443namespace {
4444  class MSP430TargetInfo : public TargetInfo {
4445    static const char * const GCCRegNames[];
4446  public:
4447    MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4448      BigEndian = false;
4449      TLSSupported = false;
4450      IntWidth = 16; IntAlign = 16;
4451      LongWidth = 32; LongLongWidth = 64;
4452      LongAlign = LongLongAlign = 16;
4453      PointerWidth = 16; PointerAlign = 16;
4454      SuitableAlign = 16;
4455      SizeType = UnsignedInt;
4456      IntMaxType = SignedLong;
4457      UIntMaxType = UnsignedLong;
4458      IntPtrType = SignedShort;
4459      PtrDiffType = SignedInt;
4460      SigAtomicType = SignedLong;
4461      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4462   }
4463    virtual void getTargetDefines(const LangOptions &Opts,
4464                                  MacroBuilder &Builder) const {
4465      Builder.defineMacro("MSP430");
4466      Builder.defineMacro("__MSP430__");
4467      // FIXME: defines for different 'flavours' of MCU
4468    }
4469    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4470                                   unsigned &NumRecords) const {
4471     // FIXME: Implement.
4472      Records = 0;
4473      NumRecords = 0;
4474    }
4475    virtual bool hasFeature(StringRef Feature) const {
4476      return Feature == "msp430";
4477    }
4478    virtual void getGCCRegNames(const char * const *&Names,
4479                                unsigned &NumNames) const;
4480    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4481                                  unsigned &NumAliases) const {
4482      // No aliases.
4483      Aliases = 0;
4484      NumAliases = 0;
4485    }
4486    virtual bool validateAsmConstraint(const char *&Name,
4487                                       TargetInfo::ConstraintInfo &info) const {
4488      // No target constraints for now.
4489      return false;
4490    }
4491    virtual const char *getClobbers() const {
4492      // FIXME: Is this really right?
4493      return "";
4494    }
4495    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4496      // FIXME: implement
4497      return TargetInfo::CharPtrBuiltinVaList;
4498   }
4499  };
4500
4501  const char * const MSP430TargetInfo::GCCRegNames[] = {
4502    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4503    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4504  };
4505
4506  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4507                                        unsigned &NumNames) const {
4508    Names = GCCRegNames;
4509    NumNames = llvm::array_lengthof(GCCRegNames);
4510  }
4511}
4512
4513namespace {
4514
4515  // LLVM and Clang cannot be used directly to output native binaries for
4516  // target, but is used to compile C code to llvm bitcode with correct
4517  // type and alignment information.
4518  //
4519  // TCE uses the llvm bitcode as input and uses it for generating customized
4520  // target processor and program binary. TCE co-design environment is
4521  // publicly available in http://tce.cs.tut.fi
4522
4523  static const unsigned TCEOpenCLAddrSpaceMap[] = {
4524      3, // opencl_global
4525      4, // opencl_local
4526      5, // opencl_constant
4527      0, // cuda_device
4528      0, // cuda_constant
4529      0  // cuda_shared
4530  };
4531
4532  class TCETargetInfo : public TargetInfo{
4533  public:
4534    TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4535      TLSSupported = false;
4536      IntWidth = 32;
4537      LongWidth = LongLongWidth = 32;
4538      PointerWidth = 32;
4539      IntAlign = 32;
4540      LongAlign = LongLongAlign = 32;
4541      PointerAlign = 32;
4542      SuitableAlign = 32;
4543      SizeType = UnsignedInt;
4544      IntMaxType = SignedLong;
4545      UIntMaxType = UnsignedLong;
4546      IntPtrType = SignedInt;
4547      PtrDiffType = SignedInt;
4548      FloatWidth = 32;
4549      FloatAlign = 32;
4550      DoubleWidth = 32;
4551      DoubleAlign = 32;
4552      LongDoubleWidth = 32;
4553      LongDoubleAlign = 32;
4554      FloatFormat = &llvm::APFloat::IEEEsingle;
4555      DoubleFormat = &llvm::APFloat::IEEEsingle;
4556      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4557      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4558                          "i16:16:32-i32:32:32-i64:32:32-"
4559                          "f32:32:32-f64:32:32-v64:32:32-"
4560                          "v128:32:32-a0:0:32-n32";
4561      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4562    }
4563
4564    virtual void getTargetDefines(const LangOptions &Opts,
4565                                  MacroBuilder &Builder) const {
4566      DefineStd(Builder, "tce", Opts);
4567      Builder.defineMacro("__TCE__");
4568      Builder.defineMacro("__TCE_V1__");
4569    }
4570    virtual bool hasFeature(StringRef Feature) const {
4571      return Feature == "tce";
4572    }
4573
4574    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4575                                   unsigned &NumRecords) const {}
4576    virtual const char *getClobbers() const {
4577      return "";
4578    }
4579    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4580      return TargetInfo::VoidPtrBuiltinVaList;
4581    }
4582    virtual void getGCCRegNames(const char * const *&Names,
4583                                unsigned &NumNames) const {}
4584    virtual bool validateAsmConstraint(const char *&Name,
4585                                       TargetInfo::ConstraintInfo &info) const {
4586      return true;
4587    }
4588    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4589                                  unsigned &NumAliases) const {}
4590  };
4591}
4592
4593namespace {
4594class MipsTargetInfoBase : public TargetInfo {
4595  static const Builtin::Info BuiltinInfo[];
4596  std::string CPU;
4597  bool IsMips16;
4598  bool IsMicromips;
4599  bool IsSingleFloat;
4600  enum MipsFloatABI {
4601    HardFloat, SoftFloat
4602  } FloatABI;
4603  enum DspRevEnum {
4604    NoDSP, DSP1, DSP2
4605  } DspRev;
4606
4607protected:
4608  std::string ABI;
4609
4610public:
4611  MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
4612                     const std::string &CPUStr)
4613      : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
4614        IsSingleFloat(false), FloatABI(HardFloat), DspRev(NoDSP), ABI(ABIStr) {}
4615
4616  virtual const char *getABI() const { return ABI.c_str(); }
4617  virtual bool setABI(const std::string &Name) = 0;
4618  virtual bool setCPU(const std::string &Name) {
4619    CPU = Name;
4620    return true;
4621  }
4622  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4623    Features[ABI] = true;
4624    Features[CPU] = true;
4625  }
4626
4627  virtual void getTargetDefines(const LangOptions &Opts,
4628                                MacroBuilder &Builder) const {
4629    DefineStd(Builder, "mips", Opts);
4630    Builder.defineMacro("_mips");
4631    Builder.defineMacro("__REGISTER_PREFIX__", "");
4632
4633    switch (FloatABI) {
4634    case HardFloat:
4635      Builder.defineMacro("__mips_hard_float", Twine(1));
4636      break;
4637    case SoftFloat:
4638      Builder.defineMacro("__mips_soft_float", Twine(1));
4639      break;
4640    }
4641
4642    if (IsSingleFloat)
4643      Builder.defineMacro("__mips_single_float", Twine(1));
4644
4645    if (IsMips16)
4646      Builder.defineMacro("__mips16", Twine(1));
4647
4648    if (IsMicromips)
4649      Builder.defineMacro("__mips_micromips", Twine(1));
4650
4651    switch (DspRev) {
4652    default:
4653      break;
4654    case DSP1:
4655      Builder.defineMacro("__mips_dsp_rev", Twine(1));
4656      Builder.defineMacro("__mips_dsp", Twine(1));
4657      break;
4658    case DSP2:
4659      Builder.defineMacro("__mips_dsp_rev", Twine(2));
4660      Builder.defineMacro("__mips_dspr2", Twine(1));
4661      Builder.defineMacro("__mips_dsp", Twine(1));
4662      break;
4663    }
4664
4665    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4666    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4667    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4668
4669    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4670    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4671  }
4672
4673  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4674                                 unsigned &NumRecords) const {
4675    Records = BuiltinInfo;
4676    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4677  }
4678  virtual bool hasFeature(StringRef Feature) const {
4679    return Feature == "mips";
4680  }
4681  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4682    return TargetInfo::VoidPtrBuiltinVaList;
4683  }
4684  virtual void getGCCRegNames(const char * const *&Names,
4685                              unsigned &NumNames) const {
4686    static const char * const GCCRegNames[] = {
4687      // CPU register names
4688      // Must match second column of GCCRegAliases
4689      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4690      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4691      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4692      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4693      // Floating point register names
4694      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4695      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4696      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4697      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4698      // Hi/lo and condition register names
4699      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4700      "$fcc5","$fcc6","$fcc7"
4701    };
4702    Names = GCCRegNames;
4703    NumNames = llvm::array_lengthof(GCCRegNames);
4704  }
4705  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4706                                unsigned &NumAliases) const = 0;
4707  virtual bool validateAsmConstraint(const char *&Name,
4708                                     TargetInfo::ConstraintInfo &Info) const {
4709    switch (*Name) {
4710    default:
4711      return false;
4712
4713    case 'r': // CPU registers.
4714    case 'd': // Equivalent to "r" unless generating MIPS16 code.
4715    case 'y': // Equivalent to "r", backwards compatibility only.
4716    case 'f': // floating-point registers.
4717    case 'c': // $25 for indirect jumps
4718    case 'l': // lo register
4719    case 'x': // hilo register pair
4720      Info.setAllowsRegister();
4721      return true;
4722    case 'R': // An address that can be used in a non-macro load or store
4723      Info.setAllowsMemory();
4724      return true;
4725    }
4726  }
4727
4728  virtual const char *getClobbers() const {
4729    // FIXME: Implement!
4730    return "";
4731  }
4732
4733  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4734                                 StringRef Name,
4735                                 bool Enabled) const {
4736    if (Name == "soft-float" || Name == "single-float" ||
4737        Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4738        Name == "mips32" || Name == "mips32r2" ||
4739        Name == "mips64" || Name == "mips64r2" ||
4740        Name == "mips16" || Name == "micromips" ||
4741        Name == "dsp" || Name == "dspr2") {
4742      Features[Name] = Enabled;
4743      return true;
4744    } else if (Name == "32") {
4745      Features["o32"] = Enabled;
4746      return true;
4747    } else if (Name == "64") {
4748      Features["n64"] = Enabled;
4749      return true;
4750    }
4751    return false;
4752  }
4753
4754  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4755    IsMips16 = false;
4756    IsMicromips = false;
4757    IsSingleFloat = false;
4758    FloatABI = HardFloat;
4759    DspRev = NoDSP;
4760
4761    for (std::vector<std::string>::iterator it = Features.begin(),
4762         ie = Features.end(); it != ie; ++it) {
4763      if (*it == "+single-float")
4764        IsSingleFloat = true;
4765      else if (*it == "+soft-float")
4766        FloatABI = SoftFloat;
4767      else if (*it == "+mips16")
4768        IsMips16 = true;
4769      else if (*it == "+micromips")
4770        IsMicromips = true;
4771      else if (*it == "+dsp")
4772        DspRev = std::max(DspRev, DSP1);
4773      else if (*it == "+dspr2")
4774        DspRev = std::max(DspRev, DSP2);
4775    }
4776
4777    // Remove front-end specific option.
4778    std::vector<std::string>::iterator it =
4779      std::find(Features.begin(), Features.end(), "+soft-float");
4780    if (it != Features.end())
4781      Features.erase(it);
4782  }
4783
4784  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4785    if (RegNo == 0) return 4;
4786    if (RegNo == 1) return 5;
4787    return -1;
4788  }
4789};
4790
4791const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4792#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4793#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4794                                              ALL_LANGUAGES },
4795#include "clang/Basic/BuiltinsMips.def"
4796};
4797
4798class Mips32TargetInfoBase : public MipsTargetInfoBase {
4799public:
4800  Mips32TargetInfoBase(const llvm::Triple &Triple)
4801      : MipsTargetInfoBase(Triple, "o32", "mips32") {
4802    SizeType = UnsignedInt;
4803    PtrDiffType = SignedInt;
4804    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4805  }
4806  virtual bool setABI(const std::string &Name) {
4807    if ((Name == "o32") || (Name == "eabi")) {
4808      ABI = Name;
4809      return true;
4810    } else if (Name == "32") {
4811      ABI = "o32";
4812      return true;
4813    } else
4814      return false;
4815  }
4816  virtual void getTargetDefines(const LangOptions &Opts,
4817                                MacroBuilder &Builder) const {
4818    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4819
4820    if (ABI == "o32") {
4821      Builder.defineMacro("__mips_o32");
4822      Builder.defineMacro("_ABIO32", "1");
4823      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4824    }
4825    else if (ABI == "eabi")
4826      Builder.defineMacro("__mips_eabi");
4827    else
4828      llvm_unreachable("Invalid ABI for Mips32.");
4829  }
4830  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4831                                unsigned &NumAliases) const {
4832    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4833      { { "at" },  "$1" },
4834      { { "v0" },  "$2" },
4835      { { "v1" },  "$3" },
4836      { { "a0" },  "$4" },
4837      { { "a1" },  "$5" },
4838      { { "a2" },  "$6" },
4839      { { "a3" },  "$7" },
4840      { { "t0" },  "$8" },
4841      { { "t1" },  "$9" },
4842      { { "t2" }, "$10" },
4843      { { "t3" }, "$11" },
4844      { { "t4" }, "$12" },
4845      { { "t5" }, "$13" },
4846      { { "t6" }, "$14" },
4847      { { "t7" }, "$15" },
4848      { { "s0" }, "$16" },
4849      { { "s1" }, "$17" },
4850      { { "s2" }, "$18" },
4851      { { "s3" }, "$19" },
4852      { { "s4" }, "$20" },
4853      { { "s5" }, "$21" },
4854      { { "s6" }, "$22" },
4855      { { "s7" }, "$23" },
4856      { { "t8" }, "$24" },
4857      { { "t9" }, "$25" },
4858      { { "k0" }, "$26" },
4859      { { "k1" }, "$27" },
4860      { { "gp" }, "$28" },
4861      { { "sp","$sp" }, "$29" },
4862      { { "fp","$fp" }, "$30" },
4863      { { "ra" }, "$31" }
4864    };
4865    Aliases = GCCRegAliases;
4866    NumAliases = llvm::array_lengthof(GCCRegAliases);
4867  }
4868};
4869
4870class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4871public:
4872  Mips32EBTargetInfo(const llvm::Triple &Triple)
4873      : Mips32TargetInfoBase(Triple) {
4874    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4875                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4876  }
4877  virtual void getTargetDefines(const LangOptions &Opts,
4878                                MacroBuilder &Builder) const {
4879    DefineStd(Builder, "MIPSEB", Opts);
4880    Builder.defineMacro("_MIPSEB");
4881    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4882  }
4883};
4884
4885class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4886public:
4887  Mips32ELTargetInfo(const llvm::Triple &Triple)
4888      : Mips32TargetInfoBase(Triple) {
4889    BigEndian = false;
4890    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4891                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4892  }
4893  virtual void getTargetDefines(const LangOptions &Opts,
4894                                MacroBuilder &Builder) const {
4895    DefineStd(Builder, "MIPSEL", Opts);
4896    Builder.defineMacro("_MIPSEL");
4897    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4898  }
4899};
4900
4901class Mips64TargetInfoBase : public MipsTargetInfoBase {
4902  virtual void SetDescriptionString(const std::string &Name) = 0;
4903public:
4904  Mips64TargetInfoBase(const llvm::Triple &Triple)
4905      : MipsTargetInfoBase(Triple, "n64", "mips64") {
4906    LongWidth = LongAlign = 64;
4907    PointerWidth = PointerAlign = 64;
4908    LongDoubleWidth = LongDoubleAlign = 128;
4909    LongDoubleFormat = &llvm::APFloat::IEEEquad;
4910    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4911      LongDoubleWidth = LongDoubleAlign = 64;
4912      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4913    }
4914    SuitableAlign = 128;
4915    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4916  }
4917  virtual bool setABI(const std::string &Name) {
4918    SetDescriptionString(Name);
4919    if (Name == "n32") {
4920      LongWidth = LongAlign = 32;
4921      PointerWidth = PointerAlign = 32;
4922      ABI = Name;
4923      return true;
4924    } else if (Name == "n64") {
4925      ABI = Name;
4926      return true;
4927    } else if (Name == "64") {
4928      ABI = "n64";
4929      return true;
4930    } else
4931      return false;
4932  }
4933  virtual void getTargetDefines(const LangOptions &Opts,
4934                                MacroBuilder &Builder) const {
4935    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4936
4937    Builder.defineMacro("__mips64");
4938    Builder.defineMacro("__mips64__");
4939
4940    if (ABI == "n32") {
4941      Builder.defineMacro("__mips_n32");
4942      Builder.defineMacro("_ABIN32", "2");
4943      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4944    }
4945    else if (ABI == "n64") {
4946      Builder.defineMacro("__mips_n64");
4947      Builder.defineMacro("_ABI64", "3");
4948      Builder.defineMacro("_MIPS_SIM", "_ABI64");
4949    }
4950    else
4951      llvm_unreachable("Invalid ABI for Mips64.");
4952  }
4953  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4954                                unsigned &NumAliases) const {
4955    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4956      { { "at" },  "$1" },
4957      { { "v0" },  "$2" },
4958      { { "v1" },  "$3" },
4959      { { "a0" },  "$4" },
4960      { { "a1" },  "$5" },
4961      { { "a2" },  "$6" },
4962      { { "a3" },  "$7" },
4963      { { "a4" },  "$8" },
4964      { { "a5" },  "$9" },
4965      { { "a6" }, "$10" },
4966      { { "a7" }, "$11" },
4967      { { "t0" }, "$12" },
4968      { { "t1" }, "$13" },
4969      { { "t2" }, "$14" },
4970      { { "t3" }, "$15" },
4971      { { "s0" }, "$16" },
4972      { { "s1" }, "$17" },
4973      { { "s2" }, "$18" },
4974      { { "s3" }, "$19" },
4975      { { "s4" }, "$20" },
4976      { { "s5" }, "$21" },
4977      { { "s6" }, "$22" },
4978      { { "s7" }, "$23" },
4979      { { "t8" }, "$24" },
4980      { { "t9" }, "$25" },
4981      { { "k0" }, "$26" },
4982      { { "k1" }, "$27" },
4983      { { "gp" }, "$28" },
4984      { { "sp","$sp" }, "$29" },
4985      { { "fp","$fp" }, "$30" },
4986      { { "ra" }, "$31" }
4987    };
4988    Aliases = GCCRegAliases;
4989    NumAliases = llvm::array_lengthof(GCCRegAliases);
4990  }
4991};
4992
4993class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4994  virtual void SetDescriptionString(const std::string &Name) {
4995    // Change DescriptionString only if ABI is n32.
4996    if (Name == "n32")
4997      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4998                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4999                          "v64:64:64-n32:64-S128";
5000  }
5001public:
5002  Mips64EBTargetInfo(const llvm::Triple &Triple)
5003      : Mips64TargetInfoBase(Triple) {
5004    // Default ABI is n64.
5005    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5006                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5007                        "v64:64:64-n32:64-S128";
5008  }
5009  virtual void getTargetDefines(const LangOptions &Opts,
5010                                MacroBuilder &Builder) const {
5011    DefineStd(Builder, "MIPSEB", Opts);
5012    Builder.defineMacro("_MIPSEB");
5013    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5014  }
5015};
5016
5017class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5018  virtual void SetDescriptionString(const std::string &Name) {
5019    // Change DescriptionString only if ABI is n32.
5020    if (Name == "n32")
5021      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5022                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
5023                          "-v64:64:64-n32:64-S128";
5024  }
5025public:
5026  Mips64ELTargetInfo(const llvm::Triple &Triple)
5027      : Mips64TargetInfoBase(Triple) {
5028    // Default ABI is n64.
5029    BigEndian = false;
5030    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5031                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5032                        "v64:64:64-n32:64-S128";
5033  }
5034  virtual void getTargetDefines(const LangOptions &Opts,
5035                                MacroBuilder &Builder) const {
5036    DefineStd(Builder, "MIPSEL", Opts);
5037    Builder.defineMacro("_MIPSEL");
5038    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5039  }
5040};
5041} // end anonymous namespace.
5042
5043namespace {
5044class PNaClTargetInfo : public TargetInfo {
5045public:
5046  PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5047    BigEndian = false;
5048    this->UserLabelPrefix = "";
5049    this->LongAlign = 32;
5050    this->LongWidth = 32;
5051    this->PointerAlign = 32;
5052    this->PointerWidth = 32;
5053    this->IntMaxType = TargetInfo::SignedLongLong;
5054    this->UIntMaxType = TargetInfo::UnsignedLongLong;
5055    this->Int64Type = TargetInfo::SignedLongLong;
5056    this->DoubleAlign = 64;
5057    this->LongDoubleWidth = 64;
5058    this->LongDoubleAlign = 64;
5059    this->SizeType = TargetInfo::UnsignedInt;
5060    this->PtrDiffType = TargetInfo::SignedInt;
5061    this->IntPtrType = TargetInfo::SignedInt;
5062    this->RegParmMax = 0; // Disallow regparm
5063    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5064                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
5065  }
5066
5067  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
5068  }
5069  virtual void getArchDefines(const LangOptions &Opts,
5070                              MacroBuilder &Builder) const {
5071    Builder.defineMacro("__le32__");
5072    Builder.defineMacro("__pnacl__");
5073  }
5074  virtual void getTargetDefines(const LangOptions &Opts,
5075                                MacroBuilder &Builder) const {
5076    Builder.defineMacro("__LITTLE_ENDIAN__");
5077    getArchDefines(Opts, Builder);
5078  }
5079  virtual bool hasFeature(StringRef Feature) const {
5080    return Feature == "pnacl";
5081  }
5082  virtual void getTargetBuiltins(const Builtin::Info *&Records,
5083                                 unsigned &NumRecords) const {
5084  }
5085  virtual BuiltinVaListKind getBuiltinVaListKind() const {
5086    return TargetInfo::PNaClABIBuiltinVaList;
5087  }
5088  virtual void getGCCRegNames(const char * const *&Names,
5089                              unsigned &NumNames) const;
5090  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5091                                unsigned &NumAliases) const;
5092  virtual bool validateAsmConstraint(const char *&Name,
5093                                     TargetInfo::ConstraintInfo &Info) const {
5094    return false;
5095  }
5096
5097  virtual const char *getClobbers() const {
5098    return "";
5099  }
5100};
5101
5102void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5103                                     unsigned &NumNames) const {
5104  Names = NULL;
5105  NumNames = 0;
5106}
5107
5108void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5109                                       unsigned &NumAliases) const {
5110  Aliases = NULL;
5111  NumAliases = 0;
5112}
5113} // end anonymous namespace.
5114
5115namespace {
5116  static const unsigned SPIRAddrSpaceMap[] = {
5117    1,    // opencl_global
5118    3,    // opencl_local
5119    2,    // opencl_constant
5120    0,    // cuda_device
5121    0,    // cuda_constant
5122    0     // cuda_shared
5123  };
5124  class SPIRTargetInfo : public TargetInfo {
5125    static const char * const GCCRegNames[];
5126    static const Builtin::Info BuiltinInfo[];
5127    std::vector<StringRef> AvailableFeatures;
5128  public:
5129    SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5130      assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5131        "SPIR target must use unknown OS");
5132      assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5133        "SPIR target must use unknown environment type");
5134      BigEndian = false;
5135      TLSSupported = false;
5136      LongWidth = LongAlign = 64;
5137      AddrSpaceMap = &SPIRAddrSpaceMap;
5138      // Define available target features
5139      // These must be defined in sorted order!
5140      NoAsmVariants = true;
5141    }
5142    virtual void getTargetDefines(const LangOptions &Opts,
5143                                  MacroBuilder &Builder) const {
5144      DefineStd(Builder, "SPIR", Opts);
5145    }
5146    virtual bool hasFeature(StringRef Feature) const {
5147      return Feature == "spir";
5148    }
5149
5150    virtual void getTargetBuiltins(const Builtin::Info *&Records,
5151                                   unsigned &NumRecords) const {}
5152    virtual const char *getClobbers() const {
5153      return "";
5154    }
5155    virtual void getGCCRegNames(const char * const *&Names,
5156                                unsigned &NumNames) const {}
5157    virtual bool validateAsmConstraint(const char *&Name,
5158                                       TargetInfo::ConstraintInfo &info) const {
5159      return true;
5160    }
5161    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5162                                  unsigned &NumAliases) const {}
5163    virtual BuiltinVaListKind getBuiltinVaListKind() const {
5164      return TargetInfo::VoidPtrBuiltinVaList;
5165    }
5166  };
5167
5168
5169  class SPIR32TargetInfo : public SPIRTargetInfo {
5170  public:
5171    SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5172      PointerWidth = PointerAlign = 32;
5173      SizeType     = TargetInfo::UnsignedInt;
5174      PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5175      DescriptionString
5176        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5177          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5178          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5179          "v512:512:512-v1024:1024:1024";
5180    }
5181    virtual void getTargetDefines(const LangOptions &Opts,
5182                                  MacroBuilder &Builder) const {
5183      DefineStd(Builder, "SPIR32", Opts);
5184    }
5185  };
5186
5187  class SPIR64TargetInfo : public SPIRTargetInfo {
5188  public:
5189    SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5190      PointerWidth = PointerAlign = 64;
5191      SizeType     = TargetInfo::UnsignedLong;
5192      PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5193      DescriptionString
5194        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5195          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5196          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5197          "v512:512:512-v1024:1024:1024";
5198    }
5199    virtual void getTargetDefines(const LangOptions &Opts,
5200                                  MacroBuilder &Builder) const {
5201      DefineStd(Builder, "SPIR64", Opts);
5202    }
5203  };
5204}
5205
5206
5207//===----------------------------------------------------------------------===//
5208// Driver code
5209//===----------------------------------------------------------------------===//
5210
5211static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
5212  llvm::Triple::OSType os = Triple.getOS();
5213
5214  switch (Triple.getArch()) {
5215  default:
5216    return NULL;
5217
5218  case llvm::Triple::hexagon:
5219    return new HexagonTargetInfo(Triple);
5220
5221  case llvm::Triple::aarch64:
5222    switch (os) {
5223    case llvm::Triple::Linux:
5224      return new LinuxTargetInfo<AArch64TargetInfo>(Triple);
5225    default:
5226      return new AArch64TargetInfo(Triple);
5227    }
5228
5229  case llvm::Triple::arm:
5230  case llvm::Triple::thumb:
5231    if (Triple.isOSDarwin())
5232      return new DarwinARMTargetInfo(Triple);
5233
5234    switch (os) {
5235    case llvm::Triple::Linux:
5236      return new LinuxTargetInfo<ARMTargetInfo>(Triple);
5237    case llvm::Triple::FreeBSD:
5238      return new FreeBSDTargetInfo<ARMTargetInfo>(Triple);
5239    case llvm::Triple::NetBSD:
5240      return new NetBSDTargetInfo<ARMTargetInfo>(Triple);
5241    case llvm::Triple::OpenBSD:
5242      return new OpenBSDTargetInfo<ARMTargetInfo>(Triple);
5243    case llvm::Triple::Bitrig:
5244      return new BitrigTargetInfo<ARMTargetInfo>(Triple);
5245    case llvm::Triple::RTEMS:
5246      return new RTEMSTargetInfo<ARMTargetInfo>(Triple);
5247    case llvm::Triple::NaCl:
5248      return new NaClTargetInfo<ARMTargetInfo>(Triple);
5249    default:
5250      return new ARMTargetInfo(Triple);
5251    }
5252
5253  case llvm::Triple::msp430:
5254    return new MSP430TargetInfo(Triple);
5255
5256  case llvm::Triple::mips:
5257    switch (os) {
5258    case llvm::Triple::Linux:
5259      return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
5260    case llvm::Triple::RTEMS:
5261      return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
5262    case llvm::Triple::FreeBSD:
5263      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5264    case llvm::Triple::NetBSD:
5265      return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5266    default:
5267      return new Mips32EBTargetInfo(Triple);
5268    }
5269
5270  case llvm::Triple::mipsel:
5271    switch (os) {
5272    case llvm::Triple::Linux:
5273      return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
5274    case llvm::Triple::RTEMS:
5275      return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
5276    case llvm::Triple::FreeBSD:
5277      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5278    case llvm::Triple::NetBSD:
5279      return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5280    default:
5281      return new Mips32ELTargetInfo(Triple);
5282    }
5283
5284  case llvm::Triple::mips64:
5285    switch (os) {
5286    case llvm::Triple::Linux:
5287      return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
5288    case llvm::Triple::RTEMS:
5289      return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
5290    case llvm::Triple::FreeBSD:
5291      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5292    case llvm::Triple::NetBSD:
5293      return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5294    case llvm::Triple::OpenBSD:
5295      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5296    default:
5297      return new Mips64EBTargetInfo(Triple);
5298    }
5299
5300  case llvm::Triple::mips64el:
5301    switch (os) {
5302    case llvm::Triple::Linux:
5303      return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
5304    case llvm::Triple::RTEMS:
5305      return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
5306    case llvm::Triple::FreeBSD:
5307      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5308    case llvm::Triple::NetBSD:
5309      return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5310    case llvm::Triple::OpenBSD:
5311      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5312    default:
5313      return new Mips64ELTargetInfo(Triple);
5314    }
5315
5316  case llvm::Triple::le32:
5317    switch (os) {
5318      case llvm::Triple::NaCl:
5319        return new NaClTargetInfo<PNaClTargetInfo>(Triple);
5320      default:
5321        return NULL;
5322    }
5323
5324  case llvm::Triple::ppc:
5325    if (Triple.isOSDarwin())
5326      return new DarwinPPC32TargetInfo(Triple);
5327    switch (os) {
5328    case llvm::Triple::Linux:
5329      return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
5330    case llvm::Triple::FreeBSD:
5331      return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
5332    case llvm::Triple::NetBSD:
5333      return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
5334    case llvm::Triple::OpenBSD:
5335      return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
5336    case llvm::Triple::RTEMS:
5337      return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
5338    default:
5339      return new PPC32TargetInfo(Triple);
5340    }
5341
5342  case llvm::Triple::ppc64:
5343    if (Triple.isOSDarwin())
5344      return new DarwinPPC64TargetInfo(Triple);
5345    switch (os) {
5346    case llvm::Triple::Linux:
5347      return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
5348    case llvm::Triple::Lv2:
5349      return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
5350    case llvm::Triple::FreeBSD:
5351      return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
5352    case llvm::Triple::NetBSD:
5353      return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
5354    default:
5355      return new PPC64TargetInfo(Triple);
5356    }
5357
5358  case llvm::Triple::nvptx:
5359    return new NVPTX32TargetInfo(Triple);
5360  case llvm::Triple::nvptx64:
5361    return new NVPTX64TargetInfo(Triple);
5362
5363  case llvm::Triple::mblaze:
5364    return new MBlazeTargetInfo(Triple);
5365
5366  case llvm::Triple::r600:
5367    return new R600TargetInfo(Triple);
5368
5369  case llvm::Triple::sparc:
5370    switch (os) {
5371    case llvm::Triple::Linux:
5372      return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
5373    case llvm::Triple::AuroraUX:
5374      return new AuroraUXSparcV8TargetInfo(Triple);
5375    case llvm::Triple::Solaris:
5376      return new SolarisSparcV8TargetInfo(Triple);
5377    case llvm::Triple::NetBSD:
5378      return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
5379    case llvm::Triple::OpenBSD:
5380      return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
5381    case llvm::Triple::RTEMS:
5382      return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
5383    default:
5384      return new SparcV8TargetInfo(Triple);
5385    }
5386
5387  case llvm::Triple::sparcv9:
5388    switch (os) {
5389    case llvm::Triple::Linux:
5390      return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
5391    case llvm::Triple::AuroraUX:
5392      return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple);
5393    case llvm::Triple::Solaris:
5394      return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
5395    case llvm::Triple::NetBSD:
5396      return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
5397    case llvm::Triple::OpenBSD:
5398      return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
5399    case llvm::Triple::FreeBSD:
5400      return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
5401    default:
5402      return new SparcV9TargetInfo(Triple);
5403    }
5404
5405  case llvm::Triple::systemz:
5406    switch (os) {
5407    case llvm::Triple::Linux:
5408      return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
5409    default:
5410      return new SystemZTargetInfo(Triple);
5411    }
5412
5413  case llvm::Triple::tce:
5414    return new TCETargetInfo(Triple);
5415
5416  case llvm::Triple::x86:
5417    if (Triple.isOSDarwin())
5418      return new DarwinI386TargetInfo(Triple);
5419
5420    switch (os) {
5421    case llvm::Triple::AuroraUX:
5422      return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple);
5423    case llvm::Triple::Linux:
5424      return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
5425    case llvm::Triple::DragonFly:
5426      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
5427    case llvm::Triple::NetBSD:
5428      return new NetBSDI386TargetInfo(Triple);
5429    case llvm::Triple::OpenBSD:
5430      return new OpenBSDI386TargetInfo(Triple);
5431    case llvm::Triple::Bitrig:
5432      return new BitrigI386TargetInfo(Triple);
5433    case llvm::Triple::FreeBSD:
5434      return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
5435    case llvm::Triple::Minix:
5436      return new MinixTargetInfo<X86_32TargetInfo>(Triple);
5437    case llvm::Triple::Solaris:
5438      return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
5439    case llvm::Triple::Cygwin:
5440      return new CygwinX86_32TargetInfo(Triple);
5441    case llvm::Triple::MinGW32:
5442      return new MinGWX86_32TargetInfo(Triple);
5443    case llvm::Triple::Win32:
5444      return new VisualStudioWindowsX86_32TargetInfo(Triple);
5445    case llvm::Triple::Haiku:
5446      return new HaikuX86_32TargetInfo(Triple);
5447    case llvm::Triple::RTEMS:
5448      return new RTEMSX86_32TargetInfo(Triple);
5449    case llvm::Triple::NaCl:
5450      return new NaClTargetInfo<X86_32TargetInfo>(Triple);
5451    default:
5452      return new X86_32TargetInfo(Triple);
5453    }
5454
5455  case llvm::Triple::x86_64:
5456    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5457      return new DarwinX86_64TargetInfo(Triple);
5458
5459    switch (os) {
5460    case llvm::Triple::AuroraUX:
5461      return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple);
5462    case llvm::Triple::Linux:
5463      return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
5464    case llvm::Triple::DragonFly:
5465      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
5466    case llvm::Triple::NetBSD:
5467      return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
5468    case llvm::Triple::OpenBSD:
5469      return new OpenBSDX86_64TargetInfo(Triple);
5470    case llvm::Triple::Bitrig:
5471      return new BitrigX86_64TargetInfo(Triple);
5472    case llvm::Triple::FreeBSD:
5473      return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
5474    case llvm::Triple::Solaris:
5475      return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
5476    case llvm::Triple::MinGW32:
5477      return new MinGWX86_64TargetInfo(Triple);
5478    case llvm::Triple::Win32:   // This is what Triple.h supports now.
5479      return new VisualStudioWindowsX86_64TargetInfo(Triple);
5480    case llvm::Triple::NaCl:
5481      return new NaClTargetInfo<X86_64TargetInfo>(Triple);
5482    default:
5483      return new X86_64TargetInfo(Triple);
5484    }
5485
5486    case llvm::Triple::spir: {
5487      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5488          Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5489        return NULL;
5490      return new SPIR32TargetInfo(Triple);
5491    }
5492    case llvm::Triple::spir64: {
5493      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5494          Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5495        return NULL;
5496      return new SPIR64TargetInfo(Triple);
5497    }
5498  }
5499}
5500
5501/// CreateTargetInfo - Return the target info object for the specified target
5502/// triple.
5503TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5504                                         TargetOptions *Opts) {
5505  llvm::Triple Triple(Opts->Triple);
5506
5507  // Construct the target
5508  OwningPtr<TargetInfo> Target(AllocateTarget(Triple));
5509  if (!Target) {
5510    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5511    return 0;
5512  }
5513  Target->setTargetOpts(Opts);
5514
5515  // Set the target CPU if specified.
5516  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5517    Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5518    return 0;
5519  }
5520
5521  // Set the target ABI if specified.
5522  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5523    Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5524    return 0;
5525  }
5526
5527  // Set the target C++ ABI.
5528  if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5529    Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5530    return 0;
5531  }
5532
5533  // Compute the default target features, we need the target to handle this
5534  // because features may have dependencies on one another.
5535  llvm::StringMap<bool> Features;
5536  Target->getDefaultFeatures(Features);
5537
5538  // Apply the user specified deltas.
5539  // First the enables.
5540  for (std::vector<std::string>::const_iterator
5541         it = Opts->FeaturesAsWritten.begin(),
5542         ie = Opts->FeaturesAsWritten.end();
5543       it != ie; ++it) {
5544    const char *Name = it->c_str();
5545
5546    if (Name[0] != '+')
5547      continue;
5548
5549    // Apply the feature via the target.
5550    if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5551      Diags.Report(diag::err_target_invalid_feature) << Name;
5552      return 0;
5553    }
5554  }
5555
5556  // Then the disables.
5557  for (std::vector<std::string>::const_iterator
5558         it = Opts->FeaturesAsWritten.begin(),
5559         ie = Opts->FeaturesAsWritten.end();
5560       it != ie; ++it) {
5561    const char *Name = it->c_str();
5562
5563    if (Name[0] == '+')
5564      continue;
5565
5566    // Apply the feature via the target.
5567    if (Name[0] != '-' ||
5568        !Target->setFeatureEnabled(Features, Name + 1, false)) {
5569      Diags.Report(diag::err_target_invalid_feature) << Name;
5570      return 0;
5571    }
5572  }
5573
5574  // Add the features to the compile options.
5575  //
5576  // FIXME: If we are completely confident that we have the right set, we only
5577  // need to pass the minuses.
5578  Opts->Features.clear();
5579  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5580         ie = Features.end(); it != ie; ++it)
5581    Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5582  Target->HandleTargetFeatures(Opts->Features);
5583
5584  return Target.take();
5585}
5586