Targets.cpp revision affa3af144eb1ae1b5e6e1c9ca0f979bc6982990 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "5621");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.getOS() == llvm::Triple::IOS) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else {
153    // Note that the Driver allows versions which aren't representable in the
154    // define (because we only get a single digit for the minor and micro
155    // revision numbers). So, we limit them to the maximum representable
156    // version.
157    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159    char Str[5];
160    Str[0] = '0' + (Maj / 10);
161    Str[1] = '0' + (Maj % 10);
162    Str[2] = '0' + std::min(Min, 9U);
163    Str[3] = '0' + std::min(Rev, 9U);
164    Str[4] = '\0';
165    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166  }
167
168  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169}
170
171namespace {
172template<typename Target>
173class DarwinTargetInfo : public OSTargetInfo<Target> {
174protected:
175  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                            MacroBuilder &Builder) const {
177    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                     this->PlatformMinVersion);
179  }
180
181public:
182  DarwinTargetInfo(const std::string& triple) :
183    OSTargetInfo<Target>(triple) {
184      llvm::Triple T = llvm::Triple(triple);
185      this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186      this->MCountName = "\01mcount";
187    }
188
189  virtual std::string isValidSectionSpecifier(StringRef SR) const {
190    // Let MCSectionMachO validate this.
191    StringRef Segment, Section;
192    unsigned TAA, StubSize;
193    bool HasTAA;
194    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                       TAA, HasTAA, StubSize);
196  }
197
198  virtual const char *getStaticInitSectionSpecifier() const {
199    // FIXME: We should return 0 when building kexts.
200    return "__TEXT,__StaticInit,regular,pure_instructions";
201  }
202
203  /// Darwin does not support protected visibility.  Darwin's "default"
204  /// is very similar to ELF's "protected";  Darwin requires a "weak"
205  /// attribute on declarations that can be dynamically replaced.
206  virtual bool hasProtectedVisibility() const {
207    return false;
208  }
209};
210
211
212// DragonFlyBSD Target
213template<typename Target>
214class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215protected:
216  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                            MacroBuilder &Builder) const {
218    // DragonFly defines; list based off of gcc output
219    Builder.defineMacro("__DragonFly__");
220    Builder.defineMacro("__DragonFly_cc_version", "100001");
221    Builder.defineMacro("__ELF__");
222    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223    Builder.defineMacro("__tune_i386__");
224    DefineStd(Builder, "unix", Opts);
225  }
226public:
227  DragonFlyBSDTargetInfo(const std::string &triple)
228    : OSTargetInfo<Target>(triple) {
229      this->UserLabelPrefix = "";
230
231      llvm::Triple Triple(triple);
232      switch (Triple.getArch()) {
233        default:
234        case llvm::Triple::x86:
235        case llvm::Triple::x86_64:
236          this->MCountName = ".mcount";
237          break;
238      }
239  }
240};
241
242// FreeBSD Target
243template<typename Target>
244class FreeBSDTargetInfo : public OSTargetInfo<Target> {
245protected:
246  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247                            MacroBuilder &Builder) const {
248    // FreeBSD defines; list based off of gcc output
249
250    unsigned Release = Triple.getOSMajorVersion();
251    if (Release == 0U)
252      Release = 8;
253
254    Builder.defineMacro("__FreeBSD__", Twine(Release));
255    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257    DefineStd(Builder, "unix", Opts);
258    Builder.defineMacro("__ELF__");
259  }
260public:
261  FreeBSDTargetInfo(const std::string &triple)
262    : OSTargetInfo<Target>(triple) {
263      this->UserLabelPrefix = "";
264
265      llvm::Triple Triple(triple);
266      switch (Triple.getArch()) {
267        default:
268        case llvm::Triple::x86:
269        case llvm::Triple::x86_64:
270          this->MCountName = ".mcount";
271          break;
272        case llvm::Triple::mips:
273        case llvm::Triple::mipsel:
274        case llvm::Triple::ppc:
275        case llvm::Triple::ppc64:
276          this->MCountName = "_mcount";
277          break;
278        case llvm::Triple::arm:
279          this->MCountName = "__mcount";
280          break;
281      }
282
283    }
284};
285
286// Minix Target
287template<typename Target>
288class MinixTargetInfo : public OSTargetInfo<Target> {
289protected:
290  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291                            MacroBuilder &Builder) const {
292    // Minix defines
293
294    Builder.defineMacro("__minix", "3");
295    Builder.defineMacro("_EM_WSIZE", "4");
296    Builder.defineMacro("_EM_PSIZE", "4");
297    Builder.defineMacro("_EM_SSIZE", "2");
298    Builder.defineMacro("_EM_LSIZE", "4");
299    Builder.defineMacro("_EM_FSIZE", "4");
300    Builder.defineMacro("_EM_DSIZE", "8");
301    Builder.defineMacro("__ELF__");
302    DefineStd(Builder, "unix", Opts);
303  }
304public:
305  MinixTargetInfo(const std::string &triple)
306    : OSTargetInfo<Target>(triple) {
307      this->UserLabelPrefix = "";
308    }
309};
310
311// Linux target
312template<typename Target>
313class LinuxTargetInfo : public OSTargetInfo<Target> {
314protected:
315  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                            MacroBuilder &Builder) const {
317    // Linux defines; list based off of gcc output
318    DefineStd(Builder, "unix", Opts);
319    DefineStd(Builder, "linux", Opts);
320    Builder.defineMacro("__gnu_linux__");
321    Builder.defineMacro("__ELF__");
322    if (Triple.getEnvironment() == llvm::Triple::Android)
323      Builder.defineMacro("__ANDROID__", "1");
324    if (Opts.POSIXThreads)
325      Builder.defineMacro("_REENTRANT");
326    if (Opts.CPlusPlus)
327      Builder.defineMacro("_GNU_SOURCE");
328  }
329public:
330  LinuxTargetInfo(const std::string& triple)
331    : OSTargetInfo<Target>(triple) {
332    this->UserLabelPrefix = "";
333    this->WIntType = TargetInfo::UnsignedInt;
334  }
335
336  virtual const char *getStaticInitSectionSpecifier() const {
337    return ".text.startup";
338  }
339};
340
341// NetBSD Target
342template<typename Target>
343class NetBSDTargetInfo : public OSTargetInfo<Target> {
344protected:
345  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346                            MacroBuilder &Builder) const {
347    // NetBSD defines; list based off of gcc output
348    Builder.defineMacro("__NetBSD__");
349    Builder.defineMacro("__unix__");
350    Builder.defineMacro("__ELF__");
351    if (Opts.POSIXThreads)
352      Builder.defineMacro("_POSIX_THREADS");
353  }
354public:
355  NetBSDTargetInfo(const std::string &triple)
356    : OSTargetInfo<Target>(triple) {
357      this->UserLabelPrefix = "";
358    }
359};
360
361// OpenBSD Target
362template<typename Target>
363class OpenBSDTargetInfo : public OSTargetInfo<Target> {
364protected:
365  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366                            MacroBuilder &Builder) const {
367    // OpenBSD defines; list based off of gcc output
368
369    Builder.defineMacro("__OpenBSD__");
370    DefineStd(Builder, "unix", Opts);
371    Builder.defineMacro("__ELF__");
372    if (Opts.POSIXThreads)
373      Builder.defineMacro("_REENTRANT");
374  }
375public:
376  OpenBSDTargetInfo(const std::string &triple)
377    : OSTargetInfo<Target>(triple) {
378      this->UserLabelPrefix = "";
379      this->TLSSupported = false;
380
381      llvm::Triple Triple(triple);
382      switch (Triple.getArch()) {
383        default:
384        case llvm::Triple::x86:
385        case llvm::Triple::x86_64:
386        case llvm::Triple::arm:
387        case llvm::Triple::sparc:
388          this->MCountName = "__mcount";
389          break;
390        case llvm::Triple::mips64:
391        case llvm::Triple::mips64el:
392        case llvm::Triple::ppc:
393        case llvm::Triple::sparcv9:
394          this->MCountName = "_mcount";
395          break;
396      }
397  }
398};
399
400// Bitrig Target
401template<typename Target>
402class BitrigTargetInfo : public OSTargetInfo<Target> {
403protected:
404  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405                            MacroBuilder &Builder) const {
406    // Bitrig defines; list based off of gcc output
407
408    Builder.defineMacro("__Bitrig__");
409    DefineStd(Builder, "unix", Opts);
410    Builder.defineMacro("__ELF__");
411    if (Opts.POSIXThreads)
412      Builder.defineMacro("_REENTRANT");
413  }
414public:
415  BitrigTargetInfo(const std::string &triple)
416    : OSTargetInfo<Target>(triple) {
417      this->UserLabelPrefix = "";
418      this->TLSSupported = false;
419      this->MCountName = "__mcount";
420  }
421};
422
423// PSP Target
424template<typename Target>
425class PSPTargetInfo : public OSTargetInfo<Target> {
426protected:
427  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428                            MacroBuilder &Builder) const {
429    // PSP defines; list based on the output of the pspdev gcc toolchain.
430    Builder.defineMacro("PSP");
431    Builder.defineMacro("_PSP");
432    Builder.defineMacro("__psp__");
433    Builder.defineMacro("__ELF__");
434  }
435public:
436  PSPTargetInfo(const std::string& triple)
437    : OSTargetInfo<Target>(triple) {
438    this->UserLabelPrefix = "";
439  }
440};
441
442// PS3 PPU Target
443template<typename Target>
444class PS3PPUTargetInfo : public OSTargetInfo<Target> {
445protected:
446  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                            MacroBuilder &Builder) const {
448    // PS3 PPU defines.
449    Builder.defineMacro("__PPC__");
450    Builder.defineMacro("__PPU__");
451    Builder.defineMacro("__CELLOS_LV2__");
452    Builder.defineMacro("__ELF__");
453    Builder.defineMacro("__LP32__");
454    Builder.defineMacro("_ARCH_PPC64");
455    Builder.defineMacro("__powerpc64__");
456  }
457public:
458  PS3PPUTargetInfo(const std::string& triple)
459    : OSTargetInfo<Target>(triple) {
460    this->UserLabelPrefix = "";
461    this->LongWidth = this->LongAlign = 32;
462    this->PointerWidth = this->PointerAlign = 32;
463    this->IntMaxType = TargetInfo::SignedLongLong;
464    this->UIntMaxType = TargetInfo::UnsignedLongLong;
465    this->Int64Type = TargetInfo::SignedLongLong;
466    this->SizeType = TargetInfo::UnsignedInt;
467    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
469  }
470};
471
472// FIXME: Need a real SPU target.
473// PS3 SPU Target
474template<typename Target>
475class PS3SPUTargetInfo : public OSTargetInfo<Target> {
476protected:
477  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478                            MacroBuilder &Builder) const {
479    // PS3 PPU defines.
480    Builder.defineMacro("__SPU__");
481    Builder.defineMacro("__ELF__");
482  }
483public:
484  PS3SPUTargetInfo(const std::string& triple)
485    : OSTargetInfo<Target>(triple) {
486    this->UserLabelPrefix = "";
487  }
488};
489
490// AuroraUX target
491template<typename Target>
492class AuroraUXTargetInfo : public OSTargetInfo<Target> {
493protected:
494  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                            MacroBuilder &Builder) const {
496    DefineStd(Builder, "sun", Opts);
497    DefineStd(Builder, "unix", Opts);
498    Builder.defineMacro("__ELF__");
499    Builder.defineMacro("__svr4__");
500    Builder.defineMacro("__SVR4");
501  }
502public:
503  AuroraUXTargetInfo(const std::string& triple)
504    : OSTargetInfo<Target>(triple) {
505    this->UserLabelPrefix = "";
506    this->WCharType = this->SignedLong;
507    // FIXME: WIntType should be SignedLong
508  }
509};
510
511// Solaris target
512template<typename Target>
513class SolarisTargetInfo : public OSTargetInfo<Target> {
514protected:
515  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516                            MacroBuilder &Builder) const {
517    DefineStd(Builder, "sun", Opts);
518    DefineStd(Builder, "unix", Opts);
519    Builder.defineMacro("__ELF__");
520    Builder.defineMacro("__svr4__");
521    Builder.defineMacro("__SVR4");
522    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523    // newer, but to 500 for everything else.  feature_test.h has a check to
524    // ensure that you are not using C99 with an old version of X/Open or C89
525    // with a new version.
526    if (Opts.C99 || Opts.C11)
527      Builder.defineMacro("_XOPEN_SOURCE", "600");
528    else
529      Builder.defineMacro("_XOPEN_SOURCE", "500");
530    if (Opts.CPlusPlus)
531      Builder.defineMacro("__C99FEATURES__");
532    Builder.defineMacro("_LARGEFILE_SOURCE");
533    Builder.defineMacro("_LARGEFILE64_SOURCE");
534    Builder.defineMacro("__EXTENSIONS__");
535    Builder.defineMacro("_REENTRANT");
536  }
537public:
538  SolarisTargetInfo(const std::string& triple)
539    : OSTargetInfo<Target>(triple) {
540    this->UserLabelPrefix = "";
541    this->WCharType = this->SignedInt;
542    // FIXME: WIntType should be SignedLong
543  }
544};
545
546// Windows target
547template<typename Target>
548class WindowsTargetInfo : public OSTargetInfo<Target> {
549protected:
550  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551                            MacroBuilder &Builder) const {
552    Builder.defineMacro("_WIN32");
553  }
554  void getVisualStudioDefines(const LangOptions &Opts,
555                              MacroBuilder &Builder) const {
556    if (Opts.CPlusPlus) {
557      if (Opts.RTTI)
558        Builder.defineMacro("_CPPRTTI");
559
560      if (Opts.Exceptions)
561        Builder.defineMacro("_CPPUNWIND");
562    }
563
564    if (!Opts.CharIsSigned)
565      Builder.defineMacro("_CHAR_UNSIGNED");
566
567    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568    //        but it works for now.
569    if (Opts.POSIXThreads)
570      Builder.defineMacro("_MT");
571
572    if (Opts.MSCVersion != 0)
573      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
574
575    if (Opts.MicrosoftExt) {
576      Builder.defineMacro("_MSC_EXTENSIONS");
577
578      if (Opts.CPlusPlus11) {
579        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
582      }
583    }
584
585    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
586  }
587
588public:
589  WindowsTargetInfo(const std::string &triple)
590    : OSTargetInfo<Target>(triple) {}
591};
592
593template <typename Target>
594class NaClTargetInfo : public OSTargetInfo<Target> {
595 protected:
596  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597                            MacroBuilder &Builder) const {
598    if (Opts.POSIXThreads)
599      Builder.defineMacro("_REENTRANT");
600    if (Opts.CPlusPlus)
601      Builder.defineMacro("_GNU_SOURCE");
602
603    DefineStd(Builder, "unix", Opts);
604    Builder.defineMacro("__ELF__");
605    Builder.defineMacro("__native_client__");
606  }
607 public:
608  NaClTargetInfo(const std::string &triple)
609    : OSTargetInfo<Target>(triple) {
610    this->UserLabelPrefix = "";
611    this->LongAlign = 32;
612    this->LongWidth = 32;
613    this->PointerAlign = 32;
614    this->PointerWidth = 32;
615    this->IntMaxType = TargetInfo::SignedLongLong;
616    this->UIntMaxType = TargetInfo::UnsignedLongLong;
617    this->Int64Type = TargetInfo::SignedLongLong;
618    this->DoubleAlign = 64;
619    this->LongDoubleWidth = 64;
620    this->LongDoubleAlign = 64;
621    this->SizeType = TargetInfo::UnsignedInt;
622    this->PtrDiffType = TargetInfo::SignedInt;
623    this->IntPtrType = TargetInfo::SignedInt;
624    this->RegParmMax = 2;
625    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
626    this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
627                              "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
628  }
629  virtual typename Target::CallingConvCheckResult checkCallingConvention(
630      CallingConv CC) const {
631    return CC == CC_PnaclCall ? Target::CCCR_OK :
632        Target::checkCallingConvention(CC);
633  }
634};
635} // end anonymous namespace.
636
637//===----------------------------------------------------------------------===//
638// Specific target implementations.
639//===----------------------------------------------------------------------===//
640
641namespace {
642// PPC abstract base class
643class PPCTargetInfo : public TargetInfo {
644  static const Builtin::Info BuiltinInfo[];
645  static const char * const GCCRegNames[];
646  static const TargetInfo::GCCRegAlias GCCRegAliases[];
647  std::string CPU;
648public:
649  PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
650    LongDoubleWidth = LongDoubleAlign = 128;
651    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
652  }
653
654  /// \brief Flags for architecture specific defines.
655  typedef enum {
656    ArchDefineNone  = 0,
657    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
658    ArchDefinePpcgr = 1 << 1,
659    ArchDefinePpcsq = 1 << 2,
660    ArchDefine440   = 1 << 3,
661    ArchDefine603   = 1 << 4,
662    ArchDefine604   = 1 << 5,
663    ArchDefinePwr4  = 1 << 6,
664    ArchDefinePwr5  = 1 << 7,
665    ArchDefinePwr5x = 1 << 8,
666    ArchDefinePwr6  = 1 << 9,
667    ArchDefinePwr6x = 1 << 10,
668    ArchDefinePwr7  = 1 << 11,
669    ArchDefineA2    = 1 << 12,
670    ArchDefineA2q   = 1 << 13
671  } ArchDefineTypes;
672
673  // Note: GCC recognizes the following additional cpus:
674  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
675  //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
676  //  titan, rs64.
677  virtual bool setCPU(const std::string &Name) {
678    bool CPUKnown = llvm::StringSwitch<bool>(Name)
679      .Case("generic", true)
680      .Case("440", true)
681      .Case("450", true)
682      .Case("601", true)
683      .Case("602", true)
684      .Case("603", true)
685      .Case("603e", true)
686      .Case("603ev", true)
687      .Case("604", true)
688      .Case("604e", true)
689      .Case("620", true)
690      .Case("630", true)
691      .Case("g3", true)
692      .Case("7400", true)
693      .Case("g4", true)
694      .Case("7450", true)
695      .Case("g4+", true)
696      .Case("750", true)
697      .Case("970", true)
698      .Case("g5", true)
699      .Case("a2", true)
700      .Case("a2q", true)
701      .Case("e500mc", true)
702      .Case("e5500", true)
703      .Case("power3", true)
704      .Case("pwr3", true)
705      .Case("power4", true)
706      .Case("pwr4", true)
707      .Case("power5", true)
708      .Case("pwr5", true)
709      .Case("power5x", true)
710      .Case("pwr5x", true)
711      .Case("power6", true)
712      .Case("pwr6", true)
713      .Case("power6x", true)
714      .Case("pwr6x", true)
715      .Case("power7", true)
716      .Case("pwr7", true)
717      .Case("powerpc", true)
718      .Case("ppc", true)
719      .Case("powerpc64", true)
720      .Case("ppc64", true)
721      .Default(false);
722
723    if (CPUKnown)
724      CPU = Name;
725
726    return CPUKnown;
727  }
728
729  virtual void getTargetBuiltins(const Builtin::Info *&Records,
730                                 unsigned &NumRecords) const {
731    Records = BuiltinInfo;
732    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
733  }
734
735  virtual bool isCLZForZeroUndef() const { return false; }
736
737  virtual void getTargetDefines(const LangOptions &Opts,
738                                MacroBuilder &Builder) const;
739
740  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
741
742  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
743                                 StringRef Name,
744                                 bool Enabled) const;
745
746  virtual bool hasFeature(StringRef Feature) const;
747
748  virtual void getGCCRegNames(const char * const *&Names,
749                              unsigned &NumNames) const;
750  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
751                                unsigned &NumAliases) const;
752  virtual bool validateAsmConstraint(const char *&Name,
753                                     TargetInfo::ConstraintInfo &Info) const {
754    switch (*Name) {
755    default: return false;
756    case 'O': // Zero
757      break;
758    case 'b': // Base register
759    case 'f': // Floating point register
760      Info.setAllowsRegister();
761      break;
762    // FIXME: The following are added to allow parsing.
763    // I just took a guess at what the actions should be.
764    // Also, is more specific checking needed?  I.e. specific registers?
765    case 'd': // Floating point register (containing 64-bit value)
766    case 'v': // Altivec vector register
767      Info.setAllowsRegister();
768      break;
769    case 'w':
770      switch (Name[1]) {
771        case 'd':// VSX vector register to hold vector double data
772        case 'f':// VSX vector register to hold vector float data
773        case 's':// VSX vector register to hold scalar float data
774        case 'a':// Any VSX register
775          break;
776        default:
777          return false;
778      }
779      Info.setAllowsRegister();
780      Name++; // Skip over 'w'.
781      break;
782    case 'h': // `MQ', `CTR', or `LINK' register
783    case 'q': // `MQ' register
784    case 'c': // `CTR' register
785    case 'l': // `LINK' register
786    case 'x': // `CR' register (condition register) number 0
787    case 'y': // `CR' register (condition register)
788    case 'z': // `XER[CA]' carry bit (part of the XER register)
789      Info.setAllowsRegister();
790      break;
791    case 'I': // Signed 16-bit constant
792    case 'J': // Unsigned 16-bit constant shifted left 16 bits
793              //  (use `L' instead for SImode constants)
794    case 'K': // Unsigned 16-bit constant
795    case 'L': // Signed 16-bit constant shifted left 16 bits
796    case 'M': // Constant larger than 31
797    case 'N': // Exact power of 2
798    case 'P': // Constant whose negation is a signed 16-bit constant
799    case 'G': // Floating point constant that can be loaded into a
800              // register with one instruction per word
801    case 'H': // Integer/Floating point constant that can be loaded
802              // into a register using three instructions
803      break;
804    case 'm': // Memory operand. Note that on PowerPC targets, m can
805              // include addresses that update the base register. It
806              // is therefore only safe to use `m' in an asm statement
807              // if that asm statement accesses the operand exactly once.
808              // The asm statement must also use `%U<opno>' as a
809              // placeholder for the "update" flag in the corresponding
810              // load or store instruction. For example:
811              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
812              // is correct but:
813              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
814              // is not. Use es rather than m if you don't want the base
815              // register to be updated.
816    case 'e':
817      if (Name[1] != 's')
818          return false;
819              // es: A "stable" memory operand; that is, one which does not
820              // include any automodification of the base register. Unlike
821              // `m', this constraint can be used in asm statements that
822              // might access the operand several times, or that might not
823              // access it at all.
824      Info.setAllowsMemory();
825      Name++; // Skip over 'e'.
826      break;
827    case 'Q': // Memory operand that is an offset from a register (it is
828              // usually better to use `m' or `es' in asm statements)
829    case 'Z': // Memory operand that is an indexed or indirect from a
830              // register (it is usually better to use `m' or `es' in
831              // asm statements)
832      Info.setAllowsMemory();
833      Info.setAllowsRegister();
834      break;
835    case 'R': // AIX TOC entry
836    case 'a': // Address operand that is an indexed or indirect from a
837              // register (`p' is preferable for asm statements)
838    case 'S': // Constant suitable as a 64-bit mask operand
839    case 'T': // Constant suitable as a 32-bit mask operand
840    case 'U': // System V Release 4 small data area reference
841    case 't': // AND masks that can be performed by two rldic{l, r}
842              // instructions
843    case 'W': // Vector constant that does not require memory
844    case 'j': // Vector constant that is all zeros.
845      break;
846    // End FIXME.
847    }
848    return true;
849  }
850  virtual const char *getClobbers() const {
851    return "";
852  }
853  int getEHDataRegisterNumber(unsigned RegNo) const {
854    if (RegNo == 0) return 3;
855    if (RegNo == 1) return 4;
856    return -1;
857  }
858};
859
860const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
861#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
862#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
863                                              ALL_LANGUAGES },
864#include "clang/Basic/BuiltinsPPC.def"
865};
866
867
868/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
869/// #defines that are not tied to a specific subtarget.
870void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
871                                     MacroBuilder &Builder) const {
872  // Target identification.
873  Builder.defineMacro("__ppc__");
874  Builder.defineMacro("_ARCH_PPC");
875  Builder.defineMacro("__powerpc__");
876  Builder.defineMacro("__POWERPC__");
877  if (PointerWidth == 64) {
878    Builder.defineMacro("_ARCH_PPC64");
879    Builder.defineMacro("__powerpc64__");
880    Builder.defineMacro("__ppc64__");
881  } else {
882    Builder.defineMacro("__ppc__");
883  }
884
885  // Target properties.
886  if (getTriple().getOS() != llvm::Triple::NetBSD &&
887      getTriple().getOS() != llvm::Triple::OpenBSD)
888    Builder.defineMacro("_BIG_ENDIAN");
889  Builder.defineMacro("__BIG_ENDIAN__");
890
891  // Subtarget options.
892  Builder.defineMacro("__NATURAL_ALIGNMENT__");
893  Builder.defineMacro("__REGISTER_PREFIX__", "");
894
895  // FIXME: Should be controlled by command line option.
896  Builder.defineMacro("__LONG_DOUBLE_128__");
897
898  if (Opts.AltiVec) {
899    Builder.defineMacro("__VEC__", "10206");
900    Builder.defineMacro("__ALTIVEC__");
901  }
902
903  // CPU identification.
904  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
905    .Case("440",   ArchDefineName)
906    .Case("450",   ArchDefineName | ArchDefine440)
907    .Case("601",   ArchDefineName)
908    .Case("602",   ArchDefineName | ArchDefinePpcgr)
909    .Case("603",   ArchDefineName | ArchDefinePpcgr)
910    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
911    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
912    .Case("604",   ArchDefineName | ArchDefinePpcgr)
913    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
914    .Case("620",   ArchDefineName | ArchDefinePpcgr)
915    .Case("630",   ArchDefineName | ArchDefinePpcgr)
916    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
917    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
918    .Case("750",   ArchDefineName | ArchDefinePpcgr)
919    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
920                     | ArchDefinePpcsq)
921    .Case("a2",    ArchDefineA2)
922    .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
923    .Case("pwr3",  ArchDefinePpcgr)
924    .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
925    .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
926                     | ArchDefinePpcsq)
927    .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
928                     | ArchDefinePpcgr | ArchDefinePpcsq)
929    .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
930                     | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
931    .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
932                     | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
933                     | ArchDefinePpcsq)
934    .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
935                     | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
936                     | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
937    .Case("power3",  ArchDefinePpcgr)
938    .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
939    .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
940                       | ArchDefinePpcsq)
941    .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
942                       | ArchDefinePpcgr | ArchDefinePpcsq)
943    .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
944                       | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
945    .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
946                       | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
947                       | ArchDefinePpcsq)
948    .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
949                       | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
950                       | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
951    .Default(ArchDefineNone);
952
953  if (defs & ArchDefineName)
954    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
955  if (defs & ArchDefinePpcgr)
956    Builder.defineMacro("_ARCH_PPCGR");
957  if (defs & ArchDefinePpcsq)
958    Builder.defineMacro("_ARCH_PPCSQ");
959  if (defs & ArchDefine440)
960    Builder.defineMacro("_ARCH_440");
961  if (defs & ArchDefine603)
962    Builder.defineMacro("_ARCH_603");
963  if (defs & ArchDefine604)
964    Builder.defineMacro("_ARCH_604");
965  if (defs & ArchDefinePwr4)
966    Builder.defineMacro("_ARCH_PWR4");
967  if (defs & ArchDefinePwr5)
968    Builder.defineMacro("_ARCH_PWR5");
969  if (defs & ArchDefinePwr5x)
970    Builder.defineMacro("_ARCH_PWR5X");
971  if (defs & ArchDefinePwr6)
972    Builder.defineMacro("_ARCH_PWR6");
973  if (defs & ArchDefinePwr6x)
974    Builder.defineMacro("_ARCH_PWR6X");
975  if (defs & ArchDefinePwr7)
976    Builder.defineMacro("_ARCH_PWR7");
977  if (defs & ArchDefineA2)
978    Builder.defineMacro("_ARCH_A2");
979  if (defs & ArchDefineA2q) {
980    Builder.defineMacro("_ARCH_A2Q");
981    Builder.defineMacro("_ARCH_QP");
982  }
983
984  if (getTriple().getVendor() == llvm::Triple::BGQ) {
985    Builder.defineMacro("__bg__");
986    Builder.defineMacro("__THW_BLUEGENE__");
987    Builder.defineMacro("__bgq__");
988    Builder.defineMacro("__TOS_BGQ__");
989  }
990
991  // FIXME: The following are not yet generated here by Clang, but are
992  //        generated by GCC:
993  //
994  //   _SOFT_FLOAT_
995  //   __RECIP_PRECISION__
996  //   __APPLE_ALTIVEC__
997  //   __VSX__
998  //   __RECIP__
999  //   __RECIPF__
1000  //   __RSQRTE__
1001  //   __RSQRTEF__
1002  //   _SOFT_DOUBLE_
1003  //   __NO_LWSYNC__
1004  //   __HAVE_BSWAP__
1005  //   __LONGDOUBLE128
1006  //   __CMODEL_MEDIUM__
1007  //   __CMODEL_LARGE__
1008  //   _CALL_SYSV
1009  //   _CALL_DARWIN
1010  //   __NO_FPRS__
1011}
1012
1013void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1014  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1015    .Case("7400", true)
1016    .Case("g4", true)
1017    .Case("7450", true)
1018    .Case("g4+", true)
1019    .Case("970", true)
1020    .Case("g5", true)
1021    .Case("pwr6", true)
1022    .Case("pwr7", true)
1023    .Case("ppc64", true)
1024    .Default(false);
1025
1026  Features["qpx"] = (CPU == "a2q");
1027}
1028
1029bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1030                                         StringRef Name,
1031                                         bool Enabled) const {
1032  if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1033      Name == "popcntd" || Name == "qpx") {
1034    Features[Name] = Enabled;
1035    return true;
1036  }
1037
1038  return false;
1039}
1040
1041bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1042  return Feature == "powerpc";
1043}
1044
1045
1046const char * const PPCTargetInfo::GCCRegNames[] = {
1047  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1048  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1049  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1050  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1051  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1052  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1053  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1054  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1055  "mq", "lr", "ctr", "ap",
1056  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1057  "xer",
1058  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1059  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1060  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1061  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1062  "vrsave", "vscr",
1063  "spe_acc", "spefscr",
1064  "sfp"
1065};
1066
1067void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1068                                   unsigned &NumNames) const {
1069  Names = GCCRegNames;
1070  NumNames = llvm::array_lengthof(GCCRegNames);
1071}
1072
1073const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1074  // While some of these aliases do map to different registers
1075  // they still share the same register name.
1076  { { "0" }, "r0" },
1077  { { "1"}, "r1" },
1078  { { "2" }, "r2" },
1079  { { "3" }, "r3" },
1080  { { "4" }, "r4" },
1081  { { "5" }, "r5" },
1082  { { "6" }, "r6" },
1083  { { "7" }, "r7" },
1084  { { "8" }, "r8" },
1085  { { "9" }, "r9" },
1086  { { "10" }, "r10" },
1087  { { "11" }, "r11" },
1088  { { "12" }, "r12" },
1089  { { "13" }, "r13" },
1090  { { "14" }, "r14" },
1091  { { "15" }, "r15" },
1092  { { "16" }, "r16" },
1093  { { "17" }, "r17" },
1094  { { "18" }, "r18" },
1095  { { "19" }, "r19" },
1096  { { "20" }, "r20" },
1097  { { "21" }, "r21" },
1098  { { "22" }, "r22" },
1099  { { "23" }, "r23" },
1100  { { "24" }, "r24" },
1101  { { "25" }, "r25" },
1102  { { "26" }, "r26" },
1103  { { "27" }, "r27" },
1104  { { "28" }, "r28" },
1105  { { "29" }, "r29" },
1106  { { "30" }, "r30" },
1107  { { "31" }, "r31" },
1108  { { "fr0" }, "f0" },
1109  { { "fr1" }, "f1" },
1110  { { "fr2" }, "f2" },
1111  { { "fr3" }, "f3" },
1112  { { "fr4" }, "f4" },
1113  { { "fr5" }, "f5" },
1114  { { "fr6" }, "f6" },
1115  { { "fr7" }, "f7" },
1116  { { "fr8" }, "f8" },
1117  { { "fr9" }, "f9" },
1118  { { "fr10" }, "f10" },
1119  { { "fr11" }, "f11" },
1120  { { "fr12" }, "f12" },
1121  { { "fr13" }, "f13" },
1122  { { "fr14" }, "f14" },
1123  { { "fr15" }, "f15" },
1124  { { "fr16" }, "f16" },
1125  { { "fr17" }, "f17" },
1126  { { "fr18" }, "f18" },
1127  { { "fr19" }, "f19" },
1128  { { "fr20" }, "f20" },
1129  { { "fr21" }, "f21" },
1130  { { "fr22" }, "f22" },
1131  { { "fr23" }, "f23" },
1132  { { "fr24" }, "f24" },
1133  { { "fr25" }, "f25" },
1134  { { "fr26" }, "f26" },
1135  { { "fr27" }, "f27" },
1136  { { "fr28" }, "f28" },
1137  { { "fr29" }, "f29" },
1138  { { "fr30" }, "f30" },
1139  { { "fr31" }, "f31" },
1140  { { "cc" }, "cr0" },
1141};
1142
1143void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1144                                     unsigned &NumAliases) const {
1145  Aliases = GCCRegAliases;
1146  NumAliases = llvm::array_lengthof(GCCRegAliases);
1147}
1148} // end anonymous namespace.
1149
1150namespace {
1151class PPC32TargetInfo : public PPCTargetInfo {
1152public:
1153  PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1154    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1155                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1156
1157    switch (getTriple().getOS()) {
1158    case llvm::Triple::Linux:
1159    case llvm::Triple::FreeBSD:
1160    case llvm::Triple::NetBSD:
1161      SizeType = UnsignedInt;
1162      PtrDiffType = SignedInt;
1163      IntPtrType = SignedInt;
1164      break;
1165    default:
1166      break;
1167    }
1168
1169    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1170      LongDoubleWidth = LongDoubleAlign = 64;
1171      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1172    }
1173
1174    // PPC32 supports atomics up to 4 bytes.
1175    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1176  }
1177
1178  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1179    // This is the ELF definition, and is overridden by the Darwin sub-target
1180    return TargetInfo::PowerABIBuiltinVaList;
1181  }
1182};
1183} // end anonymous namespace.
1184
1185namespace {
1186class PPC64TargetInfo : public PPCTargetInfo {
1187public:
1188  PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1189    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1190    IntMaxType = SignedLong;
1191    UIntMaxType = UnsignedLong;
1192    Int64Type = SignedLong;
1193
1194    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1195      LongDoubleWidth = LongDoubleAlign = 64;
1196      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1197      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1198                          "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1199                          "v128:128:128-n32:64";
1200    } else
1201      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1202                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1203                          "v128:128:128-n32:64";
1204
1205    // PPC64 supports atomics up to 8 bytes.
1206    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1207  }
1208  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1209    return TargetInfo::CharPtrBuiltinVaList;
1210  }
1211};
1212} // end anonymous namespace.
1213
1214
1215namespace {
1216class DarwinPPC32TargetInfo :
1217  public DarwinTargetInfo<PPC32TargetInfo> {
1218public:
1219  DarwinPPC32TargetInfo(const std::string& triple)
1220    : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1221    HasAlignMac68kSupport = true;
1222    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1223    LongLongAlign = 32;
1224    SuitableAlign = 128;
1225    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1226                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1227  }
1228  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1229    return TargetInfo::CharPtrBuiltinVaList;
1230  }
1231};
1232
1233class DarwinPPC64TargetInfo :
1234  public DarwinTargetInfo<PPC64TargetInfo> {
1235public:
1236  DarwinPPC64TargetInfo(const std::string& triple)
1237    : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1238    HasAlignMac68kSupport = true;
1239    SuitableAlign = 128;
1240    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1241                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1242  }
1243};
1244} // end anonymous namespace.
1245
1246namespace {
1247  static const unsigned NVPTXAddrSpaceMap[] = {
1248    1,    // opencl_global
1249    3,    // opencl_local
1250    4,    // opencl_constant
1251    1,    // cuda_device
1252    4,    // cuda_constant
1253    3,    // cuda_shared
1254  };
1255  class NVPTXTargetInfo : public TargetInfo {
1256    static const char * const GCCRegNames[];
1257    static const Builtin::Info BuiltinInfo[];
1258    std::vector<StringRef> AvailableFeatures;
1259  public:
1260    NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1261      BigEndian = false;
1262      TLSSupported = false;
1263      LongWidth = LongAlign = 64;
1264      AddrSpaceMap = &NVPTXAddrSpaceMap;
1265      // Define available target features
1266      // These must be defined in sorted order!
1267      NoAsmVariants = true;
1268    }
1269    virtual void getTargetDefines(const LangOptions &Opts,
1270                                  MacroBuilder &Builder) const {
1271      Builder.defineMacro("__PTX__");
1272      Builder.defineMacro("__NVPTX__");
1273    }
1274    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1275                                   unsigned &NumRecords) const {
1276      Records = BuiltinInfo;
1277      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1278    }
1279    virtual bool hasFeature(StringRef Feature) const {
1280      return Feature == "ptx" || Feature == "nvptx";
1281    }
1282
1283    virtual void getGCCRegNames(const char * const *&Names,
1284                                unsigned &NumNames) const;
1285    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1286                                  unsigned &NumAliases) const {
1287      // No aliases.
1288      Aliases = 0;
1289      NumAliases = 0;
1290    }
1291    virtual bool validateAsmConstraint(const char *&Name,
1292                                       TargetInfo::ConstraintInfo &info) const {
1293      // FIXME: implement
1294      return true;
1295    }
1296    virtual const char *getClobbers() const {
1297      // FIXME: Is this really right?
1298      return "";
1299    }
1300    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1301      // FIXME: implement
1302      return TargetInfo::CharPtrBuiltinVaList;
1303    }
1304    virtual bool setCPU(const std::string &Name) {
1305      bool Valid = llvm::StringSwitch<bool>(Name)
1306        .Case("sm_20", true)
1307        .Case("sm_21", true)
1308        .Case("sm_30", true)
1309        .Case("sm_35", true)
1310        .Default(false);
1311
1312      return Valid;
1313    }
1314    virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1315                                   StringRef Name,
1316                                   bool Enabled) const;
1317  };
1318
1319  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1320#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1321#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1322                                              ALL_LANGUAGES },
1323#include "clang/Basic/BuiltinsNVPTX.def"
1324  };
1325
1326  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1327    "r0"
1328  };
1329
1330  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1331                                     unsigned &NumNames) const {
1332    Names = GCCRegNames;
1333    NumNames = llvm::array_lengthof(GCCRegNames);
1334  }
1335
1336  bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1337                                          StringRef Name,
1338                                          bool Enabled) const {
1339    if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1340                          Name)) {
1341      Features[Name] = Enabled;
1342      return true;
1343    } else {
1344      return false;
1345    }
1346  }
1347
1348  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1349  public:
1350    NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1351      PointerWidth = PointerAlign = 32;
1352      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1353      DescriptionString
1354        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1355          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1356          "n16:32:64";
1357  }
1358  };
1359
1360  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1361  public:
1362    NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1363      PointerWidth = PointerAlign = 64;
1364      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1365      DescriptionString
1366        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1367          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1368          "n16:32:64";
1369  }
1370  };
1371}
1372
1373namespace {
1374
1375static const unsigned R600AddrSpaceMap[] = {
1376  1,    // opencl_global
1377  3,    // opencl_local
1378  2,    // opencl_constant
1379  1,    // cuda_device
1380  2,    // cuda_constant
1381  3     // cuda_shared
1382};
1383
1384static const char *DescriptionStringR600 =
1385  "e"
1386  "-p:32:32:32"
1387  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1388  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1389  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1390  "-n32:64";
1391
1392static const char *DescriptionStringR600DoubleOps =
1393  "e"
1394  "-p:32:32:32"
1395  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1396  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1397  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1398  "-n32:64";
1399
1400static const char *DescriptionStringSI =
1401  "e"
1402  "-p:64:64:64"
1403  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1404  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1405  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1406  "-n32:64";
1407
1408class R600TargetInfo : public TargetInfo {
1409  /// \brief The GPU profiles supported by the R600 target.
1410  enum GPUKind {
1411    GK_NONE,
1412    GK_R600,
1413    GK_R600_DOUBLE_OPS,
1414    GK_R700,
1415    GK_R700_DOUBLE_OPS,
1416    GK_EVERGREEN,
1417    GK_EVERGREEN_DOUBLE_OPS,
1418    GK_NORTHERN_ISLANDS,
1419    GK_CAYMAN,
1420    GK_SOUTHERN_ISLANDS
1421  } GPU;
1422
1423public:
1424  R600TargetInfo(const std::string& triple)
1425    : TargetInfo(triple),
1426      GPU(GK_R600) {
1427    DescriptionString = DescriptionStringR600;
1428    AddrSpaceMap = &R600AddrSpaceMap;
1429  }
1430
1431  virtual const char * getClobbers() const {
1432    return "";
1433  }
1434
1435  virtual void getGCCRegNames(const char * const *&Names,
1436                              unsigned &numNames) const  {
1437    Names = NULL;
1438    numNames = 0;
1439  }
1440
1441  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1442                                unsigned &NumAliases) const {
1443    Aliases = NULL;
1444    NumAliases = 0;
1445  }
1446
1447  virtual bool validateAsmConstraint(const char *&Name,
1448                                     TargetInfo::ConstraintInfo &info) const {
1449    return true;
1450  }
1451
1452  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1453                                 unsigned &NumRecords) const {
1454    Records = NULL;
1455    NumRecords = 0;
1456  }
1457
1458
1459  virtual void getTargetDefines(const LangOptions &Opts,
1460                                MacroBuilder &Builder) const {
1461    Builder.defineMacro("__R600__");
1462  }
1463
1464  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1465    return TargetInfo::CharPtrBuiltinVaList;
1466  }
1467
1468  virtual bool setCPU(const std::string &Name) {
1469    GPU = llvm::StringSwitch<GPUKind>(Name)
1470      .Case("r600" ,    GK_R600)
1471      .Case("rv610",    GK_R600)
1472      .Case("rv620",    GK_R600)
1473      .Case("rv630",    GK_R600)
1474      .Case("rv635",    GK_R600)
1475      .Case("rs780",    GK_R600)
1476      .Case("rs880",    GK_R600)
1477      .Case("rv670",    GK_R600_DOUBLE_OPS)
1478      .Case("rv710",    GK_R700)
1479      .Case("rv730",    GK_R700)
1480      .Case("rv740",    GK_R700_DOUBLE_OPS)
1481      .Case("rv770",    GK_R700_DOUBLE_OPS)
1482      .Case("palm",     GK_EVERGREEN)
1483      .Case("cedar",    GK_EVERGREEN)
1484      .Case("sumo",     GK_EVERGREEN)
1485      .Case("sumo2",    GK_EVERGREEN)
1486      .Case("redwood",  GK_EVERGREEN)
1487      .Case("juniper",  GK_EVERGREEN)
1488      .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1489      .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1490      .Case("barts",    GK_NORTHERN_ISLANDS)
1491      .Case("turks",    GK_NORTHERN_ISLANDS)
1492      .Case("caicos",   GK_NORTHERN_ISLANDS)
1493      .Case("cayman",   GK_CAYMAN)
1494      .Case("aruba",    GK_CAYMAN)
1495      .Case("SI",       GK_SOUTHERN_ISLANDS)
1496      .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1497      .Case("verde",    GK_SOUTHERN_ISLANDS)
1498      .Case("oland",    GK_SOUTHERN_ISLANDS)
1499      .Default(GK_NONE);
1500
1501    if (GPU == GK_NONE) {
1502      return false;
1503    }
1504
1505    // Set the correct data layout
1506    switch (GPU) {
1507    case GK_NONE:
1508    case GK_R600:
1509    case GK_R700:
1510    case GK_EVERGREEN:
1511    case GK_NORTHERN_ISLANDS:
1512      DescriptionString = DescriptionStringR600;
1513      break;
1514    case GK_R600_DOUBLE_OPS:
1515    case GK_R700_DOUBLE_OPS:
1516    case GK_EVERGREEN_DOUBLE_OPS:
1517    case GK_CAYMAN:
1518      DescriptionString = DescriptionStringR600DoubleOps;
1519      break;
1520    case GK_SOUTHERN_ISLANDS:
1521      DescriptionString = DescriptionStringSI;
1522      break;
1523    }
1524
1525    return true;
1526  }
1527};
1528
1529} // end anonymous namespace
1530
1531namespace {
1532// MBlaze abstract base class
1533class MBlazeTargetInfo : public TargetInfo {
1534  static const char * const GCCRegNames[];
1535  static const TargetInfo::GCCRegAlias GCCRegAliases[];
1536
1537public:
1538  MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1539    DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1540  }
1541
1542  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1543                                 unsigned &NumRecords) const {
1544    // FIXME: Implement.
1545    Records = 0;
1546    NumRecords = 0;
1547  }
1548
1549  virtual void getTargetDefines(const LangOptions &Opts,
1550                                MacroBuilder &Builder) const;
1551
1552  virtual bool hasFeature(StringRef Feature) const {
1553    return Feature == "mblaze";
1554  }
1555
1556  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1557    return TargetInfo::CharPtrBuiltinVaList;
1558  }
1559  virtual const char *getTargetPrefix() const {
1560    return "mblaze";
1561  }
1562  virtual void getGCCRegNames(const char * const *&Names,
1563                              unsigned &NumNames) const;
1564  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1565                                unsigned &NumAliases) const;
1566  virtual bool validateAsmConstraint(const char *&Name,
1567                                     TargetInfo::ConstraintInfo &Info) const {
1568    switch (*Name) {
1569    default: return false;
1570    case 'O': // Zero
1571      return true;
1572    case 'b': // Base register
1573    case 'f': // Floating point register
1574      Info.setAllowsRegister();
1575      return true;
1576    }
1577  }
1578  virtual const char *getClobbers() const {
1579    return "";
1580  }
1581};
1582
1583/// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1584/// #defines that are not tied to a specific subtarget.
1585void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1586                                     MacroBuilder &Builder) const {
1587  // Target identification.
1588  Builder.defineMacro("__microblaze__");
1589  Builder.defineMacro("_ARCH_MICROBLAZE");
1590  Builder.defineMacro("__MICROBLAZE__");
1591
1592  // Target properties.
1593  Builder.defineMacro("_BIG_ENDIAN");
1594  Builder.defineMacro("__BIG_ENDIAN__");
1595
1596  // Subtarget options.
1597  Builder.defineMacro("__REGISTER_PREFIX__", "");
1598}
1599
1600
1601const char * const MBlazeTargetInfo::GCCRegNames[] = {
1602  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1603  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1604  "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1605  "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1606  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1607  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1608  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1609  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1610  "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1611  "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1612};
1613
1614void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1615                                   unsigned &NumNames) const {
1616  Names = GCCRegNames;
1617  NumNames = llvm::array_lengthof(GCCRegNames);
1618}
1619
1620const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1621  { {"f0"},  "r0" },
1622  { {"f1"},  "r1" },
1623  { {"f2"},  "r2" },
1624  { {"f3"},  "r3" },
1625  { {"f4"},  "r4" },
1626  { {"f5"},  "r5" },
1627  { {"f6"},  "r6" },
1628  { {"f7"},  "r7" },
1629  { {"f8"},  "r8" },
1630  { {"f9"},  "r9" },
1631  { {"f10"}, "r10" },
1632  { {"f11"}, "r11" },
1633  { {"f12"}, "r12" },
1634  { {"f13"}, "r13" },
1635  { {"f14"}, "r14" },
1636  { {"f15"}, "r15" },
1637  { {"f16"}, "r16" },
1638  { {"f17"}, "r17" },
1639  { {"f18"}, "r18" },
1640  { {"f19"}, "r19" },
1641  { {"f20"}, "r20" },
1642  { {"f21"}, "r21" },
1643  { {"f22"}, "r22" },
1644  { {"f23"}, "r23" },
1645  { {"f24"}, "r24" },
1646  { {"f25"}, "r25" },
1647  { {"f26"}, "r26" },
1648  { {"f27"}, "r27" },
1649  { {"f28"}, "r28" },
1650  { {"f29"}, "r29" },
1651  { {"f30"}, "r30" },
1652  { {"f31"}, "r31" },
1653};
1654
1655void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1656                                     unsigned &NumAliases) const {
1657  Aliases = GCCRegAliases;
1658  NumAliases = llvm::array_lengthof(GCCRegAliases);
1659}
1660} // end anonymous namespace.
1661
1662namespace {
1663// Namespace for x86 abstract base class
1664const Builtin::Info BuiltinInfo[] = {
1665#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1666#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1667                                              ALL_LANGUAGES },
1668#include "clang/Basic/BuiltinsX86.def"
1669};
1670
1671static const char* const GCCRegNames[] = {
1672  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1673  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1674  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1675  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1676  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1677  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1678  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1679  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1680  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1681};
1682
1683const TargetInfo::AddlRegName AddlRegNames[] = {
1684  { { "al", "ah", "eax", "rax" }, 0 },
1685  { { "bl", "bh", "ebx", "rbx" }, 3 },
1686  { { "cl", "ch", "ecx", "rcx" }, 2 },
1687  { { "dl", "dh", "edx", "rdx" }, 1 },
1688  { { "esi", "rsi" }, 4 },
1689  { { "edi", "rdi" }, 5 },
1690  { { "esp", "rsp" }, 7 },
1691  { { "ebp", "rbp" }, 6 },
1692};
1693
1694// X86 target abstract base class; x86-32 and x86-64 are very close, so
1695// most of the implementation can be shared.
1696class X86TargetInfo : public TargetInfo {
1697  enum X86SSEEnum {
1698    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1699  } SSELevel;
1700  enum MMX3DNowEnum {
1701    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1702  } MMX3DNowLevel;
1703
1704  bool HasAES;
1705  bool HasPCLMUL;
1706  bool HasLZCNT;
1707  bool HasRDRND;
1708  bool HasBMI;
1709  bool HasBMI2;
1710  bool HasPOPCNT;
1711  bool HasRTM;
1712  bool HasPRFCHW;
1713  bool HasRDSEED;
1714  bool HasSSE4a;
1715  bool HasFMA4;
1716  bool HasFMA;
1717  bool HasXOP;
1718  bool HasF16C;
1719
1720  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1721  ///
1722  /// Each enumeration represents a particular CPU supported by Clang. These
1723  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1724  enum CPUKind {
1725    CK_Generic,
1726
1727    /// \name i386
1728    /// i386-generation processors.
1729    //@{
1730    CK_i386,
1731    //@}
1732
1733    /// \name i486
1734    /// i486-generation processors.
1735    //@{
1736    CK_i486,
1737    CK_WinChipC6,
1738    CK_WinChip2,
1739    CK_C3,
1740    //@}
1741
1742    /// \name i586
1743    /// i586-generation processors, P5 microarchitecture based.
1744    //@{
1745    CK_i586,
1746    CK_Pentium,
1747    CK_PentiumMMX,
1748    //@}
1749
1750    /// \name i686
1751    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1752    //@{
1753    CK_i686,
1754    CK_PentiumPro,
1755    CK_Pentium2,
1756    CK_Pentium3,
1757    CK_Pentium3M,
1758    CK_PentiumM,
1759    CK_C3_2,
1760
1761    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1762    /// Clang however has some logic to suport this.
1763    // FIXME: Warn, deprecate, and potentially remove this.
1764    CK_Yonah,
1765    //@}
1766
1767    /// \name Netburst
1768    /// Netburst microarchitecture based processors.
1769    //@{
1770    CK_Pentium4,
1771    CK_Pentium4M,
1772    CK_Prescott,
1773    CK_Nocona,
1774    //@}
1775
1776    /// \name Core
1777    /// Core microarchitecture based processors.
1778    //@{
1779    CK_Core2,
1780
1781    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1782    /// codename which GCC no longer accepts as an option to -march, but Clang
1783    /// has some logic for recognizing it.
1784    // FIXME: Warn, deprecate, and potentially remove this.
1785    CK_Penryn,
1786    //@}
1787
1788    /// \name Atom
1789    /// Atom processors
1790    //@{
1791    CK_Atom,
1792    //@}
1793
1794    /// \name Nehalem
1795    /// Nehalem microarchitecture based processors.
1796    //@{
1797    CK_Corei7,
1798    CK_Corei7AVX,
1799    CK_CoreAVXi,
1800    CK_CoreAVX2,
1801    //@}
1802
1803    /// \name K6
1804    /// K6 architecture processors.
1805    //@{
1806    CK_K6,
1807    CK_K6_2,
1808    CK_K6_3,
1809    //@}
1810
1811    /// \name K7
1812    /// K7 architecture processors.
1813    //@{
1814    CK_Athlon,
1815    CK_AthlonThunderbird,
1816    CK_Athlon4,
1817    CK_AthlonXP,
1818    CK_AthlonMP,
1819    //@}
1820
1821    /// \name K8
1822    /// K8 architecture processors.
1823    //@{
1824    CK_Athlon64,
1825    CK_Athlon64SSE3,
1826    CK_AthlonFX,
1827    CK_K8,
1828    CK_K8SSE3,
1829    CK_Opteron,
1830    CK_OpteronSSE3,
1831    CK_AMDFAM10,
1832    //@}
1833
1834    /// \name Bobcat
1835    /// Bobcat architecture processors.
1836    //@{
1837    CK_BTVER1,
1838    //@}
1839
1840    /// \name Bulldozer
1841    /// Bulldozer architecture processors.
1842    //@{
1843    CK_BDVER1,
1844    CK_BDVER2,
1845    //@}
1846
1847    /// This specification is deprecated and will be removed in the future.
1848    /// Users should prefer \see CK_K8.
1849    // FIXME: Warn on this when the CPU is set to it.
1850    CK_x86_64,
1851    //@}
1852
1853    /// \name Geode
1854    /// Geode processors.
1855    //@{
1856    CK_Geode
1857    //@}
1858  } CPU;
1859
1860public:
1861  X86TargetInfo(const std::string& triple)
1862    : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1863      HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1864      HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1865      HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1866      HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1867    BigEndian = false;
1868    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1869  }
1870  virtual unsigned getFloatEvalMethod() const {
1871    // X87 evaluates with 80 bits "long double" precision.
1872    return SSELevel == NoSSE ? 2 : 0;
1873  }
1874  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1875                                 unsigned &NumRecords) const {
1876    Records = BuiltinInfo;
1877    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1878  }
1879  virtual void getGCCRegNames(const char * const *&Names,
1880                              unsigned &NumNames) const {
1881    Names = GCCRegNames;
1882    NumNames = llvm::array_lengthof(GCCRegNames);
1883  }
1884  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1885                                unsigned &NumAliases) const {
1886    Aliases = 0;
1887    NumAliases = 0;
1888  }
1889  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1890                                  unsigned &NumNames) const {
1891    Names = AddlRegNames;
1892    NumNames = llvm::array_lengthof(AddlRegNames);
1893  }
1894  virtual bool validateAsmConstraint(const char *&Name,
1895                                     TargetInfo::ConstraintInfo &info) const;
1896  virtual std::string convertConstraint(const char *&Constraint) const;
1897  virtual const char *getClobbers() const {
1898    return "~{dirflag},~{fpsr},~{flags}";
1899  }
1900  virtual void getTargetDefines(const LangOptions &Opts,
1901                                MacroBuilder &Builder) const;
1902  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1903                                 StringRef Name,
1904                                 bool Enabled) const;
1905  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1906  virtual bool hasFeature(StringRef Feature) const;
1907  virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1908  virtual const char* getABI() const {
1909    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1910      return "avx";
1911    else if (getTriple().getArch() == llvm::Triple::x86 &&
1912             MMX3DNowLevel == NoMMX3DNow)
1913      return "no-mmx";
1914    return "";
1915  }
1916  virtual bool setCPU(const std::string &Name) {
1917    CPU = llvm::StringSwitch<CPUKind>(Name)
1918      .Case("i386", CK_i386)
1919      .Case("i486", CK_i486)
1920      .Case("winchip-c6", CK_WinChipC6)
1921      .Case("winchip2", CK_WinChip2)
1922      .Case("c3", CK_C3)
1923      .Case("i586", CK_i586)
1924      .Case("pentium", CK_Pentium)
1925      .Case("pentium-mmx", CK_PentiumMMX)
1926      .Case("i686", CK_i686)
1927      .Case("pentiumpro", CK_PentiumPro)
1928      .Case("pentium2", CK_Pentium2)
1929      .Case("pentium3", CK_Pentium3)
1930      .Case("pentium3m", CK_Pentium3M)
1931      .Case("pentium-m", CK_PentiumM)
1932      .Case("c3-2", CK_C3_2)
1933      .Case("yonah", CK_Yonah)
1934      .Case("pentium4", CK_Pentium4)
1935      .Case("pentium4m", CK_Pentium4M)
1936      .Case("prescott", CK_Prescott)
1937      .Case("nocona", CK_Nocona)
1938      .Case("core2", CK_Core2)
1939      .Case("penryn", CK_Penryn)
1940      .Case("atom", CK_Atom)
1941      .Case("corei7", CK_Corei7)
1942      .Case("corei7-avx", CK_Corei7AVX)
1943      .Case("core-avx-i", CK_CoreAVXi)
1944      .Case("core-avx2", CK_CoreAVX2)
1945      .Case("k6", CK_K6)
1946      .Case("k6-2", CK_K6_2)
1947      .Case("k6-3", CK_K6_3)
1948      .Case("athlon", CK_Athlon)
1949      .Case("athlon-tbird", CK_AthlonThunderbird)
1950      .Case("athlon-4", CK_Athlon4)
1951      .Case("athlon-xp", CK_AthlonXP)
1952      .Case("athlon-mp", CK_AthlonMP)
1953      .Case("athlon64", CK_Athlon64)
1954      .Case("athlon64-sse3", CK_Athlon64SSE3)
1955      .Case("athlon-fx", CK_AthlonFX)
1956      .Case("k8", CK_K8)
1957      .Case("k8-sse3", CK_K8SSE3)
1958      .Case("opteron", CK_Opteron)
1959      .Case("opteron-sse3", CK_OpteronSSE3)
1960      .Case("amdfam10", CK_AMDFAM10)
1961      .Case("btver1", CK_BTVER1)
1962      .Case("bdver1", CK_BDVER1)
1963      .Case("bdver2", CK_BDVER2)
1964      .Case("x86-64", CK_x86_64)
1965      .Case("geode", CK_Geode)
1966      .Default(CK_Generic);
1967
1968    // Perform any per-CPU checks necessary to determine if this CPU is
1969    // acceptable.
1970    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1971    // invalid without explaining *why*.
1972    switch (CPU) {
1973    case CK_Generic:
1974      // No processor selected!
1975      return false;
1976
1977    case CK_i386:
1978    case CK_i486:
1979    case CK_WinChipC6:
1980    case CK_WinChip2:
1981    case CK_C3:
1982    case CK_i586:
1983    case CK_Pentium:
1984    case CK_PentiumMMX:
1985    case CK_i686:
1986    case CK_PentiumPro:
1987    case CK_Pentium2:
1988    case CK_Pentium3:
1989    case CK_Pentium3M:
1990    case CK_PentiumM:
1991    case CK_Yonah:
1992    case CK_C3_2:
1993    case CK_Pentium4:
1994    case CK_Pentium4M:
1995    case CK_Prescott:
1996    case CK_K6:
1997    case CK_K6_2:
1998    case CK_K6_3:
1999    case CK_Athlon:
2000    case CK_AthlonThunderbird:
2001    case CK_Athlon4:
2002    case CK_AthlonXP:
2003    case CK_AthlonMP:
2004    case CK_Geode:
2005      // Only accept certain architectures when compiling in 32-bit mode.
2006      if (getTriple().getArch() != llvm::Triple::x86)
2007        return false;
2008
2009      // Fallthrough
2010    case CK_Nocona:
2011    case CK_Core2:
2012    case CK_Penryn:
2013    case CK_Atom:
2014    case CK_Corei7:
2015    case CK_Corei7AVX:
2016    case CK_CoreAVXi:
2017    case CK_CoreAVX2:
2018    case CK_Athlon64:
2019    case CK_Athlon64SSE3:
2020    case CK_AthlonFX:
2021    case CK_K8:
2022    case CK_K8SSE3:
2023    case CK_Opteron:
2024    case CK_OpteronSSE3:
2025    case CK_AMDFAM10:
2026    case CK_BTVER1:
2027    case CK_BDVER1:
2028    case CK_BDVER2:
2029    case CK_x86_64:
2030      return true;
2031    }
2032    llvm_unreachable("Unhandled CPU kind");
2033  }
2034
2035  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2036    // We accept all non-ARM calling conventions
2037    return (CC == CC_X86ThisCall ||
2038            CC == CC_X86FastCall ||
2039            CC == CC_X86StdCall ||
2040            CC == CC_C ||
2041            CC == CC_X86Pascal ||
2042            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2043  }
2044
2045  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2046    return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2047  }
2048};
2049
2050void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2051  // FIXME: This should not be here.
2052  Features["3dnow"] = false;
2053  Features["3dnowa"] = false;
2054  Features["mmx"] = false;
2055  Features["sse"] = false;
2056  Features["sse2"] = false;
2057  Features["sse3"] = false;
2058  Features["ssse3"] = false;
2059  Features["sse41"] = false;
2060  Features["sse42"] = false;
2061  Features["sse4a"] = false;
2062  Features["aes"] = false;
2063  Features["pclmul"] = false;
2064  Features["avx"] = false;
2065  Features["avx2"] = false;
2066  Features["lzcnt"] = false;
2067  Features["rdrand"] = false;
2068  Features["bmi"] = false;
2069  Features["bmi2"] = false;
2070  Features["popcnt"] = false;
2071  Features["rtm"] = false;
2072  Features["prfchw"] = false;
2073  Features["rdseed"] = false;
2074  Features["fma4"] = false;
2075  Features["fma"] = false;
2076  Features["xop"] = false;
2077  Features["f16c"] = false;
2078
2079  // FIXME: This *really* should not be here.
2080
2081  // X86_64 always has SSE2.
2082  if (getTriple().getArch() == llvm::Triple::x86_64)
2083    setFeatureEnabled(Features, "sse2", true);
2084
2085  switch (CPU) {
2086  case CK_Generic:
2087  case CK_i386:
2088  case CK_i486:
2089  case CK_i586:
2090  case CK_Pentium:
2091  case CK_i686:
2092  case CK_PentiumPro:
2093    break;
2094  case CK_PentiumMMX:
2095  case CK_Pentium2:
2096    setFeatureEnabled(Features, "mmx", true);
2097    break;
2098  case CK_Pentium3:
2099  case CK_Pentium3M:
2100    setFeatureEnabled(Features, "sse", true);
2101    break;
2102  case CK_PentiumM:
2103  case CK_Pentium4:
2104  case CK_Pentium4M:
2105  case CK_x86_64:
2106    setFeatureEnabled(Features, "sse2", true);
2107    break;
2108  case CK_Yonah:
2109  case CK_Prescott:
2110  case CK_Nocona:
2111    setFeatureEnabled(Features, "sse3", true);
2112    break;
2113  case CK_Core2:
2114    setFeatureEnabled(Features, "ssse3", true);
2115    break;
2116  case CK_Penryn:
2117    setFeatureEnabled(Features, "sse4.1", true);
2118    break;
2119  case CK_Atom:
2120    setFeatureEnabled(Features, "ssse3", true);
2121    break;
2122  case CK_Corei7:
2123    setFeatureEnabled(Features, "sse4", true);
2124    break;
2125  case CK_Corei7AVX:
2126    setFeatureEnabled(Features, "avx", true);
2127    setFeatureEnabled(Features, "aes", true);
2128    setFeatureEnabled(Features, "pclmul", true);
2129    break;
2130  case CK_CoreAVXi:
2131    setFeatureEnabled(Features, "avx", true);
2132    setFeatureEnabled(Features, "aes", true);
2133    setFeatureEnabled(Features, "pclmul", true);
2134    setFeatureEnabled(Features, "rdrnd", true);
2135    setFeatureEnabled(Features, "f16c", true);
2136    break;
2137  case CK_CoreAVX2:
2138    setFeatureEnabled(Features, "avx2", true);
2139    setFeatureEnabled(Features, "aes", true);
2140    setFeatureEnabled(Features, "pclmul", true);
2141    setFeatureEnabled(Features, "lzcnt", true);
2142    setFeatureEnabled(Features, "rdrnd", true);
2143    setFeatureEnabled(Features, "f16c", true);
2144    setFeatureEnabled(Features, "bmi", true);
2145    setFeatureEnabled(Features, "bmi2", true);
2146    setFeatureEnabled(Features, "rtm", true);
2147    setFeatureEnabled(Features, "fma", true);
2148    break;
2149  case CK_K6:
2150  case CK_WinChipC6:
2151    setFeatureEnabled(Features, "mmx", true);
2152    break;
2153  case CK_K6_2:
2154  case CK_K6_3:
2155  case CK_WinChip2:
2156  case CK_C3:
2157    setFeatureEnabled(Features, "3dnow", true);
2158    break;
2159  case CK_Athlon:
2160  case CK_AthlonThunderbird:
2161  case CK_Geode:
2162    setFeatureEnabled(Features, "3dnowa", true);
2163    break;
2164  case CK_Athlon4:
2165  case CK_AthlonXP:
2166  case CK_AthlonMP:
2167    setFeatureEnabled(Features, "sse", true);
2168    setFeatureEnabled(Features, "3dnowa", true);
2169    break;
2170  case CK_K8:
2171  case CK_Opteron:
2172  case CK_Athlon64:
2173  case CK_AthlonFX:
2174    setFeatureEnabled(Features, "sse2", true);
2175    setFeatureEnabled(Features, "3dnowa", true);
2176    break;
2177  case CK_K8SSE3:
2178  case CK_OpteronSSE3:
2179  case CK_Athlon64SSE3:
2180    setFeatureEnabled(Features, "sse3", true);
2181    setFeatureEnabled(Features, "3dnowa", true);
2182    break;
2183  case CK_AMDFAM10:
2184    setFeatureEnabled(Features, "sse3", true);
2185    setFeatureEnabled(Features, "sse4a", true);
2186    setFeatureEnabled(Features, "3dnowa", true);
2187    setFeatureEnabled(Features, "lzcnt", true);
2188    setFeatureEnabled(Features, "popcnt", true);
2189    break;
2190  case CK_BTVER1:
2191    setFeatureEnabled(Features, "ssse3", true);
2192    setFeatureEnabled(Features, "sse4a", true);
2193    setFeatureEnabled(Features, "lzcnt", true);
2194    setFeatureEnabled(Features, "popcnt", true);
2195    break;
2196  case CK_BDVER1:
2197    setFeatureEnabled(Features, "xop", true);
2198    setFeatureEnabled(Features, "lzcnt", true);
2199    setFeatureEnabled(Features, "aes", true);
2200    setFeatureEnabled(Features, "pclmul", true);
2201    break;
2202  case CK_BDVER2:
2203    setFeatureEnabled(Features, "xop", true);
2204    setFeatureEnabled(Features, "lzcnt", true);
2205    setFeatureEnabled(Features, "aes", true);
2206    setFeatureEnabled(Features, "pclmul", true);
2207    setFeatureEnabled(Features, "bmi", true);
2208    setFeatureEnabled(Features, "fma", true);
2209    setFeatureEnabled(Features, "f16c", true);
2210    break;
2211  case CK_C3_2:
2212    setFeatureEnabled(Features, "sse", true);
2213    break;
2214  }
2215}
2216
2217bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2218                                      StringRef Name,
2219                                      bool Enabled) const {
2220  // FIXME: This *really* should not be here.  We need some way of translating
2221  // options into llvm subtarget features.
2222  if (!Features.count(Name) &&
2223      (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2224       Name != "rdrnd"))
2225    return false;
2226
2227  // FIXME: this should probably use a switch with fall through.
2228
2229  if (Enabled) {
2230    if (Name == "mmx")
2231      Features["mmx"] = true;
2232    else if (Name == "sse")
2233      Features["mmx"] = Features["sse"] = true;
2234    else if (Name == "sse2")
2235      Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2236    else if (Name == "sse3")
2237      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2238        true;
2239    else if (Name == "ssse3")
2240      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2241        Features["ssse3"] = true;
2242    else if (Name == "sse4" || Name == "sse4.2")
2243      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2244        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2245        Features["popcnt"] = true;
2246    else if (Name == "sse4.1")
2247      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2248        Features["ssse3"] = Features["sse41"] = true;
2249    else if (Name == "3dnow")
2250      Features["mmx"] = Features["3dnow"] = true;
2251    else if (Name == "3dnowa")
2252      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2253    else if (Name == "aes")
2254      Features["sse"] = Features["sse2"] = Features["aes"] = true;
2255    else if (Name == "pclmul")
2256      Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2257    else if (Name == "avx")
2258      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2259        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2260        Features["popcnt"] = Features["avx"] = true;
2261    else if (Name == "avx2")
2262      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2263        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2264        Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2265    else if (Name == "fma")
2266      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2267        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2268        Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2269    else if (Name == "fma4")
2270      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2271        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2272        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2273        Features["fma4"] = true;
2274    else if (Name == "xop")
2275      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2276        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2277        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2278        Features["fma4"] = Features["xop"] = true;
2279    else if (Name == "sse4a")
2280      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2281        Features["sse4a"] = true;
2282    else if (Name == "lzcnt")
2283      Features["lzcnt"] = true;
2284    else if (Name == "rdrnd")
2285      Features["rdrand"] = true;
2286    else if (Name == "bmi")
2287      Features["bmi"] = true;
2288    else if (Name == "bmi2")
2289      Features["bmi2"] = true;
2290    else if (Name == "popcnt")
2291      Features["popcnt"] = true;
2292    else if (Name == "f16c")
2293      Features["f16c"] = true;
2294    else if (Name == "rtm")
2295      Features["rtm"] = true;
2296    else if (Name == "prfchw")
2297      Features["prfchw"] = true;
2298    else if (Name == "rdseed")
2299      Features["rdseed"] = true;
2300  } else {
2301    if (Name == "mmx")
2302      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2303    else if (Name == "sse")
2304      Features["sse"] = Features["sse2"] = Features["sse3"] =
2305        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2306        Features["sse4a"] = Features["avx"] = Features["avx2"] =
2307        Features["fma"] = Features["fma4"] = Features["aes"] =
2308        Features["pclmul"] = Features["xop"] = false;
2309    else if (Name == "sse2")
2310      Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2311        Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2312        Features["avx"] = Features["avx2"] = Features["fma"] =
2313        Features["fma4"] = Features["aes"] = Features["pclmul"] =
2314        Features["xop"] = false;
2315    else if (Name == "sse3")
2316      Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2317        Features["sse42"] = Features["sse4a"] = Features["avx"] =
2318        Features["avx2"] = Features["fma"] = Features["fma4"] =
2319        Features["xop"] = false;
2320    else if (Name == "ssse3")
2321      Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2322        Features["avx"] = Features["avx2"] = Features["fma"] = false;
2323    else if (Name == "sse4" || Name == "sse4.1")
2324      Features["sse41"] = Features["sse42"] = Features["avx"] =
2325        Features["avx2"] = Features["fma"] = false;
2326    else if (Name == "sse4.2")
2327      Features["sse42"] = Features["avx"] = Features["avx2"] =
2328        Features["fma"] = false;
2329    else if (Name == "3dnow")
2330      Features["3dnow"] = Features["3dnowa"] = false;
2331    else if (Name == "3dnowa")
2332      Features["3dnowa"] = false;
2333    else if (Name == "aes")
2334      Features["aes"] = false;
2335    else if (Name == "pclmul")
2336      Features["pclmul"] = false;
2337    else if (Name == "avx")
2338      Features["avx"] = Features["avx2"] = Features["fma"] =
2339        Features["fma4"] = Features["xop"] = false;
2340    else if (Name == "avx2")
2341      Features["avx2"] = false;
2342    else if (Name == "fma")
2343      Features["fma"] = false;
2344    else if (Name == "sse4a")
2345      Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2346    else if (Name == "lzcnt")
2347      Features["lzcnt"] = false;
2348    else if (Name == "rdrnd")
2349      Features["rdrand"] = false;
2350    else if (Name == "bmi")
2351      Features["bmi"] = false;
2352    else if (Name == "bmi2")
2353      Features["bmi2"] = false;
2354    else if (Name == "popcnt")
2355      Features["popcnt"] = false;
2356    else if (Name == "fma4")
2357      Features["fma4"] = Features["xop"] = false;
2358    else if (Name == "xop")
2359      Features["xop"] = false;
2360    else if (Name == "f16c")
2361      Features["f16c"] = false;
2362    else if (Name == "rtm")
2363      Features["rtm"] = false;
2364    else if (Name == "prfchw")
2365      Features["prfchw"] = false;
2366    else if (Name == "rdseed")
2367      Features["rdseed"] = false;
2368  }
2369
2370  return true;
2371}
2372
2373/// HandleTargetOptions - Perform initialization based on the user
2374/// configured set of features.
2375void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2376  // Remember the maximum enabled sselevel.
2377  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2378    // Ignore disabled features.
2379    if (Features[i][0] == '-')
2380      continue;
2381
2382    StringRef Feature = StringRef(Features[i]).substr(1);
2383
2384    if (Feature == "aes") {
2385      HasAES = true;
2386      continue;
2387    }
2388
2389    if (Feature == "pclmul") {
2390      HasPCLMUL = true;
2391      continue;
2392    }
2393
2394    if (Feature == "lzcnt") {
2395      HasLZCNT = true;
2396      continue;
2397    }
2398
2399    if (Feature == "rdrand") {
2400      HasRDRND = true;
2401      continue;
2402    }
2403
2404    if (Feature == "bmi") {
2405      HasBMI = true;
2406      continue;
2407    }
2408
2409    if (Feature == "bmi2") {
2410      HasBMI2 = true;
2411      continue;
2412    }
2413
2414    if (Feature == "popcnt") {
2415      HasPOPCNT = true;
2416      continue;
2417    }
2418
2419    if (Feature == "rtm") {
2420      HasRTM = true;
2421      continue;
2422    }
2423
2424    if (Feature == "prfchw") {
2425      HasPRFCHW = true;
2426      continue;
2427    }
2428
2429    if (Feature == "rdseed") {
2430      HasRDSEED = true;
2431      continue;
2432    }
2433
2434    if (Feature == "sse4a") {
2435      HasSSE4a = true;
2436      continue;
2437    }
2438
2439    if (Feature == "fma4") {
2440      HasFMA4 = true;
2441      continue;
2442    }
2443
2444    if (Feature == "fma") {
2445      HasFMA = true;
2446      continue;
2447    }
2448
2449    if (Feature == "xop") {
2450      HasXOP = true;
2451      continue;
2452    }
2453
2454    if (Feature == "f16c") {
2455      HasF16C = true;
2456      continue;
2457    }
2458
2459    assert(Features[i][0] == '+' && "Invalid target feature!");
2460    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2461      .Case("avx2", AVX2)
2462      .Case("avx", AVX)
2463      .Case("sse42", SSE42)
2464      .Case("sse41", SSE41)
2465      .Case("ssse3", SSSE3)
2466      .Case("sse3", SSE3)
2467      .Case("sse2", SSE2)
2468      .Case("sse", SSE1)
2469      .Default(NoSSE);
2470    SSELevel = std::max(SSELevel, Level);
2471
2472    MMX3DNowEnum ThreeDNowLevel =
2473      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2474        .Case("3dnowa", AMD3DNowAthlon)
2475        .Case("3dnow", AMD3DNow)
2476        .Case("mmx", MMX)
2477        .Default(NoMMX3DNow);
2478
2479    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2480  }
2481
2482  // Don't tell the backend if we're turning off mmx; it will end up disabling
2483  // SSE, which we don't want.
2484  std::vector<std::string>::iterator it;
2485  it = std::find(Features.begin(), Features.end(), "-mmx");
2486  if (it != Features.end())
2487    Features.erase(it);
2488}
2489
2490/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2491/// definitions for this particular subtarget.
2492void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2493                                     MacroBuilder &Builder) const {
2494  // Target identification.
2495  if (getTriple().getArch() == llvm::Triple::x86_64) {
2496    Builder.defineMacro("__amd64__");
2497    Builder.defineMacro("__amd64");
2498    Builder.defineMacro("__x86_64");
2499    Builder.defineMacro("__x86_64__");
2500  } else {
2501    DefineStd(Builder, "i386", Opts);
2502  }
2503
2504  // Subtarget options.
2505  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2506  // truly should be based on -mtune options.
2507  switch (CPU) {
2508  case CK_Generic:
2509    break;
2510  case CK_i386:
2511    // The rest are coming from the i386 define above.
2512    Builder.defineMacro("__tune_i386__");
2513    break;
2514  case CK_i486:
2515  case CK_WinChipC6:
2516  case CK_WinChip2:
2517  case CK_C3:
2518    defineCPUMacros(Builder, "i486");
2519    break;
2520  case CK_PentiumMMX:
2521    Builder.defineMacro("__pentium_mmx__");
2522    Builder.defineMacro("__tune_pentium_mmx__");
2523    // Fallthrough
2524  case CK_i586:
2525  case CK_Pentium:
2526    defineCPUMacros(Builder, "i586");
2527    defineCPUMacros(Builder, "pentium");
2528    break;
2529  case CK_Pentium3:
2530  case CK_Pentium3M:
2531  case CK_PentiumM:
2532    Builder.defineMacro("__tune_pentium3__");
2533    // Fallthrough
2534  case CK_Pentium2:
2535  case CK_C3_2:
2536    Builder.defineMacro("__tune_pentium2__");
2537    // Fallthrough
2538  case CK_PentiumPro:
2539    Builder.defineMacro("__tune_i686__");
2540    Builder.defineMacro("__tune_pentiumpro__");
2541    // Fallthrough
2542  case CK_i686:
2543    Builder.defineMacro("__i686");
2544    Builder.defineMacro("__i686__");
2545    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2546    Builder.defineMacro("__pentiumpro");
2547    Builder.defineMacro("__pentiumpro__");
2548    break;
2549  case CK_Pentium4:
2550  case CK_Pentium4M:
2551    defineCPUMacros(Builder, "pentium4");
2552    break;
2553  case CK_Yonah:
2554  case CK_Prescott:
2555  case CK_Nocona:
2556    defineCPUMacros(Builder, "nocona");
2557    break;
2558  case CK_Core2:
2559  case CK_Penryn:
2560    defineCPUMacros(Builder, "core2");
2561    break;
2562  case CK_Atom:
2563    defineCPUMacros(Builder, "atom");
2564    break;
2565  case CK_Corei7:
2566  case CK_Corei7AVX:
2567  case CK_CoreAVXi:
2568  case CK_CoreAVX2:
2569    defineCPUMacros(Builder, "corei7");
2570    break;
2571  case CK_K6_2:
2572    Builder.defineMacro("__k6_2__");
2573    Builder.defineMacro("__tune_k6_2__");
2574    // Fallthrough
2575  case CK_K6_3:
2576    if (CPU != CK_K6_2) {  // In case of fallthrough
2577      // FIXME: GCC may be enabling these in cases where some other k6
2578      // architecture is specified but -m3dnow is explicitly provided. The
2579      // exact semantics need to be determined and emulated here.
2580      Builder.defineMacro("__k6_3__");
2581      Builder.defineMacro("__tune_k6_3__");
2582    }
2583    // Fallthrough
2584  case CK_K6:
2585    defineCPUMacros(Builder, "k6");
2586    break;
2587  case CK_Athlon:
2588  case CK_AthlonThunderbird:
2589  case CK_Athlon4:
2590  case CK_AthlonXP:
2591  case CK_AthlonMP:
2592    defineCPUMacros(Builder, "athlon");
2593    if (SSELevel != NoSSE) {
2594      Builder.defineMacro("__athlon_sse__");
2595      Builder.defineMacro("__tune_athlon_sse__");
2596    }
2597    break;
2598  case CK_K8:
2599  case CK_K8SSE3:
2600  case CK_x86_64:
2601  case CK_Opteron:
2602  case CK_OpteronSSE3:
2603  case CK_Athlon64:
2604  case CK_Athlon64SSE3:
2605  case CK_AthlonFX:
2606    defineCPUMacros(Builder, "k8");
2607    break;
2608  case CK_AMDFAM10:
2609    defineCPUMacros(Builder, "amdfam10");
2610    break;
2611  case CK_BTVER1:
2612    defineCPUMacros(Builder, "btver1");
2613    break;
2614  case CK_BDVER1:
2615    defineCPUMacros(Builder, "bdver1");
2616    break;
2617  case CK_BDVER2:
2618    defineCPUMacros(Builder, "bdver2");
2619    break;
2620  case CK_Geode:
2621    defineCPUMacros(Builder, "geode");
2622    break;
2623  }
2624
2625  // Target properties.
2626  Builder.defineMacro("__LITTLE_ENDIAN__");
2627  Builder.defineMacro("__REGISTER_PREFIX__", "");
2628
2629  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2630  // functions in glibc header files that use FP Stack inline asm which the
2631  // backend can't deal with (PR879).
2632  Builder.defineMacro("__NO_MATH_INLINES");
2633
2634  if (HasAES)
2635    Builder.defineMacro("__AES__");
2636
2637  if (HasPCLMUL)
2638    Builder.defineMacro("__PCLMUL__");
2639
2640  if (HasLZCNT)
2641    Builder.defineMacro("__LZCNT__");
2642
2643  if (HasRDRND)
2644    Builder.defineMacro("__RDRND__");
2645
2646  if (HasBMI)
2647    Builder.defineMacro("__BMI__");
2648
2649  if (HasBMI2)
2650    Builder.defineMacro("__BMI2__");
2651
2652  if (HasPOPCNT)
2653    Builder.defineMacro("__POPCNT__");
2654
2655  if (HasRTM)
2656    Builder.defineMacro("__RTM__");
2657
2658  if (HasPRFCHW)
2659    Builder.defineMacro("__PRFCHW__");
2660
2661  if (HasRDSEED)
2662    Builder.defineMacro("__RDSEED__");
2663
2664  if (HasSSE4a)
2665    Builder.defineMacro("__SSE4A__");
2666
2667  if (HasFMA4)
2668    Builder.defineMacro("__FMA4__");
2669
2670  if (HasFMA)
2671    Builder.defineMacro("__FMA__");
2672
2673  if (HasXOP)
2674    Builder.defineMacro("__XOP__");
2675
2676  if (HasF16C)
2677    Builder.defineMacro("__F16C__");
2678
2679  // Each case falls through to the previous one here.
2680  switch (SSELevel) {
2681  case AVX2:
2682    Builder.defineMacro("__AVX2__");
2683  case AVX:
2684    Builder.defineMacro("__AVX__");
2685  case SSE42:
2686    Builder.defineMacro("__SSE4_2__");
2687  case SSE41:
2688    Builder.defineMacro("__SSE4_1__");
2689  case SSSE3:
2690    Builder.defineMacro("__SSSE3__");
2691  case SSE3:
2692    Builder.defineMacro("__SSE3__");
2693  case SSE2:
2694    Builder.defineMacro("__SSE2__");
2695    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2696  case SSE1:
2697    Builder.defineMacro("__SSE__");
2698    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2699  case NoSSE:
2700    break;
2701  }
2702
2703  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2704    switch (SSELevel) {
2705    case AVX2:
2706    case AVX:
2707    case SSE42:
2708    case SSE41:
2709    case SSSE3:
2710    case SSE3:
2711    case SSE2:
2712      Builder.defineMacro("_M_IX86_FP", Twine(2));
2713      break;
2714    case SSE1:
2715      Builder.defineMacro("_M_IX86_FP", Twine(1));
2716      break;
2717    default:
2718      Builder.defineMacro("_M_IX86_FP", Twine(0));
2719    }
2720  }
2721
2722  // Each case falls through to the previous one here.
2723  switch (MMX3DNowLevel) {
2724  case AMD3DNowAthlon:
2725    Builder.defineMacro("__3dNOW_A__");
2726  case AMD3DNow:
2727    Builder.defineMacro("__3dNOW__");
2728  case MMX:
2729    Builder.defineMacro("__MMX__");
2730  case NoMMX3DNow:
2731    break;
2732  }
2733}
2734
2735bool X86TargetInfo::hasFeature(StringRef Feature) const {
2736  return llvm::StringSwitch<bool>(Feature)
2737      .Case("aes", HasAES)
2738      .Case("avx", SSELevel >= AVX)
2739      .Case("avx2", SSELevel >= AVX2)
2740      .Case("bmi", HasBMI)
2741      .Case("bmi2", HasBMI2)
2742      .Case("fma", HasFMA)
2743      .Case("fma4", HasFMA4)
2744      .Case("lzcnt", HasLZCNT)
2745      .Case("rdrnd", HasRDRND)
2746      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2747      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2748      .Case("mmx", MMX3DNowLevel >= MMX)
2749      .Case("pclmul", HasPCLMUL)
2750      .Case("popcnt", HasPOPCNT)
2751      .Case("rtm", HasRTM)
2752      .Case("prfchw", HasPRFCHW)
2753      .Case("rdseed", HasRDSEED)
2754      .Case("sse", SSELevel >= SSE1)
2755      .Case("sse2", SSELevel >= SSE2)
2756      .Case("sse3", SSELevel >= SSE3)
2757      .Case("ssse3", SSELevel >= SSSE3)
2758      .Case("sse41", SSELevel >= SSE41)
2759      .Case("sse42", SSELevel >= SSE42)
2760      .Case("sse4a", HasSSE4a)
2761      .Case("x86", true)
2762      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2763      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2764      .Case("xop", HasXOP)
2765      .Case("f16c", HasF16C)
2766      .Default(false);
2767}
2768
2769bool
2770X86TargetInfo::validateAsmConstraint(const char *&Name,
2771                                     TargetInfo::ConstraintInfo &Info) const {
2772  switch (*Name) {
2773  default: return false;
2774  case 'Y': // first letter of a pair:
2775    switch (*(Name+1)) {
2776    default: return false;
2777    case '0':  // First SSE register.
2778    case 't':  // Any SSE register, when SSE2 is enabled.
2779    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2780    case 'm':  // any MMX register, when inter-unit moves enabled.
2781      break;   // falls through to setAllowsRegister.
2782  }
2783  case 'a': // eax.
2784  case 'b': // ebx.
2785  case 'c': // ecx.
2786  case 'd': // edx.
2787  case 'S': // esi.
2788  case 'D': // edi.
2789  case 'A': // edx:eax.
2790  case 'f': // any x87 floating point stack register.
2791  case 't': // top of floating point stack.
2792  case 'u': // second from top of floating point stack.
2793  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2794  case 'y': // Any MMX register.
2795  case 'x': // Any SSE register.
2796  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2797  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2798  case 'l': // "Index" registers: any general register that can be used as an
2799            // index in a base+index memory access.
2800    Info.setAllowsRegister();
2801    return true;
2802  case 'C': // SSE floating point constant.
2803  case 'G': // x87 floating point constant.
2804  case 'e': // 32-bit signed integer constant for use with zero-extending
2805            // x86_64 instructions.
2806  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2807            // x86_64 instructions.
2808    return true;
2809  }
2810}
2811
2812
2813std::string
2814X86TargetInfo::convertConstraint(const char *&Constraint) const {
2815  switch (*Constraint) {
2816  case 'a': return std::string("{ax}");
2817  case 'b': return std::string("{bx}");
2818  case 'c': return std::string("{cx}");
2819  case 'd': return std::string("{dx}");
2820  case 'S': return std::string("{si}");
2821  case 'D': return std::string("{di}");
2822  case 'p': // address
2823    return std::string("im");
2824  case 't': // top of floating point stack.
2825    return std::string("{st}");
2826  case 'u': // second from top of floating point stack.
2827    return std::string("{st(1)}"); // second from top of floating point stack.
2828  default:
2829    return std::string(1, *Constraint);
2830  }
2831}
2832} // end anonymous namespace
2833
2834namespace {
2835// X86-32 generic target
2836class X86_32TargetInfo : public X86TargetInfo {
2837public:
2838  X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2839    DoubleAlign = LongLongAlign = 32;
2840    LongDoubleWidth = 96;
2841    LongDoubleAlign = 32;
2842    SuitableAlign = 128;
2843    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2844                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2845                        "a0:0:64-f80:32:32-n8:16:32-S128";
2846    SizeType = UnsignedInt;
2847    PtrDiffType = SignedInt;
2848    IntPtrType = SignedInt;
2849    RegParmMax = 3;
2850
2851    // Use fpret for all types.
2852    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2853                             (1 << TargetInfo::Double) |
2854                             (1 << TargetInfo::LongDouble));
2855
2856    // x86-32 has atomics up to 8 bytes
2857    // FIXME: Check that we actually have cmpxchg8b before setting
2858    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2859    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2860  }
2861  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2862    return TargetInfo::CharPtrBuiltinVaList;
2863  }
2864
2865  int getEHDataRegisterNumber(unsigned RegNo) const {
2866    if (RegNo == 0) return 0;
2867    if (RegNo == 1) return 2;
2868    return -1;
2869  }
2870  virtual bool validateInputSize(StringRef Constraint,
2871                                 unsigned Size) const {
2872    switch (Constraint[0]) {
2873    default: break;
2874    case 'a':
2875    case 'b':
2876    case 'c':
2877    case 'd':
2878      return Size <= 32;
2879    }
2880
2881    return true;
2882  }
2883};
2884} // end anonymous namespace
2885
2886namespace {
2887class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2888public:
2889  NetBSDI386TargetInfo(const std::string &triple) :
2890    NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2891  }
2892
2893  virtual unsigned getFloatEvalMethod() const {
2894    // NetBSD defaults to "double" rounding
2895    return 1;
2896  }
2897};
2898} // end anonymous namespace
2899
2900namespace {
2901class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2902public:
2903  OpenBSDI386TargetInfo(const std::string& triple) :
2904    OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2905    SizeType = UnsignedLong;
2906    IntPtrType = SignedLong;
2907    PtrDiffType = SignedLong;
2908  }
2909};
2910} // end anonymous namespace
2911
2912namespace {
2913class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2914public:
2915  BitrigI386TargetInfo(const std::string& triple) :
2916    BitrigTargetInfo<X86_32TargetInfo>(triple) {
2917    SizeType = UnsignedLong;
2918    IntPtrType = SignedLong;
2919    PtrDiffType = SignedLong;
2920  }
2921};
2922} // end anonymous namespace
2923
2924namespace {
2925class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2926public:
2927  DarwinI386TargetInfo(const std::string& triple) :
2928    DarwinTargetInfo<X86_32TargetInfo>(triple) {
2929    LongDoubleWidth = 128;
2930    LongDoubleAlign = 128;
2931    SuitableAlign = 128;
2932    MaxVectorAlign = 256;
2933    SizeType = UnsignedLong;
2934    IntPtrType = SignedLong;
2935    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2936                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2937                        "a0:0:64-f80:128:128-n8:16:32-S128";
2938    HasAlignMac68kSupport = true;
2939  }
2940
2941};
2942} // end anonymous namespace
2943
2944namespace {
2945// x86-32 Windows target
2946class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2947public:
2948  WindowsX86_32TargetInfo(const std::string& triple)
2949    : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2950    TLSSupported = false;
2951    WCharType = UnsignedShort;
2952    DoubleAlign = LongLongAlign = 64;
2953    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2954                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2955                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2956  }
2957  virtual void getTargetDefines(const LangOptions &Opts,
2958                                MacroBuilder &Builder) const {
2959    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2960  }
2961};
2962} // end anonymous namespace
2963
2964namespace {
2965
2966// x86-32 Windows Visual Studio target
2967class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2968public:
2969  VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2970    : WindowsX86_32TargetInfo(triple) {
2971    LongDoubleWidth = LongDoubleAlign = 64;
2972    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2973  }
2974  virtual void getTargetDefines(const LangOptions &Opts,
2975                                MacroBuilder &Builder) const {
2976    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2977    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2978    // The value of the following reflects processor type.
2979    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2980    // We lost the original triple, so we use the default.
2981    Builder.defineMacro("_M_IX86", "600");
2982  }
2983};
2984} // end anonymous namespace
2985
2986namespace {
2987// x86-32 MinGW target
2988class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
2989public:
2990  MinGWX86_32TargetInfo(const std::string& triple)
2991    : WindowsX86_32TargetInfo(triple) {
2992  }
2993  virtual void getTargetDefines(const LangOptions &Opts,
2994                                MacroBuilder &Builder) const {
2995    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2996    DefineStd(Builder, "WIN32", Opts);
2997    DefineStd(Builder, "WINNT", Opts);
2998    Builder.defineMacro("_X86_");
2999    Builder.defineMacro("__MSVCRT__");
3000    Builder.defineMacro("__MINGW32__");
3001
3002    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3003    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3004    if (Opts.MicrosoftExt)
3005      // Provide "as-is" __declspec.
3006      Builder.defineMacro("__declspec", "__declspec");
3007    else
3008      // Provide alias of __attribute__ like mingw32-gcc.
3009      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3010  }
3011};
3012} // end anonymous namespace
3013
3014namespace {
3015// x86-32 Cygwin target
3016class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3017public:
3018  CygwinX86_32TargetInfo(const std::string& triple)
3019    : X86_32TargetInfo(triple) {
3020    TLSSupported = false;
3021    WCharType = UnsignedShort;
3022    DoubleAlign = LongLongAlign = 64;
3023    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3024                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3025                        "a0:0:64-f80:32:32-n8:16:32-S32";
3026  }
3027  virtual void getTargetDefines(const LangOptions &Opts,
3028                                MacroBuilder &Builder) const {
3029    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3030    Builder.defineMacro("_X86_");
3031    Builder.defineMacro("__CYGWIN__");
3032    Builder.defineMacro("__CYGWIN32__");
3033    DefineStd(Builder, "unix", Opts);
3034    if (Opts.CPlusPlus)
3035      Builder.defineMacro("_GNU_SOURCE");
3036  }
3037};
3038} // end anonymous namespace
3039
3040namespace {
3041// x86-32 Haiku target
3042class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3043public:
3044  HaikuX86_32TargetInfo(const std::string& triple)
3045    : X86_32TargetInfo(triple) {
3046    SizeType = UnsignedLong;
3047    IntPtrType = SignedLong;
3048    PtrDiffType = SignedLong;
3049    ProcessIDType = SignedLong;
3050    this->UserLabelPrefix = "";
3051    this->TLSSupported = false;
3052  }
3053  virtual void getTargetDefines(const LangOptions &Opts,
3054                                MacroBuilder &Builder) const {
3055    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3056    Builder.defineMacro("__INTEL__");
3057    Builder.defineMacro("__HAIKU__");
3058  }
3059};
3060} // end anonymous namespace
3061
3062// RTEMS Target
3063template<typename Target>
3064class RTEMSTargetInfo : public OSTargetInfo<Target> {
3065protected:
3066  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3067                            MacroBuilder &Builder) const {
3068    // RTEMS defines; list based off of gcc output
3069
3070    Builder.defineMacro("__rtems__");
3071    Builder.defineMacro("__ELF__");
3072  }
3073public:
3074  RTEMSTargetInfo(const std::string &triple)
3075    : OSTargetInfo<Target>(triple) {
3076      this->UserLabelPrefix = "";
3077
3078      llvm::Triple Triple(triple);
3079      switch (Triple.getArch()) {
3080        default:
3081        case llvm::Triple::x86:
3082          // this->MCountName = ".mcount";
3083          break;
3084        case llvm::Triple::mips:
3085        case llvm::Triple::mipsel:
3086        case llvm::Triple::ppc:
3087        case llvm::Triple::ppc64:
3088          // this->MCountName = "_mcount";
3089          break;
3090        case llvm::Triple::arm:
3091          // this->MCountName = "__mcount";
3092          break;
3093      }
3094
3095    }
3096};
3097
3098namespace {
3099// x86-32 RTEMS target
3100class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3101public:
3102  RTEMSX86_32TargetInfo(const std::string& triple)
3103    : X86_32TargetInfo(triple) {
3104    SizeType = UnsignedLong;
3105    IntPtrType = SignedLong;
3106    PtrDiffType = SignedLong;
3107    this->UserLabelPrefix = "";
3108  }
3109  virtual void getTargetDefines(const LangOptions &Opts,
3110                                MacroBuilder &Builder) const {
3111    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3112    Builder.defineMacro("__INTEL__");
3113    Builder.defineMacro("__rtems__");
3114  }
3115};
3116} // end anonymous namespace
3117
3118namespace {
3119// x86-64 generic target
3120class X86_64TargetInfo : public X86TargetInfo {
3121public:
3122  X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
3123    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3124    LongDoubleWidth = 128;
3125    LongDoubleAlign = 128;
3126    LargeArrayMinWidth = 128;
3127    LargeArrayAlign = 128;
3128    SuitableAlign = 128;
3129    IntMaxType = SignedLong;
3130    UIntMaxType = UnsignedLong;
3131    Int64Type = SignedLong;
3132    RegParmMax = 6;
3133
3134    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3135                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3136                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3137
3138    // Use fpret only for long double.
3139    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3140
3141    // Use fp2ret for _Complex long double.
3142    ComplexLongDoubleUsesFP2Ret = true;
3143
3144    // x86-64 has atomics up to 16 bytes.
3145    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3146    // on CPUs with cmpxchg16b
3147    MaxAtomicPromoteWidth = 128;
3148    MaxAtomicInlineWidth = 64;
3149  }
3150  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3151    return TargetInfo::X86_64ABIBuiltinVaList;
3152  }
3153
3154  int getEHDataRegisterNumber(unsigned RegNo) const {
3155    if (RegNo == 0) return 0;
3156    if (RegNo == 1) return 1;
3157    return -1;
3158  }
3159
3160  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3161    return (CC == CC_Default ||
3162            CC == CC_C ||
3163            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3164  }
3165
3166  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3167    return CC_C;
3168  }
3169
3170};
3171} // end anonymous namespace
3172
3173namespace {
3174// x86-64 Windows target
3175class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3176public:
3177  WindowsX86_64TargetInfo(const std::string& triple)
3178    : WindowsTargetInfo<X86_64TargetInfo>(triple) {
3179    TLSSupported = false;
3180    WCharType = UnsignedShort;
3181    LongWidth = LongAlign = 32;
3182    DoubleAlign = LongLongAlign = 64;
3183    IntMaxType = SignedLongLong;
3184    UIntMaxType = UnsignedLongLong;
3185    Int64Type = SignedLongLong;
3186    SizeType = UnsignedLongLong;
3187    PtrDiffType = SignedLongLong;
3188    IntPtrType = SignedLongLong;
3189    this->UserLabelPrefix = "";
3190  }
3191  virtual void getTargetDefines(const LangOptions &Opts,
3192                                MacroBuilder &Builder) const {
3193    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3194    Builder.defineMacro("_WIN64");
3195  }
3196  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3197    return TargetInfo::CharPtrBuiltinVaList;
3198  }
3199};
3200} // end anonymous namespace
3201
3202namespace {
3203// x86-64 Windows Visual Studio target
3204class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3205public:
3206  VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
3207    : WindowsX86_64TargetInfo(triple) {
3208    LongDoubleWidth = LongDoubleAlign = 64;
3209    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3210  }
3211  virtual void getTargetDefines(const LangOptions &Opts,
3212                                MacroBuilder &Builder) const {
3213    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3214    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3215    Builder.defineMacro("_M_X64");
3216    Builder.defineMacro("_M_AMD64");
3217  }
3218};
3219} // end anonymous namespace
3220
3221namespace {
3222// x86-64 MinGW target
3223class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3224public:
3225  MinGWX86_64TargetInfo(const std::string& triple)
3226    : WindowsX86_64TargetInfo(triple) {
3227  }
3228  virtual void getTargetDefines(const LangOptions &Opts,
3229                                MacroBuilder &Builder) const {
3230    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3231    DefineStd(Builder, "WIN64", Opts);
3232    Builder.defineMacro("__MSVCRT__");
3233    Builder.defineMacro("__MINGW32__");
3234    Builder.defineMacro("__MINGW64__");
3235
3236    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3237    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3238    if (Opts.MicrosoftExt)
3239      // Provide "as-is" __declspec.
3240      Builder.defineMacro("__declspec", "__declspec");
3241    else
3242      // Provide alias of __attribute__ like mingw32-gcc.
3243      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3244  }
3245};
3246} // end anonymous namespace
3247
3248namespace {
3249class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3250public:
3251  DarwinX86_64TargetInfo(const std::string& triple)
3252      : DarwinTargetInfo<X86_64TargetInfo>(triple) {
3253    Int64Type = SignedLongLong;
3254    MaxVectorAlign = 256;
3255  }
3256};
3257} // end anonymous namespace
3258
3259namespace {
3260class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3261public:
3262  OpenBSDX86_64TargetInfo(const std::string& triple)
3263      : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
3264    IntMaxType = SignedLongLong;
3265    UIntMaxType = UnsignedLongLong;
3266    Int64Type = SignedLongLong;
3267  }
3268};
3269} // end anonymous namespace
3270
3271namespace {
3272class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3273public:
3274  BitrigX86_64TargetInfo(const std::string& triple)
3275      : BitrigTargetInfo<X86_64TargetInfo>(triple) {
3276     IntMaxType = SignedLongLong;
3277     UIntMaxType = UnsignedLongLong;
3278     Int64Type = SignedLongLong;
3279  }
3280};
3281}
3282
3283namespace {
3284class AArch64TargetInfo : public TargetInfo {
3285  static const char * const GCCRegNames[];
3286  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3287public:
3288  AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) {
3289    BigEndian = false;
3290    LongWidth = LongAlign = 64;
3291    LongDoubleWidth = LongDoubleAlign = 128;
3292    PointerWidth = PointerAlign = 64;
3293    SuitableAlign = 128;
3294    DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3295                        "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3296                        "f128:128:128-n32:64-S128";
3297
3298    WCharType = UnsignedInt;
3299    LongDoubleFormat = &llvm::APFloat::IEEEquad;
3300
3301    // AArch64 backend supports 64-bit operations at the moment. In principle
3302    // 128-bit is possible if register-pairs are used.
3303    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3304
3305    TheCXXABI.set(TargetCXXABI::GenericAArch64);
3306  }
3307  virtual void getTargetDefines(const LangOptions &Opts,
3308                                MacroBuilder &Builder) const {
3309    // GCC defines theses currently
3310    Builder.defineMacro("__aarch64__");
3311    Builder.defineMacro("__AARCH64EL__");
3312
3313    // ACLE predefines. Many can only have one possible value on v8 AArch64.
3314
3315    // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3316    // which was intended to be compatible with a 64-bit implementation. They
3317    // will need updating when a real 64-bit ACLE exists. Particularly pressing
3318    // instances are: __AARCH_ISA_A32, __AARCH_ISA_T32, __ARCH_PCS.
3319    Builder.defineMacro("__AARCH_ACLE",    "101");
3320    Builder.defineMacro("__AARCH",         "8");
3321    Builder.defineMacro("__AARCH_PROFILE", "'A'");
3322
3323    Builder.defineMacro("__AARCH_FEATURE_UNALIGNED");
3324    Builder.defineMacro("__AARCH_FEATURE_CLZ");
3325    Builder.defineMacro("__AARCH_FEATURE_FMA");
3326
3327    // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3328    // 128-bit LDXP present, at which point this becomes 0x1f.
3329    Builder.defineMacro("__AARCH_FEATURE_LDREX", "0xf");
3330
3331    // 0xe implies support for half, single and double precision operations.
3332    Builder.defineMacro("__AARCH_FP", "0xe");
3333
3334    // PCS specifies this for SysV variants, which is all we support. Other ABIs
3335    // may choose __AARCH_FP16_FORMAT_ALTERNATIVE.
3336    Builder.defineMacro("__AARCH_FP16_FORMAT_IEEE");
3337
3338    if (Opts.FastMath || Opts.FiniteMathOnly)
3339      Builder.defineMacro("__AARCH_FP_FAST");
3340
3341    if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3342      Builder.defineMacro("__AARCH_FP_FENV_ROUNDING");
3343
3344    Builder.defineMacro("__AARCH_SIZEOF_WCHAR_T",
3345                        Opts.ShortWChar ? "2" : "4");
3346
3347    Builder.defineMacro("__AARCH_SIZEOF_MINIMAL_ENUM",
3348                        Opts.ShortEnums ? "1" : "4");
3349
3350    if (BigEndian)
3351      Builder.defineMacro("__AARCH_BIG_ENDIAN");
3352  }
3353  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3354                                 unsigned &NumRecords) const {
3355    Records = 0;
3356    NumRecords = 0;
3357  }
3358  virtual bool hasFeature(StringRef Feature) const {
3359    return Feature == "aarch64";
3360  }
3361  virtual void getGCCRegNames(const char * const *&Names,
3362                              unsigned &NumNames) const;
3363  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3364                                unsigned &NumAliases) const;
3365
3366  virtual bool isCLZForZeroUndef() const { return false; }
3367
3368  virtual bool validateAsmConstraint(const char *&Name,
3369                                     TargetInfo::ConstraintInfo &Info) const {
3370    switch (*Name) {
3371    default: return false;
3372    case 'w': // An FP/SIMD vector register
3373      Info.setAllowsRegister();
3374      return true;
3375    case 'I': // Constant that can be used with an ADD instruction
3376    case 'J': // Constant that can be used with a SUB instruction
3377    case 'K': // Constant that can be used with a 32-bit logical instruction
3378    case 'L': // Constant that can be used with a 64-bit logical instruction
3379    case 'M': // Constant that can be used as a 32-bit MOV immediate
3380    case 'N': // Constant that can be used as a 64-bit MOV immediate
3381    case 'Y': // Floating point constant zero
3382    case 'Z': // Integer constant zero
3383      return true;
3384    case 'Q': // A memory reference with base register and no offset
3385      Info.setAllowsMemory();
3386      return true;
3387    case 'S': // A symbolic address
3388      Info.setAllowsRegister();
3389      return true;
3390    case 'U':
3391      // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3392      // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3393      // Usa: An absolute symbolic address
3394      // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3395      llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3396    }
3397  }
3398
3399  virtual const char *getClobbers() const {
3400    // There are no AArch64 clobbers shared by all asm statements.
3401    return "";
3402  }
3403
3404  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3405    return TargetInfo::AArch64ABIBuiltinVaList;
3406  }
3407};
3408
3409const char * const AArch64TargetInfo::GCCRegNames[] = {
3410  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3411  "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3412  "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3413  "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3414
3415  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3416  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3417  "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3418  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3419
3420  "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3421  "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3422  "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3423  "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3424
3425  "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3426  "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3427  "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3428  "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3429
3430  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3431  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3432  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3433  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3434
3435  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3436  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3437  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3438  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3439
3440  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3441  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3442  "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3443  "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3444};
3445
3446void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3447                                       unsigned &NumNames) const {
3448  Names = GCCRegNames;
3449  NumNames = llvm::array_lengthof(GCCRegNames);
3450}
3451
3452const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3453  { { "x16" }, "ip0"},
3454  { { "x17" }, "ip1"},
3455  { { "x29" }, "fp" },
3456  { { "x30" }, "lr" }
3457};
3458
3459void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3460                                         unsigned &NumAliases) const {
3461  Aliases = GCCRegAliases;
3462  NumAliases = llvm::array_lengthof(GCCRegAliases);
3463
3464}
3465} // end anonymous namespace
3466
3467namespace {
3468class ARMTargetInfo : public TargetInfo {
3469  // Possible FPU choices.
3470  enum FPUMode {
3471    VFP2FPU = (1 << 0),
3472    VFP3FPU = (1 << 1),
3473    VFP4FPU = (1 << 2),
3474    NeonFPU = (1 << 3)
3475  };
3476
3477  static bool FPUModeIsVFP(FPUMode Mode) {
3478    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3479  }
3480
3481  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3482  static const char * const GCCRegNames[];
3483
3484  std::string ABI, CPU;
3485
3486  unsigned FPU : 4;
3487
3488  unsigned IsAAPCS : 1;
3489  unsigned IsThumb : 1;
3490
3491  // Initialized via features.
3492  unsigned SoftFloat : 1;
3493  unsigned SoftFloatABI : 1;
3494
3495  static const Builtin::Info BuiltinInfo[];
3496
3497public:
3498  ARMTargetInfo(const std::string &TripleStr)
3499    : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3500  {
3501    BigEndian = false;
3502    SizeType = UnsignedInt;
3503    PtrDiffType = SignedInt;
3504    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3505    WCharType = UnsignedInt;
3506
3507    // {} in inline assembly are neon specifiers, not assembly variant
3508    // specifiers.
3509    NoAsmVariants = true;
3510
3511    // FIXME: Should we just treat this as a feature?
3512    IsThumb = getTriple().getArchName().startswith("thumb");
3513    if (IsThumb) {
3514      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3515      // so set preferred for small types to 32.
3516      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3517                           "i64:64:64-f32:32:32-f64:64:64-"
3518                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3519    } else {
3520      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3521                           "i64:64:64-f32:32:32-f64:64:64-"
3522                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3523    }
3524
3525    // ARM targets default to using the ARM C++ ABI.
3526    TheCXXABI.set(TargetCXXABI::GenericARM);
3527
3528    // ARM has atomics up to 8 bytes
3529    // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e
3530    MaxAtomicPromoteWidth = 64;
3531
3532    // Do force alignment of members that follow zero length bitfields.  If
3533    // the alignment of the zero-length bitfield is greater than the member
3534    // that follows it, `bar', `bar' will be aligned as the  type of the
3535    // zero length bitfield.
3536    UseZeroLengthBitfieldAlignment = true;
3537  }
3538  virtual const char *getABI() const { return ABI.c_str(); }
3539  virtual bool setABI(const std::string &Name) {
3540    ABI = Name;
3541
3542    // The defaults (above) are for AAPCS, check if we need to change them.
3543    //
3544    // FIXME: We need support for -meabi... we could just mangle it into the
3545    // name.
3546    if (Name == "apcs-gnu") {
3547      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3548      // size_t is unsigned int on FreeBSD.
3549      if (getTriple().getOS() != llvm::Triple::FreeBSD)
3550        SizeType = UnsignedLong;
3551
3552      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3553      WCharType = SignedInt;
3554
3555      // Do not respect the alignment of bit-field types when laying out
3556      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3557      UseBitFieldTypeAlignment = false;
3558
3559      /// gcc forces the alignment to 4 bytes, regardless of the type of the
3560      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3561      /// gcc.
3562      ZeroLengthBitfieldBoundary = 32;
3563
3564      IsAAPCS = false;
3565
3566      if (IsThumb) {
3567        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3568        // so set preferred for small types to 32.
3569        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3570                             "i64:32:64-f32:32:32-f64:32:64-"
3571                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3572      } else {
3573        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3574                             "i64:32:64-f32:32:32-f64:32:64-"
3575                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3576      }
3577
3578      // FIXME: Override "preferred align" for double and long long.
3579    } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3580      IsAAPCS = true;
3581      // FIXME: Enumerated types are variable width in straight AAPCS.
3582    } else if (Name == "aapcs-linux") {
3583      IsAAPCS = true;
3584    } else
3585      return false;
3586
3587    return true;
3588  }
3589
3590  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3591    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3592      Features["vfp2"] = true;
3593    else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3594             CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3595      Features["neon"] = true;
3596    else if (CPU == "swift" || CPU == "cortex-a7") {
3597      Features["vfp4"] = true;
3598      Features["neon"] = true;
3599    }
3600  }
3601
3602  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3603                                 StringRef Name,
3604                                 bool Enabled) const {
3605    if (Name == "soft-float" || Name == "soft-float-abi" ||
3606        Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3607        Name == "d16" || Name == "neonfp") {
3608      Features[Name] = Enabled;
3609    } else
3610      return false;
3611
3612    return true;
3613  }
3614
3615  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3616    FPU = 0;
3617    SoftFloat = SoftFloatABI = false;
3618    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3619      if (Features[i] == "+soft-float")
3620        SoftFloat = true;
3621      else if (Features[i] == "+soft-float-abi")
3622        SoftFloatABI = true;
3623      else if (Features[i] == "+vfp2")
3624        FPU |= VFP2FPU;
3625      else if (Features[i] == "+vfp3")
3626        FPU |= VFP3FPU;
3627      else if (Features[i] == "+vfp4")
3628        FPU |= VFP4FPU;
3629      else if (Features[i] == "+neon")
3630        FPU |= NeonFPU;
3631    }
3632
3633    // Remove front-end specific options which the backend handles differently.
3634    std::vector<std::string>::iterator it;
3635    it = std::find(Features.begin(), Features.end(), "+soft-float");
3636    if (it != Features.end())
3637      Features.erase(it);
3638    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3639    if (it != Features.end())
3640      Features.erase(it);
3641  }
3642
3643  virtual bool hasFeature(StringRef Feature) const {
3644    return llvm::StringSwitch<bool>(Feature)
3645        .Case("arm", true)
3646        .Case("softfloat", SoftFloat)
3647        .Case("thumb", IsThumb)
3648        .Case("neon", FPU == NeonFPU && !SoftFloat &&
3649              StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3650        .Default(false);
3651  }
3652  // FIXME: Should we actually have some table instead of these switches?
3653  static const char *getCPUDefineSuffix(StringRef Name) {
3654    return llvm::StringSwitch<const char*>(Name)
3655      .Cases("arm8", "arm810", "4")
3656      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3657      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3658      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3659      .Case("ep9312", "4T")
3660      .Cases("arm10tdmi", "arm1020t", "5T")
3661      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3662      .Case("arm926ej-s", "5TEJ")
3663      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3664      .Cases("xscale", "iwmmxt", "5TE")
3665      .Case("arm1136j-s", "6J")
3666      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3667      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3668      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3669      .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3670      .Cases("cortex-a9", "cortex-a15", "7A")
3671      .Case("cortex-r5", "7R")
3672      .Case("cortex-a9-mp", "7F")
3673      .Case("swift", "7S")
3674      .Cases("cortex-m3", "cortex-m4", "7M")
3675      .Case("cortex-m0", "6M")
3676      .Default(0);
3677  }
3678  static const char *getCPUProfile(StringRef Name) {
3679    return llvm::StringSwitch<const char*>(Name)
3680      .Cases("cortex-a8", "cortex-a9", "A")
3681      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3682      .Case("cortex-r5", "R")
3683      .Default("");
3684  }
3685  virtual bool setCPU(const std::string &Name) {
3686    if (!getCPUDefineSuffix(Name))
3687      return false;
3688
3689    CPU = Name;
3690    return true;
3691  }
3692  virtual void getTargetDefines(const LangOptions &Opts,
3693                                MacroBuilder &Builder) const {
3694    // Target identification.
3695    Builder.defineMacro("__arm");
3696    Builder.defineMacro("__arm__");
3697
3698    // Target properties.
3699    Builder.defineMacro("__ARMEL__");
3700    Builder.defineMacro("__LITTLE_ENDIAN__");
3701    Builder.defineMacro("__REGISTER_PREFIX__", "");
3702
3703    StringRef CPUArch = getCPUDefineSuffix(CPU);
3704    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3705    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3706    StringRef CPUProfile = getCPUProfile(CPU);
3707    if (!CPUProfile.empty())
3708      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3709
3710    // Subtarget options.
3711
3712    // FIXME: It's more complicated than this and we don't really support
3713    // interworking.
3714    if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3715      Builder.defineMacro("__THUMB_INTERWORK__");
3716
3717    if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3718      // M-class CPUs on Darwin follow AAPCS, but not EABI.
3719      if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3720        Builder.defineMacro("__ARM_EABI__");
3721      Builder.defineMacro("__ARM_PCS", "1");
3722
3723      if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3724        Builder.defineMacro("__ARM_PCS_VFP", "1");
3725    }
3726
3727    if (SoftFloat)
3728      Builder.defineMacro("__SOFTFP__");
3729
3730    if (CPU == "xscale")
3731      Builder.defineMacro("__XSCALE__");
3732
3733    bool IsARMv7 = CPUArch.startswith("7");
3734    if (IsThumb) {
3735      Builder.defineMacro("__THUMBEL__");
3736      Builder.defineMacro("__thumb__");
3737      if (CPUArch == "6T2" || IsARMv7)
3738        Builder.defineMacro("__thumb2__");
3739    }
3740
3741    // Note, this is always on in gcc, even though it doesn't make sense.
3742    Builder.defineMacro("__APCS_32__");
3743
3744    if (FPUModeIsVFP((FPUMode) FPU)) {
3745      Builder.defineMacro("__VFP_FP__");
3746      if (FPU & VFP2FPU)
3747        Builder.defineMacro("__ARM_VFPV2__");
3748      if (FPU & VFP3FPU)
3749        Builder.defineMacro("__ARM_VFPV3__");
3750      if (FPU & VFP4FPU)
3751        Builder.defineMacro("__ARM_VFPV4__");
3752    }
3753
3754    // This only gets set when Neon instructions are actually available, unlike
3755    // the VFP define, hence the soft float and arch check. This is subtly
3756    // different from gcc, we follow the intent which was that it should be set
3757    // when Neon instructions are actually available.
3758    if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3759      Builder.defineMacro("__ARM_NEON__");
3760  }
3761  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3762                                 unsigned &NumRecords) const {
3763    Records = BuiltinInfo;
3764    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3765  }
3766  virtual bool isCLZForZeroUndef() const { return false; }
3767  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3768    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3769  }
3770  virtual void getGCCRegNames(const char * const *&Names,
3771                              unsigned &NumNames) const;
3772  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3773                                unsigned &NumAliases) const;
3774  virtual bool validateAsmConstraint(const char *&Name,
3775                                     TargetInfo::ConstraintInfo &Info) const {
3776    switch (*Name) {
3777    default: break;
3778    case 'l': // r0-r7
3779    case 'h': // r8-r15
3780    case 'w': // VFP Floating point register single precision
3781    case 'P': // VFP Floating point register double precision
3782      Info.setAllowsRegister();
3783      return true;
3784    case 'Q': // A memory address that is a single base register.
3785      Info.setAllowsMemory();
3786      return true;
3787    case 'U': // a memory reference...
3788      switch (Name[1]) {
3789      case 'q': // ...ARMV4 ldrsb
3790      case 'v': // ...VFP load/store (reg+constant offset)
3791      case 'y': // ...iWMMXt load/store
3792      case 't': // address valid for load/store opaque types wider
3793                // than 128-bits
3794      case 'n': // valid address for Neon doubleword vector load/store
3795      case 'm': // valid address for Neon element and structure load/store
3796      case 's': // valid address for non-offset loads/stores of quad-word
3797                // values in four ARM registers
3798        Info.setAllowsMemory();
3799        Name++;
3800        return true;
3801      }
3802    }
3803    return false;
3804  }
3805  virtual std::string convertConstraint(const char *&Constraint) const {
3806    std::string R;
3807    switch (*Constraint) {
3808    case 'U':   // Two-character constraint; add "^" hint for later parsing.
3809      R = std::string("^") + std::string(Constraint, 2);
3810      Constraint++;
3811      break;
3812    case 'p': // 'p' should be translated to 'r' by default.
3813      R = std::string("r");
3814      break;
3815    default:
3816      return std::string(1, *Constraint);
3817    }
3818    return R;
3819  }
3820  virtual bool validateConstraintModifier(StringRef Constraint,
3821                                          const char Modifier,
3822                                          unsigned Size) const {
3823    bool isOutput = (Constraint[0] == '=');
3824    bool isInOut = (Constraint[0] == '+');
3825
3826    // Strip off constraint modifiers.
3827    while (Constraint[0] == '=' ||
3828           Constraint[0] == '+' ||
3829           Constraint[0] == '&')
3830      Constraint = Constraint.substr(1);
3831
3832    switch (Constraint[0]) {
3833    default: break;
3834    case 'r': {
3835      switch (Modifier) {
3836      default:
3837        return isInOut || (isOutput && Size >= 32) ||
3838          (!isOutput && !isInOut && Size <= 32);
3839      case 'q':
3840        // A register of size 32 cannot fit a vector type.
3841        return false;
3842      }
3843    }
3844    }
3845
3846    return true;
3847  }
3848  virtual const char *getClobbers() const {
3849    // FIXME: Is this really right?
3850    return "";
3851  }
3852
3853  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3854    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3855  }
3856
3857  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3858    if (RegNo == 0) return 0;
3859    if (RegNo == 1) return 1;
3860    return -1;
3861  }
3862};
3863
3864const char * const ARMTargetInfo::GCCRegNames[] = {
3865  // Integer registers
3866  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3867  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3868
3869  // Float registers
3870  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3871  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3872  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3873  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3874
3875  // Double registers
3876  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3877  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3878  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3879  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3880
3881  // Quad registers
3882  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3883  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3884};
3885
3886void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3887                                   unsigned &NumNames) const {
3888  Names = GCCRegNames;
3889  NumNames = llvm::array_lengthof(GCCRegNames);
3890}
3891
3892const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3893  { { "a1" }, "r0" },
3894  { { "a2" }, "r1" },
3895  { { "a3" }, "r2" },
3896  { { "a4" }, "r3" },
3897  { { "v1" }, "r4" },
3898  { { "v2" }, "r5" },
3899  { { "v3" }, "r6" },
3900  { { "v4" }, "r7" },
3901  { { "v5" }, "r8" },
3902  { { "v6", "rfp" }, "r9" },
3903  { { "sl" }, "r10" },
3904  { { "fp" }, "r11" },
3905  { { "ip" }, "r12" },
3906  { { "r13" }, "sp" },
3907  { { "r14" }, "lr" },
3908  { { "r15" }, "pc" },
3909  // The S, D and Q registers overlap, but aren't really aliases; we
3910  // don't want to substitute one of these for a different-sized one.
3911};
3912
3913void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3914                                       unsigned &NumAliases) const {
3915  Aliases = GCCRegAliases;
3916  NumAliases = llvm::array_lengthof(GCCRegAliases);
3917}
3918
3919const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3920#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3921#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3922                                              ALL_LANGUAGES },
3923#include "clang/Basic/BuiltinsARM.def"
3924};
3925} // end anonymous namespace.
3926
3927namespace {
3928class DarwinARMTargetInfo :
3929  public DarwinTargetInfo<ARMTargetInfo> {
3930protected:
3931  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3932                            MacroBuilder &Builder) const {
3933    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3934  }
3935
3936public:
3937  DarwinARMTargetInfo(const std::string& triple)
3938    : DarwinTargetInfo<ARMTargetInfo>(triple) {
3939    HasAlignMac68kSupport = true;
3940    // iOS always has 64-bit atomic instructions.
3941    // FIXME: This should be based off of the target features in ARMTargetInfo.
3942    MaxAtomicInlineWidth = 64;
3943
3944    // Darwin on iOS uses a variant of the ARM C++ ABI.
3945    TheCXXABI.set(TargetCXXABI::iOS);
3946  }
3947};
3948} // end anonymous namespace.
3949
3950
3951namespace {
3952// Hexagon abstract base class
3953class HexagonTargetInfo : public TargetInfo {
3954  static const Builtin::Info BuiltinInfo[];
3955  static const char * const GCCRegNames[];
3956  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3957  std::string CPU;
3958public:
3959  HexagonTargetInfo(const std::string& triple) : TargetInfo(triple)  {
3960    BigEndian = false;
3961    DescriptionString = ("e-p:32:32:32-"
3962                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
3963                         "f64:64:64-f32:32:32-a0:0-n32");
3964
3965    // {} in inline assembly are packet specifiers, not assembly variant
3966    // specifiers.
3967    NoAsmVariants = true;
3968  }
3969
3970  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3971                                 unsigned &NumRecords) const {
3972    Records = BuiltinInfo;
3973    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
3974  }
3975
3976  virtual bool validateAsmConstraint(const char *&Name,
3977                                     TargetInfo::ConstraintInfo &Info) const {
3978    return true;
3979  }
3980
3981  virtual void getTargetDefines(const LangOptions &Opts,
3982                                MacroBuilder &Builder) const;
3983
3984  virtual bool hasFeature(StringRef Feature) const {
3985    return Feature == "hexagon";
3986  }
3987
3988  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3989    return TargetInfo::CharPtrBuiltinVaList;
3990  }
3991  virtual void getGCCRegNames(const char * const *&Names,
3992                              unsigned &NumNames) const;
3993  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3994                                unsigned &NumAliases) const;
3995  virtual const char *getClobbers() const {
3996    return "";
3997  }
3998
3999  static const char *getHexagonCPUSuffix(StringRef Name) {
4000    return llvm::StringSwitch<const char*>(Name)
4001      .Case("hexagonv4", "4")
4002      .Case("hexagonv5", "5")
4003      .Default(0);
4004  }
4005
4006  virtual bool setCPU(const std::string &Name) {
4007    if (!getHexagonCPUSuffix(Name))
4008      return false;
4009
4010    CPU = Name;
4011    return true;
4012  }
4013};
4014
4015void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4016                                MacroBuilder &Builder) const {
4017  Builder.defineMacro("qdsp6");
4018  Builder.defineMacro("__qdsp6", "1");
4019  Builder.defineMacro("__qdsp6__", "1");
4020
4021  Builder.defineMacro("hexagon");
4022  Builder.defineMacro("__hexagon", "1");
4023  Builder.defineMacro("__hexagon__", "1");
4024
4025  if(CPU == "hexagonv1") {
4026    Builder.defineMacro("__HEXAGON_V1__");
4027    Builder.defineMacro("__HEXAGON_ARCH__", "1");
4028    if(Opts.HexagonQdsp6Compat) {
4029      Builder.defineMacro("__QDSP6_V1__");
4030      Builder.defineMacro("__QDSP6_ARCH__", "1");
4031    }
4032  }
4033  else if(CPU == "hexagonv2") {
4034    Builder.defineMacro("__HEXAGON_V2__");
4035    Builder.defineMacro("__HEXAGON_ARCH__", "2");
4036    if(Opts.HexagonQdsp6Compat) {
4037      Builder.defineMacro("__QDSP6_V2__");
4038      Builder.defineMacro("__QDSP6_ARCH__", "2");
4039    }
4040  }
4041  else if(CPU == "hexagonv3") {
4042    Builder.defineMacro("__HEXAGON_V3__");
4043    Builder.defineMacro("__HEXAGON_ARCH__", "3");
4044    if(Opts.HexagonQdsp6Compat) {
4045      Builder.defineMacro("__QDSP6_V3__");
4046      Builder.defineMacro("__QDSP6_ARCH__", "3");
4047    }
4048  }
4049  else if(CPU == "hexagonv4") {
4050    Builder.defineMacro("__HEXAGON_V4__");
4051    Builder.defineMacro("__HEXAGON_ARCH__", "4");
4052    if(Opts.HexagonQdsp6Compat) {
4053      Builder.defineMacro("__QDSP6_V4__");
4054      Builder.defineMacro("__QDSP6_ARCH__", "4");
4055    }
4056  }
4057  else if(CPU == "hexagonv5") {
4058    Builder.defineMacro("__HEXAGON_V5__");
4059    Builder.defineMacro("__HEXAGON_ARCH__", "5");
4060    if(Opts.HexagonQdsp6Compat) {
4061      Builder.defineMacro("__QDSP6_V5__");
4062      Builder.defineMacro("__QDSP6_ARCH__", "5");
4063    }
4064  }
4065}
4066
4067const char * const HexagonTargetInfo::GCCRegNames[] = {
4068  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4069  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4070  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4071  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4072  "p0", "p1", "p2", "p3",
4073  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4074};
4075
4076void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4077                                   unsigned &NumNames) const {
4078  Names = GCCRegNames;
4079  NumNames = llvm::array_lengthof(GCCRegNames);
4080}
4081
4082
4083const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4084  { { "sp" }, "r29" },
4085  { { "fp" }, "r30" },
4086  { { "lr" }, "r31" },
4087 };
4088
4089void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4090                                     unsigned &NumAliases) const {
4091  Aliases = GCCRegAliases;
4092  NumAliases = llvm::array_lengthof(GCCRegAliases);
4093}
4094
4095
4096const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4097#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4098#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4099                                              ALL_LANGUAGES },
4100#include "clang/Basic/BuiltinsHexagon.def"
4101};
4102}
4103
4104
4105namespace {
4106class SparcV8TargetInfo : public TargetInfo {
4107  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4108  static const char * const GCCRegNames[];
4109  bool SoftFloat;
4110public:
4111  SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) {
4112    // FIXME: Support Sparc quad-precision long double?
4113    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4114                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32";
4115  }
4116  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4117                                 StringRef Name,
4118                                 bool Enabled) const {
4119    if (Name == "soft-float")
4120      Features[Name] = Enabled;
4121    else
4122      return false;
4123
4124    return true;
4125  }
4126  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4127    SoftFloat = false;
4128    for (unsigned i = 0, e = Features.size(); i != e; ++i)
4129      if (Features[i] == "+soft-float")
4130        SoftFloat = true;
4131  }
4132  virtual void getTargetDefines(const LangOptions &Opts,
4133                                MacroBuilder &Builder) const {
4134    DefineStd(Builder, "sparc", Opts);
4135    Builder.defineMacro("__sparcv8");
4136    Builder.defineMacro("__REGISTER_PREFIX__", "");
4137
4138    if (SoftFloat)
4139      Builder.defineMacro("SOFT_FLOAT", "1");
4140  }
4141
4142  virtual bool hasFeature(StringRef Feature) const {
4143    return llvm::StringSwitch<bool>(Feature)
4144             .Case("softfloat", SoftFloat)
4145             .Case("sparc", true)
4146             .Default(false);
4147  }
4148
4149  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4150                                 unsigned &NumRecords) const {
4151    // FIXME: Implement!
4152  }
4153  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4154    return TargetInfo::VoidPtrBuiltinVaList;
4155  }
4156  virtual void getGCCRegNames(const char * const *&Names,
4157                              unsigned &NumNames) const;
4158  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4159                                unsigned &NumAliases) const;
4160  virtual bool validateAsmConstraint(const char *&Name,
4161                                     TargetInfo::ConstraintInfo &info) const {
4162    // FIXME: Implement!
4163    return false;
4164  }
4165  virtual const char *getClobbers() const {
4166    // FIXME: Implement!
4167    return "";
4168  }
4169};
4170
4171const char * const SparcV8TargetInfo::GCCRegNames[] = {
4172  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4173  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4174  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4175  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4176};
4177
4178void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names,
4179                                       unsigned &NumNames) const {
4180  Names = GCCRegNames;
4181  NumNames = llvm::array_lengthof(GCCRegNames);
4182}
4183
4184const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = {
4185  { { "g0" }, "r0" },
4186  { { "g1" }, "r1" },
4187  { { "g2" }, "r2" },
4188  { { "g3" }, "r3" },
4189  { { "g4" }, "r4" },
4190  { { "g5" }, "r5" },
4191  { { "g6" }, "r6" },
4192  { { "g7" }, "r7" },
4193  { { "o0" }, "r8" },
4194  { { "o1" }, "r9" },
4195  { { "o2" }, "r10" },
4196  { { "o3" }, "r11" },
4197  { { "o4" }, "r12" },
4198  { { "o5" }, "r13" },
4199  { { "o6", "sp" }, "r14" },
4200  { { "o7" }, "r15" },
4201  { { "l0" }, "r16" },
4202  { { "l1" }, "r17" },
4203  { { "l2" }, "r18" },
4204  { { "l3" }, "r19" },
4205  { { "l4" }, "r20" },
4206  { { "l5" }, "r21" },
4207  { { "l6" }, "r22" },
4208  { { "l7" }, "r23" },
4209  { { "i0" }, "r24" },
4210  { { "i1" }, "r25" },
4211  { { "i2" }, "r26" },
4212  { { "i3" }, "r27" },
4213  { { "i4" }, "r28" },
4214  { { "i5" }, "r29" },
4215  { { "i6", "fp" }, "r30" },
4216  { { "i7" }, "r31" },
4217};
4218
4219void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4220                                         unsigned &NumAliases) const {
4221  Aliases = GCCRegAliases;
4222  NumAliases = llvm::array_lengthof(GCCRegAliases);
4223}
4224} // end anonymous namespace.
4225
4226namespace {
4227class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4228public:
4229  AuroraUXSparcV8TargetInfo(const std::string& triple) :
4230      AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
4231    SizeType = UnsignedInt;
4232    PtrDiffType = SignedInt;
4233  }
4234};
4235class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4236public:
4237  SolarisSparcV8TargetInfo(const std::string& triple) :
4238      SolarisTargetInfo<SparcV8TargetInfo>(triple) {
4239    SizeType = UnsignedInt;
4240    PtrDiffType = SignedInt;
4241  }
4242};
4243} // end anonymous namespace.
4244
4245namespace {
4246  class MSP430TargetInfo : public TargetInfo {
4247    static const char * const GCCRegNames[];
4248  public:
4249    MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
4250      BigEndian = false;
4251      TLSSupported = false;
4252      IntWidth = 16; IntAlign = 16;
4253      LongWidth = 32; LongLongWidth = 64;
4254      LongAlign = LongLongAlign = 16;
4255      PointerWidth = 16; PointerAlign = 16;
4256      SuitableAlign = 16;
4257      SizeType = UnsignedInt;
4258      IntMaxType = SignedLong;
4259      UIntMaxType = UnsignedLong;
4260      IntPtrType = SignedShort;
4261      PtrDiffType = SignedInt;
4262      SigAtomicType = SignedLong;
4263      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4264   }
4265    virtual void getTargetDefines(const LangOptions &Opts,
4266                                  MacroBuilder &Builder) const {
4267      Builder.defineMacro("MSP430");
4268      Builder.defineMacro("__MSP430__");
4269      // FIXME: defines for different 'flavours' of MCU
4270    }
4271    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4272                                   unsigned &NumRecords) const {
4273     // FIXME: Implement.
4274      Records = 0;
4275      NumRecords = 0;
4276    }
4277    virtual bool hasFeature(StringRef Feature) const {
4278      return Feature == "msp430";
4279    }
4280    virtual void getGCCRegNames(const char * const *&Names,
4281                                unsigned &NumNames) const;
4282    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4283                                  unsigned &NumAliases) const {
4284      // No aliases.
4285      Aliases = 0;
4286      NumAliases = 0;
4287    }
4288    virtual bool validateAsmConstraint(const char *&Name,
4289                                       TargetInfo::ConstraintInfo &info) const {
4290      // No target constraints for now.
4291      return false;
4292    }
4293    virtual const char *getClobbers() const {
4294      // FIXME: Is this really right?
4295      return "";
4296    }
4297    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4298      // FIXME: implement
4299      return TargetInfo::CharPtrBuiltinVaList;
4300   }
4301  };
4302
4303  const char * const MSP430TargetInfo::GCCRegNames[] = {
4304    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4305    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4306  };
4307
4308  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4309                                        unsigned &NumNames) const {
4310    Names = GCCRegNames;
4311    NumNames = llvm::array_lengthof(GCCRegNames);
4312  }
4313}
4314
4315namespace {
4316
4317  // LLVM and Clang cannot be used directly to output native binaries for
4318  // target, but is used to compile C code to llvm bitcode with correct
4319  // type and alignment information.
4320  //
4321  // TCE uses the llvm bitcode as input and uses it for generating customized
4322  // target processor and program binary. TCE co-design environment is
4323  // publicly available in http://tce.cs.tut.fi
4324
4325  static const unsigned TCEOpenCLAddrSpaceMap[] = {
4326      3, // opencl_global
4327      4, // opencl_local
4328      5, // opencl_constant
4329      0, // cuda_device
4330      0, // cuda_constant
4331      0  // cuda_shared
4332  };
4333
4334  class TCETargetInfo : public TargetInfo{
4335  public:
4336    TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
4337      TLSSupported = false;
4338      IntWidth = 32;
4339      LongWidth = LongLongWidth = 32;
4340      PointerWidth = 32;
4341      IntAlign = 32;
4342      LongAlign = LongLongAlign = 32;
4343      PointerAlign = 32;
4344      SuitableAlign = 32;
4345      SizeType = UnsignedInt;
4346      IntMaxType = SignedLong;
4347      UIntMaxType = UnsignedLong;
4348      IntPtrType = SignedInt;
4349      PtrDiffType = SignedInt;
4350      FloatWidth = 32;
4351      FloatAlign = 32;
4352      DoubleWidth = 32;
4353      DoubleAlign = 32;
4354      LongDoubleWidth = 32;
4355      LongDoubleAlign = 32;
4356      FloatFormat = &llvm::APFloat::IEEEsingle;
4357      DoubleFormat = &llvm::APFloat::IEEEsingle;
4358      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4359      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4360                          "i16:16:32-i32:32:32-i64:32:32-"
4361                          "f32:32:32-f64:32:32-v64:32:32-"
4362                          "v128:32:32-a0:0:32-n32";
4363      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4364    }
4365
4366    virtual void getTargetDefines(const LangOptions &Opts,
4367                                  MacroBuilder &Builder) const {
4368      DefineStd(Builder, "tce", Opts);
4369      Builder.defineMacro("__TCE__");
4370      Builder.defineMacro("__TCE_V1__");
4371    }
4372    virtual bool hasFeature(StringRef Feature) const {
4373      return Feature == "tce";
4374    }
4375
4376    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4377                                   unsigned &NumRecords) const {}
4378    virtual const char *getClobbers() const {
4379      return "";
4380    }
4381    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4382      return TargetInfo::VoidPtrBuiltinVaList;
4383    }
4384    virtual void getGCCRegNames(const char * const *&Names,
4385                                unsigned &NumNames) const {}
4386    virtual bool validateAsmConstraint(const char *&Name,
4387                                       TargetInfo::ConstraintInfo &info) const {
4388      return true;
4389    }
4390    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4391                                  unsigned &NumAliases) const {}
4392  };
4393}
4394
4395namespace {
4396class MipsTargetInfoBase : public TargetInfo {
4397  static const Builtin::Info BuiltinInfo[];
4398  std::string CPU;
4399  bool IsMips16;
4400  enum MipsFloatABI {
4401    HardFloat, SingleFloat, SoftFloat
4402  } FloatABI;
4403  enum DspRevEnum {
4404    NoDSP, DSP1, DSP2
4405  } DspRev;
4406
4407protected:
4408  std::string ABI;
4409
4410public:
4411  MipsTargetInfoBase(const std::string& triple,
4412                     const std::string& ABIStr,
4413                     const std::string& CPUStr)
4414    : TargetInfo(triple),
4415      CPU(CPUStr),
4416      IsMips16(false),
4417      FloatABI(HardFloat),
4418      DspRev(NoDSP),
4419      ABI(ABIStr)
4420  {}
4421
4422  virtual const char *getABI() const { return ABI.c_str(); }
4423  virtual bool setABI(const std::string &Name) = 0;
4424  virtual bool setCPU(const std::string &Name) {
4425    CPU = Name;
4426    return true;
4427  }
4428  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4429    Features[ABI] = true;
4430    Features[CPU] = true;
4431  }
4432
4433  virtual void getTargetDefines(const LangOptions &Opts,
4434                                MacroBuilder &Builder) const {
4435    DefineStd(Builder, "mips", Opts);
4436    Builder.defineMacro("_mips");
4437    Builder.defineMacro("__REGISTER_PREFIX__", "");
4438
4439    switch (FloatABI) {
4440    case HardFloat:
4441      Builder.defineMacro("__mips_hard_float", Twine(1));
4442      break;
4443    case SingleFloat:
4444      Builder.defineMacro("__mips_hard_float", Twine(1));
4445      Builder.defineMacro("__mips_single_float", Twine(1));
4446      break;
4447    case SoftFloat:
4448      Builder.defineMacro("__mips_soft_float", Twine(1));
4449      break;
4450    }
4451
4452    if (IsMips16)
4453      Builder.defineMacro("__mips16", Twine(1));
4454
4455    switch (DspRev) {
4456    default:
4457      break;
4458    case DSP1:
4459      Builder.defineMacro("__mips_dsp_rev", Twine(1));
4460      Builder.defineMacro("__mips_dsp", Twine(1));
4461      break;
4462    case DSP2:
4463      Builder.defineMacro("__mips_dsp_rev", Twine(2));
4464      Builder.defineMacro("__mips_dspr2", Twine(1));
4465      Builder.defineMacro("__mips_dsp", Twine(1));
4466      break;
4467    }
4468
4469    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4470    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4471    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4472
4473    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4474    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4475  }
4476
4477  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4478                                 unsigned &NumRecords) const {
4479    Records = BuiltinInfo;
4480    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4481  }
4482  virtual bool hasFeature(StringRef Feature) const {
4483    return Feature == "mips";
4484  }
4485  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4486    return TargetInfo::VoidPtrBuiltinVaList;
4487  }
4488  virtual void getGCCRegNames(const char * const *&Names,
4489                              unsigned &NumNames) const {
4490    static const char * const GCCRegNames[] = {
4491      // CPU register names
4492      // Must match second column of GCCRegAliases
4493      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4494      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4495      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4496      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4497      // Floating point register names
4498      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4499      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4500      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4501      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4502      // Hi/lo and condition register names
4503      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4504      "$fcc5","$fcc6","$fcc7"
4505    };
4506    Names = GCCRegNames;
4507    NumNames = llvm::array_lengthof(GCCRegNames);
4508  }
4509  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4510                                unsigned &NumAliases) const = 0;
4511  virtual bool validateAsmConstraint(const char *&Name,
4512                                     TargetInfo::ConstraintInfo &Info) const {
4513    switch (*Name) {
4514    default:
4515      return false;
4516
4517    case 'r': // CPU registers.
4518    case 'd': // Equivalent to "r" unless generating MIPS16 code.
4519    case 'y': // Equivalent to "r", backwards compatibility only.
4520    case 'f': // floating-point registers.
4521    case 'c': // $25 for indirect jumps
4522    case 'l': // lo register
4523    case 'x': // hilo register pair
4524      Info.setAllowsRegister();
4525      return true;
4526    case 'R': // An address that can be used in a non-macro load or store
4527      Info.setAllowsMemory();
4528      return true;
4529    }
4530  }
4531
4532  virtual const char *getClobbers() const {
4533    // FIXME: Implement!
4534    return "";
4535  }
4536
4537  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4538                                 StringRef Name,
4539                                 bool Enabled) const {
4540    if (Name == "soft-float" || Name == "single-float" ||
4541        Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4542        Name == "mips32" || Name == "mips32r2" ||
4543        Name == "mips64" || Name == "mips64r2" ||
4544        Name == "mips16" || Name == "dsp" || Name == "dspr2") {
4545      Features[Name] = Enabled;
4546      return true;
4547    } else if (Name == "32") {
4548      Features["o32"] = Enabled;
4549      return true;
4550    } else if (Name == "64") {
4551      Features["n64"] = Enabled;
4552      return true;
4553    }
4554    return false;
4555  }
4556
4557  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4558    IsMips16 = false;
4559    FloatABI = HardFloat;
4560    DspRev = NoDSP;
4561
4562    for (std::vector<std::string>::iterator it = Features.begin(),
4563         ie = Features.end(); it != ie; ++it) {
4564      if (*it == "+single-float")
4565        FloatABI = SingleFloat;
4566      else if (*it == "+soft-float")
4567        FloatABI = SoftFloat;
4568      else if (*it == "+mips16")
4569        IsMips16 = true;
4570      else if (*it == "+dsp")
4571        DspRev = std::max(DspRev, DSP1);
4572      else if (*it == "+dspr2")
4573        DspRev = std::max(DspRev, DSP2);
4574    }
4575
4576    // Remove front-end specific option.
4577    std::vector<std::string>::iterator it =
4578      std::find(Features.begin(), Features.end(), "+soft-float");
4579    if (it != Features.end())
4580      Features.erase(it);
4581  }
4582
4583  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4584    if (RegNo == 0) return 4;
4585    if (RegNo == 1) return 5;
4586    return -1;
4587  }
4588};
4589
4590const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4591#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4592#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4593                                              ALL_LANGUAGES },
4594#include "clang/Basic/BuiltinsMips.def"
4595};
4596
4597class Mips32TargetInfoBase : public MipsTargetInfoBase {
4598public:
4599  Mips32TargetInfoBase(const std::string& triple) :
4600    MipsTargetInfoBase(triple, "o32", "mips32") {
4601    SizeType = UnsignedInt;
4602    PtrDiffType = SignedInt;
4603    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4604  }
4605  virtual bool setABI(const std::string &Name) {
4606    if ((Name == "o32") || (Name == "eabi")) {
4607      ABI = Name;
4608      return true;
4609    } else if (Name == "32") {
4610      ABI = "o32";
4611      return true;
4612    } else
4613      return false;
4614  }
4615  virtual void getTargetDefines(const LangOptions &Opts,
4616                                MacroBuilder &Builder) const {
4617    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4618
4619    if (ABI == "o32") {
4620      Builder.defineMacro("__mips_o32");
4621      Builder.defineMacro("_ABIO32", "1");
4622      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4623    }
4624    else if (ABI == "eabi")
4625      Builder.defineMacro("__mips_eabi");
4626    else
4627      llvm_unreachable("Invalid ABI for Mips32.");
4628  }
4629  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4630                                unsigned &NumAliases) const {
4631    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4632      { { "at" },  "$1" },
4633      { { "v0" },  "$2" },
4634      { { "v1" },  "$3" },
4635      { { "a0" },  "$4" },
4636      { { "a1" },  "$5" },
4637      { { "a2" },  "$6" },
4638      { { "a3" },  "$7" },
4639      { { "t0" },  "$8" },
4640      { { "t1" },  "$9" },
4641      { { "t2" }, "$10" },
4642      { { "t3" }, "$11" },
4643      { { "t4" }, "$12" },
4644      { { "t5" }, "$13" },
4645      { { "t6" }, "$14" },
4646      { { "t7" }, "$15" },
4647      { { "s0" }, "$16" },
4648      { { "s1" }, "$17" },
4649      { { "s2" }, "$18" },
4650      { { "s3" }, "$19" },
4651      { { "s4" }, "$20" },
4652      { { "s5" }, "$21" },
4653      { { "s6" }, "$22" },
4654      { { "s7" }, "$23" },
4655      { { "t8" }, "$24" },
4656      { { "t9" }, "$25" },
4657      { { "k0" }, "$26" },
4658      { { "k1" }, "$27" },
4659      { { "gp" }, "$28" },
4660      { { "sp","$sp" }, "$29" },
4661      { { "fp","$fp" }, "$30" },
4662      { { "ra" }, "$31" }
4663    };
4664    Aliases = GCCRegAliases;
4665    NumAliases = llvm::array_lengthof(GCCRegAliases);
4666  }
4667};
4668
4669class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4670public:
4671  Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4672    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4673                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4674  }
4675  virtual void getTargetDefines(const LangOptions &Opts,
4676                                MacroBuilder &Builder) const {
4677    DefineStd(Builder, "MIPSEB", Opts);
4678    Builder.defineMacro("_MIPSEB");
4679    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4680  }
4681};
4682
4683class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4684public:
4685  Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4686    BigEndian = false;
4687    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4688                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4689  }
4690  virtual void getTargetDefines(const LangOptions &Opts,
4691                                MacroBuilder &Builder) const {
4692    DefineStd(Builder, "MIPSEL", Opts);
4693    Builder.defineMacro("_MIPSEL");
4694    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4695  }
4696};
4697
4698class Mips64TargetInfoBase : public MipsTargetInfoBase {
4699  virtual void SetDescriptionString(const std::string &Name) = 0;
4700public:
4701  Mips64TargetInfoBase(const std::string& triple) :
4702    MipsTargetInfoBase(triple, "n64", "mips64") {
4703    LongWidth = LongAlign = 64;
4704    PointerWidth = PointerAlign = 64;
4705    LongDoubleWidth = LongDoubleAlign = 128;
4706    LongDoubleFormat = &llvm::APFloat::IEEEquad;
4707    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4708      LongDoubleWidth = LongDoubleAlign = 64;
4709      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4710    }
4711    SuitableAlign = 128;
4712    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4713  }
4714  virtual bool setABI(const std::string &Name) {
4715    SetDescriptionString(Name);
4716    if (Name == "n32") {
4717      LongWidth = LongAlign = 32;
4718      PointerWidth = PointerAlign = 32;
4719      ABI = Name;
4720      return true;
4721    } else if (Name == "n64") {
4722      ABI = Name;
4723      return true;
4724    } else if (Name == "64") {
4725      ABI = "n64";
4726      return true;
4727    } else
4728      return false;
4729  }
4730  virtual void getTargetDefines(const LangOptions &Opts,
4731                                MacroBuilder &Builder) const {
4732    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4733
4734    Builder.defineMacro("__mips64");
4735    Builder.defineMacro("__mips64__");
4736
4737    if (ABI == "n32") {
4738      Builder.defineMacro("__mips_n32");
4739      Builder.defineMacro("_ABIN32", "2");
4740      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4741    }
4742    else if (ABI == "n64") {
4743      Builder.defineMacro("__mips_n64");
4744      Builder.defineMacro("_ABI64", "3");
4745      Builder.defineMacro("_MIPS_SIM", "_ABI64");
4746    }
4747    else
4748      llvm_unreachable("Invalid ABI for Mips64.");
4749  }
4750  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4751                                unsigned &NumAliases) const {
4752    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4753      { { "at" },  "$1" },
4754      { { "v0" },  "$2" },
4755      { { "v1" },  "$3" },
4756      { { "a0" },  "$4" },
4757      { { "a1" },  "$5" },
4758      { { "a2" },  "$6" },
4759      { { "a3" },  "$7" },
4760      { { "a4" },  "$8" },
4761      { { "a5" },  "$9" },
4762      { { "a6" }, "$10" },
4763      { { "a7" }, "$11" },
4764      { { "t0" }, "$12" },
4765      { { "t1" }, "$13" },
4766      { { "t2" }, "$14" },
4767      { { "t3" }, "$15" },
4768      { { "s0" }, "$16" },
4769      { { "s1" }, "$17" },
4770      { { "s2" }, "$18" },
4771      { { "s3" }, "$19" },
4772      { { "s4" }, "$20" },
4773      { { "s5" }, "$21" },
4774      { { "s6" }, "$22" },
4775      { { "s7" }, "$23" },
4776      { { "t8" }, "$24" },
4777      { { "t9" }, "$25" },
4778      { { "k0" }, "$26" },
4779      { { "k1" }, "$27" },
4780      { { "gp" }, "$28" },
4781      { { "sp","$sp" }, "$29" },
4782      { { "fp","$fp" }, "$30" },
4783      { { "ra" }, "$31" }
4784    };
4785    Aliases = GCCRegAliases;
4786    NumAliases = llvm::array_lengthof(GCCRegAliases);
4787  }
4788};
4789
4790class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4791  virtual void SetDescriptionString(const std::string &Name) {
4792    // Change DescriptionString only if ABI is n32.
4793    if (Name == "n32")
4794      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4795                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4796                          "v64:64:64-n32:64-S128";
4797  }
4798public:
4799  Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4800    // Default ABI is n64.
4801    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4802                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4803                        "v64:64:64-n32:64-S128";
4804  }
4805  virtual void getTargetDefines(const LangOptions &Opts,
4806                                MacroBuilder &Builder) const {
4807    DefineStd(Builder, "MIPSEB", Opts);
4808    Builder.defineMacro("_MIPSEB");
4809    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4810  }
4811};
4812
4813class Mips64ELTargetInfo : public Mips64TargetInfoBase {
4814  virtual void SetDescriptionString(const std::string &Name) {
4815    // Change DescriptionString only if ABI is n32.
4816    if (Name == "n32")
4817      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4818                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
4819                          "-v64:64:64-n32:64-S128";
4820  }
4821public:
4822  Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4823    // Default ABI is n64.
4824    BigEndian = false;
4825    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4826                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4827                        "v64:64:64-n32:64-S128";
4828  }
4829  virtual void getTargetDefines(const LangOptions &Opts,
4830                                MacroBuilder &Builder) const {
4831    DefineStd(Builder, "MIPSEL", Opts);
4832    Builder.defineMacro("_MIPSEL");
4833    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4834  }
4835};
4836} // end anonymous namespace.
4837
4838namespace {
4839class PNaClTargetInfo : public TargetInfo {
4840public:
4841  PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
4842    BigEndian = false;
4843    this->UserLabelPrefix = "";
4844    this->LongAlign = 32;
4845    this->LongWidth = 32;
4846    this->PointerAlign = 32;
4847    this->PointerWidth = 32;
4848    this->IntMaxType = TargetInfo::SignedLongLong;
4849    this->UIntMaxType = TargetInfo::UnsignedLongLong;
4850    this->Int64Type = TargetInfo::SignedLongLong;
4851    this->DoubleAlign = 64;
4852    this->LongDoubleWidth = 64;
4853    this->LongDoubleAlign = 64;
4854    this->SizeType = TargetInfo::UnsignedInt;
4855    this->PtrDiffType = TargetInfo::SignedInt;
4856    this->IntPtrType = TargetInfo::SignedInt;
4857    this->RegParmMax = 2;
4858    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4859                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
4860  }
4861
4862  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4863  }
4864  virtual void getArchDefines(const LangOptions &Opts,
4865                              MacroBuilder &Builder) const {
4866    Builder.defineMacro("__le32__");
4867    Builder.defineMacro("__pnacl__");
4868  }
4869  virtual void getTargetDefines(const LangOptions &Opts,
4870                                MacroBuilder &Builder) const {
4871    Builder.defineMacro("__LITTLE_ENDIAN__");
4872    getArchDefines(Opts, Builder);
4873  }
4874  virtual bool hasFeature(StringRef Feature) const {
4875    return Feature == "pnacl";
4876  }
4877  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4878                                 unsigned &NumRecords) const {
4879  }
4880  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4881    return TargetInfo::PNaClABIBuiltinVaList;
4882  }
4883  virtual void getGCCRegNames(const char * const *&Names,
4884                              unsigned &NumNames) const;
4885  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4886                                unsigned &NumAliases) const;
4887  virtual bool validateAsmConstraint(const char *&Name,
4888                                     TargetInfo::ConstraintInfo &Info) const {
4889    return false;
4890  }
4891
4892  virtual const char *getClobbers() const {
4893    return "";
4894  }
4895};
4896
4897void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
4898                                     unsigned &NumNames) const {
4899  Names = NULL;
4900  NumNames = 0;
4901}
4902
4903void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4904                                       unsigned &NumAliases) const {
4905  Aliases = NULL;
4906  NumAliases = 0;
4907}
4908} // end anonymous namespace.
4909
4910namespace {
4911  static const unsigned SPIRAddrSpaceMap[] = {
4912    1,    // opencl_global
4913    3,    // opencl_local
4914    2,    // opencl_constant
4915    0,    // cuda_device
4916    0,    // cuda_constant
4917    0     // cuda_shared
4918  };
4919  class SPIRTargetInfo : public TargetInfo {
4920    static const char * const GCCRegNames[];
4921    static const Builtin::Info BuiltinInfo[];
4922    std::vector<StringRef> AvailableFeatures;
4923  public:
4924    SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) {
4925      assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
4926        "SPIR target must use unknown OS");
4927      assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
4928        "SPIR target must use unknown environment type");
4929      BigEndian = false;
4930      TLSSupported = false;
4931      LongWidth = LongAlign = 64;
4932      AddrSpaceMap = &SPIRAddrSpaceMap;
4933      // Define available target features
4934      // These must be defined in sorted order!
4935      NoAsmVariants = true;
4936    }
4937    virtual void getTargetDefines(const LangOptions &Opts,
4938                                  MacroBuilder &Builder) const {
4939      DefineStd(Builder, "SPIR", Opts);
4940    }
4941    virtual bool hasFeature(StringRef Feature) const {
4942      return Feature == "spir";
4943    }
4944
4945    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4946                                   unsigned &NumRecords) const {}
4947    virtual const char *getClobbers() const {
4948      return "";
4949    }
4950    virtual void getGCCRegNames(const char * const *&Names,
4951                                unsigned &NumNames) const {}
4952    virtual bool validateAsmConstraint(const char *&Name,
4953                                       TargetInfo::ConstraintInfo &info) const {
4954      return true;
4955    }
4956    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4957                                  unsigned &NumAliases) const {}
4958    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4959      return TargetInfo::VoidPtrBuiltinVaList;
4960    }
4961  };
4962
4963
4964  class SPIR32TargetInfo : public SPIRTargetInfo {
4965  public:
4966    SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
4967      PointerWidth = PointerAlign = 32;
4968      SizeType     = TargetInfo::UnsignedInt;
4969      PtrDiffType = IntPtrType = TargetInfo::SignedInt;
4970      DescriptionString
4971        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4972          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
4973          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
4974          "v512:512:512-v1024:1024:1024";
4975    }
4976    virtual void getTargetDefines(const LangOptions &Opts,
4977                                  MacroBuilder &Builder) const {
4978      DefineStd(Builder, "SPIR32", Opts);
4979    }
4980  };
4981
4982  class SPIR64TargetInfo : public SPIRTargetInfo {
4983  public:
4984    SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
4985      PointerWidth = PointerAlign = 64;
4986      SizeType     = TargetInfo::UnsignedLong;
4987      PtrDiffType = IntPtrType = TargetInfo::SignedLong;
4988      DescriptionString
4989        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4990          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
4991          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
4992          "v512:512:512-v1024:1024:1024";
4993    }
4994    virtual void getTargetDefines(const LangOptions &Opts,
4995                                  MacroBuilder &Builder) const {
4996      DefineStd(Builder, "SPIR64", Opts);
4997    }
4998  };
4999}
5000
5001
5002//===----------------------------------------------------------------------===//
5003// Driver code
5004//===----------------------------------------------------------------------===//
5005
5006static TargetInfo *AllocateTarget(const std::string &T) {
5007  llvm::Triple Triple(T);
5008  llvm::Triple::OSType os = Triple.getOS();
5009
5010  switch (Triple.getArch()) {
5011  default:
5012    return NULL;
5013
5014  case llvm::Triple::hexagon:
5015    return new HexagonTargetInfo(T);
5016
5017  case llvm::Triple::aarch64:
5018    switch (os) {
5019    case llvm::Triple::Linux:
5020      return new LinuxTargetInfo<AArch64TargetInfo>(T);
5021    default:
5022      return new AArch64TargetInfo(T);
5023    }
5024
5025  case llvm::Triple::arm:
5026  case llvm::Triple::thumb:
5027    if (Triple.isOSDarwin())
5028      return new DarwinARMTargetInfo(T);
5029
5030    switch (os) {
5031    case llvm::Triple::Linux:
5032      return new LinuxTargetInfo<ARMTargetInfo>(T);
5033    case llvm::Triple::FreeBSD:
5034      return new FreeBSDTargetInfo<ARMTargetInfo>(T);
5035    case llvm::Triple::NetBSD:
5036      return new NetBSDTargetInfo<ARMTargetInfo>(T);
5037    case llvm::Triple::OpenBSD:
5038      return new OpenBSDTargetInfo<ARMTargetInfo>(T);
5039    case llvm::Triple::Bitrig:
5040      return new BitrigTargetInfo<ARMTargetInfo>(T);
5041    case llvm::Triple::RTEMS:
5042      return new RTEMSTargetInfo<ARMTargetInfo>(T);
5043    case llvm::Triple::NaCl:
5044      return new NaClTargetInfo<ARMTargetInfo>(T);
5045    default:
5046      return new ARMTargetInfo(T);
5047    }
5048
5049  case llvm::Triple::msp430:
5050    return new MSP430TargetInfo(T);
5051
5052  case llvm::Triple::mips:
5053    switch (os) {
5054    case llvm::Triple::Linux:
5055      return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
5056    case llvm::Triple::RTEMS:
5057      return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
5058    case llvm::Triple::FreeBSD:
5059      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
5060    case llvm::Triple::NetBSD:
5061      return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
5062    default:
5063      return new Mips32EBTargetInfo(T);
5064    }
5065
5066  case llvm::Triple::mipsel:
5067    switch (os) {
5068    case llvm::Triple::Linux:
5069      return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
5070    case llvm::Triple::RTEMS:
5071      return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
5072    case llvm::Triple::FreeBSD:
5073      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
5074    case llvm::Triple::NetBSD:
5075      return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
5076    default:
5077      return new Mips32ELTargetInfo(T);
5078    }
5079
5080  case llvm::Triple::mips64:
5081    switch (os) {
5082    case llvm::Triple::Linux:
5083      return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
5084    case llvm::Triple::RTEMS:
5085      return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
5086    case llvm::Triple::FreeBSD:
5087      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
5088    case llvm::Triple::NetBSD:
5089      return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
5090    case llvm::Triple::OpenBSD:
5091      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
5092    default:
5093      return new Mips64EBTargetInfo(T);
5094    }
5095
5096  case llvm::Triple::mips64el:
5097    switch (os) {
5098    case llvm::Triple::Linux:
5099      return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
5100    case llvm::Triple::RTEMS:
5101      return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
5102    case llvm::Triple::FreeBSD:
5103      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
5104    case llvm::Triple::NetBSD:
5105      return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
5106    case llvm::Triple::OpenBSD:
5107      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
5108    default:
5109      return new Mips64ELTargetInfo(T);
5110    }
5111
5112  case llvm::Triple::le32:
5113    switch (os) {
5114      case llvm::Triple::NaCl:
5115        return new NaClTargetInfo<PNaClTargetInfo>(T);
5116      default:
5117        return NULL;
5118    }
5119
5120  case llvm::Triple::ppc:
5121    if (Triple.isOSDarwin())
5122      return new DarwinPPC32TargetInfo(T);
5123    switch (os) {
5124    case llvm::Triple::Linux:
5125      return new LinuxTargetInfo<PPC32TargetInfo>(T);
5126    case llvm::Triple::FreeBSD:
5127      return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
5128    case llvm::Triple::NetBSD:
5129      return new NetBSDTargetInfo<PPC32TargetInfo>(T);
5130    case llvm::Triple::OpenBSD:
5131      return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
5132    case llvm::Triple::RTEMS:
5133      return new RTEMSTargetInfo<PPC32TargetInfo>(T);
5134    default:
5135      return new PPC32TargetInfo(T);
5136    }
5137
5138  case llvm::Triple::ppc64:
5139    if (Triple.isOSDarwin())
5140      return new DarwinPPC64TargetInfo(T);
5141    switch (os) {
5142    case llvm::Triple::Linux:
5143      return new LinuxTargetInfo<PPC64TargetInfo>(T);
5144    case llvm::Triple::Lv2:
5145      return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
5146    case llvm::Triple::FreeBSD:
5147      return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
5148    case llvm::Triple::NetBSD:
5149      return new NetBSDTargetInfo<PPC64TargetInfo>(T);
5150    default:
5151      return new PPC64TargetInfo(T);
5152    }
5153
5154  case llvm::Triple::nvptx:
5155    return new NVPTX32TargetInfo(T);
5156  case llvm::Triple::nvptx64:
5157    return new NVPTX64TargetInfo(T);
5158
5159  case llvm::Triple::mblaze:
5160    return new MBlazeTargetInfo(T);
5161
5162  case llvm::Triple::r600:
5163    return new R600TargetInfo(T);
5164
5165  case llvm::Triple::sparc:
5166    switch (os) {
5167    case llvm::Triple::Linux:
5168      return new LinuxTargetInfo<SparcV8TargetInfo>(T);
5169    case llvm::Triple::AuroraUX:
5170      return new AuroraUXSparcV8TargetInfo(T);
5171    case llvm::Triple::Solaris:
5172      return new SolarisSparcV8TargetInfo(T);
5173    case llvm::Triple::NetBSD:
5174      return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
5175    case llvm::Triple::OpenBSD:
5176      return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
5177    case llvm::Triple::RTEMS:
5178      return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
5179    default:
5180      return new SparcV8TargetInfo(T);
5181    }
5182
5183  case llvm::Triple::tce:
5184    return new TCETargetInfo(T);
5185
5186  case llvm::Triple::x86:
5187    if (Triple.isOSDarwin())
5188      return new DarwinI386TargetInfo(T);
5189
5190    switch (os) {
5191    case llvm::Triple::AuroraUX:
5192      return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
5193    case llvm::Triple::Linux:
5194      return new LinuxTargetInfo<X86_32TargetInfo>(T);
5195    case llvm::Triple::DragonFly:
5196      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
5197    case llvm::Triple::NetBSD:
5198      return new NetBSDI386TargetInfo(T);
5199    case llvm::Triple::OpenBSD:
5200      return new OpenBSDI386TargetInfo(T);
5201    case llvm::Triple::Bitrig:
5202      return new BitrigI386TargetInfo(T);
5203    case llvm::Triple::FreeBSD:
5204      return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
5205    case llvm::Triple::Minix:
5206      return new MinixTargetInfo<X86_32TargetInfo>(T);
5207    case llvm::Triple::Solaris:
5208      return new SolarisTargetInfo<X86_32TargetInfo>(T);
5209    case llvm::Triple::Cygwin:
5210      return new CygwinX86_32TargetInfo(T);
5211    case llvm::Triple::MinGW32:
5212      return new MinGWX86_32TargetInfo(T);
5213    case llvm::Triple::Win32:
5214      return new VisualStudioWindowsX86_32TargetInfo(T);
5215    case llvm::Triple::Haiku:
5216      return new HaikuX86_32TargetInfo(T);
5217    case llvm::Triple::RTEMS:
5218      return new RTEMSX86_32TargetInfo(T);
5219    case llvm::Triple::NaCl:
5220      return new NaClTargetInfo<X86_32TargetInfo>(T);
5221    default:
5222      return new X86_32TargetInfo(T);
5223    }
5224
5225  case llvm::Triple::x86_64:
5226    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5227      return new DarwinX86_64TargetInfo(T);
5228
5229    switch (os) {
5230    case llvm::Triple::AuroraUX:
5231      return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
5232    case llvm::Triple::Linux:
5233      return new LinuxTargetInfo<X86_64TargetInfo>(T);
5234    case llvm::Triple::DragonFly:
5235      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
5236    case llvm::Triple::NetBSD:
5237      return new NetBSDTargetInfo<X86_64TargetInfo>(T);
5238    case llvm::Triple::OpenBSD:
5239      return new OpenBSDX86_64TargetInfo(T);
5240    case llvm::Triple::Bitrig:
5241      return new BitrigX86_64TargetInfo(T);
5242    case llvm::Triple::FreeBSD:
5243      return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
5244    case llvm::Triple::Solaris:
5245      return new SolarisTargetInfo<X86_64TargetInfo>(T);
5246    case llvm::Triple::MinGW32:
5247      return new MinGWX86_64TargetInfo(T);
5248    case llvm::Triple::Win32:   // This is what Triple.h supports now.
5249      return new VisualStudioWindowsX86_64TargetInfo(T);
5250    case llvm::Triple::NaCl:
5251      return new NaClTargetInfo<X86_64TargetInfo>(T);
5252    default:
5253      return new X86_64TargetInfo(T);
5254    }
5255
5256    case llvm::Triple::spir: {
5257      llvm::Triple Triple(T);
5258      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5259        Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5260        return NULL;
5261      return new SPIR32TargetInfo(T);
5262    }
5263    case llvm::Triple::spir64: {
5264      llvm::Triple Triple(T);
5265      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5266        Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5267        return NULL;
5268      return new SPIR64TargetInfo(T);
5269    }
5270  }
5271}
5272
5273/// CreateTargetInfo - Return the target info object for the specified target
5274/// triple.
5275TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5276                                         TargetOptions *Opts) {
5277  llvm::Triple Triple(Opts->Triple);
5278
5279  // Construct the target
5280  OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
5281  if (!Target) {
5282    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5283    return 0;
5284  }
5285  Target->setTargetOpts(Opts);
5286
5287  // Set the target CPU if specified.
5288  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5289    Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5290    return 0;
5291  }
5292
5293  // Set the target ABI if specified.
5294  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5295    Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5296    return 0;
5297  }
5298
5299  // Set the target C++ ABI.
5300  if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5301    Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5302    return 0;
5303  }
5304
5305  // Compute the default target features, we need the target to handle this
5306  // because features may have dependencies on one another.
5307  llvm::StringMap<bool> Features;
5308  Target->getDefaultFeatures(Features);
5309
5310  // Apply the user specified deltas.
5311  // First the enables.
5312  for (std::vector<std::string>::const_iterator
5313         it = Opts->FeaturesAsWritten.begin(),
5314         ie = Opts->FeaturesAsWritten.end();
5315       it != ie; ++it) {
5316    const char *Name = it->c_str();
5317
5318    if (Name[0] != '+')
5319      continue;
5320
5321    // Apply the feature via the target.
5322    if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5323      Diags.Report(diag::err_target_invalid_feature) << Name;
5324      return 0;
5325    }
5326  }
5327
5328  // Then the disables.
5329  for (std::vector<std::string>::const_iterator
5330         it = Opts->FeaturesAsWritten.begin(),
5331         ie = Opts->FeaturesAsWritten.end();
5332       it != ie; ++it) {
5333    const char *Name = it->c_str();
5334
5335    if (Name[0] == '+')
5336      continue;
5337
5338    // Apply the feature via the target.
5339    if (Name[0] != '-' ||
5340        !Target->setFeatureEnabled(Features, Name + 1, false)) {
5341      Diags.Report(diag::err_target_invalid_feature) << Name;
5342      return 0;
5343    }
5344  }
5345
5346  // Add the features to the compile options.
5347  //
5348  // FIXME: If we are completely confident that we have the right set, we only
5349  // need to pass the minuses.
5350  Opts->Features.clear();
5351  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5352         ie = Features.end(); it != ie; ++it)
5353    Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5354  Target->HandleTargetFeatures(Opts->Features);
5355
5356  return Target.take();
5357}
5358