Targets.cpp revision e9616a4972a4c2fdc28128c057f21d7a79516c86 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "5621");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.getOS() == llvm::Triple::IOS) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else {
153    // Note that the Driver allows versions which aren't representable in the
154    // define (because we only get a single digit for the minor and micro
155    // revision numbers). So, we limit them to the maximum representable
156    // version.
157    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159    char Str[5];
160    Str[0] = '0' + (Maj / 10);
161    Str[1] = '0' + (Maj % 10);
162    Str[2] = '0' + std::min(Min, 9U);
163    Str[3] = '0' + std::min(Rev, 9U);
164    Str[4] = '\0';
165    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166  }
167
168  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169}
170
171namespace {
172template<typename Target>
173class DarwinTargetInfo : public OSTargetInfo<Target> {
174protected:
175  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                            MacroBuilder &Builder) const {
177    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                     this->PlatformMinVersion);
179  }
180
181public:
182  DarwinTargetInfo(const std::string& triple) :
183    OSTargetInfo<Target>(triple) {
184      llvm::Triple T = llvm::Triple(triple);
185      this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186      this->MCountName = "\01mcount";
187    }
188
189  virtual std::string isValidSectionSpecifier(StringRef SR) const {
190    // Let MCSectionMachO validate this.
191    StringRef Segment, Section;
192    unsigned TAA, StubSize;
193    bool HasTAA;
194    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                       TAA, HasTAA, StubSize);
196  }
197
198  virtual const char *getStaticInitSectionSpecifier() const {
199    // FIXME: We should return 0 when building kexts.
200    return "__TEXT,__StaticInit,regular,pure_instructions";
201  }
202
203  /// Darwin does not support protected visibility.  Darwin's "default"
204  /// is very similar to ELF's "protected";  Darwin requires a "weak"
205  /// attribute on declarations that can be dynamically replaced.
206  virtual bool hasProtectedVisibility() const {
207    return false;
208  }
209};
210
211
212// DragonFlyBSD Target
213template<typename Target>
214class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215protected:
216  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                            MacroBuilder &Builder) const {
218    // DragonFly defines; list based off of gcc output
219    Builder.defineMacro("__DragonFly__");
220    Builder.defineMacro("__DragonFly_cc_version", "100001");
221    Builder.defineMacro("__ELF__");
222    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223    Builder.defineMacro("__tune_i386__");
224    DefineStd(Builder, "unix", Opts);
225  }
226public:
227  DragonFlyBSDTargetInfo(const std::string &triple)
228    : OSTargetInfo<Target>(triple) {
229      this->UserLabelPrefix = "";
230
231      llvm::Triple Triple(triple);
232      switch (Triple.getArch()) {
233        default:
234        case llvm::Triple::x86:
235        case llvm::Triple::x86_64:
236          this->MCountName = ".mcount";
237          break;
238      }
239  }
240};
241
242// FreeBSD Target
243template<typename Target>
244class FreeBSDTargetInfo : public OSTargetInfo<Target> {
245protected:
246  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247                            MacroBuilder &Builder) const {
248    // FreeBSD defines; list based off of gcc output
249
250    unsigned Release = Triple.getOSMajorVersion();
251    if (Release == 0U)
252      Release = 8;
253
254    Builder.defineMacro("__FreeBSD__", Twine(Release));
255    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257    DefineStd(Builder, "unix", Opts);
258    Builder.defineMacro("__ELF__");
259  }
260public:
261  FreeBSDTargetInfo(const std::string &triple)
262    : OSTargetInfo<Target>(triple) {
263      this->UserLabelPrefix = "";
264
265      llvm::Triple Triple(triple);
266      switch (Triple.getArch()) {
267        default:
268        case llvm::Triple::x86:
269        case llvm::Triple::x86_64:
270          this->MCountName = ".mcount";
271          break;
272        case llvm::Triple::mips:
273        case llvm::Triple::mipsel:
274        case llvm::Triple::ppc:
275        case llvm::Triple::ppc64:
276          this->MCountName = "_mcount";
277          break;
278        case llvm::Triple::arm:
279          this->MCountName = "__mcount";
280          break;
281      }
282
283    }
284};
285
286// Minix Target
287template<typename Target>
288class MinixTargetInfo : public OSTargetInfo<Target> {
289protected:
290  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291                            MacroBuilder &Builder) const {
292    // Minix defines
293
294    Builder.defineMacro("__minix", "3");
295    Builder.defineMacro("_EM_WSIZE", "4");
296    Builder.defineMacro("_EM_PSIZE", "4");
297    Builder.defineMacro("_EM_SSIZE", "2");
298    Builder.defineMacro("_EM_LSIZE", "4");
299    Builder.defineMacro("_EM_FSIZE", "4");
300    Builder.defineMacro("_EM_DSIZE", "8");
301    Builder.defineMacro("__ELF__");
302    DefineStd(Builder, "unix", Opts);
303  }
304public:
305  MinixTargetInfo(const std::string &triple)
306    : OSTargetInfo<Target>(triple) {
307      this->UserLabelPrefix = "";
308    }
309};
310
311// Linux target
312template<typename Target>
313class LinuxTargetInfo : public OSTargetInfo<Target> {
314protected:
315  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                            MacroBuilder &Builder) const {
317    // Linux defines; list based off of gcc output
318    DefineStd(Builder, "unix", Opts);
319    DefineStd(Builder, "linux", Opts);
320    Builder.defineMacro("__gnu_linux__");
321    Builder.defineMacro("__ELF__");
322    if (Triple.getEnvironment() == llvm::Triple::Android)
323      Builder.defineMacro("__ANDROID__", "1");
324    if (Opts.POSIXThreads)
325      Builder.defineMacro("_REENTRANT");
326    if (Opts.CPlusPlus)
327      Builder.defineMacro("_GNU_SOURCE");
328  }
329public:
330  LinuxTargetInfo(const std::string& triple)
331    : OSTargetInfo<Target>(triple) {
332    this->UserLabelPrefix = "";
333    this->WIntType = TargetInfo::UnsignedInt;
334  }
335
336  virtual const char *getStaticInitSectionSpecifier() const {
337    return ".text.startup";
338  }
339};
340
341// NetBSD Target
342template<typename Target>
343class NetBSDTargetInfo : public OSTargetInfo<Target> {
344protected:
345  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346                            MacroBuilder &Builder) const {
347    // NetBSD defines; list based off of gcc output
348    Builder.defineMacro("__NetBSD__");
349    Builder.defineMacro("__unix__");
350    Builder.defineMacro("__ELF__");
351    if (Opts.POSIXThreads)
352      Builder.defineMacro("_POSIX_THREADS");
353  }
354public:
355  NetBSDTargetInfo(const std::string &triple)
356    : OSTargetInfo<Target>(triple) {
357      this->UserLabelPrefix = "";
358    }
359};
360
361// OpenBSD Target
362template<typename Target>
363class OpenBSDTargetInfo : public OSTargetInfo<Target> {
364protected:
365  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366                            MacroBuilder &Builder) const {
367    // OpenBSD defines; list based off of gcc output
368
369    Builder.defineMacro("__OpenBSD__");
370    DefineStd(Builder, "unix", Opts);
371    Builder.defineMacro("__ELF__");
372    if (Opts.POSIXThreads)
373      Builder.defineMacro("_REENTRANT");
374  }
375public:
376  OpenBSDTargetInfo(const std::string &triple)
377    : OSTargetInfo<Target>(triple) {
378      this->UserLabelPrefix = "";
379      this->TLSSupported = false;
380
381      llvm::Triple Triple(triple);
382      switch (Triple.getArch()) {
383        default:
384        case llvm::Triple::x86:
385        case llvm::Triple::x86_64:
386        case llvm::Triple::arm:
387        case llvm::Triple::sparc:
388          this->MCountName = "__mcount";
389          break;
390        case llvm::Triple::mips64:
391        case llvm::Triple::mips64el:
392        case llvm::Triple::ppc:
393        case llvm::Triple::sparcv9:
394          this->MCountName = "_mcount";
395          break;
396      }
397  }
398};
399
400// Bitrig Target
401template<typename Target>
402class BitrigTargetInfo : public OSTargetInfo<Target> {
403protected:
404  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405                            MacroBuilder &Builder) const {
406    // Bitrig defines; list based off of gcc output
407
408    Builder.defineMacro("__Bitrig__");
409    DefineStd(Builder, "unix", Opts);
410    Builder.defineMacro("__ELF__");
411    if (Opts.POSIXThreads)
412      Builder.defineMacro("_REENTRANT");
413  }
414public:
415  BitrigTargetInfo(const std::string &triple)
416    : OSTargetInfo<Target>(triple) {
417      this->UserLabelPrefix = "";
418      this->TLSSupported = false;
419      this->MCountName = "__mcount";
420  }
421};
422
423// PSP Target
424template<typename Target>
425class PSPTargetInfo : public OSTargetInfo<Target> {
426protected:
427  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428                            MacroBuilder &Builder) const {
429    // PSP defines; list based on the output of the pspdev gcc toolchain.
430    Builder.defineMacro("PSP");
431    Builder.defineMacro("_PSP");
432    Builder.defineMacro("__psp__");
433    Builder.defineMacro("__ELF__");
434  }
435public:
436  PSPTargetInfo(const std::string& triple)
437    : OSTargetInfo<Target>(triple) {
438    this->UserLabelPrefix = "";
439  }
440};
441
442// PS3 PPU Target
443template<typename Target>
444class PS3PPUTargetInfo : public OSTargetInfo<Target> {
445protected:
446  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                            MacroBuilder &Builder) const {
448    // PS3 PPU defines.
449    Builder.defineMacro("__PPC__");
450    Builder.defineMacro("__PPU__");
451    Builder.defineMacro("__CELLOS_LV2__");
452    Builder.defineMacro("__ELF__");
453    Builder.defineMacro("__LP32__");
454    Builder.defineMacro("_ARCH_PPC64");
455    Builder.defineMacro("__powerpc64__");
456  }
457public:
458  PS3PPUTargetInfo(const std::string& triple)
459    : OSTargetInfo<Target>(triple) {
460    this->UserLabelPrefix = "";
461    this->LongWidth = this->LongAlign = 32;
462    this->PointerWidth = this->PointerAlign = 32;
463    this->IntMaxType = TargetInfo::SignedLongLong;
464    this->UIntMaxType = TargetInfo::UnsignedLongLong;
465    this->Int64Type = TargetInfo::SignedLongLong;
466    this->SizeType = TargetInfo::UnsignedInt;
467    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
469  }
470};
471
472// FIXME: Need a real SPU target.
473// PS3 SPU Target
474template<typename Target>
475class PS3SPUTargetInfo : public OSTargetInfo<Target> {
476protected:
477  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478                            MacroBuilder &Builder) const {
479    // PS3 PPU defines.
480    Builder.defineMacro("__SPU__");
481    Builder.defineMacro("__ELF__");
482  }
483public:
484  PS3SPUTargetInfo(const std::string& triple)
485    : OSTargetInfo<Target>(triple) {
486    this->UserLabelPrefix = "";
487  }
488};
489
490// AuroraUX target
491template<typename Target>
492class AuroraUXTargetInfo : public OSTargetInfo<Target> {
493protected:
494  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                            MacroBuilder &Builder) const {
496    DefineStd(Builder, "sun", Opts);
497    DefineStd(Builder, "unix", Opts);
498    Builder.defineMacro("__ELF__");
499    Builder.defineMacro("__svr4__");
500    Builder.defineMacro("__SVR4");
501  }
502public:
503  AuroraUXTargetInfo(const std::string& triple)
504    : OSTargetInfo<Target>(triple) {
505    this->UserLabelPrefix = "";
506    this->WCharType = this->SignedLong;
507    // FIXME: WIntType should be SignedLong
508  }
509};
510
511// Solaris target
512template<typename Target>
513class SolarisTargetInfo : public OSTargetInfo<Target> {
514protected:
515  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516                            MacroBuilder &Builder) const {
517    DefineStd(Builder, "sun", Opts);
518    DefineStd(Builder, "unix", Opts);
519    Builder.defineMacro("__ELF__");
520    Builder.defineMacro("__svr4__");
521    Builder.defineMacro("__SVR4");
522    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523    // newer, but to 500 for everything else.  feature_test.h has a check to
524    // ensure that you are not using C99 with an old version of X/Open or C89
525    // with a new version.
526    if (Opts.C99 || Opts.C11)
527      Builder.defineMacro("_XOPEN_SOURCE", "600");
528    else
529      Builder.defineMacro("_XOPEN_SOURCE", "500");
530    if (Opts.CPlusPlus)
531      Builder.defineMacro("__C99FEATURES__");
532    Builder.defineMacro("_LARGEFILE_SOURCE");
533    Builder.defineMacro("_LARGEFILE64_SOURCE");
534    Builder.defineMacro("__EXTENSIONS__");
535    Builder.defineMacro("_REENTRANT");
536  }
537public:
538  SolarisTargetInfo(const std::string& triple)
539    : OSTargetInfo<Target>(triple) {
540    this->UserLabelPrefix = "";
541    this->WCharType = this->SignedInt;
542    // FIXME: WIntType should be SignedLong
543  }
544};
545
546// Windows target
547template<typename Target>
548class WindowsTargetInfo : public OSTargetInfo<Target> {
549protected:
550  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551                            MacroBuilder &Builder) const {
552    Builder.defineMacro("_WIN32");
553  }
554  void getVisualStudioDefines(const LangOptions &Opts,
555                              MacroBuilder &Builder) const {
556    if (Opts.CPlusPlus) {
557      if (Opts.RTTI)
558        Builder.defineMacro("_CPPRTTI");
559
560      if (Opts.Exceptions)
561        Builder.defineMacro("_CPPUNWIND");
562    }
563
564    if (!Opts.CharIsSigned)
565      Builder.defineMacro("_CHAR_UNSIGNED");
566
567    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568    //        but it works for now.
569    if (Opts.POSIXThreads)
570      Builder.defineMacro("_MT");
571
572    if (Opts.MSCVersion != 0)
573      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
574
575    if (Opts.MicrosoftExt) {
576      Builder.defineMacro("_MSC_EXTENSIONS");
577
578      if (Opts.CPlusPlus11) {
579        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
582      }
583    }
584
585    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
586  }
587
588public:
589  WindowsTargetInfo(const std::string &triple)
590    : OSTargetInfo<Target>(triple) {}
591};
592
593template <typename Target>
594class NaClTargetInfo : public OSTargetInfo<Target> {
595 protected:
596  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597                            MacroBuilder &Builder) const {
598    if (Opts.POSIXThreads)
599      Builder.defineMacro("_REENTRANT");
600    if (Opts.CPlusPlus)
601      Builder.defineMacro("_GNU_SOURCE");
602
603    DefineStd(Builder, "unix", Opts);
604    Builder.defineMacro("__ELF__");
605    Builder.defineMacro("__native_client__");
606  }
607 public:
608  NaClTargetInfo(const std::string &triple)
609    : OSTargetInfo<Target>(triple) {
610    this->UserLabelPrefix = "";
611    this->LongAlign = 32;
612    this->LongWidth = 32;
613    this->PointerAlign = 32;
614    this->PointerWidth = 32;
615    this->IntMaxType = TargetInfo::SignedLongLong;
616    this->UIntMaxType = TargetInfo::UnsignedLongLong;
617    this->Int64Type = TargetInfo::SignedLongLong;
618    this->DoubleAlign = 64;
619    this->LongDoubleWidth = 64;
620    this->LongDoubleAlign = 64;
621    this->SizeType = TargetInfo::UnsignedInt;
622    this->PtrDiffType = TargetInfo::SignedInt;
623    this->IntPtrType = TargetInfo::SignedInt;
624    this->RegParmMax = 2;
625    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
626    this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
627                              "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
628  }
629  virtual typename Target::CallingConvCheckResult checkCallingConvention(
630      CallingConv CC) const {
631    return CC == CC_PnaclCall ? Target::CCCR_OK :
632        Target::checkCallingConvention(CC);
633  }
634};
635} // end anonymous namespace.
636
637//===----------------------------------------------------------------------===//
638// Specific target implementations.
639//===----------------------------------------------------------------------===//
640
641namespace {
642// PPC abstract base class
643class PPCTargetInfo : public TargetInfo {
644  static const Builtin::Info BuiltinInfo[];
645  static const char * const GCCRegNames[];
646  static const TargetInfo::GCCRegAlias GCCRegAliases[];
647  std::string CPU;
648public:
649  PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
650    LongDoubleWidth = LongDoubleAlign = 128;
651    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
652  }
653
654  /// \brief Flags for architecture specific defines.
655  typedef enum {
656    ArchDefineNone  = 0,
657    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
658    ArchDefinePpcgr = 1 << 1,
659    ArchDefinePpcsq = 1 << 2,
660    ArchDefine440   = 1 << 3,
661    ArchDefine603   = 1 << 4,
662    ArchDefine604   = 1 << 5,
663    ArchDefinePwr4  = 1 << 6,
664    ArchDefinePwr5  = 1 << 7,
665    ArchDefinePwr5x = 1 << 8,
666    ArchDefinePwr6  = 1 << 9,
667    ArchDefinePwr6x = 1 << 10,
668    ArchDefinePwr7  = 1 << 11,
669    ArchDefineA2    = 1 << 12,
670    ArchDefineA2q   = 1 << 13
671  } ArchDefineTypes;
672
673  // Note: GCC recognizes the following additional cpus:
674  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
675  //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
676  //  titan, rs64.
677  virtual bool setCPU(const std::string &Name) {
678    bool CPUKnown = llvm::StringSwitch<bool>(Name)
679      .Case("generic", true)
680      .Case("440", true)
681      .Case("450", true)
682      .Case("601", true)
683      .Case("602", true)
684      .Case("603", true)
685      .Case("603e", true)
686      .Case("603ev", true)
687      .Case("604", true)
688      .Case("604e", true)
689      .Case("620", true)
690      .Case("630", true)
691      .Case("g3", true)
692      .Case("7400", true)
693      .Case("g4", true)
694      .Case("7450", true)
695      .Case("g4+", true)
696      .Case("750", true)
697      .Case("970", true)
698      .Case("g5", true)
699      .Case("a2", true)
700      .Case("a2q", true)
701      .Case("e500mc", true)
702      .Case("e5500", true)
703      .Case("power3", true)
704      .Case("pwr3", true)
705      .Case("power4", true)
706      .Case("pwr4", true)
707      .Case("power5", true)
708      .Case("pwr5", true)
709      .Case("power5x", true)
710      .Case("pwr5x", true)
711      .Case("power6", true)
712      .Case("pwr6", true)
713      .Case("power6x", true)
714      .Case("pwr6x", true)
715      .Case("power7", true)
716      .Case("pwr7", true)
717      .Case("powerpc", true)
718      .Case("ppc", true)
719      .Case("powerpc64", true)
720      .Case("ppc64", true)
721      .Default(false);
722
723    if (CPUKnown)
724      CPU = Name;
725
726    return CPUKnown;
727  }
728
729  virtual void getTargetBuiltins(const Builtin::Info *&Records,
730                                 unsigned &NumRecords) const {
731    Records = BuiltinInfo;
732    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
733  }
734
735  virtual bool isCLZForZeroUndef() const { return false; }
736
737  virtual void getTargetDefines(const LangOptions &Opts,
738                                MacroBuilder &Builder) const;
739
740  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
741
742  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
743                                 StringRef Name,
744                                 bool Enabled) const;
745
746  virtual bool hasFeature(StringRef Feature) const;
747
748  virtual void getGCCRegNames(const char * const *&Names,
749                              unsigned &NumNames) const;
750  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
751                                unsigned &NumAliases) const;
752  virtual bool validateAsmConstraint(const char *&Name,
753                                     TargetInfo::ConstraintInfo &Info) const {
754    switch (*Name) {
755    default: return false;
756    case 'O': // Zero
757      break;
758    case 'b': // Base register
759    case 'f': // Floating point register
760      Info.setAllowsRegister();
761      break;
762    // FIXME: The following are added to allow parsing.
763    // I just took a guess at what the actions should be.
764    // Also, is more specific checking needed?  I.e. specific registers?
765    case 'd': // Floating point register (containing 64-bit value)
766    case 'v': // Altivec vector register
767      Info.setAllowsRegister();
768      break;
769    case 'w':
770      switch (Name[1]) {
771        case 'd':// VSX vector register to hold vector double data
772        case 'f':// VSX vector register to hold vector float data
773        case 's':// VSX vector register to hold scalar float data
774        case 'a':// Any VSX register
775          break;
776        default:
777          return false;
778      }
779      Info.setAllowsRegister();
780      Name++; // Skip over 'w'.
781      break;
782    case 'h': // `MQ', `CTR', or `LINK' register
783    case 'q': // `MQ' register
784    case 'c': // `CTR' register
785    case 'l': // `LINK' register
786    case 'x': // `CR' register (condition register) number 0
787    case 'y': // `CR' register (condition register)
788    case 'z': // `XER[CA]' carry bit (part of the XER register)
789      Info.setAllowsRegister();
790      break;
791    case 'I': // Signed 16-bit constant
792    case 'J': // Unsigned 16-bit constant shifted left 16 bits
793              //  (use `L' instead for SImode constants)
794    case 'K': // Unsigned 16-bit constant
795    case 'L': // Signed 16-bit constant shifted left 16 bits
796    case 'M': // Constant larger than 31
797    case 'N': // Exact power of 2
798    case 'P': // Constant whose negation is a signed 16-bit constant
799    case 'G': // Floating point constant that can be loaded into a
800              // register with one instruction per word
801    case 'H': // Integer/Floating point constant that can be loaded
802              // into a register using three instructions
803      break;
804    case 'm': // Memory operand. Note that on PowerPC targets, m can
805              // include addresses that update the base register. It
806              // is therefore only safe to use `m' in an asm statement
807              // if that asm statement accesses the operand exactly once.
808              // The asm statement must also use `%U<opno>' as a
809              // placeholder for the "update" flag in the corresponding
810              // load or store instruction. For example:
811              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
812              // is correct but:
813              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
814              // is not. Use es rather than m if you don't want the base
815              // register to be updated.
816    case 'e':
817      if (Name[1] != 's')
818          return false;
819              // es: A "stable" memory operand; that is, one which does not
820              // include any automodification of the base register. Unlike
821              // `m', this constraint can be used in asm statements that
822              // might access the operand several times, or that might not
823              // access it at all.
824      Info.setAllowsMemory();
825      Name++; // Skip over 'e'.
826      break;
827    case 'Q': // Memory operand that is an offset from a register (it is
828              // usually better to use `m' or `es' in asm statements)
829    case 'Z': // Memory operand that is an indexed or indirect from a
830              // register (it is usually better to use `m' or `es' in
831              // asm statements)
832      Info.setAllowsMemory();
833      Info.setAllowsRegister();
834      break;
835    case 'R': // AIX TOC entry
836    case 'a': // Address operand that is an indexed or indirect from a
837              // register (`p' is preferable for asm statements)
838    case 'S': // Constant suitable as a 64-bit mask operand
839    case 'T': // Constant suitable as a 32-bit mask operand
840    case 'U': // System V Release 4 small data area reference
841    case 't': // AND masks that can be performed by two rldic{l, r}
842              // instructions
843    case 'W': // Vector constant that does not require memory
844    case 'j': // Vector constant that is all zeros.
845      break;
846    // End FIXME.
847    }
848    return true;
849  }
850  virtual const char *getClobbers() const {
851    return "";
852  }
853  int getEHDataRegisterNumber(unsigned RegNo) const {
854    if (RegNo == 0) return 3;
855    if (RegNo == 1) return 4;
856    return -1;
857  }
858};
859
860const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
861#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
862#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
863                                              ALL_LANGUAGES },
864#include "clang/Basic/BuiltinsPPC.def"
865};
866
867
868/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
869/// #defines that are not tied to a specific subtarget.
870void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
871                                     MacroBuilder &Builder) const {
872  // Target identification.
873  Builder.defineMacro("__ppc__");
874  Builder.defineMacro("_ARCH_PPC");
875  Builder.defineMacro("__powerpc__");
876  Builder.defineMacro("__POWERPC__");
877  if (PointerWidth == 64) {
878    Builder.defineMacro("_ARCH_PPC64");
879    Builder.defineMacro("__powerpc64__");
880    Builder.defineMacro("__ppc64__");
881  } else {
882    Builder.defineMacro("__ppc__");
883  }
884
885  // Target properties.
886  if (getTriple().getOS() != llvm::Triple::NetBSD &&
887      getTriple().getOS() != llvm::Triple::OpenBSD)
888    Builder.defineMacro("_BIG_ENDIAN");
889  Builder.defineMacro("__BIG_ENDIAN__");
890
891  // Subtarget options.
892  Builder.defineMacro("__NATURAL_ALIGNMENT__");
893  Builder.defineMacro("__REGISTER_PREFIX__", "");
894
895  // FIXME: Should be controlled by command line option.
896  Builder.defineMacro("__LONG_DOUBLE_128__");
897
898  if (Opts.AltiVec) {
899    Builder.defineMacro("__VEC__", "10206");
900    Builder.defineMacro("__ALTIVEC__");
901  }
902
903  // CPU identification.
904  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
905    .Case("440",   ArchDefineName)
906    .Case("450",   ArchDefineName | ArchDefine440)
907    .Case("601",   ArchDefineName)
908    .Case("602",   ArchDefineName | ArchDefinePpcgr)
909    .Case("603",   ArchDefineName | ArchDefinePpcgr)
910    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
911    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
912    .Case("604",   ArchDefineName | ArchDefinePpcgr)
913    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
914    .Case("620",   ArchDefineName | ArchDefinePpcgr)
915    .Case("630",   ArchDefineName | ArchDefinePpcgr)
916    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
917    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
918    .Case("750",   ArchDefineName | ArchDefinePpcgr)
919    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
920                     | ArchDefinePpcsq)
921    .Case("a2",    ArchDefineA2)
922    .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
923    .Case("pwr3",  ArchDefinePpcgr)
924    .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
925    .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
926                     | ArchDefinePpcsq)
927    .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
928                     | ArchDefinePpcgr | ArchDefinePpcsq)
929    .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
930                     | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
931    .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
932                     | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
933                     | ArchDefinePpcsq)
934    .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
935                     | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
936                     | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
937    .Case("power3",  ArchDefinePpcgr)
938    .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
939    .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
940                       | ArchDefinePpcsq)
941    .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
942                       | ArchDefinePpcgr | ArchDefinePpcsq)
943    .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
944                       | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
945    .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
946                       | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
947                       | ArchDefinePpcsq)
948    .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
949                       | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
950                       | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
951    .Default(ArchDefineNone);
952
953  if (defs & ArchDefineName)
954    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
955  if (defs & ArchDefinePpcgr)
956    Builder.defineMacro("_ARCH_PPCGR");
957  if (defs & ArchDefinePpcsq)
958    Builder.defineMacro("_ARCH_PPCSQ");
959  if (defs & ArchDefine440)
960    Builder.defineMacro("_ARCH_440");
961  if (defs & ArchDefine603)
962    Builder.defineMacro("_ARCH_603");
963  if (defs & ArchDefine604)
964    Builder.defineMacro("_ARCH_604");
965  if (defs & ArchDefinePwr4)
966    Builder.defineMacro("_ARCH_PWR4");
967  if (defs & ArchDefinePwr5)
968    Builder.defineMacro("_ARCH_PWR5");
969  if (defs & ArchDefinePwr5x)
970    Builder.defineMacro("_ARCH_PWR5X");
971  if (defs & ArchDefinePwr6)
972    Builder.defineMacro("_ARCH_PWR6");
973  if (defs & ArchDefinePwr6x)
974    Builder.defineMacro("_ARCH_PWR6X");
975  if (defs & ArchDefinePwr7)
976    Builder.defineMacro("_ARCH_PWR7");
977  if (defs & ArchDefineA2)
978    Builder.defineMacro("_ARCH_A2");
979  if (defs & ArchDefineA2q) {
980    Builder.defineMacro("_ARCH_A2Q");
981    Builder.defineMacro("_ARCH_QP");
982  }
983
984  if (getTriple().getVendor() == llvm::Triple::BGQ) {
985    Builder.defineMacro("__bg__");
986    Builder.defineMacro("__THW_BLUEGENE__");
987    Builder.defineMacro("__bgq__");
988    Builder.defineMacro("__TOS_BGQ__");
989  }
990
991  // FIXME: The following are not yet generated here by Clang, but are
992  //        generated by GCC:
993  //
994  //   _SOFT_FLOAT_
995  //   __RECIP_PRECISION__
996  //   __APPLE_ALTIVEC__
997  //   __VSX__
998  //   __RECIP__
999  //   __RECIPF__
1000  //   __RSQRTE__
1001  //   __RSQRTEF__
1002  //   _SOFT_DOUBLE_
1003  //   __NO_LWSYNC__
1004  //   __HAVE_BSWAP__
1005  //   __LONGDOUBLE128
1006  //   __CMODEL_MEDIUM__
1007  //   __CMODEL_LARGE__
1008  //   _CALL_SYSV
1009  //   _CALL_DARWIN
1010  //   __NO_FPRS__
1011}
1012
1013void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1014  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1015    .Case("7400", true)
1016    .Case("g4", true)
1017    .Case("7450", true)
1018    .Case("g4+", true)
1019    .Case("970", true)
1020    .Case("g5", true)
1021    .Case("pwr6", true)
1022    .Case("pwr7", true)
1023    .Case("ppc64", true)
1024    .Default(false);
1025
1026  Features["qpx"] = (CPU == "a2q");
1027}
1028
1029bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1030                                         StringRef Name,
1031                                         bool Enabled) const {
1032  if (Name == "altivec" || Name == "qpx") {
1033    Features[Name] = Enabled;
1034    return true;
1035  }
1036
1037  return false;
1038}
1039
1040bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1041  return Feature == "powerpc";
1042}
1043
1044
1045const char * const PPCTargetInfo::GCCRegNames[] = {
1046  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1047  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1048  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1049  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1050  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1051  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1052  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1053  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1054  "mq", "lr", "ctr", "ap",
1055  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1056  "xer",
1057  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1058  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1059  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1060  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1061  "vrsave", "vscr",
1062  "spe_acc", "spefscr",
1063  "sfp"
1064};
1065
1066void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1067                                   unsigned &NumNames) const {
1068  Names = GCCRegNames;
1069  NumNames = llvm::array_lengthof(GCCRegNames);
1070}
1071
1072const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1073  // While some of these aliases do map to different registers
1074  // they still share the same register name.
1075  { { "0" }, "r0" },
1076  { { "1"}, "r1" },
1077  { { "2" }, "r2" },
1078  { { "3" }, "r3" },
1079  { { "4" }, "r4" },
1080  { { "5" }, "r5" },
1081  { { "6" }, "r6" },
1082  { { "7" }, "r7" },
1083  { { "8" }, "r8" },
1084  { { "9" }, "r9" },
1085  { { "10" }, "r10" },
1086  { { "11" }, "r11" },
1087  { { "12" }, "r12" },
1088  { { "13" }, "r13" },
1089  { { "14" }, "r14" },
1090  { { "15" }, "r15" },
1091  { { "16" }, "r16" },
1092  { { "17" }, "r17" },
1093  { { "18" }, "r18" },
1094  { { "19" }, "r19" },
1095  { { "20" }, "r20" },
1096  { { "21" }, "r21" },
1097  { { "22" }, "r22" },
1098  { { "23" }, "r23" },
1099  { { "24" }, "r24" },
1100  { { "25" }, "r25" },
1101  { { "26" }, "r26" },
1102  { { "27" }, "r27" },
1103  { { "28" }, "r28" },
1104  { { "29" }, "r29" },
1105  { { "30" }, "r30" },
1106  { { "31" }, "r31" },
1107  { { "fr0" }, "f0" },
1108  { { "fr1" }, "f1" },
1109  { { "fr2" }, "f2" },
1110  { { "fr3" }, "f3" },
1111  { { "fr4" }, "f4" },
1112  { { "fr5" }, "f5" },
1113  { { "fr6" }, "f6" },
1114  { { "fr7" }, "f7" },
1115  { { "fr8" }, "f8" },
1116  { { "fr9" }, "f9" },
1117  { { "fr10" }, "f10" },
1118  { { "fr11" }, "f11" },
1119  { { "fr12" }, "f12" },
1120  { { "fr13" }, "f13" },
1121  { { "fr14" }, "f14" },
1122  { { "fr15" }, "f15" },
1123  { { "fr16" }, "f16" },
1124  { { "fr17" }, "f17" },
1125  { { "fr18" }, "f18" },
1126  { { "fr19" }, "f19" },
1127  { { "fr20" }, "f20" },
1128  { { "fr21" }, "f21" },
1129  { { "fr22" }, "f22" },
1130  { { "fr23" }, "f23" },
1131  { { "fr24" }, "f24" },
1132  { { "fr25" }, "f25" },
1133  { { "fr26" }, "f26" },
1134  { { "fr27" }, "f27" },
1135  { { "fr28" }, "f28" },
1136  { { "fr29" }, "f29" },
1137  { { "fr30" }, "f30" },
1138  { { "fr31" }, "f31" },
1139  { { "cc" }, "cr0" },
1140};
1141
1142void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1143                                     unsigned &NumAliases) const {
1144  Aliases = GCCRegAliases;
1145  NumAliases = llvm::array_lengthof(GCCRegAliases);
1146}
1147} // end anonymous namespace.
1148
1149namespace {
1150class PPC32TargetInfo : public PPCTargetInfo {
1151public:
1152  PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1153    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1154                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1155
1156    switch (getTriple().getOS()) {
1157    case llvm::Triple::Linux:
1158    case llvm::Triple::FreeBSD:
1159    case llvm::Triple::NetBSD:
1160      SizeType = UnsignedInt;
1161      PtrDiffType = SignedInt;
1162      IntPtrType = SignedInt;
1163      break;
1164    default:
1165      break;
1166    }
1167
1168    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1169      LongDoubleWidth = LongDoubleAlign = 64;
1170      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1171    }
1172
1173    // PPC32 supports atomics up to 4 bytes.
1174    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1175  }
1176
1177  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1178    // This is the ELF definition, and is overridden by the Darwin sub-target
1179    return TargetInfo::PowerABIBuiltinVaList;
1180  }
1181};
1182} // end anonymous namespace.
1183
1184namespace {
1185class PPC64TargetInfo : public PPCTargetInfo {
1186public:
1187  PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1188    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1189    IntMaxType = SignedLong;
1190    UIntMaxType = UnsignedLong;
1191    Int64Type = SignedLong;
1192
1193    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1194      LongDoubleWidth = LongDoubleAlign = 64;
1195      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1196      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1197                          "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1198                          "v128:128:128-n32:64";
1199    } else
1200      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1201                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1202                          "v128:128:128-n32:64";
1203
1204    // PPC64 supports atomics up to 8 bytes.
1205    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1206  }
1207  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1208    return TargetInfo::CharPtrBuiltinVaList;
1209  }
1210};
1211} // end anonymous namespace.
1212
1213
1214namespace {
1215class DarwinPPC32TargetInfo :
1216  public DarwinTargetInfo<PPC32TargetInfo> {
1217public:
1218  DarwinPPC32TargetInfo(const std::string& triple)
1219    : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1220    HasAlignMac68kSupport = true;
1221    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1222    LongLongAlign = 32;
1223    SuitableAlign = 128;
1224    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1225                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1226  }
1227  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1228    return TargetInfo::CharPtrBuiltinVaList;
1229  }
1230};
1231
1232class DarwinPPC64TargetInfo :
1233  public DarwinTargetInfo<PPC64TargetInfo> {
1234public:
1235  DarwinPPC64TargetInfo(const std::string& triple)
1236    : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1237    HasAlignMac68kSupport = true;
1238    SuitableAlign = 128;
1239    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1240                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1241  }
1242};
1243} // end anonymous namespace.
1244
1245namespace {
1246  static const unsigned NVPTXAddrSpaceMap[] = {
1247    1,    // opencl_global
1248    3,    // opencl_local
1249    4,    // opencl_constant
1250    1,    // cuda_device
1251    4,    // cuda_constant
1252    3,    // cuda_shared
1253  };
1254  class NVPTXTargetInfo : public TargetInfo {
1255    static const char * const GCCRegNames[];
1256    static const Builtin::Info BuiltinInfo[];
1257    std::vector<StringRef> AvailableFeatures;
1258  public:
1259    NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1260      BigEndian = false;
1261      TLSSupported = false;
1262      LongWidth = LongAlign = 64;
1263      AddrSpaceMap = &NVPTXAddrSpaceMap;
1264      // Define available target features
1265      // These must be defined in sorted order!
1266      NoAsmVariants = true;
1267    }
1268    virtual void getTargetDefines(const LangOptions &Opts,
1269                                  MacroBuilder &Builder) const {
1270      Builder.defineMacro("__PTX__");
1271      Builder.defineMacro("__NVPTX__");
1272    }
1273    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1274                                   unsigned &NumRecords) const {
1275      Records = BuiltinInfo;
1276      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1277    }
1278    virtual bool hasFeature(StringRef Feature) const {
1279      return Feature == "ptx" || Feature == "nvptx";
1280    }
1281
1282    virtual void getGCCRegNames(const char * const *&Names,
1283                                unsigned &NumNames) const;
1284    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1285                                  unsigned &NumAliases) const {
1286      // No aliases.
1287      Aliases = 0;
1288      NumAliases = 0;
1289    }
1290    virtual bool validateAsmConstraint(const char *&Name,
1291                                       TargetInfo::ConstraintInfo &info) const {
1292      // FIXME: implement
1293      return true;
1294    }
1295    virtual const char *getClobbers() const {
1296      // FIXME: Is this really right?
1297      return "";
1298    }
1299    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1300      // FIXME: implement
1301      return TargetInfo::CharPtrBuiltinVaList;
1302    }
1303    virtual bool setCPU(const std::string &Name) {
1304      return Name == "sm_10" || Name == "sm_13" || Name == "sm_20";
1305    }
1306    virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1307                                   StringRef Name,
1308                                   bool Enabled) const;
1309  };
1310
1311  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1312#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1313#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1314                                              ALL_LANGUAGES },
1315#include "clang/Basic/BuiltinsNVPTX.def"
1316  };
1317
1318  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1319    "r0"
1320  };
1321
1322  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1323                                     unsigned &NumNames) const {
1324    Names = GCCRegNames;
1325    NumNames = llvm::array_lengthof(GCCRegNames);
1326  }
1327
1328  bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1329                                          StringRef Name,
1330                                          bool Enabled) const {
1331    if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1332                          Name)) {
1333      Features[Name] = Enabled;
1334      return true;
1335    } else {
1336      return false;
1337    }
1338  }
1339
1340  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1341  public:
1342    NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1343      PointerWidth = PointerAlign = 32;
1344      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1345      DescriptionString
1346        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1347          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1348          "n16:32:64";
1349  }
1350  };
1351
1352  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1353  public:
1354    NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1355      PointerWidth = PointerAlign = 64;
1356      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1357      DescriptionString
1358        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1359          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1360          "n16:32:64";
1361  }
1362  };
1363}
1364
1365namespace {
1366
1367static const unsigned R600AddrSpaceMap[] = {
1368  1,    // opencl_global
1369  3,    // opencl_local
1370  2,    // opencl_constant
1371  1,    // cuda_device
1372  2,    // cuda_constant
1373  3     // cuda_shared
1374};
1375
1376class R600TargetInfo : public TargetInfo {
1377public:
1378  R600TargetInfo(const std::string& triple) : TargetInfo(triple) {
1379    DescriptionString =
1380          "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16"
1381          "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"
1382          "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"
1383          "-v96:128:128-v128:128:128-v192:256:256-v256:256:256"
1384          "-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1385          "-n8:16:32:64";
1386    AddrSpaceMap = &R600AddrSpaceMap;
1387  }
1388
1389  virtual const char * getClobbers() const {
1390    return "";
1391  }
1392
1393  virtual void getGCCRegNames(const char * const *&Names,
1394                              unsigned &numNames) const  {
1395    Names = NULL;
1396    numNames = 0;
1397  }
1398
1399  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1400                                unsigned &NumAliases) const {
1401    Aliases = NULL;
1402    NumAliases = 0;
1403  }
1404
1405  virtual bool validateAsmConstraint(const char *&Name,
1406                                     TargetInfo::ConstraintInfo &info) const {
1407    return true;
1408  }
1409
1410  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1411                                 unsigned &NumRecords) const {
1412    Records = NULL;
1413    NumRecords = 0;
1414  }
1415
1416
1417  virtual void getTargetDefines(const LangOptions &Opts,
1418                                MacroBuilder &Builder) const {
1419    Builder.defineMacro("__R600__");
1420  }
1421
1422  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1423    return TargetInfo::CharPtrBuiltinVaList;
1424  }
1425
1426};
1427
1428} // end anonymous namespace
1429
1430namespace {
1431// MBlaze abstract base class
1432class MBlazeTargetInfo : public TargetInfo {
1433  static const char * const GCCRegNames[];
1434  static const TargetInfo::GCCRegAlias GCCRegAliases[];
1435
1436public:
1437  MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1438    DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1439  }
1440
1441  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1442                                 unsigned &NumRecords) const {
1443    // FIXME: Implement.
1444    Records = 0;
1445    NumRecords = 0;
1446  }
1447
1448  virtual void getTargetDefines(const LangOptions &Opts,
1449                                MacroBuilder &Builder) const;
1450
1451  virtual bool hasFeature(StringRef Feature) const {
1452    return Feature == "mblaze";
1453  }
1454
1455  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1456    return TargetInfo::CharPtrBuiltinVaList;
1457  }
1458  virtual const char *getTargetPrefix() const {
1459    return "mblaze";
1460  }
1461  virtual void getGCCRegNames(const char * const *&Names,
1462                              unsigned &NumNames) const;
1463  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1464                                unsigned &NumAliases) const;
1465  virtual bool validateAsmConstraint(const char *&Name,
1466                                     TargetInfo::ConstraintInfo &Info) const {
1467    switch (*Name) {
1468    default: return false;
1469    case 'O': // Zero
1470      return true;
1471    case 'b': // Base register
1472    case 'f': // Floating point register
1473      Info.setAllowsRegister();
1474      return true;
1475    }
1476  }
1477  virtual const char *getClobbers() const {
1478    return "";
1479  }
1480};
1481
1482/// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1483/// #defines that are not tied to a specific subtarget.
1484void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1485                                     MacroBuilder &Builder) const {
1486  // Target identification.
1487  Builder.defineMacro("__microblaze__");
1488  Builder.defineMacro("_ARCH_MICROBLAZE");
1489  Builder.defineMacro("__MICROBLAZE__");
1490
1491  // Target properties.
1492  Builder.defineMacro("_BIG_ENDIAN");
1493  Builder.defineMacro("__BIG_ENDIAN__");
1494
1495  // Subtarget options.
1496  Builder.defineMacro("__REGISTER_PREFIX__", "");
1497}
1498
1499
1500const char * const MBlazeTargetInfo::GCCRegNames[] = {
1501  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1502  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1503  "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1504  "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1505  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1506  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1507  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1508  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1509  "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1510  "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1511};
1512
1513void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1514                                   unsigned &NumNames) const {
1515  Names = GCCRegNames;
1516  NumNames = llvm::array_lengthof(GCCRegNames);
1517}
1518
1519const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1520  { {"f0"},  "r0" },
1521  { {"f1"},  "r1" },
1522  { {"f2"},  "r2" },
1523  { {"f3"},  "r3" },
1524  { {"f4"},  "r4" },
1525  { {"f5"},  "r5" },
1526  { {"f6"},  "r6" },
1527  { {"f7"},  "r7" },
1528  { {"f8"},  "r8" },
1529  { {"f9"},  "r9" },
1530  { {"f10"}, "r10" },
1531  { {"f11"}, "r11" },
1532  { {"f12"}, "r12" },
1533  { {"f13"}, "r13" },
1534  { {"f14"}, "r14" },
1535  { {"f15"}, "r15" },
1536  { {"f16"}, "r16" },
1537  { {"f17"}, "r17" },
1538  { {"f18"}, "r18" },
1539  { {"f19"}, "r19" },
1540  { {"f20"}, "r20" },
1541  { {"f21"}, "r21" },
1542  { {"f22"}, "r22" },
1543  { {"f23"}, "r23" },
1544  { {"f24"}, "r24" },
1545  { {"f25"}, "r25" },
1546  { {"f26"}, "r26" },
1547  { {"f27"}, "r27" },
1548  { {"f28"}, "r28" },
1549  { {"f29"}, "r29" },
1550  { {"f30"}, "r30" },
1551  { {"f31"}, "r31" },
1552};
1553
1554void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1555                                     unsigned &NumAliases) const {
1556  Aliases = GCCRegAliases;
1557  NumAliases = llvm::array_lengthof(GCCRegAliases);
1558}
1559} // end anonymous namespace.
1560
1561namespace {
1562// Namespace for x86 abstract base class
1563const Builtin::Info BuiltinInfo[] = {
1564#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1565#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1566                                              ALL_LANGUAGES },
1567#include "clang/Basic/BuiltinsX86.def"
1568};
1569
1570static const char* const GCCRegNames[] = {
1571  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1572  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1573  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1574  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1575  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1576  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1577  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1578  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1579  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1580};
1581
1582const TargetInfo::AddlRegName AddlRegNames[] = {
1583  { { "al", "ah", "eax", "rax" }, 0 },
1584  { { "bl", "bh", "ebx", "rbx" }, 3 },
1585  { { "cl", "ch", "ecx", "rcx" }, 2 },
1586  { { "dl", "dh", "edx", "rdx" }, 1 },
1587  { { "esi", "rsi" }, 4 },
1588  { { "edi", "rdi" }, 5 },
1589  { { "esp", "rsp" }, 7 },
1590  { { "ebp", "rbp" }, 6 },
1591};
1592
1593// X86 target abstract base class; x86-32 and x86-64 are very close, so
1594// most of the implementation can be shared.
1595class X86TargetInfo : public TargetInfo {
1596  enum X86SSEEnum {
1597    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1598  } SSELevel;
1599  enum MMX3DNowEnum {
1600    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1601  } MMX3DNowLevel;
1602
1603  bool HasAES;
1604  bool HasPCLMUL;
1605  bool HasLZCNT;
1606  bool HasRDRND;
1607  bool HasBMI;
1608  bool HasBMI2;
1609  bool HasPOPCNT;
1610  bool HasRTM;
1611  bool HasSSE4a;
1612  bool HasFMA4;
1613  bool HasFMA;
1614  bool HasXOP;
1615  bool HasF16C;
1616
1617  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1618  ///
1619  /// Each enumeration represents a particular CPU supported by Clang. These
1620  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1621  enum CPUKind {
1622    CK_Generic,
1623
1624    /// \name i386
1625    /// i386-generation processors.
1626    //@{
1627    CK_i386,
1628    //@}
1629
1630    /// \name i486
1631    /// i486-generation processors.
1632    //@{
1633    CK_i486,
1634    CK_WinChipC6,
1635    CK_WinChip2,
1636    CK_C3,
1637    //@}
1638
1639    /// \name i586
1640    /// i586-generation processors, P5 microarchitecture based.
1641    //@{
1642    CK_i586,
1643    CK_Pentium,
1644    CK_PentiumMMX,
1645    //@}
1646
1647    /// \name i686
1648    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1649    //@{
1650    CK_i686,
1651    CK_PentiumPro,
1652    CK_Pentium2,
1653    CK_Pentium3,
1654    CK_Pentium3M,
1655    CK_PentiumM,
1656    CK_C3_2,
1657
1658    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1659    /// Clang however has some logic to suport this.
1660    // FIXME: Warn, deprecate, and potentially remove this.
1661    CK_Yonah,
1662    //@}
1663
1664    /// \name Netburst
1665    /// Netburst microarchitecture based processors.
1666    //@{
1667    CK_Pentium4,
1668    CK_Pentium4M,
1669    CK_Prescott,
1670    CK_Nocona,
1671    //@}
1672
1673    /// \name Core
1674    /// Core microarchitecture based processors.
1675    //@{
1676    CK_Core2,
1677
1678    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1679    /// codename which GCC no longer accepts as an option to -march, but Clang
1680    /// has some logic for recognizing it.
1681    // FIXME: Warn, deprecate, and potentially remove this.
1682    CK_Penryn,
1683    //@}
1684
1685    /// \name Atom
1686    /// Atom processors
1687    //@{
1688    CK_Atom,
1689    //@}
1690
1691    /// \name Nehalem
1692    /// Nehalem microarchitecture based processors.
1693    //@{
1694    CK_Corei7,
1695    CK_Corei7AVX,
1696    CK_CoreAVXi,
1697    CK_CoreAVX2,
1698    //@}
1699
1700    /// \name K6
1701    /// K6 architecture processors.
1702    //@{
1703    CK_K6,
1704    CK_K6_2,
1705    CK_K6_3,
1706    //@}
1707
1708    /// \name K7
1709    /// K7 architecture processors.
1710    //@{
1711    CK_Athlon,
1712    CK_AthlonThunderbird,
1713    CK_Athlon4,
1714    CK_AthlonXP,
1715    CK_AthlonMP,
1716    //@}
1717
1718    /// \name K8
1719    /// K8 architecture processors.
1720    //@{
1721    CK_Athlon64,
1722    CK_Athlon64SSE3,
1723    CK_AthlonFX,
1724    CK_K8,
1725    CK_K8SSE3,
1726    CK_Opteron,
1727    CK_OpteronSSE3,
1728    CK_AMDFAM10,
1729    //@}
1730
1731    /// \name Bobcat
1732    /// Bobcat architecture processors.
1733    //@{
1734    CK_BTVER1,
1735    //@}
1736
1737    /// \name Bulldozer
1738    /// Bulldozer architecture processors.
1739    //@{
1740    CK_BDVER1,
1741    CK_BDVER2,
1742    //@}
1743
1744    /// This specification is deprecated and will be removed in the future.
1745    /// Users should prefer \see CK_K8.
1746    // FIXME: Warn on this when the CPU is set to it.
1747    CK_x86_64,
1748    //@}
1749
1750    /// \name Geode
1751    /// Geode processors.
1752    //@{
1753    CK_Geode
1754    //@}
1755  } CPU;
1756
1757public:
1758  X86TargetInfo(const std::string& triple)
1759    : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1760      HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1761      HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1762      HasSSE4a(false), HasFMA4(false), HasFMA(false), HasXOP(false),
1763      HasF16C(false), CPU(CK_Generic) {
1764    BigEndian = false;
1765    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1766  }
1767  virtual unsigned getFloatEvalMethod() const {
1768    // X87 evaluates with 80 bits "long double" precision.
1769    return SSELevel == NoSSE ? 2 : 0;
1770  }
1771  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1772                                 unsigned &NumRecords) const {
1773    Records = BuiltinInfo;
1774    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1775  }
1776  virtual void getGCCRegNames(const char * const *&Names,
1777                              unsigned &NumNames) const {
1778    Names = GCCRegNames;
1779    NumNames = llvm::array_lengthof(GCCRegNames);
1780  }
1781  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1782                                unsigned &NumAliases) const {
1783    Aliases = 0;
1784    NumAliases = 0;
1785  }
1786  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1787                                  unsigned &NumNames) const {
1788    Names = AddlRegNames;
1789    NumNames = llvm::array_lengthof(AddlRegNames);
1790  }
1791  virtual bool validateAsmConstraint(const char *&Name,
1792                                     TargetInfo::ConstraintInfo &info) const;
1793  virtual std::string convertConstraint(const char *&Constraint) const;
1794  virtual const char *getClobbers() const {
1795    return "~{dirflag},~{fpsr},~{flags}";
1796  }
1797  virtual void getTargetDefines(const LangOptions &Opts,
1798                                MacroBuilder &Builder) const;
1799  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1800                                 StringRef Name,
1801                                 bool Enabled) const;
1802  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1803  virtual bool hasFeature(StringRef Feature) const;
1804  virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1805  virtual const char* getABI() const {
1806    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1807      return "avx";
1808    else if (getTriple().getArch() == llvm::Triple::x86 &&
1809             MMX3DNowLevel == NoMMX3DNow)
1810      return "no-mmx";
1811    return "";
1812  }
1813  virtual bool setCPU(const std::string &Name) {
1814    CPU = llvm::StringSwitch<CPUKind>(Name)
1815      .Case("i386", CK_i386)
1816      .Case("i486", CK_i486)
1817      .Case("winchip-c6", CK_WinChipC6)
1818      .Case("winchip2", CK_WinChip2)
1819      .Case("c3", CK_C3)
1820      .Case("i586", CK_i586)
1821      .Case("pentium", CK_Pentium)
1822      .Case("pentium-mmx", CK_PentiumMMX)
1823      .Case("i686", CK_i686)
1824      .Case("pentiumpro", CK_PentiumPro)
1825      .Case("pentium2", CK_Pentium2)
1826      .Case("pentium3", CK_Pentium3)
1827      .Case("pentium3m", CK_Pentium3M)
1828      .Case("pentium-m", CK_PentiumM)
1829      .Case("c3-2", CK_C3_2)
1830      .Case("yonah", CK_Yonah)
1831      .Case("pentium4", CK_Pentium4)
1832      .Case("pentium4m", CK_Pentium4M)
1833      .Case("prescott", CK_Prescott)
1834      .Case("nocona", CK_Nocona)
1835      .Case("core2", CK_Core2)
1836      .Case("penryn", CK_Penryn)
1837      .Case("atom", CK_Atom)
1838      .Case("corei7", CK_Corei7)
1839      .Case("corei7-avx", CK_Corei7AVX)
1840      .Case("core-avx-i", CK_CoreAVXi)
1841      .Case("core-avx2", CK_CoreAVX2)
1842      .Case("k6", CK_K6)
1843      .Case("k6-2", CK_K6_2)
1844      .Case("k6-3", CK_K6_3)
1845      .Case("athlon", CK_Athlon)
1846      .Case("athlon-tbird", CK_AthlonThunderbird)
1847      .Case("athlon-4", CK_Athlon4)
1848      .Case("athlon-xp", CK_AthlonXP)
1849      .Case("athlon-mp", CK_AthlonMP)
1850      .Case("athlon64", CK_Athlon64)
1851      .Case("athlon64-sse3", CK_Athlon64SSE3)
1852      .Case("athlon-fx", CK_AthlonFX)
1853      .Case("k8", CK_K8)
1854      .Case("k8-sse3", CK_K8SSE3)
1855      .Case("opteron", CK_Opteron)
1856      .Case("opteron-sse3", CK_OpteronSSE3)
1857      .Case("amdfam10", CK_AMDFAM10)
1858      .Case("btver1", CK_BTVER1)
1859      .Case("bdver1", CK_BDVER1)
1860      .Case("bdver2", CK_BDVER2)
1861      .Case("x86-64", CK_x86_64)
1862      .Case("geode", CK_Geode)
1863      .Default(CK_Generic);
1864
1865    // Perform any per-CPU checks necessary to determine if this CPU is
1866    // acceptable.
1867    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1868    // invalid without explaining *why*.
1869    switch (CPU) {
1870    case CK_Generic:
1871      // No processor selected!
1872      return false;
1873
1874    case CK_i386:
1875    case CK_i486:
1876    case CK_WinChipC6:
1877    case CK_WinChip2:
1878    case CK_C3:
1879    case CK_i586:
1880    case CK_Pentium:
1881    case CK_PentiumMMX:
1882    case CK_i686:
1883    case CK_PentiumPro:
1884    case CK_Pentium2:
1885    case CK_Pentium3:
1886    case CK_Pentium3M:
1887    case CK_PentiumM:
1888    case CK_Yonah:
1889    case CK_C3_2:
1890    case CK_Pentium4:
1891    case CK_Pentium4M:
1892    case CK_Prescott:
1893    case CK_K6:
1894    case CK_K6_2:
1895    case CK_K6_3:
1896    case CK_Athlon:
1897    case CK_AthlonThunderbird:
1898    case CK_Athlon4:
1899    case CK_AthlonXP:
1900    case CK_AthlonMP:
1901    case CK_Geode:
1902      // Only accept certain architectures when compiling in 32-bit mode.
1903      if (getTriple().getArch() != llvm::Triple::x86)
1904        return false;
1905
1906      // Fallthrough
1907    case CK_Nocona:
1908    case CK_Core2:
1909    case CK_Penryn:
1910    case CK_Atom:
1911    case CK_Corei7:
1912    case CK_Corei7AVX:
1913    case CK_CoreAVXi:
1914    case CK_CoreAVX2:
1915    case CK_Athlon64:
1916    case CK_Athlon64SSE3:
1917    case CK_AthlonFX:
1918    case CK_K8:
1919    case CK_K8SSE3:
1920    case CK_Opteron:
1921    case CK_OpteronSSE3:
1922    case CK_AMDFAM10:
1923    case CK_BTVER1:
1924    case CK_BDVER1:
1925    case CK_BDVER2:
1926    case CK_x86_64:
1927      return true;
1928    }
1929    llvm_unreachable("Unhandled CPU kind");
1930  }
1931
1932  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
1933    // We accept all non-ARM calling conventions
1934    return (CC == CC_X86ThisCall ||
1935            CC == CC_X86FastCall ||
1936            CC == CC_X86StdCall ||
1937            CC == CC_C ||
1938            CC == CC_X86Pascal ||
1939            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
1940  }
1941
1942  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
1943    return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
1944  }
1945};
1946
1947void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1948  // FIXME: This should not be here.
1949  Features["3dnow"] = false;
1950  Features["3dnowa"] = false;
1951  Features["mmx"] = false;
1952  Features["sse"] = false;
1953  Features["sse2"] = false;
1954  Features["sse3"] = false;
1955  Features["ssse3"] = false;
1956  Features["sse41"] = false;
1957  Features["sse42"] = false;
1958  Features["sse4a"] = false;
1959  Features["aes"] = false;
1960  Features["pclmul"] = false;
1961  Features["avx"] = false;
1962  Features["avx2"] = false;
1963  Features["lzcnt"] = false;
1964  Features["rdrand"] = false;
1965  Features["bmi"] = false;
1966  Features["bmi2"] = false;
1967  Features["popcnt"] = false;
1968  Features["rtm"] = false;
1969  Features["fma4"] = false;
1970  Features["fma"] = false;
1971  Features["xop"] = false;
1972  Features["f16c"] = false;
1973
1974  // FIXME: This *really* should not be here.
1975
1976  // X86_64 always has SSE2.
1977  if (getTriple().getArch() == llvm::Triple::x86_64)
1978    setFeatureEnabled(Features, "sse2", true);
1979
1980  switch (CPU) {
1981  case CK_Generic:
1982  case CK_i386:
1983  case CK_i486:
1984  case CK_i586:
1985  case CK_Pentium:
1986  case CK_i686:
1987  case CK_PentiumPro:
1988    break;
1989  case CK_PentiumMMX:
1990  case CK_Pentium2:
1991    setFeatureEnabled(Features, "mmx", true);
1992    break;
1993  case CK_Pentium3:
1994  case CK_Pentium3M:
1995    setFeatureEnabled(Features, "sse", true);
1996    break;
1997  case CK_PentiumM:
1998  case CK_Pentium4:
1999  case CK_Pentium4M:
2000  case CK_x86_64:
2001    setFeatureEnabled(Features, "sse2", true);
2002    break;
2003  case CK_Yonah:
2004  case CK_Prescott:
2005  case CK_Nocona:
2006    setFeatureEnabled(Features, "sse3", true);
2007    break;
2008  case CK_Core2:
2009    setFeatureEnabled(Features, "ssse3", true);
2010    break;
2011  case CK_Penryn:
2012    setFeatureEnabled(Features, "sse4.1", true);
2013    break;
2014  case CK_Atom:
2015    setFeatureEnabled(Features, "ssse3", true);
2016    break;
2017  case CK_Corei7:
2018    setFeatureEnabled(Features, "sse4", true);
2019    break;
2020  case CK_Corei7AVX:
2021    setFeatureEnabled(Features, "avx", true);
2022    setFeatureEnabled(Features, "aes", true);
2023    setFeatureEnabled(Features, "pclmul", true);
2024    break;
2025  case CK_CoreAVXi:
2026    setFeatureEnabled(Features, "avx", true);
2027    setFeatureEnabled(Features, "aes", true);
2028    setFeatureEnabled(Features, "pclmul", true);
2029    setFeatureEnabled(Features, "rdrnd", true);
2030    setFeatureEnabled(Features, "f16c", true);
2031    break;
2032  case CK_CoreAVX2:
2033    setFeatureEnabled(Features, "avx2", true);
2034    setFeatureEnabled(Features, "aes", true);
2035    setFeatureEnabled(Features, "pclmul", true);
2036    setFeatureEnabled(Features, "lzcnt", true);
2037    setFeatureEnabled(Features, "rdrnd", true);
2038    setFeatureEnabled(Features, "f16c", true);
2039    setFeatureEnabled(Features, "bmi", true);
2040    setFeatureEnabled(Features, "bmi2", true);
2041    setFeatureEnabled(Features, "rtm", true);
2042    setFeatureEnabled(Features, "fma", true);
2043    break;
2044  case CK_K6:
2045  case CK_WinChipC6:
2046    setFeatureEnabled(Features, "mmx", true);
2047    break;
2048  case CK_K6_2:
2049  case CK_K6_3:
2050  case CK_WinChip2:
2051  case CK_C3:
2052    setFeatureEnabled(Features, "3dnow", true);
2053    break;
2054  case CK_Athlon:
2055  case CK_AthlonThunderbird:
2056  case CK_Geode:
2057    setFeatureEnabled(Features, "3dnowa", true);
2058    break;
2059  case CK_Athlon4:
2060  case CK_AthlonXP:
2061  case CK_AthlonMP:
2062    setFeatureEnabled(Features, "sse", true);
2063    setFeatureEnabled(Features, "3dnowa", true);
2064    break;
2065  case CK_K8:
2066  case CK_Opteron:
2067  case CK_Athlon64:
2068  case CK_AthlonFX:
2069    setFeatureEnabled(Features, "sse2", true);
2070    setFeatureEnabled(Features, "3dnowa", true);
2071    break;
2072  case CK_K8SSE3:
2073  case CK_OpteronSSE3:
2074  case CK_Athlon64SSE3:
2075    setFeatureEnabled(Features, "sse3", true);
2076    setFeatureEnabled(Features, "3dnowa", true);
2077    break;
2078  case CK_AMDFAM10:
2079    setFeatureEnabled(Features, "sse3", true);
2080    setFeatureEnabled(Features, "sse4a", true);
2081    setFeatureEnabled(Features, "3dnowa", true);
2082    setFeatureEnabled(Features, "lzcnt", true);
2083    setFeatureEnabled(Features, "popcnt", true);
2084    break;
2085  case CK_BTVER1:
2086    setFeatureEnabled(Features, "ssse3", true);
2087    setFeatureEnabled(Features, "sse4a", true);
2088    setFeatureEnabled(Features, "lzcnt", true);
2089    setFeatureEnabled(Features, "popcnt", true);
2090    break;
2091  case CK_BDVER1:
2092    setFeatureEnabled(Features, "xop", true);
2093    setFeatureEnabled(Features, "lzcnt", true);
2094    setFeatureEnabled(Features, "aes", true);
2095    setFeatureEnabled(Features, "pclmul", true);
2096    break;
2097  case CK_BDVER2:
2098    setFeatureEnabled(Features, "xop", true);
2099    setFeatureEnabled(Features, "lzcnt", true);
2100    setFeatureEnabled(Features, "aes", true);
2101    setFeatureEnabled(Features, "pclmul", true);
2102    setFeatureEnabled(Features, "bmi", true);
2103    setFeatureEnabled(Features, "fma", true);
2104    setFeatureEnabled(Features, "f16c", true);
2105    break;
2106  case CK_C3_2:
2107    setFeatureEnabled(Features, "sse", true);
2108    break;
2109  }
2110}
2111
2112bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2113                                      StringRef Name,
2114                                      bool Enabled) const {
2115  // FIXME: This *really* should not be here.  We need some way of translating
2116  // options into llvm subtarget features.
2117  if (!Features.count(Name) &&
2118      (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2119       Name != "rdrnd"))
2120    return false;
2121
2122  // FIXME: this should probably use a switch with fall through.
2123
2124  if (Enabled) {
2125    if (Name == "mmx")
2126      Features["mmx"] = true;
2127    else if (Name == "sse")
2128      Features["mmx"] = Features["sse"] = true;
2129    else if (Name == "sse2")
2130      Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2131    else if (Name == "sse3")
2132      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2133        true;
2134    else if (Name == "ssse3")
2135      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2136        Features["ssse3"] = true;
2137    else if (Name == "sse4" || Name == "sse4.2")
2138      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2139        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2140        Features["popcnt"] = true;
2141    else if (Name == "sse4.1")
2142      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2143        Features["ssse3"] = Features["sse41"] = true;
2144    else if (Name == "3dnow")
2145      Features["mmx"] = Features["3dnow"] = true;
2146    else if (Name == "3dnowa")
2147      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2148    else if (Name == "aes")
2149      Features["sse"] = Features["sse2"] = Features["aes"] = true;
2150    else if (Name == "pclmul")
2151      Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2152    else if (Name == "avx")
2153      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2154        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2155        Features["popcnt"] = Features["avx"] = true;
2156    else if (Name == "avx2")
2157      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2158        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2159        Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2160    else if (Name == "fma")
2161      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2162        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2163        Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2164    else if (Name == "fma4")
2165      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2166        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2167        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2168        Features["fma4"] = true;
2169    else if (Name == "xop")
2170      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2171        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2172        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2173        Features["fma4"] = Features["xop"] = true;
2174    else if (Name == "sse4a")
2175      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2176        Features["sse4a"] = true;
2177    else if (Name == "lzcnt")
2178      Features["lzcnt"] = true;
2179    else if (Name == "rdrnd")
2180      Features["rdrand"] = true;
2181    else if (Name == "bmi")
2182      Features["bmi"] = true;
2183    else if (Name == "bmi2")
2184      Features["bmi2"] = true;
2185    else if (Name == "popcnt")
2186      Features["popcnt"] = true;
2187    else if (Name == "f16c")
2188      Features["f16c"] = true;
2189    else if (Name == "rtm")
2190      Features["rtm"] = true;
2191  } else {
2192    if (Name == "mmx")
2193      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2194    else if (Name == "sse")
2195      Features["sse"] = Features["sse2"] = Features["sse3"] =
2196        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2197        Features["sse4a"] = Features["avx"] = Features["avx2"] =
2198        Features["fma"] = Features["fma4"] = Features["aes"] =
2199        Features["pclmul"] = Features["xop"] = false;
2200    else if (Name == "sse2")
2201      Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2202        Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2203        Features["avx"] = Features["avx2"] = Features["fma"] =
2204        Features["fma4"] = Features["aes"] = Features["pclmul"] =
2205        Features["xop"] = false;
2206    else if (Name == "sse3")
2207      Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2208        Features["sse42"] = Features["sse4a"] = Features["avx"] =
2209        Features["avx2"] = Features["fma"] = Features["fma4"] =
2210        Features["xop"] = false;
2211    else if (Name == "ssse3")
2212      Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2213        Features["avx"] = Features["avx2"] = Features["fma"] = false;
2214    else if (Name == "sse4" || Name == "sse4.1")
2215      Features["sse41"] = Features["sse42"] = Features["avx"] =
2216        Features["avx2"] = Features["fma"] = false;
2217    else if (Name == "sse4.2")
2218      Features["sse42"] = Features["avx"] = Features["avx2"] =
2219        Features["fma"] = false;
2220    else if (Name == "3dnow")
2221      Features["3dnow"] = Features["3dnowa"] = false;
2222    else if (Name == "3dnowa")
2223      Features["3dnowa"] = false;
2224    else if (Name == "aes")
2225      Features["aes"] = false;
2226    else if (Name == "pclmul")
2227      Features["pclmul"] = false;
2228    else if (Name == "avx")
2229      Features["avx"] = Features["avx2"] = Features["fma"] =
2230        Features["fma4"] = Features["xop"] = false;
2231    else if (Name == "avx2")
2232      Features["avx2"] = false;
2233    else if (Name == "fma")
2234      Features["fma"] = false;
2235    else if (Name == "sse4a")
2236      Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2237    else if (Name == "lzcnt")
2238      Features["lzcnt"] = false;
2239    else if (Name == "rdrnd")
2240      Features["rdrand"] = false;
2241    else if (Name == "bmi")
2242      Features["bmi"] = false;
2243    else if (Name == "bmi2")
2244      Features["bmi2"] = false;
2245    else if (Name == "popcnt")
2246      Features["popcnt"] = false;
2247    else if (Name == "fma4")
2248      Features["fma4"] = Features["xop"] = false;
2249    else if (Name == "xop")
2250      Features["xop"] = false;
2251    else if (Name == "f16c")
2252      Features["f16c"] = false;
2253    else if (Name == "rtm")
2254      Features["rtm"] = false;
2255  }
2256
2257  return true;
2258}
2259
2260/// HandleTargetOptions - Perform initialization based on the user
2261/// configured set of features.
2262void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2263  // Remember the maximum enabled sselevel.
2264  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2265    // Ignore disabled features.
2266    if (Features[i][0] == '-')
2267      continue;
2268
2269    StringRef Feature = StringRef(Features[i]).substr(1);
2270
2271    if (Feature == "aes") {
2272      HasAES = true;
2273      continue;
2274    }
2275
2276    if (Feature == "pclmul") {
2277      HasPCLMUL = true;
2278      continue;
2279    }
2280
2281    if (Feature == "lzcnt") {
2282      HasLZCNT = true;
2283      continue;
2284    }
2285
2286    if (Feature == "rdrand") {
2287      HasRDRND = true;
2288      continue;
2289    }
2290
2291    if (Feature == "bmi") {
2292      HasBMI = true;
2293      continue;
2294    }
2295
2296    if (Feature == "bmi2") {
2297      HasBMI2 = true;
2298      continue;
2299    }
2300
2301    if (Feature == "popcnt") {
2302      HasPOPCNT = true;
2303      continue;
2304    }
2305
2306    if (Feature == "rtm") {
2307      HasRTM = true;
2308      continue;
2309    }
2310
2311    if (Feature == "sse4a") {
2312      HasSSE4a = true;
2313      continue;
2314    }
2315
2316    if (Feature == "fma4") {
2317      HasFMA4 = true;
2318      continue;
2319    }
2320
2321    if (Feature == "fma") {
2322      HasFMA = true;
2323      continue;
2324    }
2325
2326    if (Feature == "xop") {
2327      HasXOP = true;
2328      continue;
2329    }
2330
2331    if (Feature == "f16c") {
2332      HasF16C = true;
2333      continue;
2334    }
2335
2336    assert(Features[i][0] == '+' && "Invalid target feature!");
2337    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2338      .Case("avx2", AVX2)
2339      .Case("avx", AVX)
2340      .Case("sse42", SSE42)
2341      .Case("sse41", SSE41)
2342      .Case("ssse3", SSSE3)
2343      .Case("sse3", SSE3)
2344      .Case("sse2", SSE2)
2345      .Case("sse", SSE1)
2346      .Default(NoSSE);
2347    SSELevel = std::max(SSELevel, Level);
2348
2349    MMX3DNowEnum ThreeDNowLevel =
2350      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2351        .Case("3dnowa", AMD3DNowAthlon)
2352        .Case("3dnow", AMD3DNow)
2353        .Case("mmx", MMX)
2354        .Default(NoMMX3DNow);
2355
2356    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2357  }
2358
2359  // Don't tell the backend if we're turning off mmx; it will end up disabling
2360  // SSE, which we don't want.
2361  std::vector<std::string>::iterator it;
2362  it = std::find(Features.begin(), Features.end(), "-mmx");
2363  if (it != Features.end())
2364    Features.erase(it);
2365}
2366
2367/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2368/// definitions for this particular subtarget.
2369void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2370                                     MacroBuilder &Builder) const {
2371  // Target identification.
2372  if (getTriple().getArch() == llvm::Triple::x86_64) {
2373    Builder.defineMacro("__amd64__");
2374    Builder.defineMacro("__amd64");
2375    Builder.defineMacro("__x86_64");
2376    Builder.defineMacro("__x86_64__");
2377  } else {
2378    DefineStd(Builder, "i386", Opts);
2379  }
2380
2381  // Subtarget options.
2382  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2383  // truly should be based on -mtune options.
2384  switch (CPU) {
2385  case CK_Generic:
2386    break;
2387  case CK_i386:
2388    // The rest are coming from the i386 define above.
2389    Builder.defineMacro("__tune_i386__");
2390    break;
2391  case CK_i486:
2392  case CK_WinChipC6:
2393  case CK_WinChip2:
2394  case CK_C3:
2395    defineCPUMacros(Builder, "i486");
2396    break;
2397  case CK_PentiumMMX:
2398    Builder.defineMacro("__pentium_mmx__");
2399    Builder.defineMacro("__tune_pentium_mmx__");
2400    // Fallthrough
2401  case CK_i586:
2402  case CK_Pentium:
2403    defineCPUMacros(Builder, "i586");
2404    defineCPUMacros(Builder, "pentium");
2405    break;
2406  case CK_Pentium3:
2407  case CK_Pentium3M:
2408  case CK_PentiumM:
2409    Builder.defineMacro("__tune_pentium3__");
2410    // Fallthrough
2411  case CK_Pentium2:
2412  case CK_C3_2:
2413    Builder.defineMacro("__tune_pentium2__");
2414    // Fallthrough
2415  case CK_PentiumPro:
2416    Builder.defineMacro("__tune_i686__");
2417    Builder.defineMacro("__tune_pentiumpro__");
2418    // Fallthrough
2419  case CK_i686:
2420    Builder.defineMacro("__i686");
2421    Builder.defineMacro("__i686__");
2422    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2423    Builder.defineMacro("__pentiumpro");
2424    Builder.defineMacro("__pentiumpro__");
2425    break;
2426  case CK_Pentium4:
2427  case CK_Pentium4M:
2428    defineCPUMacros(Builder, "pentium4");
2429    break;
2430  case CK_Yonah:
2431  case CK_Prescott:
2432  case CK_Nocona:
2433    defineCPUMacros(Builder, "nocona");
2434    break;
2435  case CK_Core2:
2436  case CK_Penryn:
2437    defineCPUMacros(Builder, "core2");
2438    break;
2439  case CK_Atom:
2440    defineCPUMacros(Builder, "atom");
2441    break;
2442  case CK_Corei7:
2443  case CK_Corei7AVX:
2444  case CK_CoreAVXi:
2445  case CK_CoreAVX2:
2446    defineCPUMacros(Builder, "corei7");
2447    break;
2448  case CK_K6_2:
2449    Builder.defineMacro("__k6_2__");
2450    Builder.defineMacro("__tune_k6_2__");
2451    // Fallthrough
2452  case CK_K6_3:
2453    if (CPU != CK_K6_2) {  // In case of fallthrough
2454      // FIXME: GCC may be enabling these in cases where some other k6
2455      // architecture is specified but -m3dnow is explicitly provided. The
2456      // exact semantics need to be determined and emulated here.
2457      Builder.defineMacro("__k6_3__");
2458      Builder.defineMacro("__tune_k6_3__");
2459    }
2460    // Fallthrough
2461  case CK_K6:
2462    defineCPUMacros(Builder, "k6");
2463    break;
2464  case CK_Athlon:
2465  case CK_AthlonThunderbird:
2466  case CK_Athlon4:
2467  case CK_AthlonXP:
2468  case CK_AthlonMP:
2469    defineCPUMacros(Builder, "athlon");
2470    if (SSELevel != NoSSE) {
2471      Builder.defineMacro("__athlon_sse__");
2472      Builder.defineMacro("__tune_athlon_sse__");
2473    }
2474    break;
2475  case CK_K8:
2476  case CK_K8SSE3:
2477  case CK_x86_64:
2478  case CK_Opteron:
2479  case CK_OpteronSSE3:
2480  case CK_Athlon64:
2481  case CK_Athlon64SSE3:
2482  case CK_AthlonFX:
2483    defineCPUMacros(Builder, "k8");
2484    break;
2485  case CK_AMDFAM10:
2486    defineCPUMacros(Builder, "amdfam10");
2487    break;
2488  case CK_BTVER1:
2489    defineCPUMacros(Builder, "btver1");
2490    break;
2491  case CK_BDVER1:
2492    defineCPUMacros(Builder, "bdver1");
2493    break;
2494  case CK_BDVER2:
2495    defineCPUMacros(Builder, "bdver2");
2496    break;
2497  case CK_Geode:
2498    defineCPUMacros(Builder, "geode");
2499    break;
2500  }
2501
2502  // Target properties.
2503  Builder.defineMacro("__LITTLE_ENDIAN__");
2504  Builder.defineMacro("__REGISTER_PREFIX__", "");
2505
2506  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2507  // functions in glibc header files that use FP Stack inline asm which the
2508  // backend can't deal with (PR879).
2509  Builder.defineMacro("__NO_MATH_INLINES");
2510
2511  if (HasAES)
2512    Builder.defineMacro("__AES__");
2513
2514  if (HasPCLMUL)
2515    Builder.defineMacro("__PCLMUL__");
2516
2517  if (HasLZCNT)
2518    Builder.defineMacro("__LZCNT__");
2519
2520  if (HasRDRND)
2521    Builder.defineMacro("__RDRND__");
2522
2523  if (HasBMI)
2524    Builder.defineMacro("__BMI__");
2525
2526  if (HasBMI2)
2527    Builder.defineMacro("__BMI2__");
2528
2529  if (HasPOPCNT)
2530    Builder.defineMacro("__POPCNT__");
2531
2532  if (HasRTM)
2533    Builder.defineMacro("__RTM__");
2534
2535  if (HasSSE4a)
2536    Builder.defineMacro("__SSE4A__");
2537
2538  if (HasFMA4)
2539    Builder.defineMacro("__FMA4__");
2540
2541  if (HasFMA)
2542    Builder.defineMacro("__FMA__");
2543
2544  if (HasXOP)
2545    Builder.defineMacro("__XOP__");
2546
2547  if (HasF16C)
2548    Builder.defineMacro("__F16C__");
2549
2550  // Each case falls through to the previous one here.
2551  switch (SSELevel) {
2552  case AVX2:
2553    Builder.defineMacro("__AVX2__");
2554  case AVX:
2555    Builder.defineMacro("__AVX__");
2556  case SSE42:
2557    Builder.defineMacro("__SSE4_2__");
2558  case SSE41:
2559    Builder.defineMacro("__SSE4_1__");
2560  case SSSE3:
2561    Builder.defineMacro("__SSSE3__");
2562  case SSE3:
2563    Builder.defineMacro("__SSE3__");
2564  case SSE2:
2565    Builder.defineMacro("__SSE2__");
2566    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2567  case SSE1:
2568    Builder.defineMacro("__SSE__");
2569    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2570  case NoSSE:
2571    break;
2572  }
2573
2574  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2575    switch (SSELevel) {
2576    case AVX2:
2577    case AVX:
2578    case SSE42:
2579    case SSE41:
2580    case SSSE3:
2581    case SSE3:
2582    case SSE2:
2583      Builder.defineMacro("_M_IX86_FP", Twine(2));
2584      break;
2585    case SSE1:
2586      Builder.defineMacro("_M_IX86_FP", Twine(1));
2587      break;
2588    default:
2589      Builder.defineMacro("_M_IX86_FP", Twine(0));
2590    }
2591  }
2592
2593  // Each case falls through to the previous one here.
2594  switch (MMX3DNowLevel) {
2595  case AMD3DNowAthlon:
2596    Builder.defineMacro("__3dNOW_A__");
2597  case AMD3DNow:
2598    Builder.defineMacro("__3dNOW__");
2599  case MMX:
2600    Builder.defineMacro("__MMX__");
2601  case NoMMX3DNow:
2602    break;
2603  }
2604}
2605
2606bool X86TargetInfo::hasFeature(StringRef Feature) const {
2607  return llvm::StringSwitch<bool>(Feature)
2608      .Case("aes", HasAES)
2609      .Case("avx", SSELevel >= AVX)
2610      .Case("avx2", SSELevel >= AVX2)
2611      .Case("bmi", HasBMI)
2612      .Case("bmi2", HasBMI2)
2613      .Case("fma", HasFMA)
2614      .Case("fma4", HasFMA4)
2615      .Case("lzcnt", HasLZCNT)
2616      .Case("rdrnd", HasRDRND)
2617      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2618      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2619      .Case("mmx", MMX3DNowLevel >= MMX)
2620      .Case("pclmul", HasPCLMUL)
2621      .Case("popcnt", HasPOPCNT)
2622      .Case("rtm", HasRTM)
2623      .Case("sse", SSELevel >= SSE1)
2624      .Case("sse2", SSELevel >= SSE2)
2625      .Case("sse3", SSELevel >= SSE3)
2626      .Case("ssse3", SSELevel >= SSSE3)
2627      .Case("sse41", SSELevel >= SSE41)
2628      .Case("sse42", SSELevel >= SSE42)
2629      .Case("sse4a", HasSSE4a)
2630      .Case("x86", true)
2631      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2632      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2633      .Case("xop", HasXOP)
2634      .Case("f16c", HasF16C)
2635      .Default(false);
2636}
2637
2638bool
2639X86TargetInfo::validateAsmConstraint(const char *&Name,
2640                                     TargetInfo::ConstraintInfo &Info) const {
2641  switch (*Name) {
2642  default: return false;
2643  case 'Y': // first letter of a pair:
2644    switch (*(Name+1)) {
2645    default: return false;
2646    case '0':  // First SSE register.
2647    case 't':  // Any SSE register, when SSE2 is enabled.
2648    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2649    case 'm':  // any MMX register, when inter-unit moves enabled.
2650      break;   // falls through to setAllowsRegister.
2651  }
2652  case 'a': // eax.
2653  case 'b': // ebx.
2654  case 'c': // ecx.
2655  case 'd': // edx.
2656  case 'S': // esi.
2657  case 'D': // edi.
2658  case 'A': // edx:eax.
2659  case 'f': // any x87 floating point stack register.
2660  case 't': // top of floating point stack.
2661  case 'u': // second from top of floating point stack.
2662  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2663  case 'y': // Any MMX register.
2664  case 'x': // Any SSE register.
2665  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2666  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2667  case 'l': // "Index" registers: any general register that can be used as an
2668            // index in a base+index memory access.
2669    Info.setAllowsRegister();
2670    return true;
2671  case 'C': // SSE floating point constant.
2672  case 'G': // x87 floating point constant.
2673  case 'e': // 32-bit signed integer constant for use with zero-extending
2674            // x86_64 instructions.
2675  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2676            // x86_64 instructions.
2677    return true;
2678  }
2679}
2680
2681
2682std::string
2683X86TargetInfo::convertConstraint(const char *&Constraint) const {
2684  switch (*Constraint) {
2685  case 'a': return std::string("{ax}");
2686  case 'b': return std::string("{bx}");
2687  case 'c': return std::string("{cx}");
2688  case 'd': return std::string("{dx}");
2689  case 'S': return std::string("{si}");
2690  case 'D': return std::string("{di}");
2691  case 'p': // address
2692    return std::string("im");
2693  case 't': // top of floating point stack.
2694    return std::string("{st}");
2695  case 'u': // second from top of floating point stack.
2696    return std::string("{st(1)}"); // second from top of floating point stack.
2697  default:
2698    return std::string(1, *Constraint);
2699  }
2700}
2701} // end anonymous namespace
2702
2703namespace {
2704// X86-32 generic target
2705class X86_32TargetInfo : public X86TargetInfo {
2706public:
2707  X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2708    DoubleAlign = LongLongAlign = 32;
2709    LongDoubleWidth = 96;
2710    LongDoubleAlign = 32;
2711    SuitableAlign = 128;
2712    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2713                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2714                        "a0:0:64-f80:32:32-n8:16:32-S128";
2715    SizeType = UnsignedInt;
2716    PtrDiffType = SignedInt;
2717    IntPtrType = SignedInt;
2718    RegParmMax = 3;
2719
2720    // Use fpret for all types.
2721    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2722                             (1 << TargetInfo::Double) |
2723                             (1 << TargetInfo::LongDouble));
2724
2725    // x86-32 has atomics up to 8 bytes
2726    // FIXME: Check that we actually have cmpxchg8b before setting
2727    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2728    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2729  }
2730  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2731    return TargetInfo::CharPtrBuiltinVaList;
2732  }
2733
2734  int getEHDataRegisterNumber(unsigned RegNo) const {
2735    if (RegNo == 0) return 0;
2736    if (RegNo == 1) return 2;
2737    return -1;
2738  }
2739  virtual bool validateInputSize(StringRef Constraint,
2740                                 unsigned Size) const {
2741    switch (Constraint[0]) {
2742    default: break;
2743    case 'a':
2744    case 'b':
2745    case 'c':
2746    case 'd':
2747      return Size <= 32;
2748    }
2749
2750    return true;
2751  }
2752};
2753} // end anonymous namespace
2754
2755namespace {
2756class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2757public:
2758  NetBSDI386TargetInfo(const std::string &triple) :
2759    NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2760  }
2761
2762  virtual unsigned getFloatEvalMethod() const {
2763    // NetBSD defaults to "double" rounding
2764    return 1;
2765  }
2766};
2767} // end anonymous namespace
2768
2769namespace {
2770class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2771public:
2772  OpenBSDI386TargetInfo(const std::string& triple) :
2773    OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2774    SizeType = UnsignedLong;
2775    IntPtrType = SignedLong;
2776    PtrDiffType = SignedLong;
2777  }
2778};
2779} // end anonymous namespace
2780
2781namespace {
2782class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2783public:
2784  BitrigI386TargetInfo(const std::string& triple) :
2785    BitrigTargetInfo<X86_32TargetInfo>(triple) {
2786    SizeType = UnsignedLong;
2787    IntPtrType = SignedLong;
2788    PtrDiffType = SignedLong;
2789  }
2790};
2791} // end anonymous namespace
2792
2793namespace {
2794class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2795public:
2796  DarwinI386TargetInfo(const std::string& triple) :
2797    DarwinTargetInfo<X86_32TargetInfo>(triple) {
2798    LongDoubleWidth = 128;
2799    LongDoubleAlign = 128;
2800    SuitableAlign = 128;
2801    MaxVectorAlign = 256;
2802    SizeType = UnsignedLong;
2803    IntPtrType = SignedLong;
2804    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2805                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2806                        "a0:0:64-f80:128:128-n8:16:32-S128";
2807    HasAlignMac68kSupport = true;
2808  }
2809
2810};
2811} // end anonymous namespace
2812
2813namespace {
2814// x86-32 Windows target
2815class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2816public:
2817  WindowsX86_32TargetInfo(const std::string& triple)
2818    : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2819    TLSSupported = false;
2820    WCharType = UnsignedShort;
2821    DoubleAlign = LongLongAlign = 64;
2822    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2823                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2824                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2825  }
2826  virtual void getTargetDefines(const LangOptions &Opts,
2827                                MacroBuilder &Builder) const {
2828    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2829  }
2830};
2831} // end anonymous namespace
2832
2833namespace {
2834
2835// x86-32 Windows Visual Studio target
2836class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2837public:
2838  VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2839    : WindowsX86_32TargetInfo(triple) {
2840    LongDoubleWidth = LongDoubleAlign = 64;
2841    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2842  }
2843  virtual void getTargetDefines(const LangOptions &Opts,
2844                                MacroBuilder &Builder) const {
2845    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2846    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2847    // The value of the following reflects processor type.
2848    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2849    // We lost the original triple, so we use the default.
2850    Builder.defineMacro("_M_IX86", "600");
2851  }
2852};
2853} // end anonymous namespace
2854
2855namespace {
2856// x86-32 MinGW target
2857class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
2858public:
2859  MinGWX86_32TargetInfo(const std::string& triple)
2860    : WindowsX86_32TargetInfo(triple) {
2861  }
2862  virtual void getTargetDefines(const LangOptions &Opts,
2863                                MacroBuilder &Builder) const {
2864    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2865    DefineStd(Builder, "WIN32", Opts);
2866    DefineStd(Builder, "WINNT", Opts);
2867    Builder.defineMacro("_X86_");
2868    Builder.defineMacro("__MSVCRT__");
2869    Builder.defineMacro("__MINGW32__");
2870
2871    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
2872    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
2873    if (Opts.MicrosoftExt)
2874      // Provide "as-is" __declspec.
2875      Builder.defineMacro("__declspec", "__declspec");
2876    else
2877      // Provide alias of __attribute__ like mingw32-gcc.
2878      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
2879  }
2880};
2881} // end anonymous namespace
2882
2883namespace {
2884// x86-32 Cygwin target
2885class CygwinX86_32TargetInfo : public X86_32TargetInfo {
2886public:
2887  CygwinX86_32TargetInfo(const std::string& triple)
2888    : X86_32TargetInfo(triple) {
2889    TLSSupported = false;
2890    WCharType = UnsignedShort;
2891    DoubleAlign = LongLongAlign = 64;
2892    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2893                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
2894                        "a0:0:64-f80:32:32-n8:16:32-S32";
2895  }
2896  virtual void getTargetDefines(const LangOptions &Opts,
2897                                MacroBuilder &Builder) const {
2898    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2899    Builder.defineMacro("_X86_");
2900    Builder.defineMacro("__CYGWIN__");
2901    Builder.defineMacro("__CYGWIN32__");
2902    DefineStd(Builder, "unix", Opts);
2903    if (Opts.CPlusPlus)
2904      Builder.defineMacro("_GNU_SOURCE");
2905  }
2906};
2907} // end anonymous namespace
2908
2909namespace {
2910// x86-32 Haiku target
2911class HaikuX86_32TargetInfo : public X86_32TargetInfo {
2912public:
2913  HaikuX86_32TargetInfo(const std::string& triple)
2914    : X86_32TargetInfo(triple) {
2915    SizeType = UnsignedLong;
2916    IntPtrType = SignedLong;
2917    PtrDiffType = SignedLong;
2918    ProcessIDType = SignedLong;
2919    this->UserLabelPrefix = "";
2920    this->TLSSupported = false;
2921  }
2922  virtual void getTargetDefines(const LangOptions &Opts,
2923                                MacroBuilder &Builder) const {
2924    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2925    Builder.defineMacro("__INTEL__");
2926    Builder.defineMacro("__HAIKU__");
2927  }
2928};
2929} // end anonymous namespace
2930
2931// RTEMS Target
2932template<typename Target>
2933class RTEMSTargetInfo : public OSTargetInfo<Target> {
2934protected:
2935  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
2936                            MacroBuilder &Builder) const {
2937    // RTEMS defines; list based off of gcc output
2938
2939    Builder.defineMacro("__rtems__");
2940    Builder.defineMacro("__ELF__");
2941  }
2942public:
2943  RTEMSTargetInfo(const std::string &triple)
2944    : OSTargetInfo<Target>(triple) {
2945      this->UserLabelPrefix = "";
2946
2947      llvm::Triple Triple(triple);
2948      switch (Triple.getArch()) {
2949        default:
2950        case llvm::Triple::x86:
2951          // this->MCountName = ".mcount";
2952          break;
2953        case llvm::Triple::mips:
2954        case llvm::Triple::mipsel:
2955        case llvm::Triple::ppc:
2956        case llvm::Triple::ppc64:
2957          // this->MCountName = "_mcount";
2958          break;
2959        case llvm::Triple::arm:
2960          // this->MCountName = "__mcount";
2961          break;
2962      }
2963
2964    }
2965};
2966
2967namespace {
2968// x86-32 RTEMS target
2969class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
2970public:
2971  RTEMSX86_32TargetInfo(const std::string& triple)
2972    : X86_32TargetInfo(triple) {
2973    SizeType = UnsignedLong;
2974    IntPtrType = SignedLong;
2975    PtrDiffType = SignedLong;
2976    this->UserLabelPrefix = "";
2977  }
2978  virtual void getTargetDefines(const LangOptions &Opts,
2979                                MacroBuilder &Builder) const {
2980    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2981    Builder.defineMacro("__INTEL__");
2982    Builder.defineMacro("__rtems__");
2983  }
2984};
2985} // end anonymous namespace
2986
2987namespace {
2988// x86-64 generic target
2989class X86_64TargetInfo : public X86TargetInfo {
2990public:
2991  X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
2992    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
2993    LongDoubleWidth = 128;
2994    LongDoubleAlign = 128;
2995    LargeArrayMinWidth = 128;
2996    LargeArrayAlign = 128;
2997    SuitableAlign = 128;
2998    IntMaxType = SignedLong;
2999    UIntMaxType = UnsignedLong;
3000    Int64Type = SignedLong;
3001    RegParmMax = 6;
3002
3003    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3004                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3005                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3006
3007    // Use fpret only for long double.
3008    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3009
3010    // Use fp2ret for _Complex long double.
3011    ComplexLongDoubleUsesFP2Ret = true;
3012
3013    // x86-64 has atomics up to 16 bytes.
3014    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3015    // on CPUs with cmpxchg16b
3016    MaxAtomicPromoteWidth = 128;
3017    MaxAtomicInlineWidth = 64;
3018  }
3019  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3020    return TargetInfo::X86_64ABIBuiltinVaList;
3021  }
3022
3023  int getEHDataRegisterNumber(unsigned RegNo) const {
3024    if (RegNo == 0) return 0;
3025    if (RegNo == 1) return 1;
3026    return -1;
3027  }
3028
3029  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3030    return (CC == CC_Default ||
3031            CC == CC_C ||
3032            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3033  }
3034
3035  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3036    return CC_C;
3037  }
3038
3039};
3040} // end anonymous namespace
3041
3042namespace {
3043// x86-64 Windows target
3044class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3045public:
3046  WindowsX86_64TargetInfo(const std::string& triple)
3047    : WindowsTargetInfo<X86_64TargetInfo>(triple) {
3048    TLSSupported = false;
3049    WCharType = UnsignedShort;
3050    LongWidth = LongAlign = 32;
3051    DoubleAlign = LongLongAlign = 64;
3052    IntMaxType = SignedLongLong;
3053    UIntMaxType = UnsignedLongLong;
3054    Int64Type = SignedLongLong;
3055    SizeType = UnsignedLongLong;
3056    PtrDiffType = SignedLongLong;
3057    IntPtrType = SignedLongLong;
3058    this->UserLabelPrefix = "";
3059  }
3060  virtual void getTargetDefines(const LangOptions &Opts,
3061                                MacroBuilder &Builder) const {
3062    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3063    Builder.defineMacro("_WIN64");
3064  }
3065  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3066    return TargetInfo::CharPtrBuiltinVaList;
3067  }
3068};
3069} // end anonymous namespace
3070
3071namespace {
3072// x86-64 Windows Visual Studio target
3073class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3074public:
3075  VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
3076    : WindowsX86_64TargetInfo(triple) {
3077    LongDoubleWidth = LongDoubleAlign = 64;
3078    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3079  }
3080  virtual void getTargetDefines(const LangOptions &Opts,
3081                                MacroBuilder &Builder) const {
3082    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3083    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3084    Builder.defineMacro("_M_X64");
3085    Builder.defineMacro("_M_AMD64");
3086  }
3087};
3088} // end anonymous namespace
3089
3090namespace {
3091// x86-64 MinGW target
3092class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3093public:
3094  MinGWX86_64TargetInfo(const std::string& triple)
3095    : WindowsX86_64TargetInfo(triple) {
3096  }
3097  virtual void getTargetDefines(const LangOptions &Opts,
3098                                MacroBuilder &Builder) const {
3099    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3100    DefineStd(Builder, "WIN64", Opts);
3101    Builder.defineMacro("__MSVCRT__");
3102    Builder.defineMacro("__MINGW32__");
3103    Builder.defineMacro("__MINGW64__");
3104
3105    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3106    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3107    if (Opts.MicrosoftExt)
3108      // Provide "as-is" __declspec.
3109      Builder.defineMacro("__declspec", "__declspec");
3110    else
3111      // Provide alias of __attribute__ like mingw32-gcc.
3112      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3113  }
3114};
3115} // end anonymous namespace
3116
3117namespace {
3118class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3119public:
3120  DarwinX86_64TargetInfo(const std::string& triple)
3121      : DarwinTargetInfo<X86_64TargetInfo>(triple) {
3122    Int64Type = SignedLongLong;
3123    MaxVectorAlign = 256;
3124  }
3125};
3126} // end anonymous namespace
3127
3128namespace {
3129class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3130public:
3131  OpenBSDX86_64TargetInfo(const std::string& triple)
3132      : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
3133    IntMaxType = SignedLongLong;
3134    UIntMaxType = UnsignedLongLong;
3135    Int64Type = SignedLongLong;
3136  }
3137};
3138} // end anonymous namespace
3139
3140namespace {
3141class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3142public:
3143  BitrigX86_64TargetInfo(const std::string& triple)
3144      : BitrigTargetInfo<X86_64TargetInfo>(triple) {
3145     IntMaxType = SignedLongLong;
3146     UIntMaxType = UnsignedLongLong;
3147     Int64Type = SignedLongLong;
3148  }
3149};
3150}
3151
3152namespace {
3153class AArch64TargetInfo : public TargetInfo {
3154  static const char * const GCCRegNames[];
3155  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3156public:
3157  AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) {
3158    BigEndian = false;
3159    LongWidth = LongAlign = 64;
3160    LongDoubleWidth = LongDoubleAlign = 128;
3161    PointerWidth = PointerAlign = 64;
3162    SuitableAlign = 128;
3163    DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3164                        "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3165                        "f128:128:128-n32:64-S128";
3166
3167    WCharType = UnsignedInt;
3168    LongDoubleFormat = &llvm::APFloat::IEEEquad;
3169
3170    // AArch64 backend supports 64-bit operations at the moment. In principle
3171    // 128-bit is possible if register-pairs are used.
3172    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3173
3174    TheCXXABI.set(TargetCXXABI::GenericAArch64);
3175  }
3176  virtual void getTargetDefines(const LangOptions &Opts,
3177                                MacroBuilder &Builder) const {
3178    // GCC defines theses currently
3179    Builder.defineMacro("__aarch64__");
3180    Builder.defineMacro("__AARCH64EL__");
3181
3182    // ACLE predefines. Many can only have one possible value on v8 AArch64.
3183
3184    // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3185    // which was intended to be compatible with a 64-bit implementation. They
3186    // will need updating when a real 64-bit ACLE exists. Particularly pressing
3187    // instances are: __AARCH_ISA_A32, __AARCH_ISA_T32, __ARCH_PCS.
3188    Builder.defineMacro("__AARCH_ACLE",    "101");
3189    Builder.defineMacro("__AARCH",         "8");
3190    Builder.defineMacro("__AARCH_PROFILE", "'A'");
3191
3192    Builder.defineMacro("__AARCH_FEATURE_UNALIGNED");
3193    Builder.defineMacro("__AARCH_FEATURE_CLZ");
3194    Builder.defineMacro("__AARCH_FEATURE_FMA");
3195
3196    // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3197    // 128-bit LDXP present, at which point this becomes 0x1f.
3198    Builder.defineMacro("__AARCH_FEATURE_LDREX", "0xf");
3199
3200    // 0xe implies support for half, single and double precision operations.
3201    Builder.defineMacro("__AARCH_FP", "0xe");
3202
3203    // PCS specifies this for SysV variants, which is all we support. Other ABIs
3204    // may choose __AARCH_FP16_FORMAT_ALTERNATIVE.
3205    Builder.defineMacro("__AARCH_FP16_FORMAT_IEEE");
3206
3207    if (Opts.FastMath || Opts.FiniteMathOnly)
3208      Builder.defineMacro("__AARCH_FP_FAST");
3209
3210    if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3211      Builder.defineMacro("__AARCH_FP_FENV_ROUNDING");
3212
3213    Builder.defineMacro("__AARCH_SIZEOF_WCHAR_T",
3214                        Opts.ShortWChar ? "2" : "4");
3215
3216    Builder.defineMacro("__AARCH_SIZEOF_MINIMAL_ENUM",
3217                        Opts.ShortEnums ? "1" : "4");
3218
3219    if (BigEndian)
3220      Builder.defineMacro("__AARCH_BIG_ENDIAN");
3221  }
3222  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3223                                 unsigned &NumRecords) const {
3224    Records = 0;
3225    NumRecords = 0;
3226  }
3227  virtual bool hasFeature(StringRef Feature) const {
3228    return Feature == "aarch64";
3229  }
3230  virtual void getGCCRegNames(const char * const *&Names,
3231                              unsigned &NumNames) const;
3232  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3233                                unsigned &NumAliases) const;
3234
3235  virtual bool isCLZForZeroUndef() const { return false; }
3236
3237  virtual bool validateAsmConstraint(const char *&Name,
3238                                     TargetInfo::ConstraintInfo &Info) const {
3239    switch (*Name) {
3240    default: return false;
3241    case 'w': // An FP/SIMD vector register
3242      Info.setAllowsRegister();
3243      return true;
3244    case 'I': // Constant that can be used with an ADD instruction
3245    case 'J': // Constant that can be used with a SUB instruction
3246    case 'K': // Constant that can be used with a 32-bit logical instruction
3247    case 'L': // Constant that can be used with a 64-bit logical instruction
3248    case 'M': // Constant that can be used as a 32-bit MOV immediate
3249    case 'N': // Constant that can be used as a 64-bit MOV immediate
3250    case 'Y': // Floating point constant zero
3251    case 'Z': // Integer constant zero
3252      return true;
3253    case 'Q': // A memory reference with base register and no offset
3254      Info.setAllowsMemory();
3255      return true;
3256    case 'S': // A symbolic address
3257      Info.setAllowsRegister();
3258      return true;
3259    case 'U':
3260      // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3261      // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3262      // Usa: An absolute symbolic address
3263      // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3264      llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3265    }
3266  }
3267
3268  virtual const char *getClobbers() const {
3269    // There are no AArch64 clobbers shared by all asm statements.
3270    return "";
3271  }
3272
3273  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3274    return TargetInfo::AArch64ABIBuiltinVaList;
3275  }
3276};
3277
3278const char * const AArch64TargetInfo::GCCRegNames[] = {
3279  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3280  "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3281  "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3282  "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3283
3284  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3285  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3286  "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3287  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3288
3289  "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3290  "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3291  "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3292  "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3293
3294  "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3295  "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3296  "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3297  "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3298
3299  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3300  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3301  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3302  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3303
3304  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3305  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3306  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3307  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3308
3309  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3310  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3311  "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3312  "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3313};
3314
3315void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3316                                       unsigned &NumNames) const {
3317  Names = GCCRegNames;
3318  NumNames = llvm::array_lengthof(GCCRegNames);
3319}
3320
3321const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3322  { { "x16" }, "ip0"},
3323  { { "x17" }, "ip1"},
3324  { { "x29" }, "fp" },
3325  { { "x30" }, "lr" }
3326};
3327
3328void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3329                                         unsigned &NumAliases) const {
3330  Aliases = GCCRegAliases;
3331  NumAliases = llvm::array_lengthof(GCCRegAliases);
3332
3333}
3334} // end anonymous namespace
3335
3336namespace {
3337class ARMTargetInfo : public TargetInfo {
3338  // Possible FPU choices.
3339  enum FPUMode {
3340    VFP2FPU = (1 << 0),
3341    VFP3FPU = (1 << 1),
3342    VFP4FPU = (1 << 2),
3343    NeonFPU = (1 << 3)
3344  };
3345
3346  static bool FPUModeIsVFP(FPUMode Mode) {
3347    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3348  }
3349
3350  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3351  static const char * const GCCRegNames[];
3352
3353  std::string ABI, CPU;
3354
3355  unsigned FPU : 4;
3356
3357  unsigned IsAAPCS : 1;
3358  unsigned IsThumb : 1;
3359
3360  // Initialized via features.
3361  unsigned SoftFloat : 1;
3362  unsigned SoftFloatABI : 1;
3363
3364  static const Builtin::Info BuiltinInfo[];
3365
3366public:
3367  ARMTargetInfo(const std::string &TripleStr)
3368    : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3369  {
3370    BigEndian = false;
3371    SizeType = UnsignedInt;
3372    PtrDiffType = SignedInt;
3373    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3374    WCharType = UnsignedInt;
3375
3376    // {} in inline assembly are neon specifiers, not assembly variant
3377    // specifiers.
3378    NoAsmVariants = true;
3379
3380    // FIXME: Should we just treat this as a feature?
3381    IsThumb = getTriple().getArchName().startswith("thumb");
3382    if (IsThumb) {
3383      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3384      // so set preferred for small types to 32.
3385      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3386                           "i64:64:64-f32:32:32-f64:64:64-"
3387                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3388    } else {
3389      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3390                           "i64:64:64-f32:32:32-f64:64:64-"
3391                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3392    }
3393
3394    // ARM targets default to using the ARM C++ ABI.
3395    TheCXXABI.set(TargetCXXABI::GenericARM);
3396
3397    // ARM has atomics up to 8 bytes
3398    // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e
3399    MaxAtomicPromoteWidth = 64;
3400
3401    // Do force alignment of members that follow zero length bitfields.  If
3402    // the alignment of the zero-length bitfield is greater than the member
3403    // that follows it, `bar', `bar' will be aligned as the  type of the
3404    // zero length bitfield.
3405    UseZeroLengthBitfieldAlignment = true;
3406  }
3407  virtual const char *getABI() const { return ABI.c_str(); }
3408  virtual bool setABI(const std::string &Name) {
3409    ABI = Name;
3410
3411    // The defaults (above) are for AAPCS, check if we need to change them.
3412    //
3413    // FIXME: We need support for -meabi... we could just mangle it into the
3414    // name.
3415    if (Name == "apcs-gnu") {
3416      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3417      // size_t is unsigned int on FreeBSD.
3418      if (getTriple().getOS() != llvm::Triple::FreeBSD)
3419        SizeType = UnsignedLong;
3420
3421      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3422      WCharType = SignedInt;
3423
3424      // Do not respect the alignment of bit-field types when laying out
3425      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3426      UseBitFieldTypeAlignment = false;
3427
3428      /// gcc forces the alignment to 4 bytes, regardless of the type of the
3429      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3430      /// gcc.
3431      ZeroLengthBitfieldBoundary = 32;
3432
3433      IsAAPCS = false;
3434
3435      if (IsThumb) {
3436        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3437        // so set preferred for small types to 32.
3438        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3439                             "i64:32:64-f32:32:32-f64:32:64-"
3440                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3441      } else {
3442        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3443                             "i64:32:64-f32:32:32-f64:32:64-"
3444                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3445      }
3446
3447      // FIXME: Override "preferred align" for double and long long.
3448    } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3449      IsAAPCS = true;
3450      // FIXME: Enumerated types are variable width in straight AAPCS.
3451    } else if (Name == "aapcs-linux") {
3452      IsAAPCS = true;
3453    } else
3454      return false;
3455
3456    return true;
3457  }
3458
3459  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3460    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3461      Features["vfp2"] = true;
3462    else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3463             CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3464      Features["neon"] = true;
3465    else if (CPU == "swift") {
3466      Features["vfp4"] = true;
3467      Features["neon"] = true;
3468    }
3469  }
3470
3471  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3472                                 StringRef Name,
3473                                 bool Enabled) const {
3474    if (Name == "soft-float" || Name == "soft-float-abi" ||
3475        Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3476        Name == "d16" || Name == "neonfp") {
3477      Features[Name] = Enabled;
3478    } else
3479      return false;
3480
3481    return true;
3482  }
3483
3484  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3485    FPU = 0;
3486    SoftFloat = SoftFloatABI = false;
3487    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3488      if (Features[i] == "+soft-float")
3489        SoftFloat = true;
3490      else if (Features[i] == "+soft-float-abi")
3491        SoftFloatABI = true;
3492      else if (Features[i] == "+vfp2")
3493        FPU |= VFP2FPU;
3494      else if (Features[i] == "+vfp3")
3495        FPU |= VFP3FPU;
3496      else if (Features[i] == "+vfp4")
3497        FPU |= VFP4FPU;
3498      else if (Features[i] == "+neon")
3499        FPU |= NeonFPU;
3500    }
3501
3502    // Remove front-end specific options which the backend handles differently.
3503    std::vector<std::string>::iterator it;
3504    it = std::find(Features.begin(), Features.end(), "+soft-float");
3505    if (it != Features.end())
3506      Features.erase(it);
3507    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3508    if (it != Features.end())
3509      Features.erase(it);
3510  }
3511
3512  virtual bool hasFeature(StringRef Feature) const {
3513    return llvm::StringSwitch<bool>(Feature)
3514        .Case("arm", true)
3515        .Case("softfloat", SoftFloat)
3516        .Case("thumb", IsThumb)
3517        .Case("neon", FPU == NeonFPU && !SoftFloat &&
3518              StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3519        .Default(false);
3520  }
3521  // FIXME: Should we actually have some table instead of these switches?
3522  static const char *getCPUDefineSuffix(StringRef Name) {
3523    return llvm::StringSwitch<const char*>(Name)
3524      .Cases("arm8", "arm810", "4")
3525      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3526      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3527      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3528      .Case("ep9312", "4T")
3529      .Cases("arm10tdmi", "arm1020t", "5T")
3530      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3531      .Case("arm926ej-s", "5TEJ")
3532      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3533      .Cases("xscale", "iwmmxt", "5TE")
3534      .Case("arm1136j-s", "6J")
3535      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3536      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3537      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3538      .Cases("cortex-a5", "cortex-a8", "cortex-a9", "cortex-a15", "7A")
3539      .Case("cortex-r5", "7R")
3540      .Case("cortex-a9-mp", "7F")
3541      .Case("swift", "7S")
3542      .Cases("cortex-m3", "cortex-m4", "7M")
3543      .Case("cortex-m0", "6M")
3544      .Default(0);
3545  }
3546  static const char *getCPUProfile(StringRef Name) {
3547    return llvm::StringSwitch<const char*>(Name)
3548      .Cases("cortex-a8", "cortex-a9", "A")
3549      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3550      .Case("cortex-r5", "R")
3551      .Default("");
3552  }
3553  virtual bool setCPU(const std::string &Name) {
3554    if (!getCPUDefineSuffix(Name))
3555      return false;
3556
3557    CPU = Name;
3558    return true;
3559  }
3560  virtual void getTargetDefines(const LangOptions &Opts,
3561                                MacroBuilder &Builder) const {
3562    // Target identification.
3563    Builder.defineMacro("__arm");
3564    Builder.defineMacro("__arm__");
3565
3566    // Target properties.
3567    Builder.defineMacro("__ARMEL__");
3568    Builder.defineMacro("__LITTLE_ENDIAN__");
3569    Builder.defineMacro("__REGISTER_PREFIX__", "");
3570
3571    StringRef CPUArch = getCPUDefineSuffix(CPU);
3572    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3573    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3574    StringRef CPUProfile = getCPUProfile(CPU);
3575    if (!CPUProfile.empty())
3576      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3577
3578    // Subtarget options.
3579
3580    // FIXME: It's more complicated than this and we don't really support
3581    // interworking.
3582    if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3583      Builder.defineMacro("__THUMB_INTERWORK__");
3584
3585    if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3586      // M-class CPUs on Darwin follow AAPCS, but not EABI.
3587      if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3588        Builder.defineMacro("__ARM_EABI__");
3589      Builder.defineMacro("__ARM_PCS", "1");
3590
3591      if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3592        Builder.defineMacro("__ARM_PCS_VFP", "1");
3593    }
3594
3595    if (SoftFloat)
3596      Builder.defineMacro("__SOFTFP__");
3597
3598    if (CPU == "xscale")
3599      Builder.defineMacro("__XSCALE__");
3600
3601    bool IsARMv7 = CPUArch.startswith("7");
3602    if (IsThumb) {
3603      Builder.defineMacro("__THUMBEL__");
3604      Builder.defineMacro("__thumb__");
3605      if (CPUArch == "6T2" || IsARMv7)
3606        Builder.defineMacro("__thumb2__");
3607    }
3608
3609    // Note, this is always on in gcc, even though it doesn't make sense.
3610    Builder.defineMacro("__APCS_32__");
3611
3612    if (FPUModeIsVFP((FPUMode) FPU)) {
3613      Builder.defineMacro("__VFP_FP__");
3614      if (FPU & VFP2FPU)
3615        Builder.defineMacro("__ARM_VFPV2__");
3616      if (FPU & VFP3FPU)
3617        Builder.defineMacro("__ARM_VFPV3__");
3618      if (FPU & VFP4FPU)
3619        Builder.defineMacro("__ARM_VFPV4__");
3620    }
3621
3622    // This only gets set when Neon instructions are actually available, unlike
3623    // the VFP define, hence the soft float and arch check. This is subtly
3624    // different from gcc, we follow the intent which was that it should be set
3625    // when Neon instructions are actually available.
3626    if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3627      Builder.defineMacro("__ARM_NEON__");
3628  }
3629  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3630                                 unsigned &NumRecords) const {
3631    Records = BuiltinInfo;
3632    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3633  }
3634  virtual bool isCLZForZeroUndef() const { return false; }
3635  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3636    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3637  }
3638  virtual void getGCCRegNames(const char * const *&Names,
3639                              unsigned &NumNames) const;
3640  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3641                                unsigned &NumAliases) const;
3642  virtual bool validateAsmConstraint(const char *&Name,
3643                                     TargetInfo::ConstraintInfo &Info) const {
3644    switch (*Name) {
3645    default: break;
3646    case 'l': // r0-r7
3647    case 'h': // r8-r15
3648    case 'w': // VFP Floating point register single precision
3649    case 'P': // VFP Floating point register double precision
3650      Info.setAllowsRegister();
3651      return true;
3652    case 'Q': // A memory address that is a single base register.
3653      Info.setAllowsMemory();
3654      return true;
3655    case 'U': // a memory reference...
3656      switch (Name[1]) {
3657      case 'q': // ...ARMV4 ldrsb
3658      case 'v': // ...VFP load/store (reg+constant offset)
3659      case 'y': // ...iWMMXt load/store
3660      case 't': // address valid for load/store opaque types wider
3661                // than 128-bits
3662      case 'n': // valid address for Neon doubleword vector load/store
3663      case 'm': // valid address for Neon element and structure load/store
3664      case 's': // valid address for non-offset loads/stores of quad-word
3665                // values in four ARM registers
3666        Info.setAllowsMemory();
3667        Name++;
3668        return true;
3669      }
3670    }
3671    return false;
3672  }
3673  virtual std::string convertConstraint(const char *&Constraint) const {
3674    std::string R;
3675    switch (*Constraint) {
3676    case 'U':   // Two-character constraint; add "^" hint for later parsing.
3677      R = std::string("^") + std::string(Constraint, 2);
3678      Constraint++;
3679      break;
3680    case 'p': // 'p' should be translated to 'r' by default.
3681      R = std::string("r");
3682      break;
3683    default:
3684      return std::string(1, *Constraint);
3685    }
3686    return R;
3687  }
3688  virtual bool validateConstraintModifier(StringRef Constraint,
3689                                          const char Modifier,
3690                                          unsigned Size) const {
3691    bool isOutput = (Constraint[0] == '=');
3692    bool isInOut = (Constraint[0] == '+');
3693
3694    // Strip off constraint modifiers.
3695    while (Constraint[0] == '=' ||
3696           Constraint[0] == '+' ||
3697           Constraint[0] == '&')
3698      Constraint = Constraint.substr(1);
3699
3700    switch (Constraint[0]) {
3701    default: break;
3702    case 'r': {
3703      switch (Modifier) {
3704      default:
3705        return isInOut || (isOutput && Size >= 32) ||
3706          (!isOutput && !isInOut && Size <= 32);
3707      case 'q':
3708        // A register of size 32 cannot fit a vector type.
3709        return false;
3710      }
3711    }
3712    }
3713
3714    return true;
3715  }
3716  virtual const char *getClobbers() const {
3717    // FIXME: Is this really right?
3718    return "";
3719  }
3720
3721  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3722    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3723  }
3724
3725  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3726    if (RegNo == 0) return 0;
3727    if (RegNo == 1) return 1;
3728    return -1;
3729  }
3730};
3731
3732const char * const ARMTargetInfo::GCCRegNames[] = {
3733  // Integer registers
3734  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3735  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3736
3737  // Float registers
3738  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3739  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3740  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3741  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3742
3743  // Double registers
3744  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3745  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3746  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3747  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3748
3749  // Quad registers
3750  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3751  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3752};
3753
3754void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3755                                   unsigned &NumNames) const {
3756  Names = GCCRegNames;
3757  NumNames = llvm::array_lengthof(GCCRegNames);
3758}
3759
3760const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3761  { { "a1" }, "r0" },
3762  { { "a2" }, "r1" },
3763  { { "a3" }, "r2" },
3764  { { "a4" }, "r3" },
3765  { { "v1" }, "r4" },
3766  { { "v2" }, "r5" },
3767  { { "v3" }, "r6" },
3768  { { "v4" }, "r7" },
3769  { { "v5" }, "r8" },
3770  { { "v6", "rfp" }, "r9" },
3771  { { "sl" }, "r10" },
3772  { { "fp" }, "r11" },
3773  { { "ip" }, "r12" },
3774  { { "r13" }, "sp" },
3775  { { "r14" }, "lr" },
3776  { { "r15" }, "pc" },
3777  // The S, D and Q registers overlap, but aren't really aliases; we
3778  // don't want to substitute one of these for a different-sized one.
3779};
3780
3781void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3782                                       unsigned &NumAliases) const {
3783  Aliases = GCCRegAliases;
3784  NumAliases = llvm::array_lengthof(GCCRegAliases);
3785}
3786
3787const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3788#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3789#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3790                                              ALL_LANGUAGES },
3791#include "clang/Basic/BuiltinsARM.def"
3792};
3793} // end anonymous namespace.
3794
3795namespace {
3796class DarwinARMTargetInfo :
3797  public DarwinTargetInfo<ARMTargetInfo> {
3798protected:
3799  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3800                            MacroBuilder &Builder) const {
3801    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3802  }
3803
3804public:
3805  DarwinARMTargetInfo(const std::string& triple)
3806    : DarwinTargetInfo<ARMTargetInfo>(triple) {
3807    HasAlignMac68kSupport = true;
3808    // iOS always has 64-bit atomic instructions.
3809    // FIXME: This should be based off of the target features in ARMTargetInfo.
3810    MaxAtomicInlineWidth = 64;
3811
3812    // Darwin on iOS uses a variant of the ARM C++ ABI.
3813    TheCXXABI.set(TargetCXXABI::iOS);
3814  }
3815};
3816} // end anonymous namespace.
3817
3818
3819namespace {
3820// Hexagon abstract base class
3821class HexagonTargetInfo : public TargetInfo {
3822  static const Builtin::Info BuiltinInfo[];
3823  static const char * const GCCRegNames[];
3824  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3825  std::string CPU;
3826public:
3827  HexagonTargetInfo(const std::string& triple) : TargetInfo(triple)  {
3828    BigEndian = false;
3829    DescriptionString = ("e-p:32:32:32-"
3830                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
3831                         "f64:64:64-f32:32:32-a0:0-n32");
3832
3833    // {} in inline assembly are packet specifiers, not assembly variant
3834    // specifiers.
3835    NoAsmVariants = true;
3836  }
3837
3838  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3839                                 unsigned &NumRecords) const {
3840    Records = BuiltinInfo;
3841    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
3842  }
3843
3844  virtual bool validateAsmConstraint(const char *&Name,
3845                                     TargetInfo::ConstraintInfo &Info) const {
3846    return true;
3847  }
3848
3849  virtual void getTargetDefines(const LangOptions &Opts,
3850                                MacroBuilder &Builder) const;
3851
3852  virtual bool hasFeature(StringRef Feature) const {
3853    return Feature == "hexagon";
3854  }
3855
3856  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3857    return TargetInfo::CharPtrBuiltinVaList;
3858  }
3859  virtual void getGCCRegNames(const char * const *&Names,
3860                              unsigned &NumNames) const;
3861  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3862                                unsigned &NumAliases) const;
3863  virtual const char *getClobbers() const {
3864    return "";
3865  }
3866
3867  static const char *getHexagonCPUSuffix(StringRef Name) {
3868    return llvm::StringSwitch<const char*>(Name)
3869      .Case("hexagonv2", "2")
3870      .Case("hexagonv3", "3")
3871      .Case("hexagonv4", "4")
3872      .Case("hexagonv5", "5")
3873      .Default(0);
3874  }
3875
3876  virtual bool setCPU(const std::string &Name) {
3877    if (!getHexagonCPUSuffix(Name))
3878      return false;
3879
3880    CPU = Name;
3881    return true;
3882  }
3883};
3884
3885void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
3886                                MacroBuilder &Builder) const {
3887  Builder.defineMacro("qdsp6");
3888  Builder.defineMacro("__qdsp6", "1");
3889  Builder.defineMacro("__qdsp6__", "1");
3890
3891  Builder.defineMacro("hexagon");
3892  Builder.defineMacro("__hexagon", "1");
3893  Builder.defineMacro("__hexagon__", "1");
3894
3895  if(CPU == "hexagonv1") {
3896    Builder.defineMacro("__HEXAGON_V1__");
3897    Builder.defineMacro("__HEXAGON_ARCH__", "1");
3898    if(Opts.HexagonQdsp6Compat) {
3899      Builder.defineMacro("__QDSP6_V1__");
3900      Builder.defineMacro("__QDSP6_ARCH__", "1");
3901    }
3902  }
3903  else if(CPU == "hexagonv2") {
3904    Builder.defineMacro("__HEXAGON_V2__");
3905    Builder.defineMacro("__HEXAGON_ARCH__", "2");
3906    if(Opts.HexagonQdsp6Compat) {
3907      Builder.defineMacro("__QDSP6_V2__");
3908      Builder.defineMacro("__QDSP6_ARCH__", "2");
3909    }
3910  }
3911  else if(CPU == "hexagonv3") {
3912    Builder.defineMacro("__HEXAGON_V3__");
3913    Builder.defineMacro("__HEXAGON_ARCH__", "3");
3914    if(Opts.HexagonQdsp6Compat) {
3915      Builder.defineMacro("__QDSP6_V3__");
3916      Builder.defineMacro("__QDSP6_ARCH__", "3");
3917    }
3918  }
3919  else if(CPU == "hexagonv4") {
3920    Builder.defineMacro("__HEXAGON_V4__");
3921    Builder.defineMacro("__HEXAGON_ARCH__", "4");
3922    if(Opts.HexagonQdsp6Compat) {
3923      Builder.defineMacro("__QDSP6_V4__");
3924      Builder.defineMacro("__QDSP6_ARCH__", "4");
3925    }
3926  }
3927  else if(CPU == "hexagonv5") {
3928    Builder.defineMacro("__HEXAGON_V5__");
3929    Builder.defineMacro("__HEXAGON_ARCH__", "5");
3930    if(Opts.HexagonQdsp6Compat) {
3931      Builder.defineMacro("__QDSP6_V5__");
3932      Builder.defineMacro("__QDSP6_ARCH__", "5");
3933    }
3934  }
3935}
3936
3937const char * const HexagonTargetInfo::GCCRegNames[] = {
3938  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3939  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3940  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3941  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
3942  "p0", "p1", "p2", "p3",
3943  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
3944};
3945
3946void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
3947                                   unsigned &NumNames) const {
3948  Names = GCCRegNames;
3949  NumNames = llvm::array_lengthof(GCCRegNames);
3950}
3951
3952
3953const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
3954  { { "sp" }, "r29" },
3955  { { "fp" }, "r30" },
3956  { { "lr" }, "r31" },
3957 };
3958
3959void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3960                                     unsigned &NumAliases) const {
3961  Aliases = GCCRegAliases;
3962  NumAliases = llvm::array_lengthof(GCCRegAliases);
3963}
3964
3965
3966const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
3967#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3968#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3969                                              ALL_LANGUAGES },
3970#include "clang/Basic/BuiltinsHexagon.def"
3971};
3972}
3973
3974
3975namespace {
3976class SparcV8TargetInfo : public TargetInfo {
3977  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3978  static const char * const GCCRegNames[];
3979  bool SoftFloat;
3980public:
3981  SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) {
3982    // FIXME: Support Sparc quad-precision long double?
3983    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3984                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32";
3985  }
3986  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3987                                 StringRef Name,
3988                                 bool Enabled) const {
3989    if (Name == "soft-float")
3990      Features[Name] = Enabled;
3991    else
3992      return false;
3993
3994    return true;
3995  }
3996  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3997    SoftFloat = false;
3998    for (unsigned i = 0, e = Features.size(); i != e; ++i)
3999      if (Features[i] == "+soft-float")
4000        SoftFloat = true;
4001  }
4002  virtual void getTargetDefines(const LangOptions &Opts,
4003                                MacroBuilder &Builder) const {
4004    DefineStd(Builder, "sparc", Opts);
4005    Builder.defineMacro("__sparcv8");
4006    Builder.defineMacro("__REGISTER_PREFIX__", "");
4007
4008    if (SoftFloat)
4009      Builder.defineMacro("SOFT_FLOAT", "1");
4010  }
4011
4012  virtual bool hasFeature(StringRef Feature) const {
4013    return llvm::StringSwitch<bool>(Feature)
4014             .Case("softfloat", SoftFloat)
4015             .Case("sparc", true)
4016             .Default(false);
4017  }
4018
4019  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4020                                 unsigned &NumRecords) const {
4021    // FIXME: Implement!
4022  }
4023  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4024    return TargetInfo::VoidPtrBuiltinVaList;
4025  }
4026  virtual void getGCCRegNames(const char * const *&Names,
4027                              unsigned &NumNames) const;
4028  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4029                                unsigned &NumAliases) const;
4030  virtual bool validateAsmConstraint(const char *&Name,
4031                                     TargetInfo::ConstraintInfo &info) const {
4032    // FIXME: Implement!
4033    return false;
4034  }
4035  virtual const char *getClobbers() const {
4036    // FIXME: Implement!
4037    return "";
4038  }
4039};
4040
4041const char * const SparcV8TargetInfo::GCCRegNames[] = {
4042  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4043  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4044  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4045  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4046};
4047
4048void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names,
4049                                       unsigned &NumNames) const {
4050  Names = GCCRegNames;
4051  NumNames = llvm::array_lengthof(GCCRegNames);
4052}
4053
4054const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = {
4055  { { "g0" }, "r0" },
4056  { { "g1" }, "r1" },
4057  { { "g2" }, "r2" },
4058  { { "g3" }, "r3" },
4059  { { "g4" }, "r4" },
4060  { { "g5" }, "r5" },
4061  { { "g6" }, "r6" },
4062  { { "g7" }, "r7" },
4063  { { "o0" }, "r8" },
4064  { { "o1" }, "r9" },
4065  { { "o2" }, "r10" },
4066  { { "o3" }, "r11" },
4067  { { "o4" }, "r12" },
4068  { { "o5" }, "r13" },
4069  { { "o6", "sp" }, "r14" },
4070  { { "o7" }, "r15" },
4071  { { "l0" }, "r16" },
4072  { { "l1" }, "r17" },
4073  { { "l2" }, "r18" },
4074  { { "l3" }, "r19" },
4075  { { "l4" }, "r20" },
4076  { { "l5" }, "r21" },
4077  { { "l6" }, "r22" },
4078  { { "l7" }, "r23" },
4079  { { "i0" }, "r24" },
4080  { { "i1" }, "r25" },
4081  { { "i2" }, "r26" },
4082  { { "i3" }, "r27" },
4083  { { "i4" }, "r28" },
4084  { { "i5" }, "r29" },
4085  { { "i6", "fp" }, "r30" },
4086  { { "i7" }, "r31" },
4087};
4088
4089void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4090                                         unsigned &NumAliases) const {
4091  Aliases = GCCRegAliases;
4092  NumAliases = llvm::array_lengthof(GCCRegAliases);
4093}
4094} // end anonymous namespace.
4095
4096namespace {
4097class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4098public:
4099  AuroraUXSparcV8TargetInfo(const std::string& triple) :
4100      AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
4101    SizeType = UnsignedInt;
4102    PtrDiffType = SignedInt;
4103  }
4104};
4105class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4106public:
4107  SolarisSparcV8TargetInfo(const std::string& triple) :
4108      SolarisTargetInfo<SparcV8TargetInfo>(triple) {
4109    SizeType = UnsignedInt;
4110    PtrDiffType = SignedInt;
4111  }
4112};
4113} // end anonymous namespace.
4114
4115namespace {
4116  class MSP430TargetInfo : public TargetInfo {
4117    static const char * const GCCRegNames[];
4118  public:
4119    MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
4120      BigEndian = false;
4121      TLSSupported = false;
4122      IntWidth = 16; IntAlign = 16;
4123      LongWidth = 32; LongLongWidth = 64;
4124      LongAlign = LongLongAlign = 16;
4125      PointerWidth = 16; PointerAlign = 16;
4126      SuitableAlign = 16;
4127      SizeType = UnsignedInt;
4128      IntMaxType = SignedLong;
4129      UIntMaxType = UnsignedLong;
4130      IntPtrType = SignedShort;
4131      PtrDiffType = SignedInt;
4132      SigAtomicType = SignedLong;
4133      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4134   }
4135    virtual void getTargetDefines(const LangOptions &Opts,
4136                                  MacroBuilder &Builder) const {
4137      Builder.defineMacro("MSP430");
4138      Builder.defineMacro("__MSP430__");
4139      // FIXME: defines for different 'flavours' of MCU
4140    }
4141    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4142                                   unsigned &NumRecords) const {
4143     // FIXME: Implement.
4144      Records = 0;
4145      NumRecords = 0;
4146    }
4147    virtual bool hasFeature(StringRef Feature) const {
4148      return Feature == "msp430";
4149    }
4150    virtual void getGCCRegNames(const char * const *&Names,
4151                                unsigned &NumNames) const;
4152    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4153                                  unsigned &NumAliases) const {
4154      // No aliases.
4155      Aliases = 0;
4156      NumAliases = 0;
4157    }
4158    virtual bool validateAsmConstraint(const char *&Name,
4159                                       TargetInfo::ConstraintInfo &info) const {
4160      // No target constraints for now.
4161      return false;
4162    }
4163    virtual const char *getClobbers() const {
4164      // FIXME: Is this really right?
4165      return "";
4166    }
4167    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4168      // FIXME: implement
4169      return TargetInfo::CharPtrBuiltinVaList;
4170   }
4171  };
4172
4173  const char * const MSP430TargetInfo::GCCRegNames[] = {
4174    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4175    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4176  };
4177
4178  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4179                                        unsigned &NumNames) const {
4180    Names = GCCRegNames;
4181    NumNames = llvm::array_lengthof(GCCRegNames);
4182  }
4183}
4184
4185namespace {
4186
4187  // LLVM and Clang cannot be used directly to output native binaries for
4188  // target, but is used to compile C code to llvm bitcode with correct
4189  // type and alignment information.
4190  //
4191  // TCE uses the llvm bitcode as input and uses it for generating customized
4192  // target processor and program binary. TCE co-design environment is
4193  // publicly available in http://tce.cs.tut.fi
4194
4195  static const unsigned TCEOpenCLAddrSpaceMap[] = {
4196      3, // opencl_global
4197      4, // opencl_local
4198      5, // opencl_constant
4199      0, // cuda_device
4200      0, // cuda_constant
4201      0  // cuda_shared
4202  };
4203
4204  class TCETargetInfo : public TargetInfo{
4205  public:
4206    TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
4207      TLSSupported = false;
4208      IntWidth = 32;
4209      LongWidth = LongLongWidth = 32;
4210      PointerWidth = 32;
4211      IntAlign = 32;
4212      LongAlign = LongLongAlign = 32;
4213      PointerAlign = 32;
4214      SuitableAlign = 32;
4215      SizeType = UnsignedInt;
4216      IntMaxType = SignedLong;
4217      UIntMaxType = UnsignedLong;
4218      IntPtrType = SignedInt;
4219      PtrDiffType = SignedInt;
4220      FloatWidth = 32;
4221      FloatAlign = 32;
4222      DoubleWidth = 32;
4223      DoubleAlign = 32;
4224      LongDoubleWidth = 32;
4225      LongDoubleAlign = 32;
4226      FloatFormat = &llvm::APFloat::IEEEsingle;
4227      DoubleFormat = &llvm::APFloat::IEEEsingle;
4228      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4229      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4230                          "i16:16:32-i32:32:32-i64:32:32-"
4231                          "f32:32:32-f64:32:32-v64:32:32-"
4232                          "v128:32:32-a0:0:32-n32";
4233      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4234    }
4235
4236    virtual void getTargetDefines(const LangOptions &Opts,
4237                                  MacroBuilder &Builder) const {
4238      DefineStd(Builder, "tce", Opts);
4239      Builder.defineMacro("__TCE__");
4240      Builder.defineMacro("__TCE_V1__");
4241    }
4242    virtual bool hasFeature(StringRef Feature) const {
4243      return Feature == "tce";
4244    }
4245
4246    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4247                                   unsigned &NumRecords) const {}
4248    virtual const char *getClobbers() const {
4249      return "";
4250    }
4251    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4252      return TargetInfo::VoidPtrBuiltinVaList;
4253    }
4254    virtual void getGCCRegNames(const char * const *&Names,
4255                                unsigned &NumNames) const {}
4256    virtual bool validateAsmConstraint(const char *&Name,
4257                                       TargetInfo::ConstraintInfo &info) const {
4258      return true;
4259    }
4260    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4261                                  unsigned &NumAliases) const {}
4262  };
4263}
4264
4265namespace {
4266class MipsTargetInfoBase : public TargetInfo {
4267  static const Builtin::Info BuiltinInfo[];
4268  std::string CPU;
4269  bool IsMips16;
4270  enum MipsFloatABI {
4271    HardFloat, SingleFloat, SoftFloat
4272  } FloatABI;
4273  enum DspRevEnum {
4274    NoDSP, DSP1, DSP2
4275  } DspRev;
4276
4277protected:
4278  std::string ABI;
4279
4280public:
4281  MipsTargetInfoBase(const std::string& triple,
4282                     const std::string& ABIStr,
4283                     const std::string& CPUStr)
4284    : TargetInfo(triple),
4285      CPU(CPUStr),
4286      IsMips16(false),
4287      FloatABI(HardFloat),
4288      DspRev(NoDSP),
4289      ABI(ABIStr)
4290  {}
4291
4292  virtual const char *getABI() const { return ABI.c_str(); }
4293  virtual bool setABI(const std::string &Name) = 0;
4294  virtual bool setCPU(const std::string &Name) {
4295    CPU = Name;
4296    return true;
4297  }
4298  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4299    Features[ABI] = true;
4300    Features[CPU] = true;
4301  }
4302
4303  virtual void getTargetDefines(const LangOptions &Opts,
4304                                MacroBuilder &Builder) const {
4305    DefineStd(Builder, "mips", Opts);
4306    Builder.defineMacro("_mips");
4307    Builder.defineMacro("__REGISTER_PREFIX__", "");
4308
4309    switch (FloatABI) {
4310    case HardFloat:
4311      Builder.defineMacro("__mips_hard_float", Twine(1));
4312      break;
4313    case SingleFloat:
4314      Builder.defineMacro("__mips_hard_float", Twine(1));
4315      Builder.defineMacro("__mips_single_float", Twine(1));
4316      break;
4317    case SoftFloat:
4318      Builder.defineMacro("__mips_soft_float", Twine(1));
4319      break;
4320    }
4321
4322    if (IsMips16)
4323      Builder.defineMacro("__mips16", Twine(1));
4324
4325    switch (DspRev) {
4326    default:
4327      break;
4328    case DSP1:
4329      Builder.defineMacro("__mips_dsp_rev", Twine(1));
4330      Builder.defineMacro("__mips_dsp", Twine(1));
4331      break;
4332    case DSP2:
4333      Builder.defineMacro("__mips_dsp_rev", Twine(2));
4334      Builder.defineMacro("__mips_dspr2", Twine(1));
4335      Builder.defineMacro("__mips_dsp", Twine(1));
4336      break;
4337    }
4338
4339    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4340    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4341    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4342
4343    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4344    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4345  }
4346
4347  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4348                                 unsigned &NumRecords) const {
4349    Records = BuiltinInfo;
4350    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4351  }
4352  virtual bool hasFeature(StringRef Feature) const {
4353    return Feature == "mips";
4354  }
4355  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4356    return TargetInfo::VoidPtrBuiltinVaList;
4357  }
4358  virtual void getGCCRegNames(const char * const *&Names,
4359                              unsigned &NumNames) const {
4360    static const char * const GCCRegNames[] = {
4361      // CPU register names
4362      // Must match second column of GCCRegAliases
4363      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4364      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4365      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4366      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4367      // Floating point register names
4368      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4369      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4370      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4371      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4372      // Hi/lo and condition register names
4373      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4374      "$fcc5","$fcc6","$fcc7"
4375    };
4376    Names = GCCRegNames;
4377    NumNames = llvm::array_lengthof(GCCRegNames);
4378  }
4379  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4380                                unsigned &NumAliases) const = 0;
4381  virtual bool validateAsmConstraint(const char *&Name,
4382                                     TargetInfo::ConstraintInfo &Info) const {
4383    switch (*Name) {
4384    default:
4385      return false;
4386
4387    case 'r': // CPU registers.
4388    case 'd': // Equivalent to "r" unless generating MIPS16 code.
4389    case 'y': // Equivalent to "r", backwards compatibility only.
4390    case 'f': // floating-point registers.
4391    case 'c': // $25 for indirect jumps
4392    case 'l': // lo register
4393    case 'x': // hilo register pair
4394      Info.setAllowsRegister();
4395      return true;
4396    }
4397  }
4398
4399  virtual const char *getClobbers() const {
4400    // FIXME: Implement!
4401    return "";
4402  }
4403
4404  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4405                                 StringRef Name,
4406                                 bool Enabled) const {
4407    if (Name == "soft-float" || Name == "single-float" ||
4408        Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4409        Name == "mips32" || Name == "mips32r2" ||
4410        Name == "mips64" || Name == "mips64r2" ||
4411        Name == "mips16" || Name == "dsp" || Name == "dspr2") {
4412      Features[Name] = Enabled;
4413      return true;
4414    } else if (Name == "32") {
4415      Features["o32"] = Enabled;
4416      return true;
4417    } else if (Name == "64") {
4418      Features["n64"] = Enabled;
4419      return true;
4420    }
4421    return false;
4422  }
4423
4424  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4425    IsMips16 = false;
4426    FloatABI = HardFloat;
4427    DspRev = NoDSP;
4428
4429    for (std::vector<std::string>::iterator it = Features.begin(),
4430         ie = Features.end(); it != ie; ++it) {
4431      if (*it == "+single-float")
4432        FloatABI = SingleFloat;
4433      else if (*it == "+soft-float")
4434        FloatABI = SoftFloat;
4435      else if (*it == "+mips16")
4436        IsMips16 = true;
4437      else if (*it == "+dsp")
4438        DspRev = std::max(DspRev, DSP1);
4439      else if (*it == "+dspr2")
4440        DspRev = std::max(DspRev, DSP2);
4441    }
4442
4443    // Remove front-end specific option.
4444    std::vector<std::string>::iterator it =
4445      std::find(Features.begin(), Features.end(), "+soft-float");
4446    if (it != Features.end())
4447      Features.erase(it);
4448  }
4449
4450  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4451    if (RegNo == 0) return 4;
4452    if (RegNo == 1) return 5;
4453    return -1;
4454  }
4455};
4456
4457const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4458#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4459#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4460                                              ALL_LANGUAGES },
4461#include "clang/Basic/BuiltinsMips.def"
4462};
4463
4464class Mips32TargetInfoBase : public MipsTargetInfoBase {
4465public:
4466  Mips32TargetInfoBase(const std::string& triple) :
4467    MipsTargetInfoBase(triple, "o32", "mips32") {
4468    SizeType = UnsignedInt;
4469    PtrDiffType = SignedInt;
4470    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4471  }
4472  virtual bool setABI(const std::string &Name) {
4473    if ((Name == "o32") || (Name == "eabi")) {
4474      ABI = Name;
4475      return true;
4476    } else if (Name == "32") {
4477      ABI = "o32";
4478      return true;
4479    } else
4480      return false;
4481  }
4482  virtual void getTargetDefines(const LangOptions &Opts,
4483                                MacroBuilder &Builder) const {
4484    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4485
4486    if (ABI == "o32") {
4487      Builder.defineMacro("__mips_o32");
4488      Builder.defineMacro("_ABIO32", "1");
4489      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4490    }
4491    else if (ABI == "eabi")
4492      Builder.defineMacro("__mips_eabi");
4493    else
4494      llvm_unreachable("Invalid ABI for Mips32.");
4495  }
4496  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4497                                unsigned &NumAliases) const {
4498    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4499      { { "at" },  "$1" },
4500      { { "v0" },  "$2" },
4501      { { "v1" },  "$3" },
4502      { { "a0" },  "$4" },
4503      { { "a1" },  "$5" },
4504      { { "a2" },  "$6" },
4505      { { "a3" },  "$7" },
4506      { { "t0" },  "$8" },
4507      { { "t1" },  "$9" },
4508      { { "t2" }, "$10" },
4509      { { "t3" }, "$11" },
4510      { { "t4" }, "$12" },
4511      { { "t5" }, "$13" },
4512      { { "t6" }, "$14" },
4513      { { "t7" }, "$15" },
4514      { { "s0" }, "$16" },
4515      { { "s1" }, "$17" },
4516      { { "s2" }, "$18" },
4517      { { "s3" }, "$19" },
4518      { { "s4" }, "$20" },
4519      { { "s5" }, "$21" },
4520      { { "s6" }, "$22" },
4521      { { "s7" }, "$23" },
4522      { { "t8" }, "$24" },
4523      { { "t9" }, "$25" },
4524      { { "k0" }, "$26" },
4525      { { "k1" }, "$27" },
4526      { { "gp" }, "$28" },
4527      { { "sp","$sp" }, "$29" },
4528      { { "fp","$fp" }, "$30" },
4529      { { "ra" }, "$31" }
4530    };
4531    Aliases = GCCRegAliases;
4532    NumAliases = llvm::array_lengthof(GCCRegAliases);
4533  }
4534};
4535
4536class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4537public:
4538  Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4539    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4540                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4541  }
4542  virtual void getTargetDefines(const LangOptions &Opts,
4543                                MacroBuilder &Builder) const {
4544    DefineStd(Builder, "MIPSEB", Opts);
4545    Builder.defineMacro("_MIPSEB");
4546    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4547  }
4548};
4549
4550class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4551public:
4552  Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4553    BigEndian = false;
4554    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4555                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4556  }
4557  virtual void getTargetDefines(const LangOptions &Opts,
4558                                MacroBuilder &Builder) const {
4559    DefineStd(Builder, "MIPSEL", Opts);
4560    Builder.defineMacro("_MIPSEL");
4561    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4562  }
4563};
4564
4565class Mips64TargetInfoBase : public MipsTargetInfoBase {
4566  virtual void SetDescriptionString(const std::string &Name) = 0;
4567public:
4568  Mips64TargetInfoBase(const std::string& triple) :
4569    MipsTargetInfoBase(triple, "n64", "mips64") {
4570    LongWidth = LongAlign = 64;
4571    PointerWidth = PointerAlign = 64;
4572    LongDoubleWidth = LongDoubleAlign = 128;
4573    LongDoubleFormat = &llvm::APFloat::IEEEquad;
4574    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4575      LongDoubleWidth = LongDoubleAlign = 64;
4576      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4577    }
4578    SuitableAlign = 128;
4579    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4580  }
4581  virtual bool setABI(const std::string &Name) {
4582    SetDescriptionString(Name);
4583    if (Name == "n32") {
4584      LongWidth = LongAlign = 32;
4585      PointerWidth = PointerAlign = 32;
4586      ABI = Name;
4587      return true;
4588    } else if (Name == "n64") {
4589      ABI = Name;
4590      return true;
4591    } else if (Name == "64") {
4592      ABI = "n64";
4593      return true;
4594    } else
4595      return false;
4596  }
4597  virtual void getTargetDefines(const LangOptions &Opts,
4598                                MacroBuilder &Builder) const {
4599    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4600
4601    Builder.defineMacro("__mips64");
4602    Builder.defineMacro("__mips64__");
4603
4604    if (ABI == "n32") {
4605      Builder.defineMacro("__mips_n32");
4606      Builder.defineMacro("_ABIN32", "2");
4607      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4608    }
4609    else if (ABI == "n64") {
4610      Builder.defineMacro("__mips_n64");
4611      Builder.defineMacro("_ABI64", "3");
4612      Builder.defineMacro("_MIPS_SIM", "_ABI64");
4613    }
4614    else
4615      llvm_unreachable("Invalid ABI for Mips64.");
4616  }
4617  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4618                                unsigned &NumAliases) const {
4619    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4620      { { "at" },  "$1" },
4621      { { "v0" },  "$2" },
4622      { { "v1" },  "$3" },
4623      { { "a0" },  "$4" },
4624      { { "a1" },  "$5" },
4625      { { "a2" },  "$6" },
4626      { { "a3" },  "$7" },
4627      { { "a4" },  "$8" },
4628      { { "a5" },  "$9" },
4629      { { "a6" }, "$10" },
4630      { { "a7" }, "$11" },
4631      { { "t0" }, "$12" },
4632      { { "t1" }, "$13" },
4633      { { "t2" }, "$14" },
4634      { { "t3" }, "$15" },
4635      { { "s0" }, "$16" },
4636      { { "s1" }, "$17" },
4637      { { "s2" }, "$18" },
4638      { { "s3" }, "$19" },
4639      { { "s4" }, "$20" },
4640      { { "s5" }, "$21" },
4641      { { "s6" }, "$22" },
4642      { { "s7" }, "$23" },
4643      { { "t8" }, "$24" },
4644      { { "t9" }, "$25" },
4645      { { "k0" }, "$26" },
4646      { { "k1" }, "$27" },
4647      { { "gp" }, "$28" },
4648      { { "sp","$sp" }, "$29" },
4649      { { "fp","$fp" }, "$30" },
4650      { { "ra" }, "$31" }
4651    };
4652    Aliases = GCCRegAliases;
4653    NumAliases = llvm::array_lengthof(GCCRegAliases);
4654  }
4655};
4656
4657class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4658  virtual void SetDescriptionString(const std::string &Name) {
4659    // Change DescriptionString only if ABI is n32.
4660    if (Name == "n32")
4661      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4662                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4663                          "v64:64:64-n32:64-S128";
4664  }
4665public:
4666  Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4667    // Default ABI is n64.
4668    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4669                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4670                        "v64:64:64-n32:64-S128";
4671  }
4672  virtual void getTargetDefines(const LangOptions &Opts,
4673                                MacroBuilder &Builder) const {
4674    DefineStd(Builder, "MIPSEB", Opts);
4675    Builder.defineMacro("_MIPSEB");
4676    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4677  }
4678};
4679
4680class Mips64ELTargetInfo : public Mips64TargetInfoBase {
4681  virtual void SetDescriptionString(const std::string &Name) {
4682    // Change DescriptionString only if ABI is n32.
4683    if (Name == "n32")
4684      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4685                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
4686                          "-v64:64:64-n32:64-S128";
4687  }
4688public:
4689  Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4690    // Default ABI is n64.
4691    BigEndian = false;
4692    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4693                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4694                        "v64:64:64-n32:64-S128";
4695  }
4696  virtual void getTargetDefines(const LangOptions &Opts,
4697                                MacroBuilder &Builder) const {
4698    DefineStd(Builder, "MIPSEL", Opts);
4699    Builder.defineMacro("_MIPSEL");
4700    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4701  }
4702};
4703} // end anonymous namespace.
4704
4705namespace {
4706class PNaClTargetInfo : public TargetInfo {
4707public:
4708  PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
4709    BigEndian = false;
4710    this->UserLabelPrefix = "";
4711    this->LongAlign = 32;
4712    this->LongWidth = 32;
4713    this->PointerAlign = 32;
4714    this->PointerWidth = 32;
4715    this->IntMaxType = TargetInfo::SignedLongLong;
4716    this->UIntMaxType = TargetInfo::UnsignedLongLong;
4717    this->Int64Type = TargetInfo::SignedLongLong;
4718    this->DoubleAlign = 64;
4719    this->LongDoubleWidth = 64;
4720    this->LongDoubleAlign = 64;
4721    this->SizeType = TargetInfo::UnsignedInt;
4722    this->PtrDiffType = TargetInfo::SignedInt;
4723    this->IntPtrType = TargetInfo::SignedInt;
4724    this->RegParmMax = 2;
4725    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4726                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
4727  }
4728
4729  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4730  }
4731  virtual void getArchDefines(const LangOptions &Opts,
4732                              MacroBuilder &Builder) const {
4733    Builder.defineMacro("__le32__");
4734    Builder.defineMacro("__pnacl__");
4735  }
4736  virtual void getTargetDefines(const LangOptions &Opts,
4737                                MacroBuilder &Builder) const {
4738    Builder.defineMacro("__LITTLE_ENDIAN__");
4739    getArchDefines(Opts, Builder);
4740  }
4741  virtual bool hasFeature(StringRef Feature) const {
4742    return Feature == "pnacl";
4743  }
4744  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4745                                 unsigned &NumRecords) const {
4746  }
4747  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4748    return TargetInfo::PNaClABIBuiltinVaList;
4749  }
4750  virtual void getGCCRegNames(const char * const *&Names,
4751                              unsigned &NumNames) const;
4752  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4753                                unsigned &NumAliases) const;
4754  virtual bool validateAsmConstraint(const char *&Name,
4755                                     TargetInfo::ConstraintInfo &Info) const {
4756    return false;
4757  }
4758
4759  virtual const char *getClobbers() const {
4760    return "";
4761  }
4762};
4763
4764void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
4765                                     unsigned &NumNames) const {
4766  Names = NULL;
4767  NumNames = 0;
4768}
4769
4770void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4771                                       unsigned &NumAliases) const {
4772  Aliases = NULL;
4773  NumAliases = 0;
4774}
4775} // end anonymous namespace.
4776
4777namespace {
4778  static const unsigned SPIRAddrSpaceMap[] = {
4779    1,    // opencl_global
4780    3,    // opencl_local
4781    2,    // opencl_constant
4782    0,    // cuda_device
4783    0,    // cuda_constant
4784    0     // cuda_shared
4785  };
4786  class SPIRTargetInfo : public TargetInfo {
4787    static const char * const GCCRegNames[];
4788    static const Builtin::Info BuiltinInfo[];
4789    std::vector<StringRef> AvailableFeatures;
4790  public:
4791    SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) {
4792      assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
4793        "SPIR target must use unknown OS");
4794      assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
4795        "SPIR target must use unknown environment type");
4796      BigEndian = false;
4797      TLSSupported = false;
4798      LongWidth = LongAlign = 64;
4799      AddrSpaceMap = &SPIRAddrSpaceMap;
4800      // Define available target features
4801      // These must be defined in sorted order!
4802      NoAsmVariants = true;
4803    }
4804    virtual void getTargetDefines(const LangOptions &Opts,
4805                                  MacroBuilder &Builder) const {
4806      DefineStd(Builder, "SPIR", Opts);
4807    }
4808    virtual bool hasFeature(StringRef Feature) const {
4809      return Feature == "spir";
4810    }
4811
4812    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4813                                   unsigned &NumRecords) const {}
4814    virtual const char *getClobbers() const {
4815      return "";
4816    }
4817    virtual void getGCCRegNames(const char * const *&Names,
4818                                unsigned &NumNames) const {}
4819    virtual bool validateAsmConstraint(const char *&Name,
4820                                       TargetInfo::ConstraintInfo &info) const {
4821      return true;
4822    }
4823    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4824                                  unsigned &NumAliases) const {}
4825    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4826      return TargetInfo::VoidPtrBuiltinVaList;
4827    }
4828  };
4829
4830
4831  class SPIR32TargetInfo : public SPIRTargetInfo {
4832  public:
4833    SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
4834      PointerWidth = PointerAlign = 32;
4835      SizeType     = TargetInfo::UnsignedInt;
4836      PtrDiffType = IntPtrType = TargetInfo::SignedInt;
4837      DescriptionString
4838        = "p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4839          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
4840          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
4841          "v512:512:512-v1024:1024:1024";
4842  }
4843  };
4844
4845  class SPIR64TargetInfo : public SPIRTargetInfo {
4846  public:
4847    SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
4848      PointerWidth = PointerAlign = 64;
4849      SizeType     = TargetInfo::UnsignedLong;
4850      PtrDiffType = IntPtrType = TargetInfo::SignedLong;
4851      DescriptionString
4852        = "p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4853          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
4854          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
4855          "v512:512:512-v1024:1024:1024";
4856  }
4857  };
4858}
4859
4860
4861//===----------------------------------------------------------------------===//
4862// Driver code
4863//===----------------------------------------------------------------------===//
4864
4865static TargetInfo *AllocateTarget(const std::string &T) {
4866  llvm::Triple Triple(T);
4867  llvm::Triple::OSType os = Triple.getOS();
4868
4869  switch (Triple.getArch()) {
4870  default:
4871    return NULL;
4872
4873  case llvm::Triple::hexagon:
4874    return new HexagonTargetInfo(T);
4875
4876  case llvm::Triple::aarch64:
4877    switch (os) {
4878    case llvm::Triple::Linux:
4879      return new LinuxTargetInfo<AArch64TargetInfo>(T);
4880    default:
4881      return new AArch64TargetInfo(T);
4882    }
4883
4884  case llvm::Triple::arm:
4885  case llvm::Triple::thumb:
4886    if (Triple.isOSDarwin())
4887      return new DarwinARMTargetInfo(T);
4888
4889    switch (os) {
4890    case llvm::Triple::Linux:
4891      return new LinuxTargetInfo<ARMTargetInfo>(T);
4892    case llvm::Triple::FreeBSD:
4893      return new FreeBSDTargetInfo<ARMTargetInfo>(T);
4894    case llvm::Triple::NetBSD:
4895      return new NetBSDTargetInfo<ARMTargetInfo>(T);
4896    case llvm::Triple::OpenBSD:
4897      return new OpenBSDTargetInfo<ARMTargetInfo>(T);
4898    case llvm::Triple::Bitrig:
4899      return new BitrigTargetInfo<ARMTargetInfo>(T);
4900    case llvm::Triple::RTEMS:
4901      return new RTEMSTargetInfo<ARMTargetInfo>(T);
4902    case llvm::Triple::NaCl:
4903      return new NaClTargetInfo<ARMTargetInfo>(T);
4904    default:
4905      return new ARMTargetInfo(T);
4906    }
4907
4908  case llvm::Triple::msp430:
4909    return new MSP430TargetInfo(T);
4910
4911  case llvm::Triple::mips:
4912    switch (os) {
4913    case llvm::Triple::Linux:
4914      return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
4915    case llvm::Triple::RTEMS:
4916      return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
4917    case llvm::Triple::FreeBSD:
4918      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
4919    case llvm::Triple::NetBSD:
4920      return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
4921    default:
4922      return new Mips32EBTargetInfo(T);
4923    }
4924
4925  case llvm::Triple::mipsel:
4926    switch (os) {
4927    case llvm::Triple::Linux:
4928      return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
4929    case llvm::Triple::RTEMS:
4930      return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
4931    case llvm::Triple::FreeBSD:
4932      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
4933    case llvm::Triple::NetBSD:
4934      return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
4935    default:
4936      return new Mips32ELTargetInfo(T);
4937    }
4938
4939  case llvm::Triple::mips64:
4940    switch (os) {
4941    case llvm::Triple::Linux:
4942      return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
4943    case llvm::Triple::RTEMS:
4944      return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
4945    case llvm::Triple::FreeBSD:
4946      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
4947    case llvm::Triple::NetBSD:
4948      return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
4949    case llvm::Triple::OpenBSD:
4950      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
4951    default:
4952      return new Mips64EBTargetInfo(T);
4953    }
4954
4955  case llvm::Triple::mips64el:
4956    switch (os) {
4957    case llvm::Triple::Linux:
4958      return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
4959    case llvm::Triple::RTEMS:
4960      return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
4961    case llvm::Triple::FreeBSD:
4962      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
4963    case llvm::Triple::NetBSD:
4964      return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
4965    case llvm::Triple::OpenBSD:
4966      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
4967    default:
4968      return new Mips64ELTargetInfo(T);
4969    }
4970
4971  case llvm::Triple::le32:
4972    switch (os) {
4973      case llvm::Triple::NaCl:
4974        return new NaClTargetInfo<PNaClTargetInfo>(T);
4975      default:
4976        return NULL;
4977    }
4978
4979  case llvm::Triple::ppc:
4980    if (Triple.isOSDarwin())
4981      return new DarwinPPC32TargetInfo(T);
4982    switch (os) {
4983    case llvm::Triple::Linux:
4984      return new LinuxTargetInfo<PPC32TargetInfo>(T);
4985    case llvm::Triple::FreeBSD:
4986      return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
4987    case llvm::Triple::NetBSD:
4988      return new NetBSDTargetInfo<PPC32TargetInfo>(T);
4989    case llvm::Triple::OpenBSD:
4990      return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
4991    case llvm::Triple::RTEMS:
4992      return new RTEMSTargetInfo<PPC32TargetInfo>(T);
4993    default:
4994      return new PPC32TargetInfo(T);
4995    }
4996
4997  case llvm::Triple::ppc64:
4998    if (Triple.isOSDarwin())
4999      return new DarwinPPC64TargetInfo(T);
5000    switch (os) {
5001    case llvm::Triple::Linux:
5002      return new LinuxTargetInfo<PPC64TargetInfo>(T);
5003    case llvm::Triple::Lv2:
5004      return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
5005    case llvm::Triple::FreeBSD:
5006      return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
5007    case llvm::Triple::NetBSD:
5008      return new NetBSDTargetInfo<PPC64TargetInfo>(T);
5009    default:
5010      return new PPC64TargetInfo(T);
5011    }
5012
5013  case llvm::Triple::nvptx:
5014    return new NVPTX32TargetInfo(T);
5015  case llvm::Triple::nvptx64:
5016    return new NVPTX64TargetInfo(T);
5017
5018  case llvm::Triple::mblaze:
5019    return new MBlazeTargetInfo(T);
5020
5021  case llvm::Triple::r600:
5022    return new R600TargetInfo(T);
5023
5024  case llvm::Triple::sparc:
5025    switch (os) {
5026    case llvm::Triple::Linux:
5027      return new LinuxTargetInfo<SparcV8TargetInfo>(T);
5028    case llvm::Triple::AuroraUX:
5029      return new AuroraUXSparcV8TargetInfo(T);
5030    case llvm::Triple::Solaris:
5031      return new SolarisSparcV8TargetInfo(T);
5032    case llvm::Triple::NetBSD:
5033      return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
5034    case llvm::Triple::OpenBSD:
5035      return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
5036    case llvm::Triple::RTEMS:
5037      return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
5038    default:
5039      return new SparcV8TargetInfo(T);
5040    }
5041
5042  case llvm::Triple::tce:
5043    return new TCETargetInfo(T);
5044
5045  case llvm::Triple::x86:
5046    if (Triple.isOSDarwin())
5047      return new DarwinI386TargetInfo(T);
5048
5049    switch (os) {
5050    case llvm::Triple::AuroraUX:
5051      return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
5052    case llvm::Triple::Linux:
5053      return new LinuxTargetInfo<X86_32TargetInfo>(T);
5054    case llvm::Triple::DragonFly:
5055      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
5056    case llvm::Triple::NetBSD:
5057      return new NetBSDI386TargetInfo(T);
5058    case llvm::Triple::OpenBSD:
5059      return new OpenBSDI386TargetInfo(T);
5060    case llvm::Triple::Bitrig:
5061      return new BitrigI386TargetInfo(T);
5062    case llvm::Triple::FreeBSD:
5063      return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
5064    case llvm::Triple::Minix:
5065      return new MinixTargetInfo<X86_32TargetInfo>(T);
5066    case llvm::Triple::Solaris:
5067      return new SolarisTargetInfo<X86_32TargetInfo>(T);
5068    case llvm::Triple::Cygwin:
5069      return new CygwinX86_32TargetInfo(T);
5070    case llvm::Triple::MinGW32:
5071      return new MinGWX86_32TargetInfo(T);
5072    case llvm::Triple::Win32:
5073      return new VisualStudioWindowsX86_32TargetInfo(T);
5074    case llvm::Triple::Haiku:
5075      return new HaikuX86_32TargetInfo(T);
5076    case llvm::Triple::RTEMS:
5077      return new RTEMSX86_32TargetInfo(T);
5078    case llvm::Triple::NaCl:
5079      return new NaClTargetInfo<X86_32TargetInfo>(T);
5080    default:
5081      return new X86_32TargetInfo(T);
5082    }
5083
5084  case llvm::Triple::x86_64:
5085    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5086      return new DarwinX86_64TargetInfo(T);
5087
5088    switch (os) {
5089    case llvm::Triple::AuroraUX:
5090      return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
5091    case llvm::Triple::Linux:
5092      return new LinuxTargetInfo<X86_64TargetInfo>(T);
5093    case llvm::Triple::DragonFly:
5094      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
5095    case llvm::Triple::NetBSD:
5096      return new NetBSDTargetInfo<X86_64TargetInfo>(T);
5097    case llvm::Triple::OpenBSD:
5098      return new OpenBSDX86_64TargetInfo(T);
5099    case llvm::Triple::Bitrig:
5100      return new BitrigX86_64TargetInfo(T);
5101    case llvm::Triple::FreeBSD:
5102      return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
5103    case llvm::Triple::Solaris:
5104      return new SolarisTargetInfo<X86_64TargetInfo>(T);
5105    case llvm::Triple::MinGW32:
5106      return new MinGWX86_64TargetInfo(T);
5107    case llvm::Triple::Win32:   // This is what Triple.h supports now.
5108      return new VisualStudioWindowsX86_64TargetInfo(T);
5109    case llvm::Triple::NaCl:
5110      return new NaClTargetInfo<X86_64TargetInfo>(T);
5111    default:
5112      return new X86_64TargetInfo(T);
5113    }
5114
5115    case llvm::Triple::spir: {
5116      llvm::Triple Triple(T);
5117      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5118        Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5119        return NULL;
5120      return new SPIR32TargetInfo(T);
5121    }
5122    case llvm::Triple::spir64: {
5123      llvm::Triple Triple(T);
5124      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5125        Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5126        return NULL;
5127      return new SPIR64TargetInfo(T);
5128    }
5129  }
5130}
5131
5132/// CreateTargetInfo - Return the target info object for the specified target
5133/// triple.
5134TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5135                                         TargetOptions *Opts) {
5136  llvm::Triple Triple(Opts->Triple);
5137
5138  // Construct the target
5139  OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
5140  if (!Target) {
5141    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5142    return 0;
5143  }
5144  Target->setTargetOpts(Opts);
5145
5146  // Set the target CPU if specified.
5147  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5148    Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5149    return 0;
5150  }
5151
5152  // Set the target ABI if specified.
5153  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5154    Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5155    return 0;
5156  }
5157
5158  // Set the target C++ ABI.
5159  if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5160    Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5161    return 0;
5162  }
5163
5164  // Compute the default target features, we need the target to handle this
5165  // because features may have dependencies on one another.
5166  llvm::StringMap<bool> Features;
5167  Target->getDefaultFeatures(Features);
5168
5169  // Apply the user specified deltas.
5170  // First the enables.
5171  for (std::vector<std::string>::const_iterator
5172         it = Opts->FeaturesAsWritten.begin(),
5173         ie = Opts->FeaturesAsWritten.end();
5174       it != ie; ++it) {
5175    const char *Name = it->c_str();
5176
5177    if (Name[0] != '+')
5178      continue;
5179
5180    // Apply the feature via the target.
5181    if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5182      Diags.Report(diag::err_target_invalid_feature) << Name;
5183      return 0;
5184    }
5185  }
5186
5187  // Then the disables.
5188  for (std::vector<std::string>::const_iterator
5189         it = Opts->FeaturesAsWritten.begin(),
5190         ie = Opts->FeaturesAsWritten.end();
5191       it != ie; ++it) {
5192    const char *Name = it->c_str();
5193
5194    if (Name[0] == '+')
5195      continue;
5196
5197    // Apply the feature via the target.
5198    if (Name[0] != '-' ||
5199        !Target->setFeatureEnabled(Features, Name + 1, false)) {
5200      Diags.Report(diag::err_target_invalid_feature) << Name;
5201      return 0;
5202    }
5203  }
5204
5205  // Add the features to the compile options.
5206  //
5207  // FIXME: If we are completely confident that we have the right set, we only
5208  // need to pass the minuses.
5209  Opts->Features.clear();
5210  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5211         ie = Features.end(); it != ie; ++it)
5212    Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5213  Target->HandleTargetFeatures(Opts->Features);
5214
5215  return Target.take();
5216}
5217