Targets.cpp revision fe6b2713656c2d1bf559be357f0e0bf2d09bebd6 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "5621");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.getOS() == llvm::Triple::IOS) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else {
153    // Note that the Driver allows versions which aren't representable in the
154    // define (because we only get a single digit for the minor and micro
155    // revision numbers). So, we limit them to the maximum representable
156    // version.
157    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159    char Str[5];
160    Str[0] = '0' + (Maj / 10);
161    Str[1] = '0' + (Maj % 10);
162    Str[2] = '0' + std::min(Min, 9U);
163    Str[3] = '0' + std::min(Rev, 9U);
164    Str[4] = '\0';
165    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166  }
167
168  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169}
170
171namespace {
172template<typename Target>
173class DarwinTargetInfo : public OSTargetInfo<Target> {
174protected:
175  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                            MacroBuilder &Builder) const {
177    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                     this->PlatformMinVersion);
179  }
180
181public:
182  DarwinTargetInfo(const std::string& triple) :
183    OSTargetInfo<Target>(triple) {
184      llvm::Triple T = llvm::Triple(triple);
185      this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186      this->MCountName = "\01mcount";
187    }
188
189  virtual std::string isValidSectionSpecifier(StringRef SR) const {
190    // Let MCSectionMachO validate this.
191    StringRef Segment, Section;
192    unsigned TAA, StubSize;
193    bool HasTAA;
194    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                       TAA, HasTAA, StubSize);
196  }
197
198  virtual const char *getStaticInitSectionSpecifier() const {
199    // FIXME: We should return 0 when building kexts.
200    return "__TEXT,__StaticInit,regular,pure_instructions";
201  }
202
203  /// Darwin does not support protected visibility.  Darwin's "default"
204  /// is very similar to ELF's "protected";  Darwin requires a "weak"
205  /// attribute on declarations that can be dynamically replaced.
206  virtual bool hasProtectedVisibility() const {
207    return false;
208  }
209};
210
211
212// DragonFlyBSD Target
213template<typename Target>
214class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215protected:
216  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                            MacroBuilder &Builder) const {
218    // DragonFly defines; list based off of gcc output
219    Builder.defineMacro("__DragonFly__");
220    Builder.defineMacro("__DragonFly_cc_version", "100001");
221    Builder.defineMacro("__ELF__");
222    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223    Builder.defineMacro("__tune_i386__");
224    DefineStd(Builder, "unix", Opts);
225  }
226public:
227  DragonFlyBSDTargetInfo(const std::string &triple)
228    : OSTargetInfo<Target>(triple) {
229      this->UserLabelPrefix = "";
230
231      llvm::Triple Triple(triple);
232      switch (Triple.getArch()) {
233        default:
234        case llvm::Triple::x86:
235        case llvm::Triple::x86_64:
236          this->MCountName = ".mcount";
237          break;
238      }
239  }
240};
241
242// FreeBSD Target
243template<typename Target>
244class FreeBSDTargetInfo : public OSTargetInfo<Target> {
245protected:
246  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247                            MacroBuilder &Builder) const {
248    // FreeBSD defines; list based off of gcc output
249
250    unsigned Release = Triple.getOSMajorVersion();
251    if (Release == 0U)
252      Release = 8;
253
254    Builder.defineMacro("__FreeBSD__", Twine(Release));
255    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257    DefineStd(Builder, "unix", Opts);
258    Builder.defineMacro("__ELF__");
259  }
260public:
261  FreeBSDTargetInfo(const std::string &triple)
262    : OSTargetInfo<Target>(triple) {
263      this->UserLabelPrefix = "";
264
265      llvm::Triple Triple(triple);
266      switch (Triple.getArch()) {
267        default:
268        case llvm::Triple::x86:
269        case llvm::Triple::x86_64:
270          this->MCountName = ".mcount";
271          break;
272        case llvm::Triple::mips:
273        case llvm::Triple::mipsel:
274        case llvm::Triple::ppc:
275        case llvm::Triple::ppc64:
276          this->MCountName = "_mcount";
277          break;
278        case llvm::Triple::arm:
279          this->MCountName = "__mcount";
280          break;
281      }
282
283    }
284};
285
286// Minix Target
287template<typename Target>
288class MinixTargetInfo : public OSTargetInfo<Target> {
289protected:
290  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291                            MacroBuilder &Builder) const {
292    // Minix defines
293
294    Builder.defineMacro("__minix", "3");
295    Builder.defineMacro("_EM_WSIZE", "4");
296    Builder.defineMacro("_EM_PSIZE", "4");
297    Builder.defineMacro("_EM_SSIZE", "2");
298    Builder.defineMacro("_EM_LSIZE", "4");
299    Builder.defineMacro("_EM_FSIZE", "4");
300    Builder.defineMacro("_EM_DSIZE", "8");
301    Builder.defineMacro("__ELF__");
302    DefineStd(Builder, "unix", Opts);
303  }
304public:
305  MinixTargetInfo(const std::string &triple)
306    : OSTargetInfo<Target>(triple) {
307      this->UserLabelPrefix = "";
308    }
309};
310
311// Linux target
312template<typename Target>
313class LinuxTargetInfo : public OSTargetInfo<Target> {
314protected:
315  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                            MacroBuilder &Builder) const {
317    // Linux defines; list based off of gcc output
318    DefineStd(Builder, "unix", Opts);
319    DefineStd(Builder, "linux", Opts);
320    Builder.defineMacro("__gnu_linux__");
321    Builder.defineMacro("__ELF__");
322    if (Triple.getEnvironment() == llvm::Triple::Android)
323      Builder.defineMacro("__ANDROID__", "1");
324    if (Opts.POSIXThreads)
325      Builder.defineMacro("_REENTRANT");
326    if (Opts.CPlusPlus)
327      Builder.defineMacro("_GNU_SOURCE");
328  }
329public:
330  LinuxTargetInfo(const std::string& triple)
331    : OSTargetInfo<Target>(triple) {
332    this->UserLabelPrefix = "";
333    this->WIntType = TargetInfo::UnsignedInt;
334  }
335
336  virtual const char *getStaticInitSectionSpecifier() const {
337    return ".text.startup";
338  }
339};
340
341// NetBSD Target
342template<typename Target>
343class NetBSDTargetInfo : public OSTargetInfo<Target> {
344protected:
345  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346                            MacroBuilder &Builder) const {
347    // NetBSD defines; list based off of gcc output
348    Builder.defineMacro("__NetBSD__");
349    Builder.defineMacro("__unix__");
350    Builder.defineMacro("__ELF__");
351    if (Opts.POSIXThreads)
352      Builder.defineMacro("_POSIX_THREADS");
353  }
354public:
355  NetBSDTargetInfo(const std::string &triple)
356    : OSTargetInfo<Target>(triple) {
357      this->UserLabelPrefix = "";
358    }
359};
360
361// OpenBSD Target
362template<typename Target>
363class OpenBSDTargetInfo : public OSTargetInfo<Target> {
364protected:
365  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366                            MacroBuilder &Builder) const {
367    // OpenBSD defines; list based off of gcc output
368
369    Builder.defineMacro("__OpenBSD__");
370    DefineStd(Builder, "unix", Opts);
371    Builder.defineMacro("__ELF__");
372    if (Opts.POSIXThreads)
373      Builder.defineMacro("_REENTRANT");
374  }
375public:
376  OpenBSDTargetInfo(const std::string &triple)
377    : OSTargetInfo<Target>(triple) {
378      this->UserLabelPrefix = "";
379      this->TLSSupported = false;
380
381      llvm::Triple Triple(triple);
382      switch (Triple.getArch()) {
383        default:
384        case llvm::Triple::x86:
385        case llvm::Triple::x86_64:
386        case llvm::Triple::arm:
387        case llvm::Triple::sparc:
388          this->MCountName = "__mcount";
389          break;
390        case llvm::Triple::mips64:
391        case llvm::Triple::mips64el:
392        case llvm::Triple::ppc:
393        case llvm::Triple::sparcv9:
394          this->MCountName = "_mcount";
395          break;
396      }
397  }
398};
399
400// Bitrig Target
401template<typename Target>
402class BitrigTargetInfo : public OSTargetInfo<Target> {
403protected:
404  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405                            MacroBuilder &Builder) const {
406    // Bitrig defines; list based off of gcc output
407
408    Builder.defineMacro("__Bitrig__");
409    DefineStd(Builder, "unix", Opts);
410    Builder.defineMacro("__ELF__");
411    if (Opts.POSIXThreads)
412      Builder.defineMacro("_REENTRANT");
413  }
414public:
415  BitrigTargetInfo(const std::string &triple)
416    : OSTargetInfo<Target>(triple) {
417      this->UserLabelPrefix = "";
418      this->TLSSupported = false;
419      this->MCountName = "__mcount";
420  }
421};
422
423// PSP Target
424template<typename Target>
425class PSPTargetInfo : public OSTargetInfo<Target> {
426protected:
427  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428                            MacroBuilder &Builder) const {
429    // PSP defines; list based on the output of the pspdev gcc toolchain.
430    Builder.defineMacro("PSP");
431    Builder.defineMacro("_PSP");
432    Builder.defineMacro("__psp__");
433    Builder.defineMacro("__ELF__");
434  }
435public:
436  PSPTargetInfo(const std::string& triple)
437    : OSTargetInfo<Target>(triple) {
438    this->UserLabelPrefix = "";
439  }
440};
441
442// PS3 PPU Target
443template<typename Target>
444class PS3PPUTargetInfo : public OSTargetInfo<Target> {
445protected:
446  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                            MacroBuilder &Builder) const {
448    // PS3 PPU defines.
449    Builder.defineMacro("__PPC__");
450    Builder.defineMacro("__PPU__");
451    Builder.defineMacro("__CELLOS_LV2__");
452    Builder.defineMacro("__ELF__");
453    Builder.defineMacro("__LP32__");
454    Builder.defineMacro("_ARCH_PPC64");
455    Builder.defineMacro("__powerpc64__");
456  }
457public:
458  PS3PPUTargetInfo(const std::string& triple)
459    : OSTargetInfo<Target>(triple) {
460    this->UserLabelPrefix = "";
461    this->LongWidth = this->LongAlign = 32;
462    this->PointerWidth = this->PointerAlign = 32;
463    this->IntMaxType = TargetInfo::SignedLongLong;
464    this->UIntMaxType = TargetInfo::UnsignedLongLong;
465    this->Int64Type = TargetInfo::SignedLongLong;
466    this->SizeType = TargetInfo::UnsignedInt;
467    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
469  }
470};
471
472// FIXME: Need a real SPU target.
473// PS3 SPU Target
474template<typename Target>
475class PS3SPUTargetInfo : public OSTargetInfo<Target> {
476protected:
477  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478                            MacroBuilder &Builder) const {
479    // PS3 PPU defines.
480    Builder.defineMacro("__SPU__");
481    Builder.defineMacro("__ELF__");
482  }
483public:
484  PS3SPUTargetInfo(const std::string& triple)
485    : OSTargetInfo<Target>(triple) {
486    this->UserLabelPrefix = "";
487  }
488};
489
490// AuroraUX target
491template<typename Target>
492class AuroraUXTargetInfo : public OSTargetInfo<Target> {
493protected:
494  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                            MacroBuilder &Builder) const {
496    DefineStd(Builder, "sun", Opts);
497    DefineStd(Builder, "unix", Opts);
498    Builder.defineMacro("__ELF__");
499    Builder.defineMacro("__svr4__");
500    Builder.defineMacro("__SVR4");
501  }
502public:
503  AuroraUXTargetInfo(const std::string& triple)
504    : OSTargetInfo<Target>(triple) {
505    this->UserLabelPrefix = "";
506    this->WCharType = this->SignedLong;
507    // FIXME: WIntType should be SignedLong
508  }
509};
510
511// Solaris target
512template<typename Target>
513class SolarisTargetInfo : public OSTargetInfo<Target> {
514protected:
515  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516                            MacroBuilder &Builder) const {
517    DefineStd(Builder, "sun", Opts);
518    DefineStd(Builder, "unix", Opts);
519    Builder.defineMacro("__ELF__");
520    Builder.defineMacro("__svr4__");
521    Builder.defineMacro("__SVR4");
522    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523    // newer, but to 500 for everything else.  feature_test.h has a check to
524    // ensure that you are not using C99 with an old version of X/Open or C89
525    // with a new version.
526    if (Opts.C99 || Opts.C11)
527      Builder.defineMacro("_XOPEN_SOURCE", "600");
528    else
529      Builder.defineMacro("_XOPEN_SOURCE", "500");
530    if (Opts.CPlusPlus)
531      Builder.defineMacro("__C99FEATURES__");
532    Builder.defineMacro("_LARGEFILE_SOURCE");
533    Builder.defineMacro("_LARGEFILE64_SOURCE");
534    Builder.defineMacro("__EXTENSIONS__");
535    Builder.defineMacro("_REENTRANT");
536  }
537public:
538  SolarisTargetInfo(const std::string& triple)
539    : OSTargetInfo<Target>(triple) {
540    this->UserLabelPrefix = "";
541    this->WCharType = this->SignedInt;
542    // FIXME: WIntType should be SignedLong
543  }
544};
545
546// Windows target
547template<typename Target>
548class WindowsTargetInfo : public OSTargetInfo<Target> {
549protected:
550  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551                            MacroBuilder &Builder) const {
552    Builder.defineMacro("_WIN32");
553  }
554  void getVisualStudioDefines(const LangOptions &Opts,
555                              MacroBuilder &Builder) const {
556    if (Opts.CPlusPlus) {
557      if (Opts.RTTI)
558        Builder.defineMacro("_CPPRTTI");
559
560      if (Opts.Exceptions)
561        Builder.defineMacro("_CPPUNWIND");
562    }
563
564    if (!Opts.CharIsSigned)
565      Builder.defineMacro("_CHAR_UNSIGNED");
566
567    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568    //        but it works for now.
569    if (Opts.POSIXThreads)
570      Builder.defineMacro("_MT");
571
572    if (Opts.MSCVersion != 0)
573      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
574
575    if (Opts.MicrosoftExt) {
576      Builder.defineMacro("_MSC_EXTENSIONS");
577
578      if (Opts.CPlusPlus11) {
579        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
582      }
583    }
584
585    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
586  }
587
588public:
589  WindowsTargetInfo(const std::string &triple)
590    : OSTargetInfo<Target>(triple) {}
591};
592
593template <typename Target>
594class NaClTargetInfo : public OSTargetInfo<Target> {
595 protected:
596  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597                            MacroBuilder &Builder) const {
598    if (Opts.POSIXThreads)
599      Builder.defineMacro("_REENTRANT");
600    if (Opts.CPlusPlus)
601      Builder.defineMacro("_GNU_SOURCE");
602
603    DefineStd(Builder, "unix", Opts);
604    Builder.defineMacro("__ELF__");
605    Builder.defineMacro("__native_client__");
606  }
607 public:
608  NaClTargetInfo(const std::string &triple)
609    : OSTargetInfo<Target>(triple) {
610    this->UserLabelPrefix = "";
611    this->LongAlign = 32;
612    this->LongWidth = 32;
613    this->PointerAlign = 32;
614    this->PointerWidth = 32;
615    this->IntMaxType = TargetInfo::SignedLongLong;
616    this->UIntMaxType = TargetInfo::UnsignedLongLong;
617    this->Int64Type = TargetInfo::SignedLongLong;
618    this->DoubleAlign = 64;
619    this->LongDoubleWidth = 64;
620    this->LongDoubleAlign = 64;
621    this->SizeType = TargetInfo::UnsignedInt;
622    this->PtrDiffType = TargetInfo::SignedInt;
623    this->IntPtrType = TargetInfo::SignedInt;
624    this->RegParmMax = 2;
625    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
626    this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
627                              "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
628  }
629  virtual typename Target::CallingConvCheckResult checkCallingConvention(
630      CallingConv CC) const {
631    return CC == CC_PnaclCall ? Target::CCCR_OK :
632        Target::checkCallingConvention(CC);
633  }
634};
635} // end anonymous namespace.
636
637//===----------------------------------------------------------------------===//
638// Specific target implementations.
639//===----------------------------------------------------------------------===//
640
641namespace {
642// PPC abstract base class
643class PPCTargetInfo : public TargetInfo {
644  static const Builtin::Info BuiltinInfo[];
645  static const char * const GCCRegNames[];
646  static const TargetInfo::GCCRegAlias GCCRegAliases[];
647  std::string CPU;
648public:
649  PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
650    LongDoubleWidth = LongDoubleAlign = 128;
651    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
652  }
653
654  /// \brief Flags for architecture specific defines.
655  typedef enum {
656    ArchDefineNone  = 0,
657    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
658    ArchDefinePpcgr = 1 << 1,
659    ArchDefinePpcsq = 1 << 2,
660    ArchDefine440   = 1 << 3,
661    ArchDefine603   = 1 << 4,
662    ArchDefine604   = 1 << 5,
663    ArchDefinePwr4  = 1 << 6,
664    ArchDefinePwr5  = 1 << 7,
665    ArchDefinePwr5x = 1 << 8,
666    ArchDefinePwr6  = 1 << 9,
667    ArchDefinePwr6x = 1 << 10,
668    ArchDefinePwr7  = 1 << 11,
669    ArchDefineA2    = 1 << 12,
670    ArchDefineA2q   = 1 << 13
671  } ArchDefineTypes;
672
673  // Note: GCC recognizes the following additional cpus:
674  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
675  //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
676  //  titan, rs64.
677  virtual bool setCPU(const std::string &Name) {
678    bool CPUKnown = llvm::StringSwitch<bool>(Name)
679      .Case("generic", true)
680      .Case("440", true)
681      .Case("450", true)
682      .Case("601", true)
683      .Case("602", true)
684      .Case("603", true)
685      .Case("603e", true)
686      .Case("603ev", true)
687      .Case("604", true)
688      .Case("604e", true)
689      .Case("620", true)
690      .Case("630", true)
691      .Case("g3", true)
692      .Case("7400", true)
693      .Case("g4", true)
694      .Case("7450", true)
695      .Case("g4+", true)
696      .Case("750", true)
697      .Case("970", true)
698      .Case("g5", true)
699      .Case("a2", true)
700      .Case("a2q", true)
701      .Case("e500mc", true)
702      .Case("e5500", true)
703      .Case("power3", true)
704      .Case("pwr3", true)
705      .Case("power4", true)
706      .Case("pwr4", true)
707      .Case("power5", true)
708      .Case("pwr5", true)
709      .Case("power5x", true)
710      .Case("pwr5x", true)
711      .Case("power6", true)
712      .Case("pwr6", true)
713      .Case("power6x", true)
714      .Case("pwr6x", true)
715      .Case("power7", true)
716      .Case("pwr7", true)
717      .Case("powerpc", true)
718      .Case("ppc", true)
719      .Case("powerpc64", true)
720      .Case("ppc64", true)
721      .Default(false);
722
723    if (CPUKnown)
724      CPU = Name;
725
726    return CPUKnown;
727  }
728
729  virtual void getTargetBuiltins(const Builtin::Info *&Records,
730                                 unsigned &NumRecords) const {
731    Records = BuiltinInfo;
732    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
733  }
734
735  virtual bool isCLZForZeroUndef() const { return false; }
736
737  virtual void getTargetDefines(const LangOptions &Opts,
738                                MacroBuilder &Builder) const;
739
740  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
741
742  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
743                                 StringRef Name,
744                                 bool Enabled) const;
745
746  virtual bool hasFeature(StringRef Feature) const;
747
748  virtual void getGCCRegNames(const char * const *&Names,
749                              unsigned &NumNames) const;
750  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
751                                unsigned &NumAliases) const;
752  virtual bool validateAsmConstraint(const char *&Name,
753                                     TargetInfo::ConstraintInfo &Info) const {
754    switch (*Name) {
755    default: return false;
756    case 'O': // Zero
757      break;
758    case 'b': // Base register
759    case 'f': // Floating point register
760      Info.setAllowsRegister();
761      break;
762    // FIXME: The following are added to allow parsing.
763    // I just took a guess at what the actions should be.
764    // Also, is more specific checking needed?  I.e. specific registers?
765    case 'd': // Floating point register (containing 64-bit value)
766    case 'v': // Altivec vector register
767      Info.setAllowsRegister();
768      break;
769    case 'w':
770      switch (Name[1]) {
771        case 'd':// VSX vector register to hold vector double data
772        case 'f':// VSX vector register to hold vector float data
773        case 's':// VSX vector register to hold scalar float data
774        case 'a':// Any VSX register
775          break;
776        default:
777          return false;
778      }
779      Info.setAllowsRegister();
780      Name++; // Skip over 'w'.
781      break;
782    case 'h': // `MQ', `CTR', or `LINK' register
783    case 'q': // `MQ' register
784    case 'c': // `CTR' register
785    case 'l': // `LINK' register
786    case 'x': // `CR' register (condition register) number 0
787    case 'y': // `CR' register (condition register)
788    case 'z': // `XER[CA]' carry bit (part of the XER register)
789      Info.setAllowsRegister();
790      break;
791    case 'I': // Signed 16-bit constant
792    case 'J': // Unsigned 16-bit constant shifted left 16 bits
793              //  (use `L' instead for SImode constants)
794    case 'K': // Unsigned 16-bit constant
795    case 'L': // Signed 16-bit constant shifted left 16 bits
796    case 'M': // Constant larger than 31
797    case 'N': // Exact power of 2
798    case 'P': // Constant whose negation is a signed 16-bit constant
799    case 'G': // Floating point constant that can be loaded into a
800              // register with one instruction per word
801    case 'H': // Integer/Floating point constant that can be loaded
802              // into a register using three instructions
803      break;
804    case 'm': // Memory operand. Note that on PowerPC targets, m can
805              // include addresses that update the base register. It
806              // is therefore only safe to use `m' in an asm statement
807              // if that asm statement accesses the operand exactly once.
808              // The asm statement must also use `%U<opno>' as a
809              // placeholder for the "update" flag in the corresponding
810              // load or store instruction. For example:
811              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
812              // is correct but:
813              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
814              // is not. Use es rather than m if you don't want the base
815              // register to be updated.
816    case 'e':
817      if (Name[1] != 's')
818          return false;
819              // es: A "stable" memory operand; that is, one which does not
820              // include any automodification of the base register. Unlike
821              // `m', this constraint can be used in asm statements that
822              // might access the operand several times, or that might not
823              // access it at all.
824      Info.setAllowsMemory();
825      Name++; // Skip over 'e'.
826      break;
827    case 'Q': // Memory operand that is an offset from a register (it is
828              // usually better to use `m' or `es' in asm statements)
829    case 'Z': // Memory operand that is an indexed or indirect from a
830              // register (it is usually better to use `m' or `es' in
831              // asm statements)
832      Info.setAllowsMemory();
833      Info.setAllowsRegister();
834      break;
835    case 'R': // AIX TOC entry
836    case 'a': // Address operand that is an indexed or indirect from a
837              // register (`p' is preferable for asm statements)
838    case 'S': // Constant suitable as a 64-bit mask operand
839    case 'T': // Constant suitable as a 32-bit mask operand
840    case 'U': // System V Release 4 small data area reference
841    case 't': // AND masks that can be performed by two rldic{l, r}
842              // instructions
843    case 'W': // Vector constant that does not require memory
844    case 'j': // Vector constant that is all zeros.
845      break;
846    // End FIXME.
847    }
848    return true;
849  }
850  virtual const char *getClobbers() const {
851    return "";
852  }
853  int getEHDataRegisterNumber(unsigned RegNo) const {
854    if (RegNo == 0) return 3;
855    if (RegNo == 1) return 4;
856    return -1;
857  }
858};
859
860const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
861#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
862#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
863                                              ALL_LANGUAGES },
864#include "clang/Basic/BuiltinsPPC.def"
865};
866
867
868/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
869/// #defines that are not tied to a specific subtarget.
870void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
871                                     MacroBuilder &Builder) const {
872  // Target identification.
873  Builder.defineMacro("__ppc__");
874  Builder.defineMacro("_ARCH_PPC");
875  Builder.defineMacro("__powerpc__");
876  Builder.defineMacro("__POWERPC__");
877  if (PointerWidth == 64) {
878    Builder.defineMacro("_ARCH_PPC64");
879    Builder.defineMacro("__powerpc64__");
880    Builder.defineMacro("__ppc64__");
881  } else {
882    Builder.defineMacro("__ppc__");
883  }
884
885  // Target properties.
886  if (getTriple().getOS() != llvm::Triple::NetBSD &&
887      getTriple().getOS() != llvm::Triple::OpenBSD)
888    Builder.defineMacro("_BIG_ENDIAN");
889  Builder.defineMacro("__BIG_ENDIAN__");
890
891  // Subtarget options.
892  Builder.defineMacro("__NATURAL_ALIGNMENT__");
893  Builder.defineMacro("__REGISTER_PREFIX__", "");
894
895  // FIXME: Should be controlled by command line option.
896  Builder.defineMacro("__LONG_DOUBLE_128__");
897
898  if (Opts.AltiVec) {
899    Builder.defineMacro("__VEC__", "10206");
900    Builder.defineMacro("__ALTIVEC__");
901  }
902
903  // CPU identification.
904  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
905    .Case("440",   ArchDefineName)
906    .Case("450",   ArchDefineName | ArchDefine440)
907    .Case("601",   ArchDefineName)
908    .Case("602",   ArchDefineName | ArchDefinePpcgr)
909    .Case("603",   ArchDefineName | ArchDefinePpcgr)
910    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
911    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
912    .Case("604",   ArchDefineName | ArchDefinePpcgr)
913    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
914    .Case("620",   ArchDefineName | ArchDefinePpcgr)
915    .Case("630",   ArchDefineName | ArchDefinePpcgr)
916    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
917    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
918    .Case("750",   ArchDefineName | ArchDefinePpcgr)
919    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
920                     | ArchDefinePpcsq)
921    .Case("a2",    ArchDefineA2)
922    .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
923    .Case("pwr3",  ArchDefinePpcgr)
924    .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
925    .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
926                     | ArchDefinePpcsq)
927    .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
928                     | ArchDefinePpcgr | ArchDefinePpcsq)
929    .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
930                     | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
931    .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
932                     | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
933                     | ArchDefinePpcsq)
934    .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
935                     | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
936                     | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
937    .Case("power3",  ArchDefinePpcgr)
938    .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
939    .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
940                       | ArchDefinePpcsq)
941    .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
942                       | ArchDefinePpcgr | ArchDefinePpcsq)
943    .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
944                       | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
945    .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
946                       | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
947                       | ArchDefinePpcsq)
948    .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
949                       | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
950                       | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
951    .Default(ArchDefineNone);
952
953  if (defs & ArchDefineName)
954    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
955  if (defs & ArchDefinePpcgr)
956    Builder.defineMacro("_ARCH_PPCGR");
957  if (defs & ArchDefinePpcsq)
958    Builder.defineMacro("_ARCH_PPCSQ");
959  if (defs & ArchDefine440)
960    Builder.defineMacro("_ARCH_440");
961  if (defs & ArchDefine603)
962    Builder.defineMacro("_ARCH_603");
963  if (defs & ArchDefine604)
964    Builder.defineMacro("_ARCH_604");
965  if (defs & ArchDefinePwr4)
966    Builder.defineMacro("_ARCH_PWR4");
967  if (defs & ArchDefinePwr5)
968    Builder.defineMacro("_ARCH_PWR5");
969  if (defs & ArchDefinePwr5x)
970    Builder.defineMacro("_ARCH_PWR5X");
971  if (defs & ArchDefinePwr6)
972    Builder.defineMacro("_ARCH_PWR6");
973  if (defs & ArchDefinePwr6x)
974    Builder.defineMacro("_ARCH_PWR6X");
975  if (defs & ArchDefinePwr7)
976    Builder.defineMacro("_ARCH_PWR7");
977  if (defs & ArchDefineA2)
978    Builder.defineMacro("_ARCH_A2");
979  if (defs & ArchDefineA2q) {
980    Builder.defineMacro("_ARCH_A2Q");
981    Builder.defineMacro("_ARCH_QP");
982  }
983
984  if (getTriple().getVendor() == llvm::Triple::BGQ) {
985    Builder.defineMacro("__bg__");
986    Builder.defineMacro("__THW_BLUEGENE__");
987    Builder.defineMacro("__bgq__");
988    Builder.defineMacro("__TOS_BGQ__");
989  }
990
991  // FIXME: The following are not yet generated here by Clang, but are
992  //        generated by GCC:
993  //
994  //   _SOFT_FLOAT_
995  //   __RECIP_PRECISION__
996  //   __APPLE_ALTIVEC__
997  //   __VSX__
998  //   __RECIP__
999  //   __RECIPF__
1000  //   __RSQRTE__
1001  //   __RSQRTEF__
1002  //   _SOFT_DOUBLE_
1003  //   __NO_LWSYNC__
1004  //   __HAVE_BSWAP__
1005  //   __LONGDOUBLE128
1006  //   __CMODEL_MEDIUM__
1007  //   __CMODEL_LARGE__
1008  //   _CALL_SYSV
1009  //   _CALL_DARWIN
1010  //   __NO_FPRS__
1011}
1012
1013void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1014  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1015    .Case("7400", true)
1016    .Case("g4", true)
1017    .Case("7450", true)
1018    .Case("g4+", true)
1019    .Case("970", true)
1020    .Case("g5", true)
1021    .Case("pwr6", true)
1022    .Case("pwr7", true)
1023    .Case("ppc64", true)
1024    .Default(false);
1025
1026  Features["qpx"] = (CPU == "a2q");
1027}
1028
1029bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1030                                         StringRef Name,
1031                                         bool Enabled) const {
1032  if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1033      Name == "popcntd" || Name == "qpx") {
1034    Features[Name] = Enabled;
1035    return true;
1036  }
1037
1038  return false;
1039}
1040
1041bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1042  return Feature == "powerpc";
1043}
1044
1045
1046const char * const PPCTargetInfo::GCCRegNames[] = {
1047  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1048  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1049  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1050  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1051  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1052  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1053  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1054  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1055  "mq", "lr", "ctr", "ap",
1056  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1057  "xer",
1058  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1059  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1060  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1061  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1062  "vrsave", "vscr",
1063  "spe_acc", "spefscr",
1064  "sfp"
1065};
1066
1067void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1068                                   unsigned &NumNames) const {
1069  Names = GCCRegNames;
1070  NumNames = llvm::array_lengthof(GCCRegNames);
1071}
1072
1073const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1074  // While some of these aliases do map to different registers
1075  // they still share the same register name.
1076  { { "0" }, "r0" },
1077  { { "1"}, "r1" },
1078  { { "2" }, "r2" },
1079  { { "3" }, "r3" },
1080  { { "4" }, "r4" },
1081  { { "5" }, "r5" },
1082  { { "6" }, "r6" },
1083  { { "7" }, "r7" },
1084  { { "8" }, "r8" },
1085  { { "9" }, "r9" },
1086  { { "10" }, "r10" },
1087  { { "11" }, "r11" },
1088  { { "12" }, "r12" },
1089  { { "13" }, "r13" },
1090  { { "14" }, "r14" },
1091  { { "15" }, "r15" },
1092  { { "16" }, "r16" },
1093  { { "17" }, "r17" },
1094  { { "18" }, "r18" },
1095  { { "19" }, "r19" },
1096  { { "20" }, "r20" },
1097  { { "21" }, "r21" },
1098  { { "22" }, "r22" },
1099  { { "23" }, "r23" },
1100  { { "24" }, "r24" },
1101  { { "25" }, "r25" },
1102  { { "26" }, "r26" },
1103  { { "27" }, "r27" },
1104  { { "28" }, "r28" },
1105  { { "29" }, "r29" },
1106  { { "30" }, "r30" },
1107  { { "31" }, "r31" },
1108  { { "fr0" }, "f0" },
1109  { { "fr1" }, "f1" },
1110  { { "fr2" }, "f2" },
1111  { { "fr3" }, "f3" },
1112  { { "fr4" }, "f4" },
1113  { { "fr5" }, "f5" },
1114  { { "fr6" }, "f6" },
1115  { { "fr7" }, "f7" },
1116  { { "fr8" }, "f8" },
1117  { { "fr9" }, "f9" },
1118  { { "fr10" }, "f10" },
1119  { { "fr11" }, "f11" },
1120  { { "fr12" }, "f12" },
1121  { { "fr13" }, "f13" },
1122  { { "fr14" }, "f14" },
1123  { { "fr15" }, "f15" },
1124  { { "fr16" }, "f16" },
1125  { { "fr17" }, "f17" },
1126  { { "fr18" }, "f18" },
1127  { { "fr19" }, "f19" },
1128  { { "fr20" }, "f20" },
1129  { { "fr21" }, "f21" },
1130  { { "fr22" }, "f22" },
1131  { { "fr23" }, "f23" },
1132  { { "fr24" }, "f24" },
1133  { { "fr25" }, "f25" },
1134  { { "fr26" }, "f26" },
1135  { { "fr27" }, "f27" },
1136  { { "fr28" }, "f28" },
1137  { { "fr29" }, "f29" },
1138  { { "fr30" }, "f30" },
1139  { { "fr31" }, "f31" },
1140  { { "cc" }, "cr0" },
1141};
1142
1143void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1144                                     unsigned &NumAliases) const {
1145  Aliases = GCCRegAliases;
1146  NumAliases = llvm::array_lengthof(GCCRegAliases);
1147}
1148} // end anonymous namespace.
1149
1150namespace {
1151class PPC32TargetInfo : public PPCTargetInfo {
1152public:
1153  PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1154    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1155                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1156
1157    switch (getTriple().getOS()) {
1158    case llvm::Triple::Linux:
1159    case llvm::Triple::FreeBSD:
1160    case llvm::Triple::NetBSD:
1161      SizeType = UnsignedInt;
1162      PtrDiffType = SignedInt;
1163      IntPtrType = SignedInt;
1164      break;
1165    default:
1166      break;
1167    }
1168
1169    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1170      LongDoubleWidth = LongDoubleAlign = 64;
1171      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1172    }
1173
1174    // PPC32 supports atomics up to 4 bytes.
1175    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1176  }
1177
1178  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1179    // This is the ELF definition, and is overridden by the Darwin sub-target
1180    return TargetInfo::PowerABIBuiltinVaList;
1181  }
1182};
1183} // end anonymous namespace.
1184
1185namespace {
1186class PPC64TargetInfo : public PPCTargetInfo {
1187public:
1188  PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1189    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1190    IntMaxType = SignedLong;
1191    UIntMaxType = UnsignedLong;
1192    Int64Type = SignedLong;
1193
1194    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1195      LongDoubleWidth = LongDoubleAlign = 64;
1196      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1197      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1198                          "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1199                          "v128:128:128-n32:64";
1200    } else
1201      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1202                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1203                          "v128:128:128-n32:64";
1204
1205    // PPC64 supports atomics up to 8 bytes.
1206    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1207  }
1208  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1209    return TargetInfo::CharPtrBuiltinVaList;
1210  }
1211};
1212} // end anonymous namespace.
1213
1214
1215namespace {
1216class DarwinPPC32TargetInfo :
1217  public DarwinTargetInfo<PPC32TargetInfo> {
1218public:
1219  DarwinPPC32TargetInfo(const std::string& triple)
1220    : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1221    HasAlignMac68kSupport = true;
1222    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1223    LongLongAlign = 32;
1224    SuitableAlign = 128;
1225    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1226                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1227  }
1228  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1229    return TargetInfo::CharPtrBuiltinVaList;
1230  }
1231};
1232
1233class DarwinPPC64TargetInfo :
1234  public DarwinTargetInfo<PPC64TargetInfo> {
1235public:
1236  DarwinPPC64TargetInfo(const std::string& triple)
1237    : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1238    HasAlignMac68kSupport = true;
1239    SuitableAlign = 128;
1240    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1241                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1242  }
1243};
1244} // end anonymous namespace.
1245
1246namespace {
1247  static const unsigned NVPTXAddrSpaceMap[] = {
1248    1,    // opencl_global
1249    3,    // opencl_local
1250    4,    // opencl_constant
1251    1,    // cuda_device
1252    4,    // cuda_constant
1253    3,    // cuda_shared
1254  };
1255  class NVPTXTargetInfo : public TargetInfo {
1256    static const char * const GCCRegNames[];
1257    static const Builtin::Info BuiltinInfo[];
1258    std::vector<StringRef> AvailableFeatures;
1259  public:
1260    NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1261      BigEndian = false;
1262      TLSSupported = false;
1263      LongWidth = LongAlign = 64;
1264      AddrSpaceMap = &NVPTXAddrSpaceMap;
1265      // Define available target features
1266      // These must be defined in sorted order!
1267      NoAsmVariants = true;
1268    }
1269    virtual void getTargetDefines(const LangOptions &Opts,
1270                                  MacroBuilder &Builder) const {
1271      Builder.defineMacro("__PTX__");
1272      Builder.defineMacro("__NVPTX__");
1273    }
1274    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1275                                   unsigned &NumRecords) const {
1276      Records = BuiltinInfo;
1277      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1278    }
1279    virtual bool hasFeature(StringRef Feature) const {
1280      return Feature == "ptx" || Feature == "nvptx";
1281    }
1282
1283    virtual void getGCCRegNames(const char * const *&Names,
1284                                unsigned &NumNames) const;
1285    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1286                                  unsigned &NumAliases) const {
1287      // No aliases.
1288      Aliases = 0;
1289      NumAliases = 0;
1290    }
1291    virtual bool validateAsmConstraint(const char *&Name,
1292                                       TargetInfo::ConstraintInfo &info) const {
1293      // FIXME: implement
1294      return true;
1295    }
1296    virtual const char *getClobbers() const {
1297      // FIXME: Is this really right?
1298      return "";
1299    }
1300    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1301      // FIXME: implement
1302      return TargetInfo::CharPtrBuiltinVaList;
1303    }
1304    virtual bool setCPU(const std::string &Name) {
1305      return Name == "sm_10" || Name == "sm_13" || Name == "sm_20";
1306    }
1307    virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1308                                   StringRef Name,
1309                                   bool Enabled) const;
1310  };
1311
1312  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1313#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1314#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1315                                              ALL_LANGUAGES },
1316#include "clang/Basic/BuiltinsNVPTX.def"
1317  };
1318
1319  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1320    "r0"
1321  };
1322
1323  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1324                                     unsigned &NumNames) const {
1325    Names = GCCRegNames;
1326    NumNames = llvm::array_lengthof(GCCRegNames);
1327  }
1328
1329  bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1330                                          StringRef Name,
1331                                          bool Enabled) const {
1332    if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1333                          Name)) {
1334      Features[Name] = Enabled;
1335      return true;
1336    } else {
1337      return false;
1338    }
1339  }
1340
1341  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1342  public:
1343    NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1344      PointerWidth = PointerAlign = 32;
1345      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1346      DescriptionString
1347        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1348          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1349          "n16:32:64";
1350  }
1351  };
1352
1353  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1354  public:
1355    NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1356      PointerWidth = PointerAlign = 64;
1357      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1358      DescriptionString
1359        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1360          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1361          "n16:32:64";
1362  }
1363  };
1364}
1365
1366namespace {
1367
1368static const unsigned R600AddrSpaceMap[] = {
1369  1,    // opencl_global
1370  3,    // opencl_local
1371  2,    // opencl_constant
1372  1,    // cuda_device
1373  2,    // cuda_constant
1374  3     // cuda_shared
1375};
1376
1377static const char *DescriptionStringR600 =
1378  "e"
1379  "-p:32:32:32"
1380  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1381  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1382  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1383  "-n32:64";
1384
1385static const char *DescriptionStringR600DoubleOps =
1386  "e"
1387  "-p:32:32:32"
1388  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1389  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1390  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1391  "-n32:64";
1392
1393static const char *DescriptionStringSI =
1394  "e"
1395  "-p:64:64:64"
1396  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1397  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1398  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1399  "-n32:64";
1400
1401class R600TargetInfo : public TargetInfo {
1402  /// \brief The GPU profiles supported by the R600 target.
1403  enum GPUKind {
1404    GK_NONE,
1405    GK_R600,
1406    GK_R600_DOUBLE_OPS,
1407    GK_R700,
1408    GK_R700_DOUBLE_OPS,
1409    GK_EVERGREEN,
1410    GK_EVERGREEN_DOUBLE_OPS,
1411    GK_NORTHERN_ISLANDS,
1412    GK_CAYMAN,
1413    GK_SOUTHERN_ISLANDS
1414  } GPU;
1415
1416public:
1417  R600TargetInfo(const std::string& triple)
1418    : TargetInfo(triple),
1419      GPU(GK_R600) {
1420    DescriptionString = DescriptionStringR600;
1421    AddrSpaceMap = &R600AddrSpaceMap;
1422  }
1423
1424  virtual const char * getClobbers() const {
1425    return "";
1426  }
1427
1428  virtual void getGCCRegNames(const char * const *&Names,
1429                              unsigned &numNames) const  {
1430    Names = NULL;
1431    numNames = 0;
1432  }
1433
1434  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1435                                unsigned &NumAliases) const {
1436    Aliases = NULL;
1437    NumAliases = 0;
1438  }
1439
1440  virtual bool validateAsmConstraint(const char *&Name,
1441                                     TargetInfo::ConstraintInfo &info) const {
1442    return true;
1443  }
1444
1445  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1446                                 unsigned &NumRecords) const {
1447    Records = NULL;
1448    NumRecords = 0;
1449  }
1450
1451
1452  virtual void getTargetDefines(const LangOptions &Opts,
1453                                MacroBuilder &Builder) const {
1454    Builder.defineMacro("__R600__");
1455  }
1456
1457  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1458    return TargetInfo::CharPtrBuiltinVaList;
1459  }
1460
1461  virtual bool setCPU(const std::string &Name) {
1462    GPU = llvm::StringSwitch<GPUKind>(Name)
1463      .Case("r600" ,    GK_R600)
1464      .Case("rv610",    GK_R600)
1465      .Case("rv620",    GK_R600)
1466      .Case("rv630",    GK_R600)
1467      .Case("rv635",    GK_R600)
1468      .Case("rs780",    GK_R600)
1469      .Case("rs880",    GK_R600)
1470      .Case("rv670",    GK_R600_DOUBLE_OPS)
1471      .Case("rv710",    GK_R700)
1472      .Case("rv730",    GK_R700)
1473      .Case("rv740",    GK_R700_DOUBLE_OPS)
1474      .Case("rv770",    GK_R700_DOUBLE_OPS)
1475      .Case("palm",     GK_EVERGREEN)
1476      .Case("cedar",    GK_EVERGREEN)
1477      .Case("sumo",     GK_EVERGREEN)
1478      .Case("sumo2",    GK_EVERGREEN)
1479      .Case("redwood",  GK_EVERGREEN)
1480      .Case("juniper",  GK_EVERGREEN)
1481      .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1482      .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1483      .Case("barts",    GK_NORTHERN_ISLANDS)
1484      .Case("turks",    GK_NORTHERN_ISLANDS)
1485      .Case("caicos",   GK_NORTHERN_ISLANDS)
1486      .Case("cayman",   GK_CAYMAN)
1487      .Case("aruba",    GK_CAYMAN)
1488      .Case("SI",       GK_SOUTHERN_ISLANDS)
1489      .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1490      .Case("verde",    GK_SOUTHERN_ISLANDS)
1491      .Case("oland",    GK_SOUTHERN_ISLANDS)
1492      .Default(GK_NONE);
1493
1494    if (GPU == GK_NONE) {
1495      return false;
1496    }
1497
1498    // Set the correct data layout
1499    switch (GPU) {
1500    case GK_NONE:
1501    case GK_R600:
1502    case GK_R700:
1503    case GK_EVERGREEN:
1504    case GK_NORTHERN_ISLANDS:
1505      DescriptionString = DescriptionStringR600;
1506      break;
1507    case GK_R600_DOUBLE_OPS:
1508    case GK_R700_DOUBLE_OPS:
1509    case GK_EVERGREEN_DOUBLE_OPS:
1510    case GK_CAYMAN:
1511      DescriptionString = DescriptionStringR600DoubleOps;
1512      break;
1513    case GK_SOUTHERN_ISLANDS:
1514      DescriptionString = DescriptionStringSI;
1515      break;
1516    }
1517
1518    return true;
1519  }
1520};
1521
1522} // end anonymous namespace
1523
1524namespace {
1525// MBlaze abstract base class
1526class MBlazeTargetInfo : public TargetInfo {
1527  static const char * const GCCRegNames[];
1528  static const TargetInfo::GCCRegAlias GCCRegAliases[];
1529
1530public:
1531  MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1532    DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1533  }
1534
1535  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1536                                 unsigned &NumRecords) const {
1537    // FIXME: Implement.
1538    Records = 0;
1539    NumRecords = 0;
1540  }
1541
1542  virtual void getTargetDefines(const LangOptions &Opts,
1543                                MacroBuilder &Builder) const;
1544
1545  virtual bool hasFeature(StringRef Feature) const {
1546    return Feature == "mblaze";
1547  }
1548
1549  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1550    return TargetInfo::CharPtrBuiltinVaList;
1551  }
1552  virtual const char *getTargetPrefix() const {
1553    return "mblaze";
1554  }
1555  virtual void getGCCRegNames(const char * const *&Names,
1556                              unsigned &NumNames) const;
1557  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1558                                unsigned &NumAliases) const;
1559  virtual bool validateAsmConstraint(const char *&Name,
1560                                     TargetInfo::ConstraintInfo &Info) const {
1561    switch (*Name) {
1562    default: return false;
1563    case 'O': // Zero
1564      return true;
1565    case 'b': // Base register
1566    case 'f': // Floating point register
1567      Info.setAllowsRegister();
1568      return true;
1569    }
1570  }
1571  virtual const char *getClobbers() const {
1572    return "";
1573  }
1574};
1575
1576/// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1577/// #defines that are not tied to a specific subtarget.
1578void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1579                                     MacroBuilder &Builder) const {
1580  // Target identification.
1581  Builder.defineMacro("__microblaze__");
1582  Builder.defineMacro("_ARCH_MICROBLAZE");
1583  Builder.defineMacro("__MICROBLAZE__");
1584
1585  // Target properties.
1586  Builder.defineMacro("_BIG_ENDIAN");
1587  Builder.defineMacro("__BIG_ENDIAN__");
1588
1589  // Subtarget options.
1590  Builder.defineMacro("__REGISTER_PREFIX__", "");
1591}
1592
1593
1594const char * const MBlazeTargetInfo::GCCRegNames[] = {
1595  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1596  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1597  "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1598  "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1599  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1600  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1601  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1602  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1603  "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1604  "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1605};
1606
1607void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1608                                   unsigned &NumNames) const {
1609  Names = GCCRegNames;
1610  NumNames = llvm::array_lengthof(GCCRegNames);
1611}
1612
1613const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1614  { {"f0"},  "r0" },
1615  { {"f1"},  "r1" },
1616  { {"f2"},  "r2" },
1617  { {"f3"},  "r3" },
1618  { {"f4"},  "r4" },
1619  { {"f5"},  "r5" },
1620  { {"f6"},  "r6" },
1621  { {"f7"},  "r7" },
1622  { {"f8"},  "r8" },
1623  { {"f9"},  "r9" },
1624  { {"f10"}, "r10" },
1625  { {"f11"}, "r11" },
1626  { {"f12"}, "r12" },
1627  { {"f13"}, "r13" },
1628  { {"f14"}, "r14" },
1629  { {"f15"}, "r15" },
1630  { {"f16"}, "r16" },
1631  { {"f17"}, "r17" },
1632  { {"f18"}, "r18" },
1633  { {"f19"}, "r19" },
1634  { {"f20"}, "r20" },
1635  { {"f21"}, "r21" },
1636  { {"f22"}, "r22" },
1637  { {"f23"}, "r23" },
1638  { {"f24"}, "r24" },
1639  { {"f25"}, "r25" },
1640  { {"f26"}, "r26" },
1641  { {"f27"}, "r27" },
1642  { {"f28"}, "r28" },
1643  { {"f29"}, "r29" },
1644  { {"f30"}, "r30" },
1645  { {"f31"}, "r31" },
1646};
1647
1648void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1649                                     unsigned &NumAliases) const {
1650  Aliases = GCCRegAliases;
1651  NumAliases = llvm::array_lengthof(GCCRegAliases);
1652}
1653} // end anonymous namespace.
1654
1655namespace {
1656// Namespace for x86 abstract base class
1657const Builtin::Info BuiltinInfo[] = {
1658#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1659#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1660                                              ALL_LANGUAGES },
1661#include "clang/Basic/BuiltinsX86.def"
1662};
1663
1664static const char* const GCCRegNames[] = {
1665  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1666  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1667  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1668  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1669  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1670  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1671  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1672  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1673  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1674};
1675
1676const TargetInfo::AddlRegName AddlRegNames[] = {
1677  { { "al", "ah", "eax", "rax" }, 0 },
1678  { { "bl", "bh", "ebx", "rbx" }, 3 },
1679  { { "cl", "ch", "ecx", "rcx" }, 2 },
1680  { { "dl", "dh", "edx", "rdx" }, 1 },
1681  { { "esi", "rsi" }, 4 },
1682  { { "edi", "rdi" }, 5 },
1683  { { "esp", "rsp" }, 7 },
1684  { { "ebp", "rbp" }, 6 },
1685};
1686
1687// X86 target abstract base class; x86-32 and x86-64 are very close, so
1688// most of the implementation can be shared.
1689class X86TargetInfo : public TargetInfo {
1690  enum X86SSEEnum {
1691    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1692  } SSELevel;
1693  enum MMX3DNowEnum {
1694    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1695  } MMX3DNowLevel;
1696
1697  bool HasAES;
1698  bool HasPCLMUL;
1699  bool HasLZCNT;
1700  bool HasRDRND;
1701  bool HasBMI;
1702  bool HasBMI2;
1703  bool HasPOPCNT;
1704  bool HasRTM;
1705  bool HasPRFCHW;
1706  bool HasRDSEED;
1707  bool HasSSE4a;
1708  bool HasFMA4;
1709  bool HasFMA;
1710  bool HasXOP;
1711  bool HasF16C;
1712
1713  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1714  ///
1715  /// Each enumeration represents a particular CPU supported by Clang. These
1716  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1717  enum CPUKind {
1718    CK_Generic,
1719
1720    /// \name i386
1721    /// i386-generation processors.
1722    //@{
1723    CK_i386,
1724    //@}
1725
1726    /// \name i486
1727    /// i486-generation processors.
1728    //@{
1729    CK_i486,
1730    CK_WinChipC6,
1731    CK_WinChip2,
1732    CK_C3,
1733    //@}
1734
1735    /// \name i586
1736    /// i586-generation processors, P5 microarchitecture based.
1737    //@{
1738    CK_i586,
1739    CK_Pentium,
1740    CK_PentiumMMX,
1741    //@}
1742
1743    /// \name i686
1744    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1745    //@{
1746    CK_i686,
1747    CK_PentiumPro,
1748    CK_Pentium2,
1749    CK_Pentium3,
1750    CK_Pentium3M,
1751    CK_PentiumM,
1752    CK_C3_2,
1753
1754    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1755    /// Clang however has some logic to suport this.
1756    // FIXME: Warn, deprecate, and potentially remove this.
1757    CK_Yonah,
1758    //@}
1759
1760    /// \name Netburst
1761    /// Netburst microarchitecture based processors.
1762    //@{
1763    CK_Pentium4,
1764    CK_Pentium4M,
1765    CK_Prescott,
1766    CK_Nocona,
1767    //@}
1768
1769    /// \name Core
1770    /// Core microarchitecture based processors.
1771    //@{
1772    CK_Core2,
1773
1774    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1775    /// codename which GCC no longer accepts as an option to -march, but Clang
1776    /// has some logic for recognizing it.
1777    // FIXME: Warn, deprecate, and potentially remove this.
1778    CK_Penryn,
1779    //@}
1780
1781    /// \name Atom
1782    /// Atom processors
1783    //@{
1784    CK_Atom,
1785    //@}
1786
1787    /// \name Nehalem
1788    /// Nehalem microarchitecture based processors.
1789    //@{
1790    CK_Corei7,
1791    CK_Corei7AVX,
1792    CK_CoreAVXi,
1793    CK_CoreAVX2,
1794    //@}
1795
1796    /// \name K6
1797    /// K6 architecture processors.
1798    //@{
1799    CK_K6,
1800    CK_K6_2,
1801    CK_K6_3,
1802    //@}
1803
1804    /// \name K7
1805    /// K7 architecture processors.
1806    //@{
1807    CK_Athlon,
1808    CK_AthlonThunderbird,
1809    CK_Athlon4,
1810    CK_AthlonXP,
1811    CK_AthlonMP,
1812    //@}
1813
1814    /// \name K8
1815    /// K8 architecture processors.
1816    //@{
1817    CK_Athlon64,
1818    CK_Athlon64SSE3,
1819    CK_AthlonFX,
1820    CK_K8,
1821    CK_K8SSE3,
1822    CK_Opteron,
1823    CK_OpteronSSE3,
1824    CK_AMDFAM10,
1825    //@}
1826
1827    /// \name Bobcat
1828    /// Bobcat architecture processors.
1829    //@{
1830    CK_BTVER1,
1831    //@}
1832
1833    /// \name Bulldozer
1834    /// Bulldozer architecture processors.
1835    //@{
1836    CK_BDVER1,
1837    CK_BDVER2,
1838    //@}
1839
1840    /// This specification is deprecated and will be removed in the future.
1841    /// Users should prefer \see CK_K8.
1842    // FIXME: Warn on this when the CPU is set to it.
1843    CK_x86_64,
1844    //@}
1845
1846    /// \name Geode
1847    /// Geode processors.
1848    //@{
1849    CK_Geode
1850    //@}
1851  } CPU;
1852
1853public:
1854  X86TargetInfo(const std::string& triple)
1855    : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1856      HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1857      HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1858      HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1859      HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1860    BigEndian = false;
1861    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1862  }
1863  virtual unsigned getFloatEvalMethod() const {
1864    // X87 evaluates with 80 bits "long double" precision.
1865    return SSELevel == NoSSE ? 2 : 0;
1866  }
1867  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1868                                 unsigned &NumRecords) const {
1869    Records = BuiltinInfo;
1870    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1871  }
1872  virtual void getGCCRegNames(const char * const *&Names,
1873                              unsigned &NumNames) const {
1874    Names = GCCRegNames;
1875    NumNames = llvm::array_lengthof(GCCRegNames);
1876  }
1877  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1878                                unsigned &NumAliases) const {
1879    Aliases = 0;
1880    NumAliases = 0;
1881  }
1882  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1883                                  unsigned &NumNames) const {
1884    Names = AddlRegNames;
1885    NumNames = llvm::array_lengthof(AddlRegNames);
1886  }
1887  virtual bool validateAsmConstraint(const char *&Name,
1888                                     TargetInfo::ConstraintInfo &info) const;
1889  virtual std::string convertConstraint(const char *&Constraint) const;
1890  virtual const char *getClobbers() const {
1891    return "~{dirflag},~{fpsr},~{flags}";
1892  }
1893  virtual void getTargetDefines(const LangOptions &Opts,
1894                                MacroBuilder &Builder) const;
1895  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1896                                 StringRef Name,
1897                                 bool Enabled) const;
1898  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1899  virtual bool hasFeature(StringRef Feature) const;
1900  virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1901  virtual const char* getABI() const {
1902    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1903      return "avx";
1904    else if (getTriple().getArch() == llvm::Triple::x86 &&
1905             MMX3DNowLevel == NoMMX3DNow)
1906      return "no-mmx";
1907    return "";
1908  }
1909  virtual bool setCPU(const std::string &Name) {
1910    CPU = llvm::StringSwitch<CPUKind>(Name)
1911      .Case("i386", CK_i386)
1912      .Case("i486", CK_i486)
1913      .Case("winchip-c6", CK_WinChipC6)
1914      .Case("winchip2", CK_WinChip2)
1915      .Case("c3", CK_C3)
1916      .Case("i586", CK_i586)
1917      .Case("pentium", CK_Pentium)
1918      .Case("pentium-mmx", CK_PentiumMMX)
1919      .Case("i686", CK_i686)
1920      .Case("pentiumpro", CK_PentiumPro)
1921      .Case("pentium2", CK_Pentium2)
1922      .Case("pentium3", CK_Pentium3)
1923      .Case("pentium3m", CK_Pentium3M)
1924      .Case("pentium-m", CK_PentiumM)
1925      .Case("c3-2", CK_C3_2)
1926      .Case("yonah", CK_Yonah)
1927      .Case("pentium4", CK_Pentium4)
1928      .Case("pentium4m", CK_Pentium4M)
1929      .Case("prescott", CK_Prescott)
1930      .Case("nocona", CK_Nocona)
1931      .Case("core2", CK_Core2)
1932      .Case("penryn", CK_Penryn)
1933      .Case("atom", CK_Atom)
1934      .Case("corei7", CK_Corei7)
1935      .Case("corei7-avx", CK_Corei7AVX)
1936      .Case("core-avx-i", CK_CoreAVXi)
1937      .Case("core-avx2", CK_CoreAVX2)
1938      .Case("k6", CK_K6)
1939      .Case("k6-2", CK_K6_2)
1940      .Case("k6-3", CK_K6_3)
1941      .Case("athlon", CK_Athlon)
1942      .Case("athlon-tbird", CK_AthlonThunderbird)
1943      .Case("athlon-4", CK_Athlon4)
1944      .Case("athlon-xp", CK_AthlonXP)
1945      .Case("athlon-mp", CK_AthlonMP)
1946      .Case("athlon64", CK_Athlon64)
1947      .Case("athlon64-sse3", CK_Athlon64SSE3)
1948      .Case("athlon-fx", CK_AthlonFX)
1949      .Case("k8", CK_K8)
1950      .Case("k8-sse3", CK_K8SSE3)
1951      .Case("opteron", CK_Opteron)
1952      .Case("opteron-sse3", CK_OpteronSSE3)
1953      .Case("amdfam10", CK_AMDFAM10)
1954      .Case("btver1", CK_BTVER1)
1955      .Case("bdver1", CK_BDVER1)
1956      .Case("bdver2", CK_BDVER2)
1957      .Case("x86-64", CK_x86_64)
1958      .Case("geode", CK_Geode)
1959      .Default(CK_Generic);
1960
1961    // Perform any per-CPU checks necessary to determine if this CPU is
1962    // acceptable.
1963    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1964    // invalid without explaining *why*.
1965    switch (CPU) {
1966    case CK_Generic:
1967      // No processor selected!
1968      return false;
1969
1970    case CK_i386:
1971    case CK_i486:
1972    case CK_WinChipC6:
1973    case CK_WinChip2:
1974    case CK_C3:
1975    case CK_i586:
1976    case CK_Pentium:
1977    case CK_PentiumMMX:
1978    case CK_i686:
1979    case CK_PentiumPro:
1980    case CK_Pentium2:
1981    case CK_Pentium3:
1982    case CK_Pentium3M:
1983    case CK_PentiumM:
1984    case CK_Yonah:
1985    case CK_C3_2:
1986    case CK_Pentium4:
1987    case CK_Pentium4M:
1988    case CK_Prescott:
1989    case CK_K6:
1990    case CK_K6_2:
1991    case CK_K6_3:
1992    case CK_Athlon:
1993    case CK_AthlonThunderbird:
1994    case CK_Athlon4:
1995    case CK_AthlonXP:
1996    case CK_AthlonMP:
1997    case CK_Geode:
1998      // Only accept certain architectures when compiling in 32-bit mode.
1999      if (getTriple().getArch() != llvm::Triple::x86)
2000        return false;
2001
2002      // Fallthrough
2003    case CK_Nocona:
2004    case CK_Core2:
2005    case CK_Penryn:
2006    case CK_Atom:
2007    case CK_Corei7:
2008    case CK_Corei7AVX:
2009    case CK_CoreAVXi:
2010    case CK_CoreAVX2:
2011    case CK_Athlon64:
2012    case CK_Athlon64SSE3:
2013    case CK_AthlonFX:
2014    case CK_K8:
2015    case CK_K8SSE3:
2016    case CK_Opteron:
2017    case CK_OpteronSSE3:
2018    case CK_AMDFAM10:
2019    case CK_BTVER1:
2020    case CK_BDVER1:
2021    case CK_BDVER2:
2022    case CK_x86_64:
2023      return true;
2024    }
2025    llvm_unreachable("Unhandled CPU kind");
2026  }
2027
2028  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2029    // We accept all non-ARM calling conventions
2030    return (CC == CC_X86ThisCall ||
2031            CC == CC_X86FastCall ||
2032            CC == CC_X86StdCall ||
2033            CC == CC_C ||
2034            CC == CC_X86Pascal ||
2035            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2036  }
2037
2038  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2039    return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2040  }
2041};
2042
2043void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2044  // FIXME: This should not be here.
2045  Features["3dnow"] = false;
2046  Features["3dnowa"] = false;
2047  Features["mmx"] = false;
2048  Features["sse"] = false;
2049  Features["sse2"] = false;
2050  Features["sse3"] = false;
2051  Features["ssse3"] = false;
2052  Features["sse41"] = false;
2053  Features["sse42"] = false;
2054  Features["sse4a"] = false;
2055  Features["aes"] = false;
2056  Features["pclmul"] = false;
2057  Features["avx"] = false;
2058  Features["avx2"] = false;
2059  Features["lzcnt"] = false;
2060  Features["rdrand"] = false;
2061  Features["bmi"] = false;
2062  Features["bmi2"] = false;
2063  Features["popcnt"] = false;
2064  Features["rtm"] = false;
2065  Features["prfchw"] = false;
2066  Features["rdseed"] = false;
2067  Features["fma4"] = false;
2068  Features["fma"] = false;
2069  Features["xop"] = false;
2070  Features["f16c"] = false;
2071
2072  // FIXME: This *really* should not be here.
2073
2074  // X86_64 always has SSE2.
2075  if (getTriple().getArch() == llvm::Triple::x86_64)
2076    setFeatureEnabled(Features, "sse2", true);
2077
2078  switch (CPU) {
2079  case CK_Generic:
2080  case CK_i386:
2081  case CK_i486:
2082  case CK_i586:
2083  case CK_Pentium:
2084  case CK_i686:
2085  case CK_PentiumPro:
2086    break;
2087  case CK_PentiumMMX:
2088  case CK_Pentium2:
2089    setFeatureEnabled(Features, "mmx", true);
2090    break;
2091  case CK_Pentium3:
2092  case CK_Pentium3M:
2093    setFeatureEnabled(Features, "sse", true);
2094    break;
2095  case CK_PentiumM:
2096  case CK_Pentium4:
2097  case CK_Pentium4M:
2098  case CK_x86_64:
2099    setFeatureEnabled(Features, "sse2", true);
2100    break;
2101  case CK_Yonah:
2102  case CK_Prescott:
2103  case CK_Nocona:
2104    setFeatureEnabled(Features, "sse3", true);
2105    break;
2106  case CK_Core2:
2107    setFeatureEnabled(Features, "ssse3", true);
2108    break;
2109  case CK_Penryn:
2110    setFeatureEnabled(Features, "sse4.1", true);
2111    break;
2112  case CK_Atom:
2113    setFeatureEnabled(Features, "ssse3", true);
2114    break;
2115  case CK_Corei7:
2116    setFeatureEnabled(Features, "sse4", true);
2117    break;
2118  case CK_Corei7AVX:
2119    setFeatureEnabled(Features, "avx", true);
2120    setFeatureEnabled(Features, "aes", true);
2121    setFeatureEnabled(Features, "pclmul", true);
2122    break;
2123  case CK_CoreAVXi:
2124    setFeatureEnabled(Features, "avx", true);
2125    setFeatureEnabled(Features, "aes", true);
2126    setFeatureEnabled(Features, "pclmul", true);
2127    setFeatureEnabled(Features, "rdrnd", true);
2128    setFeatureEnabled(Features, "f16c", true);
2129    break;
2130  case CK_CoreAVX2:
2131    setFeatureEnabled(Features, "avx2", true);
2132    setFeatureEnabled(Features, "aes", true);
2133    setFeatureEnabled(Features, "pclmul", true);
2134    setFeatureEnabled(Features, "lzcnt", true);
2135    setFeatureEnabled(Features, "rdrnd", true);
2136    setFeatureEnabled(Features, "f16c", true);
2137    setFeatureEnabled(Features, "bmi", true);
2138    setFeatureEnabled(Features, "bmi2", true);
2139    setFeatureEnabled(Features, "rtm", true);
2140    setFeatureEnabled(Features, "fma", true);
2141    break;
2142  case CK_K6:
2143  case CK_WinChipC6:
2144    setFeatureEnabled(Features, "mmx", true);
2145    break;
2146  case CK_K6_2:
2147  case CK_K6_3:
2148  case CK_WinChip2:
2149  case CK_C3:
2150    setFeatureEnabled(Features, "3dnow", true);
2151    break;
2152  case CK_Athlon:
2153  case CK_AthlonThunderbird:
2154  case CK_Geode:
2155    setFeatureEnabled(Features, "3dnowa", true);
2156    break;
2157  case CK_Athlon4:
2158  case CK_AthlonXP:
2159  case CK_AthlonMP:
2160    setFeatureEnabled(Features, "sse", true);
2161    setFeatureEnabled(Features, "3dnowa", true);
2162    break;
2163  case CK_K8:
2164  case CK_Opteron:
2165  case CK_Athlon64:
2166  case CK_AthlonFX:
2167    setFeatureEnabled(Features, "sse2", true);
2168    setFeatureEnabled(Features, "3dnowa", true);
2169    break;
2170  case CK_K8SSE3:
2171  case CK_OpteronSSE3:
2172  case CK_Athlon64SSE3:
2173    setFeatureEnabled(Features, "sse3", true);
2174    setFeatureEnabled(Features, "3dnowa", true);
2175    break;
2176  case CK_AMDFAM10:
2177    setFeatureEnabled(Features, "sse3", true);
2178    setFeatureEnabled(Features, "sse4a", true);
2179    setFeatureEnabled(Features, "3dnowa", true);
2180    setFeatureEnabled(Features, "lzcnt", true);
2181    setFeatureEnabled(Features, "popcnt", true);
2182    break;
2183  case CK_BTVER1:
2184    setFeatureEnabled(Features, "ssse3", true);
2185    setFeatureEnabled(Features, "sse4a", true);
2186    setFeatureEnabled(Features, "lzcnt", true);
2187    setFeatureEnabled(Features, "popcnt", true);
2188    break;
2189  case CK_BDVER1:
2190    setFeatureEnabled(Features, "xop", true);
2191    setFeatureEnabled(Features, "lzcnt", true);
2192    setFeatureEnabled(Features, "aes", true);
2193    setFeatureEnabled(Features, "pclmul", true);
2194    break;
2195  case CK_BDVER2:
2196    setFeatureEnabled(Features, "xop", true);
2197    setFeatureEnabled(Features, "lzcnt", true);
2198    setFeatureEnabled(Features, "aes", true);
2199    setFeatureEnabled(Features, "pclmul", true);
2200    setFeatureEnabled(Features, "bmi", true);
2201    setFeatureEnabled(Features, "fma", true);
2202    setFeatureEnabled(Features, "f16c", true);
2203    break;
2204  case CK_C3_2:
2205    setFeatureEnabled(Features, "sse", true);
2206    break;
2207  }
2208}
2209
2210bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2211                                      StringRef Name,
2212                                      bool Enabled) const {
2213  // FIXME: This *really* should not be here.  We need some way of translating
2214  // options into llvm subtarget features.
2215  if (!Features.count(Name) &&
2216      (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2217       Name != "rdrnd"))
2218    return false;
2219
2220  // FIXME: this should probably use a switch with fall through.
2221
2222  if (Enabled) {
2223    if (Name == "mmx")
2224      Features["mmx"] = true;
2225    else if (Name == "sse")
2226      Features["mmx"] = Features["sse"] = true;
2227    else if (Name == "sse2")
2228      Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2229    else if (Name == "sse3")
2230      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2231        true;
2232    else if (Name == "ssse3")
2233      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2234        Features["ssse3"] = true;
2235    else if (Name == "sse4" || Name == "sse4.2")
2236      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2237        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2238        Features["popcnt"] = true;
2239    else if (Name == "sse4.1")
2240      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2241        Features["ssse3"] = Features["sse41"] = true;
2242    else if (Name == "3dnow")
2243      Features["mmx"] = Features["3dnow"] = true;
2244    else if (Name == "3dnowa")
2245      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2246    else if (Name == "aes")
2247      Features["sse"] = Features["sse2"] = Features["aes"] = true;
2248    else if (Name == "pclmul")
2249      Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2250    else if (Name == "avx")
2251      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2252        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2253        Features["popcnt"] = Features["avx"] = true;
2254    else if (Name == "avx2")
2255      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2256        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2257        Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2258    else if (Name == "fma")
2259      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2260        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2261        Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2262    else if (Name == "fma4")
2263      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2264        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2265        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2266        Features["fma4"] = true;
2267    else if (Name == "xop")
2268      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2269        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2270        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2271        Features["fma4"] = Features["xop"] = true;
2272    else if (Name == "sse4a")
2273      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2274        Features["sse4a"] = true;
2275    else if (Name == "lzcnt")
2276      Features["lzcnt"] = true;
2277    else if (Name == "rdrnd")
2278      Features["rdrand"] = true;
2279    else if (Name == "bmi")
2280      Features["bmi"] = true;
2281    else if (Name == "bmi2")
2282      Features["bmi2"] = true;
2283    else if (Name == "popcnt")
2284      Features["popcnt"] = true;
2285    else if (Name == "f16c")
2286      Features["f16c"] = true;
2287    else if (Name == "rtm")
2288      Features["rtm"] = true;
2289    else if (Name == "prfchw")
2290      Features["prfchw"] = true;
2291    else if (Name == "rdseed")
2292      Features["rdseed"] = true;
2293  } else {
2294    if (Name == "mmx")
2295      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2296    else if (Name == "sse")
2297      Features["sse"] = Features["sse2"] = Features["sse3"] =
2298        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2299        Features["sse4a"] = Features["avx"] = Features["avx2"] =
2300        Features["fma"] = Features["fma4"] = Features["aes"] =
2301        Features["pclmul"] = Features["xop"] = false;
2302    else if (Name == "sse2")
2303      Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2304        Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2305        Features["avx"] = Features["avx2"] = Features["fma"] =
2306        Features["fma4"] = Features["aes"] = Features["pclmul"] =
2307        Features["xop"] = false;
2308    else if (Name == "sse3")
2309      Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2310        Features["sse42"] = Features["sse4a"] = Features["avx"] =
2311        Features["avx2"] = Features["fma"] = Features["fma4"] =
2312        Features["xop"] = false;
2313    else if (Name == "ssse3")
2314      Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2315        Features["avx"] = Features["avx2"] = Features["fma"] = false;
2316    else if (Name == "sse4" || Name == "sse4.1")
2317      Features["sse41"] = Features["sse42"] = Features["avx"] =
2318        Features["avx2"] = Features["fma"] = false;
2319    else if (Name == "sse4.2")
2320      Features["sse42"] = Features["avx"] = Features["avx2"] =
2321        Features["fma"] = false;
2322    else if (Name == "3dnow")
2323      Features["3dnow"] = Features["3dnowa"] = false;
2324    else if (Name == "3dnowa")
2325      Features["3dnowa"] = false;
2326    else if (Name == "aes")
2327      Features["aes"] = false;
2328    else if (Name == "pclmul")
2329      Features["pclmul"] = false;
2330    else if (Name == "avx")
2331      Features["avx"] = Features["avx2"] = Features["fma"] =
2332        Features["fma4"] = Features["xop"] = false;
2333    else if (Name == "avx2")
2334      Features["avx2"] = false;
2335    else if (Name == "fma")
2336      Features["fma"] = false;
2337    else if (Name == "sse4a")
2338      Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2339    else if (Name == "lzcnt")
2340      Features["lzcnt"] = false;
2341    else if (Name == "rdrnd")
2342      Features["rdrand"] = false;
2343    else if (Name == "bmi")
2344      Features["bmi"] = false;
2345    else if (Name == "bmi2")
2346      Features["bmi2"] = false;
2347    else if (Name == "popcnt")
2348      Features["popcnt"] = false;
2349    else if (Name == "fma4")
2350      Features["fma4"] = Features["xop"] = false;
2351    else if (Name == "xop")
2352      Features["xop"] = false;
2353    else if (Name == "f16c")
2354      Features["f16c"] = false;
2355    else if (Name == "rtm")
2356      Features["rtm"] = false;
2357    else if (Name == "prfchw")
2358      Features["prfchw"] = false;
2359    else if (Name == "rdseed")
2360      Features["rdseed"] = false;
2361  }
2362
2363  return true;
2364}
2365
2366/// HandleTargetOptions - Perform initialization based on the user
2367/// configured set of features.
2368void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2369  // Remember the maximum enabled sselevel.
2370  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2371    // Ignore disabled features.
2372    if (Features[i][0] == '-')
2373      continue;
2374
2375    StringRef Feature = StringRef(Features[i]).substr(1);
2376
2377    if (Feature == "aes") {
2378      HasAES = true;
2379      continue;
2380    }
2381
2382    if (Feature == "pclmul") {
2383      HasPCLMUL = true;
2384      continue;
2385    }
2386
2387    if (Feature == "lzcnt") {
2388      HasLZCNT = true;
2389      continue;
2390    }
2391
2392    if (Feature == "rdrand") {
2393      HasRDRND = true;
2394      continue;
2395    }
2396
2397    if (Feature == "bmi") {
2398      HasBMI = true;
2399      continue;
2400    }
2401
2402    if (Feature == "bmi2") {
2403      HasBMI2 = true;
2404      continue;
2405    }
2406
2407    if (Feature == "popcnt") {
2408      HasPOPCNT = true;
2409      continue;
2410    }
2411
2412    if (Feature == "rtm") {
2413      HasRTM = true;
2414      continue;
2415    }
2416
2417    if (Feature == "prfchw") {
2418      HasPRFCHW = true;
2419      continue;
2420    }
2421
2422    if (Feature == "rdseed") {
2423      HasRDSEED = true;
2424      continue;
2425    }
2426
2427    if (Feature == "sse4a") {
2428      HasSSE4a = true;
2429      continue;
2430    }
2431
2432    if (Feature == "fma4") {
2433      HasFMA4 = true;
2434      continue;
2435    }
2436
2437    if (Feature == "fma") {
2438      HasFMA = true;
2439      continue;
2440    }
2441
2442    if (Feature == "xop") {
2443      HasXOP = true;
2444      continue;
2445    }
2446
2447    if (Feature == "f16c") {
2448      HasF16C = true;
2449      continue;
2450    }
2451
2452    assert(Features[i][0] == '+' && "Invalid target feature!");
2453    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2454      .Case("avx2", AVX2)
2455      .Case("avx", AVX)
2456      .Case("sse42", SSE42)
2457      .Case("sse41", SSE41)
2458      .Case("ssse3", SSSE3)
2459      .Case("sse3", SSE3)
2460      .Case("sse2", SSE2)
2461      .Case("sse", SSE1)
2462      .Default(NoSSE);
2463    SSELevel = std::max(SSELevel, Level);
2464
2465    MMX3DNowEnum ThreeDNowLevel =
2466      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2467        .Case("3dnowa", AMD3DNowAthlon)
2468        .Case("3dnow", AMD3DNow)
2469        .Case("mmx", MMX)
2470        .Default(NoMMX3DNow);
2471
2472    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2473  }
2474
2475  // Don't tell the backend if we're turning off mmx; it will end up disabling
2476  // SSE, which we don't want.
2477  std::vector<std::string>::iterator it;
2478  it = std::find(Features.begin(), Features.end(), "-mmx");
2479  if (it != Features.end())
2480    Features.erase(it);
2481}
2482
2483/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2484/// definitions for this particular subtarget.
2485void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2486                                     MacroBuilder &Builder) const {
2487  // Target identification.
2488  if (getTriple().getArch() == llvm::Triple::x86_64) {
2489    Builder.defineMacro("__amd64__");
2490    Builder.defineMacro("__amd64");
2491    Builder.defineMacro("__x86_64");
2492    Builder.defineMacro("__x86_64__");
2493  } else {
2494    DefineStd(Builder, "i386", Opts);
2495  }
2496
2497  // Subtarget options.
2498  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2499  // truly should be based on -mtune options.
2500  switch (CPU) {
2501  case CK_Generic:
2502    break;
2503  case CK_i386:
2504    // The rest are coming from the i386 define above.
2505    Builder.defineMacro("__tune_i386__");
2506    break;
2507  case CK_i486:
2508  case CK_WinChipC6:
2509  case CK_WinChip2:
2510  case CK_C3:
2511    defineCPUMacros(Builder, "i486");
2512    break;
2513  case CK_PentiumMMX:
2514    Builder.defineMacro("__pentium_mmx__");
2515    Builder.defineMacro("__tune_pentium_mmx__");
2516    // Fallthrough
2517  case CK_i586:
2518  case CK_Pentium:
2519    defineCPUMacros(Builder, "i586");
2520    defineCPUMacros(Builder, "pentium");
2521    break;
2522  case CK_Pentium3:
2523  case CK_Pentium3M:
2524  case CK_PentiumM:
2525    Builder.defineMacro("__tune_pentium3__");
2526    // Fallthrough
2527  case CK_Pentium2:
2528  case CK_C3_2:
2529    Builder.defineMacro("__tune_pentium2__");
2530    // Fallthrough
2531  case CK_PentiumPro:
2532    Builder.defineMacro("__tune_i686__");
2533    Builder.defineMacro("__tune_pentiumpro__");
2534    // Fallthrough
2535  case CK_i686:
2536    Builder.defineMacro("__i686");
2537    Builder.defineMacro("__i686__");
2538    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2539    Builder.defineMacro("__pentiumpro");
2540    Builder.defineMacro("__pentiumpro__");
2541    break;
2542  case CK_Pentium4:
2543  case CK_Pentium4M:
2544    defineCPUMacros(Builder, "pentium4");
2545    break;
2546  case CK_Yonah:
2547  case CK_Prescott:
2548  case CK_Nocona:
2549    defineCPUMacros(Builder, "nocona");
2550    break;
2551  case CK_Core2:
2552  case CK_Penryn:
2553    defineCPUMacros(Builder, "core2");
2554    break;
2555  case CK_Atom:
2556    defineCPUMacros(Builder, "atom");
2557    break;
2558  case CK_Corei7:
2559  case CK_Corei7AVX:
2560  case CK_CoreAVXi:
2561  case CK_CoreAVX2:
2562    defineCPUMacros(Builder, "corei7");
2563    break;
2564  case CK_K6_2:
2565    Builder.defineMacro("__k6_2__");
2566    Builder.defineMacro("__tune_k6_2__");
2567    // Fallthrough
2568  case CK_K6_3:
2569    if (CPU != CK_K6_2) {  // In case of fallthrough
2570      // FIXME: GCC may be enabling these in cases where some other k6
2571      // architecture is specified but -m3dnow is explicitly provided. The
2572      // exact semantics need to be determined and emulated here.
2573      Builder.defineMacro("__k6_3__");
2574      Builder.defineMacro("__tune_k6_3__");
2575    }
2576    // Fallthrough
2577  case CK_K6:
2578    defineCPUMacros(Builder, "k6");
2579    break;
2580  case CK_Athlon:
2581  case CK_AthlonThunderbird:
2582  case CK_Athlon4:
2583  case CK_AthlonXP:
2584  case CK_AthlonMP:
2585    defineCPUMacros(Builder, "athlon");
2586    if (SSELevel != NoSSE) {
2587      Builder.defineMacro("__athlon_sse__");
2588      Builder.defineMacro("__tune_athlon_sse__");
2589    }
2590    break;
2591  case CK_K8:
2592  case CK_K8SSE3:
2593  case CK_x86_64:
2594  case CK_Opteron:
2595  case CK_OpteronSSE3:
2596  case CK_Athlon64:
2597  case CK_Athlon64SSE3:
2598  case CK_AthlonFX:
2599    defineCPUMacros(Builder, "k8");
2600    break;
2601  case CK_AMDFAM10:
2602    defineCPUMacros(Builder, "amdfam10");
2603    break;
2604  case CK_BTVER1:
2605    defineCPUMacros(Builder, "btver1");
2606    break;
2607  case CK_BDVER1:
2608    defineCPUMacros(Builder, "bdver1");
2609    break;
2610  case CK_BDVER2:
2611    defineCPUMacros(Builder, "bdver2");
2612    break;
2613  case CK_Geode:
2614    defineCPUMacros(Builder, "geode");
2615    break;
2616  }
2617
2618  // Target properties.
2619  Builder.defineMacro("__LITTLE_ENDIAN__");
2620  Builder.defineMacro("__REGISTER_PREFIX__", "");
2621
2622  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2623  // functions in glibc header files that use FP Stack inline asm which the
2624  // backend can't deal with (PR879).
2625  Builder.defineMacro("__NO_MATH_INLINES");
2626
2627  if (HasAES)
2628    Builder.defineMacro("__AES__");
2629
2630  if (HasPCLMUL)
2631    Builder.defineMacro("__PCLMUL__");
2632
2633  if (HasLZCNT)
2634    Builder.defineMacro("__LZCNT__");
2635
2636  if (HasRDRND)
2637    Builder.defineMacro("__RDRND__");
2638
2639  if (HasBMI)
2640    Builder.defineMacro("__BMI__");
2641
2642  if (HasBMI2)
2643    Builder.defineMacro("__BMI2__");
2644
2645  if (HasPOPCNT)
2646    Builder.defineMacro("__POPCNT__");
2647
2648  if (HasRTM)
2649    Builder.defineMacro("__RTM__");
2650
2651  if (HasPRFCHW)
2652    Builder.defineMacro("__PRFCHW__");
2653
2654  if (HasRDSEED)
2655    Builder.defineMacro("__RDSEED__");
2656
2657  if (HasSSE4a)
2658    Builder.defineMacro("__SSE4A__");
2659
2660  if (HasFMA4)
2661    Builder.defineMacro("__FMA4__");
2662
2663  if (HasFMA)
2664    Builder.defineMacro("__FMA__");
2665
2666  if (HasXOP)
2667    Builder.defineMacro("__XOP__");
2668
2669  if (HasF16C)
2670    Builder.defineMacro("__F16C__");
2671
2672  // Each case falls through to the previous one here.
2673  switch (SSELevel) {
2674  case AVX2:
2675    Builder.defineMacro("__AVX2__");
2676  case AVX:
2677    Builder.defineMacro("__AVX__");
2678  case SSE42:
2679    Builder.defineMacro("__SSE4_2__");
2680  case SSE41:
2681    Builder.defineMacro("__SSE4_1__");
2682  case SSSE3:
2683    Builder.defineMacro("__SSSE3__");
2684  case SSE3:
2685    Builder.defineMacro("__SSE3__");
2686  case SSE2:
2687    Builder.defineMacro("__SSE2__");
2688    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2689  case SSE1:
2690    Builder.defineMacro("__SSE__");
2691    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2692  case NoSSE:
2693    break;
2694  }
2695
2696  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2697    switch (SSELevel) {
2698    case AVX2:
2699    case AVX:
2700    case SSE42:
2701    case SSE41:
2702    case SSSE3:
2703    case SSE3:
2704    case SSE2:
2705      Builder.defineMacro("_M_IX86_FP", Twine(2));
2706      break;
2707    case SSE1:
2708      Builder.defineMacro("_M_IX86_FP", Twine(1));
2709      break;
2710    default:
2711      Builder.defineMacro("_M_IX86_FP", Twine(0));
2712    }
2713  }
2714
2715  // Each case falls through to the previous one here.
2716  switch (MMX3DNowLevel) {
2717  case AMD3DNowAthlon:
2718    Builder.defineMacro("__3dNOW_A__");
2719  case AMD3DNow:
2720    Builder.defineMacro("__3dNOW__");
2721  case MMX:
2722    Builder.defineMacro("__MMX__");
2723  case NoMMX3DNow:
2724    break;
2725  }
2726}
2727
2728bool X86TargetInfo::hasFeature(StringRef Feature) const {
2729  return llvm::StringSwitch<bool>(Feature)
2730      .Case("aes", HasAES)
2731      .Case("avx", SSELevel >= AVX)
2732      .Case("avx2", SSELevel >= AVX2)
2733      .Case("bmi", HasBMI)
2734      .Case("bmi2", HasBMI2)
2735      .Case("fma", HasFMA)
2736      .Case("fma4", HasFMA4)
2737      .Case("lzcnt", HasLZCNT)
2738      .Case("rdrnd", HasRDRND)
2739      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2740      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2741      .Case("mmx", MMX3DNowLevel >= MMX)
2742      .Case("pclmul", HasPCLMUL)
2743      .Case("popcnt", HasPOPCNT)
2744      .Case("rtm", HasRTM)
2745      .Case("prfchw", HasPRFCHW)
2746      .Case("rdseed", HasRDSEED)
2747      .Case("sse", SSELevel >= SSE1)
2748      .Case("sse2", SSELevel >= SSE2)
2749      .Case("sse3", SSELevel >= SSE3)
2750      .Case("ssse3", SSELevel >= SSSE3)
2751      .Case("sse41", SSELevel >= SSE41)
2752      .Case("sse42", SSELevel >= SSE42)
2753      .Case("sse4a", HasSSE4a)
2754      .Case("x86", true)
2755      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2756      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2757      .Case("xop", HasXOP)
2758      .Case("f16c", HasF16C)
2759      .Default(false);
2760}
2761
2762bool
2763X86TargetInfo::validateAsmConstraint(const char *&Name,
2764                                     TargetInfo::ConstraintInfo &Info) const {
2765  switch (*Name) {
2766  default: return false;
2767  case 'Y': // first letter of a pair:
2768    switch (*(Name+1)) {
2769    default: return false;
2770    case '0':  // First SSE register.
2771    case 't':  // Any SSE register, when SSE2 is enabled.
2772    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2773    case 'm':  // any MMX register, when inter-unit moves enabled.
2774      break;   // falls through to setAllowsRegister.
2775  }
2776  case 'a': // eax.
2777  case 'b': // ebx.
2778  case 'c': // ecx.
2779  case 'd': // edx.
2780  case 'S': // esi.
2781  case 'D': // edi.
2782  case 'A': // edx:eax.
2783  case 'f': // any x87 floating point stack register.
2784  case 't': // top of floating point stack.
2785  case 'u': // second from top of floating point stack.
2786  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2787  case 'y': // Any MMX register.
2788  case 'x': // Any SSE register.
2789  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2790  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2791  case 'l': // "Index" registers: any general register that can be used as an
2792            // index in a base+index memory access.
2793    Info.setAllowsRegister();
2794    return true;
2795  case 'C': // SSE floating point constant.
2796  case 'G': // x87 floating point constant.
2797  case 'e': // 32-bit signed integer constant for use with zero-extending
2798            // x86_64 instructions.
2799  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2800            // x86_64 instructions.
2801    return true;
2802  }
2803}
2804
2805
2806std::string
2807X86TargetInfo::convertConstraint(const char *&Constraint) const {
2808  switch (*Constraint) {
2809  case 'a': return std::string("{ax}");
2810  case 'b': return std::string("{bx}");
2811  case 'c': return std::string("{cx}");
2812  case 'd': return std::string("{dx}");
2813  case 'S': return std::string("{si}");
2814  case 'D': return std::string("{di}");
2815  case 'p': // address
2816    return std::string("im");
2817  case 't': // top of floating point stack.
2818    return std::string("{st}");
2819  case 'u': // second from top of floating point stack.
2820    return std::string("{st(1)}"); // second from top of floating point stack.
2821  default:
2822    return std::string(1, *Constraint);
2823  }
2824}
2825} // end anonymous namespace
2826
2827namespace {
2828// X86-32 generic target
2829class X86_32TargetInfo : public X86TargetInfo {
2830public:
2831  X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2832    DoubleAlign = LongLongAlign = 32;
2833    LongDoubleWidth = 96;
2834    LongDoubleAlign = 32;
2835    SuitableAlign = 128;
2836    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2837                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2838                        "a0:0:64-f80:32:32-n8:16:32-S128";
2839    SizeType = UnsignedInt;
2840    PtrDiffType = SignedInt;
2841    IntPtrType = SignedInt;
2842    RegParmMax = 3;
2843
2844    // Use fpret for all types.
2845    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2846                             (1 << TargetInfo::Double) |
2847                             (1 << TargetInfo::LongDouble));
2848
2849    // x86-32 has atomics up to 8 bytes
2850    // FIXME: Check that we actually have cmpxchg8b before setting
2851    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2852    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2853  }
2854  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2855    return TargetInfo::CharPtrBuiltinVaList;
2856  }
2857
2858  int getEHDataRegisterNumber(unsigned RegNo) const {
2859    if (RegNo == 0) return 0;
2860    if (RegNo == 1) return 2;
2861    return -1;
2862  }
2863  virtual bool validateInputSize(StringRef Constraint,
2864                                 unsigned Size) const {
2865    switch (Constraint[0]) {
2866    default: break;
2867    case 'a':
2868    case 'b':
2869    case 'c':
2870    case 'd':
2871      return Size <= 32;
2872    }
2873
2874    return true;
2875  }
2876};
2877} // end anonymous namespace
2878
2879namespace {
2880class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2881public:
2882  NetBSDI386TargetInfo(const std::string &triple) :
2883    NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2884  }
2885
2886  virtual unsigned getFloatEvalMethod() const {
2887    // NetBSD defaults to "double" rounding
2888    return 1;
2889  }
2890};
2891} // end anonymous namespace
2892
2893namespace {
2894class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2895public:
2896  OpenBSDI386TargetInfo(const std::string& triple) :
2897    OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2898    SizeType = UnsignedLong;
2899    IntPtrType = SignedLong;
2900    PtrDiffType = SignedLong;
2901  }
2902};
2903} // end anonymous namespace
2904
2905namespace {
2906class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2907public:
2908  BitrigI386TargetInfo(const std::string& triple) :
2909    BitrigTargetInfo<X86_32TargetInfo>(triple) {
2910    SizeType = UnsignedLong;
2911    IntPtrType = SignedLong;
2912    PtrDiffType = SignedLong;
2913  }
2914};
2915} // end anonymous namespace
2916
2917namespace {
2918class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2919public:
2920  DarwinI386TargetInfo(const std::string& triple) :
2921    DarwinTargetInfo<X86_32TargetInfo>(triple) {
2922    LongDoubleWidth = 128;
2923    LongDoubleAlign = 128;
2924    SuitableAlign = 128;
2925    MaxVectorAlign = 256;
2926    SizeType = UnsignedLong;
2927    IntPtrType = SignedLong;
2928    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2929                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2930                        "a0:0:64-f80:128:128-n8:16:32-S128";
2931    HasAlignMac68kSupport = true;
2932  }
2933
2934};
2935} // end anonymous namespace
2936
2937namespace {
2938// x86-32 Windows target
2939class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2940public:
2941  WindowsX86_32TargetInfo(const std::string& triple)
2942    : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2943    TLSSupported = false;
2944    WCharType = UnsignedShort;
2945    DoubleAlign = LongLongAlign = 64;
2946    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2947                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2948                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2949  }
2950  virtual void getTargetDefines(const LangOptions &Opts,
2951                                MacroBuilder &Builder) const {
2952    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2953  }
2954};
2955} // end anonymous namespace
2956
2957namespace {
2958
2959// x86-32 Windows Visual Studio target
2960class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2961public:
2962  VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2963    : WindowsX86_32TargetInfo(triple) {
2964    LongDoubleWidth = LongDoubleAlign = 64;
2965    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2966  }
2967  virtual void getTargetDefines(const LangOptions &Opts,
2968                                MacroBuilder &Builder) const {
2969    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2970    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2971    // The value of the following reflects processor type.
2972    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2973    // We lost the original triple, so we use the default.
2974    Builder.defineMacro("_M_IX86", "600");
2975  }
2976};
2977} // end anonymous namespace
2978
2979namespace {
2980// x86-32 MinGW target
2981class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
2982public:
2983  MinGWX86_32TargetInfo(const std::string& triple)
2984    : WindowsX86_32TargetInfo(triple) {
2985  }
2986  virtual void getTargetDefines(const LangOptions &Opts,
2987                                MacroBuilder &Builder) const {
2988    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2989    DefineStd(Builder, "WIN32", Opts);
2990    DefineStd(Builder, "WINNT", Opts);
2991    Builder.defineMacro("_X86_");
2992    Builder.defineMacro("__MSVCRT__");
2993    Builder.defineMacro("__MINGW32__");
2994
2995    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
2996    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
2997    if (Opts.MicrosoftExt)
2998      // Provide "as-is" __declspec.
2999      Builder.defineMacro("__declspec", "__declspec");
3000    else
3001      // Provide alias of __attribute__ like mingw32-gcc.
3002      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3003  }
3004};
3005} // end anonymous namespace
3006
3007namespace {
3008// x86-32 Cygwin target
3009class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3010public:
3011  CygwinX86_32TargetInfo(const std::string& triple)
3012    : X86_32TargetInfo(triple) {
3013    TLSSupported = false;
3014    WCharType = UnsignedShort;
3015    DoubleAlign = LongLongAlign = 64;
3016    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3017                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3018                        "a0:0:64-f80:32:32-n8:16:32-S32";
3019  }
3020  virtual void getTargetDefines(const LangOptions &Opts,
3021                                MacroBuilder &Builder) const {
3022    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3023    Builder.defineMacro("_X86_");
3024    Builder.defineMacro("__CYGWIN__");
3025    Builder.defineMacro("__CYGWIN32__");
3026    DefineStd(Builder, "unix", Opts);
3027    if (Opts.CPlusPlus)
3028      Builder.defineMacro("_GNU_SOURCE");
3029  }
3030};
3031} // end anonymous namespace
3032
3033namespace {
3034// x86-32 Haiku target
3035class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3036public:
3037  HaikuX86_32TargetInfo(const std::string& triple)
3038    : X86_32TargetInfo(triple) {
3039    SizeType = UnsignedLong;
3040    IntPtrType = SignedLong;
3041    PtrDiffType = SignedLong;
3042    ProcessIDType = SignedLong;
3043    this->UserLabelPrefix = "";
3044    this->TLSSupported = false;
3045  }
3046  virtual void getTargetDefines(const LangOptions &Opts,
3047                                MacroBuilder &Builder) const {
3048    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3049    Builder.defineMacro("__INTEL__");
3050    Builder.defineMacro("__HAIKU__");
3051  }
3052};
3053} // end anonymous namespace
3054
3055// RTEMS Target
3056template<typename Target>
3057class RTEMSTargetInfo : public OSTargetInfo<Target> {
3058protected:
3059  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3060                            MacroBuilder &Builder) const {
3061    // RTEMS defines; list based off of gcc output
3062
3063    Builder.defineMacro("__rtems__");
3064    Builder.defineMacro("__ELF__");
3065  }
3066public:
3067  RTEMSTargetInfo(const std::string &triple)
3068    : OSTargetInfo<Target>(triple) {
3069      this->UserLabelPrefix = "";
3070
3071      llvm::Triple Triple(triple);
3072      switch (Triple.getArch()) {
3073        default:
3074        case llvm::Triple::x86:
3075          // this->MCountName = ".mcount";
3076          break;
3077        case llvm::Triple::mips:
3078        case llvm::Triple::mipsel:
3079        case llvm::Triple::ppc:
3080        case llvm::Triple::ppc64:
3081          // this->MCountName = "_mcount";
3082          break;
3083        case llvm::Triple::arm:
3084          // this->MCountName = "__mcount";
3085          break;
3086      }
3087
3088    }
3089};
3090
3091namespace {
3092// x86-32 RTEMS target
3093class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3094public:
3095  RTEMSX86_32TargetInfo(const std::string& triple)
3096    : X86_32TargetInfo(triple) {
3097    SizeType = UnsignedLong;
3098    IntPtrType = SignedLong;
3099    PtrDiffType = SignedLong;
3100    this->UserLabelPrefix = "";
3101  }
3102  virtual void getTargetDefines(const LangOptions &Opts,
3103                                MacroBuilder &Builder) const {
3104    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3105    Builder.defineMacro("__INTEL__");
3106    Builder.defineMacro("__rtems__");
3107  }
3108};
3109} // end anonymous namespace
3110
3111namespace {
3112// x86-64 generic target
3113class X86_64TargetInfo : public X86TargetInfo {
3114public:
3115  X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
3116    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3117    LongDoubleWidth = 128;
3118    LongDoubleAlign = 128;
3119    LargeArrayMinWidth = 128;
3120    LargeArrayAlign = 128;
3121    SuitableAlign = 128;
3122    IntMaxType = SignedLong;
3123    UIntMaxType = UnsignedLong;
3124    Int64Type = SignedLong;
3125    RegParmMax = 6;
3126
3127    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3128                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3129                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3130
3131    // Use fpret only for long double.
3132    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3133
3134    // Use fp2ret for _Complex long double.
3135    ComplexLongDoubleUsesFP2Ret = true;
3136
3137    // x86-64 has atomics up to 16 bytes.
3138    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3139    // on CPUs with cmpxchg16b
3140    MaxAtomicPromoteWidth = 128;
3141    MaxAtomicInlineWidth = 64;
3142  }
3143  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3144    return TargetInfo::X86_64ABIBuiltinVaList;
3145  }
3146
3147  int getEHDataRegisterNumber(unsigned RegNo) const {
3148    if (RegNo == 0) return 0;
3149    if (RegNo == 1) return 1;
3150    return -1;
3151  }
3152
3153  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3154    return (CC == CC_Default ||
3155            CC == CC_C ||
3156            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3157  }
3158
3159  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3160    return CC_C;
3161  }
3162
3163};
3164} // end anonymous namespace
3165
3166namespace {
3167// x86-64 Windows target
3168class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3169public:
3170  WindowsX86_64TargetInfo(const std::string& triple)
3171    : WindowsTargetInfo<X86_64TargetInfo>(triple) {
3172    TLSSupported = false;
3173    WCharType = UnsignedShort;
3174    LongWidth = LongAlign = 32;
3175    DoubleAlign = LongLongAlign = 64;
3176    IntMaxType = SignedLongLong;
3177    UIntMaxType = UnsignedLongLong;
3178    Int64Type = SignedLongLong;
3179    SizeType = UnsignedLongLong;
3180    PtrDiffType = SignedLongLong;
3181    IntPtrType = SignedLongLong;
3182    this->UserLabelPrefix = "";
3183  }
3184  virtual void getTargetDefines(const LangOptions &Opts,
3185                                MacroBuilder &Builder) const {
3186    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3187    Builder.defineMacro("_WIN64");
3188  }
3189  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3190    return TargetInfo::CharPtrBuiltinVaList;
3191  }
3192};
3193} // end anonymous namespace
3194
3195namespace {
3196// x86-64 Windows Visual Studio target
3197class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3198public:
3199  VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
3200    : WindowsX86_64TargetInfo(triple) {
3201    LongDoubleWidth = LongDoubleAlign = 64;
3202    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3203  }
3204  virtual void getTargetDefines(const LangOptions &Opts,
3205                                MacroBuilder &Builder) const {
3206    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3207    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3208    Builder.defineMacro("_M_X64");
3209    Builder.defineMacro("_M_AMD64");
3210  }
3211};
3212} // end anonymous namespace
3213
3214namespace {
3215// x86-64 MinGW target
3216class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3217public:
3218  MinGWX86_64TargetInfo(const std::string& triple)
3219    : WindowsX86_64TargetInfo(triple) {
3220  }
3221  virtual void getTargetDefines(const LangOptions &Opts,
3222                                MacroBuilder &Builder) const {
3223    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3224    DefineStd(Builder, "WIN64", Opts);
3225    Builder.defineMacro("__MSVCRT__");
3226    Builder.defineMacro("__MINGW32__");
3227    Builder.defineMacro("__MINGW64__");
3228
3229    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3230    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3231    if (Opts.MicrosoftExt)
3232      // Provide "as-is" __declspec.
3233      Builder.defineMacro("__declspec", "__declspec");
3234    else
3235      // Provide alias of __attribute__ like mingw32-gcc.
3236      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3237  }
3238};
3239} // end anonymous namespace
3240
3241namespace {
3242class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3243public:
3244  DarwinX86_64TargetInfo(const std::string& triple)
3245      : DarwinTargetInfo<X86_64TargetInfo>(triple) {
3246    Int64Type = SignedLongLong;
3247    MaxVectorAlign = 256;
3248  }
3249};
3250} // end anonymous namespace
3251
3252namespace {
3253class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3254public:
3255  OpenBSDX86_64TargetInfo(const std::string& triple)
3256      : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
3257    IntMaxType = SignedLongLong;
3258    UIntMaxType = UnsignedLongLong;
3259    Int64Type = SignedLongLong;
3260  }
3261};
3262} // end anonymous namespace
3263
3264namespace {
3265class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3266public:
3267  BitrigX86_64TargetInfo(const std::string& triple)
3268      : BitrigTargetInfo<X86_64TargetInfo>(triple) {
3269     IntMaxType = SignedLongLong;
3270     UIntMaxType = UnsignedLongLong;
3271     Int64Type = SignedLongLong;
3272  }
3273};
3274}
3275
3276namespace {
3277class AArch64TargetInfo : public TargetInfo {
3278  static const char * const GCCRegNames[];
3279  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3280public:
3281  AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) {
3282    BigEndian = false;
3283    LongWidth = LongAlign = 64;
3284    LongDoubleWidth = LongDoubleAlign = 128;
3285    PointerWidth = PointerAlign = 64;
3286    SuitableAlign = 128;
3287    DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3288                        "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3289                        "f128:128:128-n32:64-S128";
3290
3291    WCharType = UnsignedInt;
3292    LongDoubleFormat = &llvm::APFloat::IEEEquad;
3293
3294    // AArch64 backend supports 64-bit operations at the moment. In principle
3295    // 128-bit is possible if register-pairs are used.
3296    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3297
3298    TheCXXABI.set(TargetCXXABI::GenericAArch64);
3299  }
3300  virtual void getTargetDefines(const LangOptions &Opts,
3301                                MacroBuilder &Builder) const {
3302    // GCC defines theses currently
3303    Builder.defineMacro("__aarch64__");
3304    Builder.defineMacro("__AARCH64EL__");
3305
3306    // ACLE predefines. Many can only have one possible value on v8 AArch64.
3307
3308    // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3309    // which was intended to be compatible with a 64-bit implementation. They
3310    // will need updating when a real 64-bit ACLE exists. Particularly pressing
3311    // instances are: __AARCH_ISA_A32, __AARCH_ISA_T32, __ARCH_PCS.
3312    Builder.defineMacro("__AARCH_ACLE",    "101");
3313    Builder.defineMacro("__AARCH",         "8");
3314    Builder.defineMacro("__AARCH_PROFILE", "'A'");
3315
3316    Builder.defineMacro("__AARCH_FEATURE_UNALIGNED");
3317    Builder.defineMacro("__AARCH_FEATURE_CLZ");
3318    Builder.defineMacro("__AARCH_FEATURE_FMA");
3319
3320    // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3321    // 128-bit LDXP present, at which point this becomes 0x1f.
3322    Builder.defineMacro("__AARCH_FEATURE_LDREX", "0xf");
3323
3324    // 0xe implies support for half, single and double precision operations.
3325    Builder.defineMacro("__AARCH_FP", "0xe");
3326
3327    // PCS specifies this for SysV variants, which is all we support. Other ABIs
3328    // may choose __AARCH_FP16_FORMAT_ALTERNATIVE.
3329    Builder.defineMacro("__AARCH_FP16_FORMAT_IEEE");
3330
3331    if (Opts.FastMath || Opts.FiniteMathOnly)
3332      Builder.defineMacro("__AARCH_FP_FAST");
3333
3334    if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3335      Builder.defineMacro("__AARCH_FP_FENV_ROUNDING");
3336
3337    Builder.defineMacro("__AARCH_SIZEOF_WCHAR_T",
3338                        Opts.ShortWChar ? "2" : "4");
3339
3340    Builder.defineMacro("__AARCH_SIZEOF_MINIMAL_ENUM",
3341                        Opts.ShortEnums ? "1" : "4");
3342
3343    if (BigEndian)
3344      Builder.defineMacro("__AARCH_BIG_ENDIAN");
3345  }
3346  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3347                                 unsigned &NumRecords) const {
3348    Records = 0;
3349    NumRecords = 0;
3350  }
3351  virtual bool hasFeature(StringRef Feature) const {
3352    return Feature == "aarch64";
3353  }
3354  virtual void getGCCRegNames(const char * const *&Names,
3355                              unsigned &NumNames) const;
3356  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3357                                unsigned &NumAliases) const;
3358
3359  virtual bool isCLZForZeroUndef() const { return false; }
3360
3361  virtual bool validateAsmConstraint(const char *&Name,
3362                                     TargetInfo::ConstraintInfo &Info) const {
3363    switch (*Name) {
3364    default: return false;
3365    case 'w': // An FP/SIMD vector register
3366      Info.setAllowsRegister();
3367      return true;
3368    case 'I': // Constant that can be used with an ADD instruction
3369    case 'J': // Constant that can be used with a SUB instruction
3370    case 'K': // Constant that can be used with a 32-bit logical instruction
3371    case 'L': // Constant that can be used with a 64-bit logical instruction
3372    case 'M': // Constant that can be used as a 32-bit MOV immediate
3373    case 'N': // Constant that can be used as a 64-bit MOV immediate
3374    case 'Y': // Floating point constant zero
3375    case 'Z': // Integer constant zero
3376      return true;
3377    case 'Q': // A memory reference with base register and no offset
3378      Info.setAllowsMemory();
3379      return true;
3380    case 'S': // A symbolic address
3381      Info.setAllowsRegister();
3382      return true;
3383    case 'U':
3384      // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3385      // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3386      // Usa: An absolute symbolic address
3387      // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3388      llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3389    }
3390  }
3391
3392  virtual const char *getClobbers() const {
3393    // There are no AArch64 clobbers shared by all asm statements.
3394    return "";
3395  }
3396
3397  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3398    return TargetInfo::AArch64ABIBuiltinVaList;
3399  }
3400};
3401
3402const char * const AArch64TargetInfo::GCCRegNames[] = {
3403  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3404  "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3405  "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3406  "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3407
3408  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3409  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3410  "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3411  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3412
3413  "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3414  "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3415  "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3416  "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3417
3418  "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3419  "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3420  "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3421  "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3422
3423  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3424  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3425  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3426  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3427
3428  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3429  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3430  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3431  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3432
3433  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3434  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3435  "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3436  "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3437};
3438
3439void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3440                                       unsigned &NumNames) const {
3441  Names = GCCRegNames;
3442  NumNames = llvm::array_lengthof(GCCRegNames);
3443}
3444
3445const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3446  { { "x16" }, "ip0"},
3447  { { "x17" }, "ip1"},
3448  { { "x29" }, "fp" },
3449  { { "x30" }, "lr" }
3450};
3451
3452void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3453                                         unsigned &NumAliases) const {
3454  Aliases = GCCRegAliases;
3455  NumAliases = llvm::array_lengthof(GCCRegAliases);
3456
3457}
3458} // end anonymous namespace
3459
3460namespace {
3461class ARMTargetInfo : public TargetInfo {
3462  // Possible FPU choices.
3463  enum FPUMode {
3464    VFP2FPU = (1 << 0),
3465    VFP3FPU = (1 << 1),
3466    VFP4FPU = (1 << 2),
3467    NeonFPU = (1 << 3)
3468  };
3469
3470  static bool FPUModeIsVFP(FPUMode Mode) {
3471    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3472  }
3473
3474  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3475  static const char * const GCCRegNames[];
3476
3477  std::string ABI, CPU;
3478
3479  unsigned FPU : 4;
3480
3481  unsigned IsAAPCS : 1;
3482  unsigned IsThumb : 1;
3483
3484  // Initialized via features.
3485  unsigned SoftFloat : 1;
3486  unsigned SoftFloatABI : 1;
3487
3488  static const Builtin::Info BuiltinInfo[];
3489
3490public:
3491  ARMTargetInfo(const std::string &TripleStr)
3492    : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3493  {
3494    BigEndian = false;
3495    SizeType = UnsignedInt;
3496    PtrDiffType = SignedInt;
3497    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3498    WCharType = UnsignedInt;
3499
3500    // {} in inline assembly are neon specifiers, not assembly variant
3501    // specifiers.
3502    NoAsmVariants = true;
3503
3504    // FIXME: Should we just treat this as a feature?
3505    IsThumb = getTriple().getArchName().startswith("thumb");
3506    if (IsThumb) {
3507      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3508      // so set preferred for small types to 32.
3509      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3510                           "i64:64:64-f32:32:32-f64:64:64-"
3511                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3512    } else {
3513      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3514                           "i64:64:64-f32:32:32-f64:64:64-"
3515                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3516    }
3517
3518    // ARM targets default to using the ARM C++ ABI.
3519    TheCXXABI.set(TargetCXXABI::GenericARM);
3520
3521    // ARM has atomics up to 8 bytes
3522    // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e
3523    MaxAtomicPromoteWidth = 64;
3524
3525    // Do force alignment of members that follow zero length bitfields.  If
3526    // the alignment of the zero-length bitfield is greater than the member
3527    // that follows it, `bar', `bar' will be aligned as the  type of the
3528    // zero length bitfield.
3529    UseZeroLengthBitfieldAlignment = true;
3530  }
3531  virtual const char *getABI() const { return ABI.c_str(); }
3532  virtual bool setABI(const std::string &Name) {
3533    ABI = Name;
3534
3535    // The defaults (above) are for AAPCS, check if we need to change them.
3536    //
3537    // FIXME: We need support for -meabi... we could just mangle it into the
3538    // name.
3539    if (Name == "apcs-gnu") {
3540      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3541      // size_t is unsigned int on FreeBSD.
3542      if (getTriple().getOS() != llvm::Triple::FreeBSD)
3543        SizeType = UnsignedLong;
3544
3545      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3546      WCharType = SignedInt;
3547
3548      // Do not respect the alignment of bit-field types when laying out
3549      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3550      UseBitFieldTypeAlignment = false;
3551
3552      /// gcc forces the alignment to 4 bytes, regardless of the type of the
3553      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3554      /// gcc.
3555      ZeroLengthBitfieldBoundary = 32;
3556
3557      IsAAPCS = false;
3558
3559      if (IsThumb) {
3560        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3561        // so set preferred for small types to 32.
3562        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3563                             "i64:32:64-f32:32:32-f64:32:64-"
3564                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3565      } else {
3566        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3567                             "i64:32:64-f32:32:32-f64:32:64-"
3568                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3569      }
3570
3571      // FIXME: Override "preferred align" for double and long long.
3572    } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3573      IsAAPCS = true;
3574      // FIXME: Enumerated types are variable width in straight AAPCS.
3575    } else if (Name == "aapcs-linux") {
3576      IsAAPCS = true;
3577    } else
3578      return false;
3579
3580    return true;
3581  }
3582
3583  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3584    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3585      Features["vfp2"] = true;
3586    else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3587             CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3588      Features["neon"] = true;
3589    else if (CPU == "swift" || CPU == "cortex-a7") {
3590      Features["vfp4"] = true;
3591      Features["neon"] = true;
3592    }
3593  }
3594
3595  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3596                                 StringRef Name,
3597                                 bool Enabled) const {
3598    if (Name == "soft-float" || Name == "soft-float-abi" ||
3599        Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3600        Name == "d16" || Name == "neonfp") {
3601      Features[Name] = Enabled;
3602    } else
3603      return false;
3604
3605    return true;
3606  }
3607
3608  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3609    FPU = 0;
3610    SoftFloat = SoftFloatABI = false;
3611    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3612      if (Features[i] == "+soft-float")
3613        SoftFloat = true;
3614      else if (Features[i] == "+soft-float-abi")
3615        SoftFloatABI = true;
3616      else if (Features[i] == "+vfp2")
3617        FPU |= VFP2FPU;
3618      else if (Features[i] == "+vfp3")
3619        FPU |= VFP3FPU;
3620      else if (Features[i] == "+vfp4")
3621        FPU |= VFP4FPU;
3622      else if (Features[i] == "+neon")
3623        FPU |= NeonFPU;
3624    }
3625
3626    // Remove front-end specific options which the backend handles differently.
3627    std::vector<std::string>::iterator it;
3628    it = std::find(Features.begin(), Features.end(), "+soft-float");
3629    if (it != Features.end())
3630      Features.erase(it);
3631    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3632    if (it != Features.end())
3633      Features.erase(it);
3634  }
3635
3636  virtual bool hasFeature(StringRef Feature) const {
3637    return llvm::StringSwitch<bool>(Feature)
3638        .Case("arm", true)
3639        .Case("softfloat", SoftFloat)
3640        .Case("thumb", IsThumb)
3641        .Case("neon", FPU == NeonFPU && !SoftFloat &&
3642              StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3643        .Default(false);
3644  }
3645  // FIXME: Should we actually have some table instead of these switches?
3646  static const char *getCPUDefineSuffix(StringRef Name) {
3647    return llvm::StringSwitch<const char*>(Name)
3648      .Cases("arm8", "arm810", "4")
3649      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3650      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3651      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3652      .Case("ep9312", "4T")
3653      .Cases("arm10tdmi", "arm1020t", "5T")
3654      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3655      .Case("arm926ej-s", "5TEJ")
3656      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3657      .Cases("xscale", "iwmmxt", "5TE")
3658      .Case("arm1136j-s", "6J")
3659      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3660      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3661      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3662      .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3663      .Cases("cortex-a9", "cortex-a15", "7A")
3664      .Case("cortex-r5", "7R")
3665      .Case("cortex-a9-mp", "7F")
3666      .Case("swift", "7S")
3667      .Cases("cortex-m3", "cortex-m4", "7M")
3668      .Case("cortex-m0", "6M")
3669      .Default(0);
3670  }
3671  static const char *getCPUProfile(StringRef Name) {
3672    return llvm::StringSwitch<const char*>(Name)
3673      .Cases("cortex-a8", "cortex-a9", "A")
3674      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3675      .Case("cortex-r5", "R")
3676      .Default("");
3677  }
3678  virtual bool setCPU(const std::string &Name) {
3679    if (!getCPUDefineSuffix(Name))
3680      return false;
3681
3682    CPU = Name;
3683    return true;
3684  }
3685  virtual void getTargetDefines(const LangOptions &Opts,
3686                                MacroBuilder &Builder) const {
3687    // Target identification.
3688    Builder.defineMacro("__arm");
3689    Builder.defineMacro("__arm__");
3690
3691    // Target properties.
3692    Builder.defineMacro("__ARMEL__");
3693    Builder.defineMacro("__LITTLE_ENDIAN__");
3694    Builder.defineMacro("__REGISTER_PREFIX__", "");
3695
3696    StringRef CPUArch = getCPUDefineSuffix(CPU);
3697    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3698    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3699    StringRef CPUProfile = getCPUProfile(CPU);
3700    if (!CPUProfile.empty())
3701      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3702
3703    // Subtarget options.
3704
3705    // FIXME: It's more complicated than this and we don't really support
3706    // interworking.
3707    if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3708      Builder.defineMacro("__THUMB_INTERWORK__");
3709
3710    if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3711      // M-class CPUs on Darwin follow AAPCS, but not EABI.
3712      if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3713        Builder.defineMacro("__ARM_EABI__");
3714      Builder.defineMacro("__ARM_PCS", "1");
3715
3716      if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3717        Builder.defineMacro("__ARM_PCS_VFP", "1");
3718    }
3719
3720    if (SoftFloat)
3721      Builder.defineMacro("__SOFTFP__");
3722
3723    if (CPU == "xscale")
3724      Builder.defineMacro("__XSCALE__");
3725
3726    bool IsARMv7 = CPUArch.startswith("7");
3727    if (IsThumb) {
3728      Builder.defineMacro("__THUMBEL__");
3729      Builder.defineMacro("__thumb__");
3730      if (CPUArch == "6T2" || IsARMv7)
3731        Builder.defineMacro("__thumb2__");
3732    }
3733
3734    // Note, this is always on in gcc, even though it doesn't make sense.
3735    Builder.defineMacro("__APCS_32__");
3736
3737    if (FPUModeIsVFP((FPUMode) FPU)) {
3738      Builder.defineMacro("__VFP_FP__");
3739      if (FPU & VFP2FPU)
3740        Builder.defineMacro("__ARM_VFPV2__");
3741      if (FPU & VFP3FPU)
3742        Builder.defineMacro("__ARM_VFPV3__");
3743      if (FPU & VFP4FPU)
3744        Builder.defineMacro("__ARM_VFPV4__");
3745    }
3746
3747    // This only gets set when Neon instructions are actually available, unlike
3748    // the VFP define, hence the soft float and arch check. This is subtly
3749    // different from gcc, we follow the intent which was that it should be set
3750    // when Neon instructions are actually available.
3751    if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3752      Builder.defineMacro("__ARM_NEON__");
3753  }
3754  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3755                                 unsigned &NumRecords) const {
3756    Records = BuiltinInfo;
3757    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3758  }
3759  virtual bool isCLZForZeroUndef() const { return false; }
3760  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3761    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3762  }
3763  virtual void getGCCRegNames(const char * const *&Names,
3764                              unsigned &NumNames) const;
3765  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3766                                unsigned &NumAliases) const;
3767  virtual bool validateAsmConstraint(const char *&Name,
3768                                     TargetInfo::ConstraintInfo &Info) const {
3769    switch (*Name) {
3770    default: break;
3771    case 'l': // r0-r7
3772    case 'h': // r8-r15
3773    case 'w': // VFP Floating point register single precision
3774    case 'P': // VFP Floating point register double precision
3775      Info.setAllowsRegister();
3776      return true;
3777    case 'Q': // A memory address that is a single base register.
3778      Info.setAllowsMemory();
3779      return true;
3780    case 'U': // a memory reference...
3781      switch (Name[1]) {
3782      case 'q': // ...ARMV4 ldrsb
3783      case 'v': // ...VFP load/store (reg+constant offset)
3784      case 'y': // ...iWMMXt load/store
3785      case 't': // address valid for load/store opaque types wider
3786                // than 128-bits
3787      case 'n': // valid address for Neon doubleword vector load/store
3788      case 'm': // valid address for Neon element and structure load/store
3789      case 's': // valid address for non-offset loads/stores of quad-word
3790                // values in four ARM registers
3791        Info.setAllowsMemory();
3792        Name++;
3793        return true;
3794      }
3795    }
3796    return false;
3797  }
3798  virtual std::string convertConstraint(const char *&Constraint) const {
3799    std::string R;
3800    switch (*Constraint) {
3801    case 'U':   // Two-character constraint; add "^" hint for later parsing.
3802      R = std::string("^") + std::string(Constraint, 2);
3803      Constraint++;
3804      break;
3805    case 'p': // 'p' should be translated to 'r' by default.
3806      R = std::string("r");
3807      break;
3808    default:
3809      return std::string(1, *Constraint);
3810    }
3811    return R;
3812  }
3813  virtual bool validateConstraintModifier(StringRef Constraint,
3814                                          const char Modifier,
3815                                          unsigned Size) const {
3816    bool isOutput = (Constraint[0] == '=');
3817    bool isInOut = (Constraint[0] == '+');
3818
3819    // Strip off constraint modifiers.
3820    while (Constraint[0] == '=' ||
3821           Constraint[0] == '+' ||
3822           Constraint[0] == '&')
3823      Constraint = Constraint.substr(1);
3824
3825    switch (Constraint[0]) {
3826    default: break;
3827    case 'r': {
3828      switch (Modifier) {
3829      default:
3830        return isInOut || (isOutput && Size >= 32) ||
3831          (!isOutput && !isInOut && Size <= 32);
3832      case 'q':
3833        // A register of size 32 cannot fit a vector type.
3834        return false;
3835      }
3836    }
3837    }
3838
3839    return true;
3840  }
3841  virtual const char *getClobbers() const {
3842    // FIXME: Is this really right?
3843    return "";
3844  }
3845
3846  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3847    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3848  }
3849
3850  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3851    if (RegNo == 0) return 0;
3852    if (RegNo == 1) return 1;
3853    return -1;
3854  }
3855};
3856
3857const char * const ARMTargetInfo::GCCRegNames[] = {
3858  // Integer registers
3859  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3860  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3861
3862  // Float registers
3863  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3864  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3865  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3866  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3867
3868  // Double registers
3869  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3870  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3871  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3872  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3873
3874  // Quad registers
3875  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3876  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3877};
3878
3879void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3880                                   unsigned &NumNames) const {
3881  Names = GCCRegNames;
3882  NumNames = llvm::array_lengthof(GCCRegNames);
3883}
3884
3885const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3886  { { "a1" }, "r0" },
3887  { { "a2" }, "r1" },
3888  { { "a3" }, "r2" },
3889  { { "a4" }, "r3" },
3890  { { "v1" }, "r4" },
3891  { { "v2" }, "r5" },
3892  { { "v3" }, "r6" },
3893  { { "v4" }, "r7" },
3894  { { "v5" }, "r8" },
3895  { { "v6", "rfp" }, "r9" },
3896  { { "sl" }, "r10" },
3897  { { "fp" }, "r11" },
3898  { { "ip" }, "r12" },
3899  { { "r13" }, "sp" },
3900  { { "r14" }, "lr" },
3901  { { "r15" }, "pc" },
3902  // The S, D and Q registers overlap, but aren't really aliases; we
3903  // don't want to substitute one of these for a different-sized one.
3904};
3905
3906void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3907                                       unsigned &NumAliases) const {
3908  Aliases = GCCRegAliases;
3909  NumAliases = llvm::array_lengthof(GCCRegAliases);
3910}
3911
3912const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3913#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3914#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3915                                              ALL_LANGUAGES },
3916#include "clang/Basic/BuiltinsARM.def"
3917};
3918} // end anonymous namespace.
3919
3920namespace {
3921class DarwinARMTargetInfo :
3922  public DarwinTargetInfo<ARMTargetInfo> {
3923protected:
3924  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3925                            MacroBuilder &Builder) const {
3926    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3927  }
3928
3929public:
3930  DarwinARMTargetInfo(const std::string& triple)
3931    : DarwinTargetInfo<ARMTargetInfo>(triple) {
3932    HasAlignMac68kSupport = true;
3933    // iOS always has 64-bit atomic instructions.
3934    // FIXME: This should be based off of the target features in ARMTargetInfo.
3935    MaxAtomicInlineWidth = 64;
3936
3937    // Darwin on iOS uses a variant of the ARM C++ ABI.
3938    TheCXXABI.set(TargetCXXABI::iOS);
3939  }
3940};
3941} // end anonymous namespace.
3942
3943
3944namespace {
3945// Hexagon abstract base class
3946class HexagonTargetInfo : public TargetInfo {
3947  static const Builtin::Info BuiltinInfo[];
3948  static const char * const GCCRegNames[];
3949  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3950  std::string CPU;
3951public:
3952  HexagonTargetInfo(const std::string& triple) : TargetInfo(triple)  {
3953    BigEndian = false;
3954    DescriptionString = ("e-p:32:32:32-"
3955                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
3956                         "f64:64:64-f32:32:32-a0:0-n32");
3957
3958    // {} in inline assembly are packet specifiers, not assembly variant
3959    // specifiers.
3960    NoAsmVariants = true;
3961  }
3962
3963  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3964                                 unsigned &NumRecords) const {
3965    Records = BuiltinInfo;
3966    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
3967  }
3968
3969  virtual bool validateAsmConstraint(const char *&Name,
3970                                     TargetInfo::ConstraintInfo &Info) const {
3971    return true;
3972  }
3973
3974  virtual void getTargetDefines(const LangOptions &Opts,
3975                                MacroBuilder &Builder) const;
3976
3977  virtual bool hasFeature(StringRef Feature) const {
3978    return Feature == "hexagon";
3979  }
3980
3981  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3982    return TargetInfo::CharPtrBuiltinVaList;
3983  }
3984  virtual void getGCCRegNames(const char * const *&Names,
3985                              unsigned &NumNames) const;
3986  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3987                                unsigned &NumAliases) const;
3988  virtual const char *getClobbers() const {
3989    return "";
3990  }
3991
3992  static const char *getHexagonCPUSuffix(StringRef Name) {
3993    return llvm::StringSwitch<const char*>(Name)
3994      .Case("hexagonv4", "4")
3995      .Case("hexagonv5", "5")
3996      .Default(0);
3997  }
3998
3999  virtual bool setCPU(const std::string &Name) {
4000    if (!getHexagonCPUSuffix(Name))
4001      return false;
4002
4003    CPU = Name;
4004    return true;
4005  }
4006};
4007
4008void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4009                                MacroBuilder &Builder) const {
4010  Builder.defineMacro("qdsp6");
4011  Builder.defineMacro("__qdsp6", "1");
4012  Builder.defineMacro("__qdsp6__", "1");
4013
4014  Builder.defineMacro("hexagon");
4015  Builder.defineMacro("__hexagon", "1");
4016  Builder.defineMacro("__hexagon__", "1");
4017
4018  if(CPU == "hexagonv1") {
4019    Builder.defineMacro("__HEXAGON_V1__");
4020    Builder.defineMacro("__HEXAGON_ARCH__", "1");
4021    if(Opts.HexagonQdsp6Compat) {
4022      Builder.defineMacro("__QDSP6_V1__");
4023      Builder.defineMacro("__QDSP6_ARCH__", "1");
4024    }
4025  }
4026  else if(CPU == "hexagonv2") {
4027    Builder.defineMacro("__HEXAGON_V2__");
4028    Builder.defineMacro("__HEXAGON_ARCH__", "2");
4029    if(Opts.HexagonQdsp6Compat) {
4030      Builder.defineMacro("__QDSP6_V2__");
4031      Builder.defineMacro("__QDSP6_ARCH__", "2");
4032    }
4033  }
4034  else if(CPU == "hexagonv3") {
4035    Builder.defineMacro("__HEXAGON_V3__");
4036    Builder.defineMacro("__HEXAGON_ARCH__", "3");
4037    if(Opts.HexagonQdsp6Compat) {
4038      Builder.defineMacro("__QDSP6_V3__");
4039      Builder.defineMacro("__QDSP6_ARCH__", "3");
4040    }
4041  }
4042  else if(CPU == "hexagonv4") {
4043    Builder.defineMacro("__HEXAGON_V4__");
4044    Builder.defineMacro("__HEXAGON_ARCH__", "4");
4045    if(Opts.HexagonQdsp6Compat) {
4046      Builder.defineMacro("__QDSP6_V4__");
4047      Builder.defineMacro("__QDSP6_ARCH__", "4");
4048    }
4049  }
4050  else if(CPU == "hexagonv5") {
4051    Builder.defineMacro("__HEXAGON_V5__");
4052    Builder.defineMacro("__HEXAGON_ARCH__", "5");
4053    if(Opts.HexagonQdsp6Compat) {
4054      Builder.defineMacro("__QDSP6_V5__");
4055      Builder.defineMacro("__QDSP6_ARCH__", "5");
4056    }
4057  }
4058}
4059
4060const char * const HexagonTargetInfo::GCCRegNames[] = {
4061  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4062  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4063  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4064  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4065  "p0", "p1", "p2", "p3",
4066  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4067};
4068
4069void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4070                                   unsigned &NumNames) const {
4071  Names = GCCRegNames;
4072  NumNames = llvm::array_lengthof(GCCRegNames);
4073}
4074
4075
4076const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4077  { { "sp" }, "r29" },
4078  { { "fp" }, "r30" },
4079  { { "lr" }, "r31" },
4080 };
4081
4082void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4083                                     unsigned &NumAliases) const {
4084  Aliases = GCCRegAliases;
4085  NumAliases = llvm::array_lengthof(GCCRegAliases);
4086}
4087
4088
4089const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4090#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4091#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4092                                              ALL_LANGUAGES },
4093#include "clang/Basic/BuiltinsHexagon.def"
4094};
4095}
4096
4097
4098namespace {
4099class SparcV8TargetInfo : public TargetInfo {
4100  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4101  static const char * const GCCRegNames[];
4102  bool SoftFloat;
4103public:
4104  SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) {
4105    // FIXME: Support Sparc quad-precision long double?
4106    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4107                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32";
4108  }
4109  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4110                                 StringRef Name,
4111                                 bool Enabled) const {
4112    if (Name == "soft-float")
4113      Features[Name] = Enabled;
4114    else
4115      return false;
4116
4117    return true;
4118  }
4119  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4120    SoftFloat = false;
4121    for (unsigned i = 0, e = Features.size(); i != e; ++i)
4122      if (Features[i] == "+soft-float")
4123        SoftFloat = true;
4124  }
4125  virtual void getTargetDefines(const LangOptions &Opts,
4126                                MacroBuilder &Builder) const {
4127    DefineStd(Builder, "sparc", Opts);
4128    Builder.defineMacro("__sparcv8");
4129    Builder.defineMacro("__REGISTER_PREFIX__", "");
4130
4131    if (SoftFloat)
4132      Builder.defineMacro("SOFT_FLOAT", "1");
4133  }
4134
4135  virtual bool hasFeature(StringRef Feature) const {
4136    return llvm::StringSwitch<bool>(Feature)
4137             .Case("softfloat", SoftFloat)
4138             .Case("sparc", true)
4139             .Default(false);
4140  }
4141
4142  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4143                                 unsigned &NumRecords) const {
4144    // FIXME: Implement!
4145  }
4146  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4147    return TargetInfo::VoidPtrBuiltinVaList;
4148  }
4149  virtual void getGCCRegNames(const char * const *&Names,
4150                              unsigned &NumNames) const;
4151  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4152                                unsigned &NumAliases) const;
4153  virtual bool validateAsmConstraint(const char *&Name,
4154                                     TargetInfo::ConstraintInfo &info) const {
4155    // FIXME: Implement!
4156    return false;
4157  }
4158  virtual const char *getClobbers() const {
4159    // FIXME: Implement!
4160    return "";
4161  }
4162};
4163
4164const char * const SparcV8TargetInfo::GCCRegNames[] = {
4165  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4166  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4167  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4168  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4169};
4170
4171void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names,
4172                                       unsigned &NumNames) const {
4173  Names = GCCRegNames;
4174  NumNames = llvm::array_lengthof(GCCRegNames);
4175}
4176
4177const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = {
4178  { { "g0" }, "r0" },
4179  { { "g1" }, "r1" },
4180  { { "g2" }, "r2" },
4181  { { "g3" }, "r3" },
4182  { { "g4" }, "r4" },
4183  { { "g5" }, "r5" },
4184  { { "g6" }, "r6" },
4185  { { "g7" }, "r7" },
4186  { { "o0" }, "r8" },
4187  { { "o1" }, "r9" },
4188  { { "o2" }, "r10" },
4189  { { "o3" }, "r11" },
4190  { { "o4" }, "r12" },
4191  { { "o5" }, "r13" },
4192  { { "o6", "sp" }, "r14" },
4193  { { "o7" }, "r15" },
4194  { { "l0" }, "r16" },
4195  { { "l1" }, "r17" },
4196  { { "l2" }, "r18" },
4197  { { "l3" }, "r19" },
4198  { { "l4" }, "r20" },
4199  { { "l5" }, "r21" },
4200  { { "l6" }, "r22" },
4201  { { "l7" }, "r23" },
4202  { { "i0" }, "r24" },
4203  { { "i1" }, "r25" },
4204  { { "i2" }, "r26" },
4205  { { "i3" }, "r27" },
4206  { { "i4" }, "r28" },
4207  { { "i5" }, "r29" },
4208  { { "i6", "fp" }, "r30" },
4209  { { "i7" }, "r31" },
4210};
4211
4212void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4213                                         unsigned &NumAliases) const {
4214  Aliases = GCCRegAliases;
4215  NumAliases = llvm::array_lengthof(GCCRegAliases);
4216}
4217} // end anonymous namespace.
4218
4219namespace {
4220class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4221public:
4222  AuroraUXSparcV8TargetInfo(const std::string& triple) :
4223      AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
4224    SizeType = UnsignedInt;
4225    PtrDiffType = SignedInt;
4226  }
4227};
4228class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4229public:
4230  SolarisSparcV8TargetInfo(const std::string& triple) :
4231      SolarisTargetInfo<SparcV8TargetInfo>(triple) {
4232    SizeType = UnsignedInt;
4233    PtrDiffType = SignedInt;
4234  }
4235};
4236} // end anonymous namespace.
4237
4238namespace {
4239  class MSP430TargetInfo : public TargetInfo {
4240    static const char * const GCCRegNames[];
4241  public:
4242    MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
4243      BigEndian = false;
4244      TLSSupported = false;
4245      IntWidth = 16; IntAlign = 16;
4246      LongWidth = 32; LongLongWidth = 64;
4247      LongAlign = LongLongAlign = 16;
4248      PointerWidth = 16; PointerAlign = 16;
4249      SuitableAlign = 16;
4250      SizeType = UnsignedInt;
4251      IntMaxType = SignedLong;
4252      UIntMaxType = UnsignedLong;
4253      IntPtrType = SignedShort;
4254      PtrDiffType = SignedInt;
4255      SigAtomicType = SignedLong;
4256      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4257   }
4258    virtual void getTargetDefines(const LangOptions &Opts,
4259                                  MacroBuilder &Builder) const {
4260      Builder.defineMacro("MSP430");
4261      Builder.defineMacro("__MSP430__");
4262      // FIXME: defines for different 'flavours' of MCU
4263    }
4264    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4265                                   unsigned &NumRecords) const {
4266     // FIXME: Implement.
4267      Records = 0;
4268      NumRecords = 0;
4269    }
4270    virtual bool hasFeature(StringRef Feature) const {
4271      return Feature == "msp430";
4272    }
4273    virtual void getGCCRegNames(const char * const *&Names,
4274                                unsigned &NumNames) const;
4275    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4276                                  unsigned &NumAliases) const {
4277      // No aliases.
4278      Aliases = 0;
4279      NumAliases = 0;
4280    }
4281    virtual bool validateAsmConstraint(const char *&Name,
4282                                       TargetInfo::ConstraintInfo &info) const {
4283      // No target constraints for now.
4284      return false;
4285    }
4286    virtual const char *getClobbers() const {
4287      // FIXME: Is this really right?
4288      return "";
4289    }
4290    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4291      // FIXME: implement
4292      return TargetInfo::CharPtrBuiltinVaList;
4293   }
4294  };
4295
4296  const char * const MSP430TargetInfo::GCCRegNames[] = {
4297    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4298    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4299  };
4300
4301  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4302                                        unsigned &NumNames) const {
4303    Names = GCCRegNames;
4304    NumNames = llvm::array_lengthof(GCCRegNames);
4305  }
4306}
4307
4308namespace {
4309
4310  // LLVM and Clang cannot be used directly to output native binaries for
4311  // target, but is used to compile C code to llvm bitcode with correct
4312  // type and alignment information.
4313  //
4314  // TCE uses the llvm bitcode as input and uses it for generating customized
4315  // target processor and program binary. TCE co-design environment is
4316  // publicly available in http://tce.cs.tut.fi
4317
4318  static const unsigned TCEOpenCLAddrSpaceMap[] = {
4319      3, // opencl_global
4320      4, // opencl_local
4321      5, // opencl_constant
4322      0, // cuda_device
4323      0, // cuda_constant
4324      0  // cuda_shared
4325  };
4326
4327  class TCETargetInfo : public TargetInfo{
4328  public:
4329    TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
4330      TLSSupported = false;
4331      IntWidth = 32;
4332      LongWidth = LongLongWidth = 32;
4333      PointerWidth = 32;
4334      IntAlign = 32;
4335      LongAlign = LongLongAlign = 32;
4336      PointerAlign = 32;
4337      SuitableAlign = 32;
4338      SizeType = UnsignedInt;
4339      IntMaxType = SignedLong;
4340      UIntMaxType = UnsignedLong;
4341      IntPtrType = SignedInt;
4342      PtrDiffType = SignedInt;
4343      FloatWidth = 32;
4344      FloatAlign = 32;
4345      DoubleWidth = 32;
4346      DoubleAlign = 32;
4347      LongDoubleWidth = 32;
4348      LongDoubleAlign = 32;
4349      FloatFormat = &llvm::APFloat::IEEEsingle;
4350      DoubleFormat = &llvm::APFloat::IEEEsingle;
4351      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4352      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4353                          "i16:16:32-i32:32:32-i64:32:32-"
4354                          "f32:32:32-f64:32:32-v64:32:32-"
4355                          "v128:32:32-a0:0:32-n32";
4356      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4357    }
4358
4359    virtual void getTargetDefines(const LangOptions &Opts,
4360                                  MacroBuilder &Builder) const {
4361      DefineStd(Builder, "tce", Opts);
4362      Builder.defineMacro("__TCE__");
4363      Builder.defineMacro("__TCE_V1__");
4364    }
4365    virtual bool hasFeature(StringRef Feature) const {
4366      return Feature == "tce";
4367    }
4368
4369    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4370                                   unsigned &NumRecords) const {}
4371    virtual const char *getClobbers() const {
4372      return "";
4373    }
4374    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4375      return TargetInfo::VoidPtrBuiltinVaList;
4376    }
4377    virtual void getGCCRegNames(const char * const *&Names,
4378                                unsigned &NumNames) const {}
4379    virtual bool validateAsmConstraint(const char *&Name,
4380                                       TargetInfo::ConstraintInfo &info) const {
4381      return true;
4382    }
4383    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4384                                  unsigned &NumAliases) const {}
4385  };
4386}
4387
4388namespace {
4389class MipsTargetInfoBase : public TargetInfo {
4390  static const Builtin::Info BuiltinInfo[];
4391  std::string CPU;
4392  bool IsMips16;
4393  enum MipsFloatABI {
4394    HardFloat, SingleFloat, SoftFloat
4395  } FloatABI;
4396  enum DspRevEnum {
4397    NoDSP, DSP1, DSP2
4398  } DspRev;
4399
4400protected:
4401  std::string ABI;
4402
4403public:
4404  MipsTargetInfoBase(const std::string& triple,
4405                     const std::string& ABIStr,
4406                     const std::string& CPUStr)
4407    : TargetInfo(triple),
4408      CPU(CPUStr),
4409      IsMips16(false),
4410      FloatABI(HardFloat),
4411      DspRev(NoDSP),
4412      ABI(ABIStr)
4413  {}
4414
4415  virtual const char *getABI() const { return ABI.c_str(); }
4416  virtual bool setABI(const std::string &Name) = 0;
4417  virtual bool setCPU(const std::string &Name) {
4418    CPU = Name;
4419    return true;
4420  }
4421  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4422    Features[ABI] = true;
4423    Features[CPU] = true;
4424  }
4425
4426  virtual void getTargetDefines(const LangOptions &Opts,
4427                                MacroBuilder &Builder) const {
4428    DefineStd(Builder, "mips", Opts);
4429    Builder.defineMacro("_mips");
4430    Builder.defineMacro("__REGISTER_PREFIX__", "");
4431
4432    switch (FloatABI) {
4433    case HardFloat:
4434      Builder.defineMacro("__mips_hard_float", Twine(1));
4435      break;
4436    case SingleFloat:
4437      Builder.defineMacro("__mips_hard_float", Twine(1));
4438      Builder.defineMacro("__mips_single_float", Twine(1));
4439      break;
4440    case SoftFloat:
4441      Builder.defineMacro("__mips_soft_float", Twine(1));
4442      break;
4443    }
4444
4445    if (IsMips16)
4446      Builder.defineMacro("__mips16", Twine(1));
4447
4448    switch (DspRev) {
4449    default:
4450      break;
4451    case DSP1:
4452      Builder.defineMacro("__mips_dsp_rev", Twine(1));
4453      Builder.defineMacro("__mips_dsp", Twine(1));
4454      break;
4455    case DSP2:
4456      Builder.defineMacro("__mips_dsp_rev", Twine(2));
4457      Builder.defineMacro("__mips_dspr2", Twine(1));
4458      Builder.defineMacro("__mips_dsp", Twine(1));
4459      break;
4460    }
4461
4462    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4463    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4464    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4465
4466    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4467    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4468  }
4469
4470  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4471                                 unsigned &NumRecords) const {
4472    Records = BuiltinInfo;
4473    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4474  }
4475  virtual bool hasFeature(StringRef Feature) const {
4476    return Feature == "mips";
4477  }
4478  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4479    return TargetInfo::VoidPtrBuiltinVaList;
4480  }
4481  virtual void getGCCRegNames(const char * const *&Names,
4482                              unsigned &NumNames) const {
4483    static const char * const GCCRegNames[] = {
4484      // CPU register names
4485      // Must match second column of GCCRegAliases
4486      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4487      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4488      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4489      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4490      // Floating point register names
4491      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4492      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4493      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4494      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4495      // Hi/lo and condition register names
4496      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4497      "$fcc5","$fcc6","$fcc7"
4498    };
4499    Names = GCCRegNames;
4500    NumNames = llvm::array_lengthof(GCCRegNames);
4501  }
4502  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4503                                unsigned &NumAliases) const = 0;
4504  virtual bool validateAsmConstraint(const char *&Name,
4505                                     TargetInfo::ConstraintInfo &Info) const {
4506    switch (*Name) {
4507    default:
4508      return false;
4509
4510    case 'r': // CPU registers.
4511    case 'd': // Equivalent to "r" unless generating MIPS16 code.
4512    case 'y': // Equivalent to "r", backwards compatibility only.
4513    case 'f': // floating-point registers.
4514    case 'c': // $25 for indirect jumps
4515    case 'l': // lo register
4516    case 'x': // hilo register pair
4517      Info.setAllowsRegister();
4518      return true;
4519    case 'R': // An address that can be used in a non-macro load or store
4520      Info.setAllowsMemory();
4521      return true;
4522    }
4523  }
4524
4525  virtual const char *getClobbers() const {
4526    // FIXME: Implement!
4527    return "";
4528  }
4529
4530  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4531                                 StringRef Name,
4532                                 bool Enabled) const {
4533    if (Name == "soft-float" || Name == "single-float" ||
4534        Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4535        Name == "mips32" || Name == "mips32r2" ||
4536        Name == "mips64" || Name == "mips64r2" ||
4537        Name == "mips16" || Name == "dsp" || Name == "dspr2") {
4538      Features[Name] = Enabled;
4539      return true;
4540    } else if (Name == "32") {
4541      Features["o32"] = Enabled;
4542      return true;
4543    } else if (Name == "64") {
4544      Features["n64"] = Enabled;
4545      return true;
4546    }
4547    return false;
4548  }
4549
4550  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4551    IsMips16 = false;
4552    FloatABI = HardFloat;
4553    DspRev = NoDSP;
4554
4555    for (std::vector<std::string>::iterator it = Features.begin(),
4556         ie = Features.end(); it != ie; ++it) {
4557      if (*it == "+single-float")
4558        FloatABI = SingleFloat;
4559      else if (*it == "+soft-float")
4560        FloatABI = SoftFloat;
4561      else if (*it == "+mips16")
4562        IsMips16 = true;
4563      else if (*it == "+dsp")
4564        DspRev = std::max(DspRev, DSP1);
4565      else if (*it == "+dspr2")
4566        DspRev = std::max(DspRev, DSP2);
4567    }
4568
4569    // Remove front-end specific option.
4570    std::vector<std::string>::iterator it =
4571      std::find(Features.begin(), Features.end(), "+soft-float");
4572    if (it != Features.end())
4573      Features.erase(it);
4574  }
4575
4576  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4577    if (RegNo == 0) return 4;
4578    if (RegNo == 1) return 5;
4579    return -1;
4580  }
4581};
4582
4583const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4584#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4585#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4586                                              ALL_LANGUAGES },
4587#include "clang/Basic/BuiltinsMips.def"
4588};
4589
4590class Mips32TargetInfoBase : public MipsTargetInfoBase {
4591public:
4592  Mips32TargetInfoBase(const std::string& triple) :
4593    MipsTargetInfoBase(triple, "o32", "mips32") {
4594    SizeType = UnsignedInt;
4595    PtrDiffType = SignedInt;
4596    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4597  }
4598  virtual bool setABI(const std::string &Name) {
4599    if ((Name == "o32") || (Name == "eabi")) {
4600      ABI = Name;
4601      return true;
4602    } else if (Name == "32") {
4603      ABI = "o32";
4604      return true;
4605    } else
4606      return false;
4607  }
4608  virtual void getTargetDefines(const LangOptions &Opts,
4609                                MacroBuilder &Builder) const {
4610    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4611
4612    if (ABI == "o32") {
4613      Builder.defineMacro("__mips_o32");
4614      Builder.defineMacro("_ABIO32", "1");
4615      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4616    }
4617    else if (ABI == "eabi")
4618      Builder.defineMacro("__mips_eabi");
4619    else
4620      llvm_unreachable("Invalid ABI for Mips32.");
4621  }
4622  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4623                                unsigned &NumAliases) const {
4624    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4625      { { "at" },  "$1" },
4626      { { "v0" },  "$2" },
4627      { { "v1" },  "$3" },
4628      { { "a0" },  "$4" },
4629      { { "a1" },  "$5" },
4630      { { "a2" },  "$6" },
4631      { { "a3" },  "$7" },
4632      { { "t0" },  "$8" },
4633      { { "t1" },  "$9" },
4634      { { "t2" }, "$10" },
4635      { { "t3" }, "$11" },
4636      { { "t4" }, "$12" },
4637      { { "t5" }, "$13" },
4638      { { "t6" }, "$14" },
4639      { { "t7" }, "$15" },
4640      { { "s0" }, "$16" },
4641      { { "s1" }, "$17" },
4642      { { "s2" }, "$18" },
4643      { { "s3" }, "$19" },
4644      { { "s4" }, "$20" },
4645      { { "s5" }, "$21" },
4646      { { "s6" }, "$22" },
4647      { { "s7" }, "$23" },
4648      { { "t8" }, "$24" },
4649      { { "t9" }, "$25" },
4650      { { "k0" }, "$26" },
4651      { { "k1" }, "$27" },
4652      { { "gp" }, "$28" },
4653      { { "sp","$sp" }, "$29" },
4654      { { "fp","$fp" }, "$30" },
4655      { { "ra" }, "$31" }
4656    };
4657    Aliases = GCCRegAliases;
4658    NumAliases = llvm::array_lengthof(GCCRegAliases);
4659  }
4660};
4661
4662class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4663public:
4664  Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4665    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4666                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4667  }
4668  virtual void getTargetDefines(const LangOptions &Opts,
4669                                MacroBuilder &Builder) const {
4670    DefineStd(Builder, "MIPSEB", Opts);
4671    Builder.defineMacro("_MIPSEB");
4672    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4673  }
4674};
4675
4676class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4677public:
4678  Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4679    BigEndian = false;
4680    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4681                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4682  }
4683  virtual void getTargetDefines(const LangOptions &Opts,
4684                                MacroBuilder &Builder) const {
4685    DefineStd(Builder, "MIPSEL", Opts);
4686    Builder.defineMacro("_MIPSEL");
4687    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4688  }
4689};
4690
4691class Mips64TargetInfoBase : public MipsTargetInfoBase {
4692  virtual void SetDescriptionString(const std::string &Name) = 0;
4693public:
4694  Mips64TargetInfoBase(const std::string& triple) :
4695    MipsTargetInfoBase(triple, "n64", "mips64") {
4696    LongWidth = LongAlign = 64;
4697    PointerWidth = PointerAlign = 64;
4698    LongDoubleWidth = LongDoubleAlign = 128;
4699    LongDoubleFormat = &llvm::APFloat::IEEEquad;
4700    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4701      LongDoubleWidth = LongDoubleAlign = 64;
4702      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4703    }
4704    SuitableAlign = 128;
4705    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4706  }
4707  virtual bool setABI(const std::string &Name) {
4708    SetDescriptionString(Name);
4709    if (Name == "n32") {
4710      LongWidth = LongAlign = 32;
4711      PointerWidth = PointerAlign = 32;
4712      ABI = Name;
4713      return true;
4714    } else if (Name == "n64") {
4715      ABI = Name;
4716      return true;
4717    } else if (Name == "64") {
4718      ABI = "n64";
4719      return true;
4720    } else
4721      return false;
4722  }
4723  virtual void getTargetDefines(const LangOptions &Opts,
4724                                MacroBuilder &Builder) const {
4725    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4726
4727    Builder.defineMacro("__mips64");
4728    Builder.defineMacro("__mips64__");
4729
4730    if (ABI == "n32") {
4731      Builder.defineMacro("__mips_n32");
4732      Builder.defineMacro("_ABIN32", "2");
4733      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4734    }
4735    else if (ABI == "n64") {
4736      Builder.defineMacro("__mips_n64");
4737      Builder.defineMacro("_ABI64", "3");
4738      Builder.defineMacro("_MIPS_SIM", "_ABI64");
4739    }
4740    else
4741      llvm_unreachable("Invalid ABI for Mips64.");
4742  }
4743  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4744                                unsigned &NumAliases) const {
4745    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4746      { { "at" },  "$1" },
4747      { { "v0" },  "$2" },
4748      { { "v1" },  "$3" },
4749      { { "a0" },  "$4" },
4750      { { "a1" },  "$5" },
4751      { { "a2" },  "$6" },
4752      { { "a3" },  "$7" },
4753      { { "a4" },  "$8" },
4754      { { "a5" },  "$9" },
4755      { { "a6" }, "$10" },
4756      { { "a7" }, "$11" },
4757      { { "t0" }, "$12" },
4758      { { "t1" }, "$13" },
4759      { { "t2" }, "$14" },
4760      { { "t3" }, "$15" },
4761      { { "s0" }, "$16" },
4762      { { "s1" }, "$17" },
4763      { { "s2" }, "$18" },
4764      { { "s3" }, "$19" },
4765      { { "s4" }, "$20" },
4766      { { "s5" }, "$21" },
4767      { { "s6" }, "$22" },
4768      { { "s7" }, "$23" },
4769      { { "t8" }, "$24" },
4770      { { "t9" }, "$25" },
4771      { { "k0" }, "$26" },
4772      { { "k1" }, "$27" },
4773      { { "gp" }, "$28" },
4774      { { "sp","$sp" }, "$29" },
4775      { { "fp","$fp" }, "$30" },
4776      { { "ra" }, "$31" }
4777    };
4778    Aliases = GCCRegAliases;
4779    NumAliases = llvm::array_lengthof(GCCRegAliases);
4780  }
4781};
4782
4783class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4784  virtual void SetDescriptionString(const std::string &Name) {
4785    // Change DescriptionString only if ABI is n32.
4786    if (Name == "n32")
4787      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4788                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4789                          "v64:64:64-n32:64-S128";
4790  }
4791public:
4792  Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4793    // Default ABI is n64.
4794    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4795                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4796                        "v64:64:64-n32:64-S128";
4797  }
4798  virtual void getTargetDefines(const LangOptions &Opts,
4799                                MacroBuilder &Builder) const {
4800    DefineStd(Builder, "MIPSEB", Opts);
4801    Builder.defineMacro("_MIPSEB");
4802    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4803  }
4804};
4805
4806class Mips64ELTargetInfo : public Mips64TargetInfoBase {
4807  virtual void SetDescriptionString(const std::string &Name) {
4808    // Change DescriptionString only if ABI is n32.
4809    if (Name == "n32")
4810      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4811                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
4812                          "-v64:64:64-n32:64-S128";
4813  }
4814public:
4815  Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4816    // Default ABI is n64.
4817    BigEndian = false;
4818    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4819                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4820                        "v64:64:64-n32:64-S128";
4821  }
4822  virtual void getTargetDefines(const LangOptions &Opts,
4823                                MacroBuilder &Builder) const {
4824    DefineStd(Builder, "MIPSEL", Opts);
4825    Builder.defineMacro("_MIPSEL");
4826    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4827  }
4828};
4829} // end anonymous namespace.
4830
4831namespace {
4832class PNaClTargetInfo : public TargetInfo {
4833public:
4834  PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
4835    BigEndian = false;
4836    this->UserLabelPrefix = "";
4837    this->LongAlign = 32;
4838    this->LongWidth = 32;
4839    this->PointerAlign = 32;
4840    this->PointerWidth = 32;
4841    this->IntMaxType = TargetInfo::SignedLongLong;
4842    this->UIntMaxType = TargetInfo::UnsignedLongLong;
4843    this->Int64Type = TargetInfo::SignedLongLong;
4844    this->DoubleAlign = 64;
4845    this->LongDoubleWidth = 64;
4846    this->LongDoubleAlign = 64;
4847    this->SizeType = TargetInfo::UnsignedInt;
4848    this->PtrDiffType = TargetInfo::SignedInt;
4849    this->IntPtrType = TargetInfo::SignedInt;
4850    this->RegParmMax = 2;
4851    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4852                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
4853  }
4854
4855  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4856  }
4857  virtual void getArchDefines(const LangOptions &Opts,
4858                              MacroBuilder &Builder) const {
4859    Builder.defineMacro("__le32__");
4860    Builder.defineMacro("__pnacl__");
4861  }
4862  virtual void getTargetDefines(const LangOptions &Opts,
4863                                MacroBuilder &Builder) const {
4864    Builder.defineMacro("__LITTLE_ENDIAN__");
4865    getArchDefines(Opts, Builder);
4866  }
4867  virtual bool hasFeature(StringRef Feature) const {
4868    return Feature == "pnacl";
4869  }
4870  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4871                                 unsigned &NumRecords) const {
4872  }
4873  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4874    return TargetInfo::PNaClABIBuiltinVaList;
4875  }
4876  virtual void getGCCRegNames(const char * const *&Names,
4877                              unsigned &NumNames) const;
4878  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4879                                unsigned &NumAliases) const;
4880  virtual bool validateAsmConstraint(const char *&Name,
4881                                     TargetInfo::ConstraintInfo &Info) const {
4882    return false;
4883  }
4884
4885  virtual const char *getClobbers() const {
4886    return "";
4887  }
4888};
4889
4890void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
4891                                     unsigned &NumNames) const {
4892  Names = NULL;
4893  NumNames = 0;
4894}
4895
4896void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4897                                       unsigned &NumAliases) const {
4898  Aliases = NULL;
4899  NumAliases = 0;
4900}
4901} // end anonymous namespace.
4902
4903namespace {
4904  static const unsigned SPIRAddrSpaceMap[] = {
4905    1,    // opencl_global
4906    3,    // opencl_local
4907    2,    // opencl_constant
4908    0,    // cuda_device
4909    0,    // cuda_constant
4910    0     // cuda_shared
4911  };
4912  class SPIRTargetInfo : public TargetInfo {
4913    static const char * const GCCRegNames[];
4914    static const Builtin::Info BuiltinInfo[];
4915    std::vector<StringRef> AvailableFeatures;
4916  public:
4917    SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) {
4918      assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
4919        "SPIR target must use unknown OS");
4920      assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
4921        "SPIR target must use unknown environment type");
4922      BigEndian = false;
4923      TLSSupported = false;
4924      LongWidth = LongAlign = 64;
4925      AddrSpaceMap = &SPIRAddrSpaceMap;
4926      // Define available target features
4927      // These must be defined in sorted order!
4928      NoAsmVariants = true;
4929    }
4930    virtual void getTargetDefines(const LangOptions &Opts,
4931                                  MacroBuilder &Builder) const {
4932      DefineStd(Builder, "SPIR", Opts);
4933    }
4934    virtual bool hasFeature(StringRef Feature) const {
4935      return Feature == "spir";
4936    }
4937
4938    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4939                                   unsigned &NumRecords) const {}
4940    virtual const char *getClobbers() const {
4941      return "";
4942    }
4943    virtual void getGCCRegNames(const char * const *&Names,
4944                                unsigned &NumNames) const {}
4945    virtual bool validateAsmConstraint(const char *&Name,
4946                                       TargetInfo::ConstraintInfo &info) const {
4947      return true;
4948    }
4949    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4950                                  unsigned &NumAliases) const {}
4951    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4952      return TargetInfo::VoidPtrBuiltinVaList;
4953    }
4954  };
4955
4956
4957  class SPIR32TargetInfo : public SPIRTargetInfo {
4958  public:
4959    SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
4960      PointerWidth = PointerAlign = 32;
4961      SizeType     = TargetInfo::UnsignedInt;
4962      PtrDiffType = IntPtrType = TargetInfo::SignedInt;
4963      DescriptionString
4964        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4965          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
4966          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
4967          "v512:512:512-v1024:1024:1024";
4968    }
4969    virtual void getTargetDefines(const LangOptions &Opts,
4970                                  MacroBuilder &Builder) const {
4971      DefineStd(Builder, "SPIR32", Opts);
4972    }
4973  };
4974
4975  class SPIR64TargetInfo : public SPIRTargetInfo {
4976  public:
4977    SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
4978      PointerWidth = PointerAlign = 64;
4979      SizeType     = TargetInfo::UnsignedLong;
4980      PtrDiffType = IntPtrType = TargetInfo::SignedLong;
4981      DescriptionString
4982        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4983          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
4984          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
4985          "v512:512:512-v1024:1024:1024";
4986    }
4987    virtual void getTargetDefines(const LangOptions &Opts,
4988                                  MacroBuilder &Builder) const {
4989      DefineStd(Builder, "SPIR64", Opts);
4990    }
4991  };
4992}
4993
4994
4995//===----------------------------------------------------------------------===//
4996// Driver code
4997//===----------------------------------------------------------------------===//
4998
4999static TargetInfo *AllocateTarget(const std::string &T) {
5000  llvm::Triple Triple(T);
5001  llvm::Triple::OSType os = Triple.getOS();
5002
5003  switch (Triple.getArch()) {
5004  default:
5005    return NULL;
5006
5007  case llvm::Triple::hexagon:
5008    return new HexagonTargetInfo(T);
5009
5010  case llvm::Triple::aarch64:
5011    switch (os) {
5012    case llvm::Triple::Linux:
5013      return new LinuxTargetInfo<AArch64TargetInfo>(T);
5014    default:
5015      return new AArch64TargetInfo(T);
5016    }
5017
5018  case llvm::Triple::arm:
5019  case llvm::Triple::thumb:
5020    if (Triple.isOSDarwin())
5021      return new DarwinARMTargetInfo(T);
5022
5023    switch (os) {
5024    case llvm::Triple::Linux:
5025      return new LinuxTargetInfo<ARMTargetInfo>(T);
5026    case llvm::Triple::FreeBSD:
5027      return new FreeBSDTargetInfo<ARMTargetInfo>(T);
5028    case llvm::Triple::NetBSD:
5029      return new NetBSDTargetInfo<ARMTargetInfo>(T);
5030    case llvm::Triple::OpenBSD:
5031      return new OpenBSDTargetInfo<ARMTargetInfo>(T);
5032    case llvm::Triple::Bitrig:
5033      return new BitrigTargetInfo<ARMTargetInfo>(T);
5034    case llvm::Triple::RTEMS:
5035      return new RTEMSTargetInfo<ARMTargetInfo>(T);
5036    case llvm::Triple::NaCl:
5037      return new NaClTargetInfo<ARMTargetInfo>(T);
5038    default:
5039      return new ARMTargetInfo(T);
5040    }
5041
5042  case llvm::Triple::msp430:
5043    return new MSP430TargetInfo(T);
5044
5045  case llvm::Triple::mips:
5046    switch (os) {
5047    case llvm::Triple::Linux:
5048      return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
5049    case llvm::Triple::RTEMS:
5050      return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
5051    case llvm::Triple::FreeBSD:
5052      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
5053    case llvm::Triple::NetBSD:
5054      return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
5055    default:
5056      return new Mips32EBTargetInfo(T);
5057    }
5058
5059  case llvm::Triple::mipsel:
5060    switch (os) {
5061    case llvm::Triple::Linux:
5062      return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
5063    case llvm::Triple::RTEMS:
5064      return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
5065    case llvm::Triple::FreeBSD:
5066      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
5067    case llvm::Triple::NetBSD:
5068      return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
5069    default:
5070      return new Mips32ELTargetInfo(T);
5071    }
5072
5073  case llvm::Triple::mips64:
5074    switch (os) {
5075    case llvm::Triple::Linux:
5076      return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
5077    case llvm::Triple::RTEMS:
5078      return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
5079    case llvm::Triple::FreeBSD:
5080      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
5081    case llvm::Triple::NetBSD:
5082      return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
5083    case llvm::Triple::OpenBSD:
5084      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
5085    default:
5086      return new Mips64EBTargetInfo(T);
5087    }
5088
5089  case llvm::Triple::mips64el:
5090    switch (os) {
5091    case llvm::Triple::Linux:
5092      return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
5093    case llvm::Triple::RTEMS:
5094      return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
5095    case llvm::Triple::FreeBSD:
5096      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
5097    case llvm::Triple::NetBSD:
5098      return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
5099    case llvm::Triple::OpenBSD:
5100      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
5101    default:
5102      return new Mips64ELTargetInfo(T);
5103    }
5104
5105  case llvm::Triple::le32:
5106    switch (os) {
5107      case llvm::Triple::NaCl:
5108        return new NaClTargetInfo<PNaClTargetInfo>(T);
5109      default:
5110        return NULL;
5111    }
5112
5113  case llvm::Triple::ppc:
5114    if (Triple.isOSDarwin())
5115      return new DarwinPPC32TargetInfo(T);
5116    switch (os) {
5117    case llvm::Triple::Linux:
5118      return new LinuxTargetInfo<PPC32TargetInfo>(T);
5119    case llvm::Triple::FreeBSD:
5120      return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
5121    case llvm::Triple::NetBSD:
5122      return new NetBSDTargetInfo<PPC32TargetInfo>(T);
5123    case llvm::Triple::OpenBSD:
5124      return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
5125    case llvm::Triple::RTEMS:
5126      return new RTEMSTargetInfo<PPC32TargetInfo>(T);
5127    default:
5128      return new PPC32TargetInfo(T);
5129    }
5130
5131  case llvm::Triple::ppc64:
5132    if (Triple.isOSDarwin())
5133      return new DarwinPPC64TargetInfo(T);
5134    switch (os) {
5135    case llvm::Triple::Linux:
5136      return new LinuxTargetInfo<PPC64TargetInfo>(T);
5137    case llvm::Triple::Lv2:
5138      return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
5139    case llvm::Triple::FreeBSD:
5140      return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
5141    case llvm::Triple::NetBSD:
5142      return new NetBSDTargetInfo<PPC64TargetInfo>(T);
5143    default:
5144      return new PPC64TargetInfo(T);
5145    }
5146
5147  case llvm::Triple::nvptx:
5148    return new NVPTX32TargetInfo(T);
5149  case llvm::Triple::nvptx64:
5150    return new NVPTX64TargetInfo(T);
5151
5152  case llvm::Triple::mblaze:
5153    return new MBlazeTargetInfo(T);
5154
5155  case llvm::Triple::r600:
5156    return new R600TargetInfo(T);
5157
5158  case llvm::Triple::sparc:
5159    switch (os) {
5160    case llvm::Triple::Linux:
5161      return new LinuxTargetInfo<SparcV8TargetInfo>(T);
5162    case llvm::Triple::AuroraUX:
5163      return new AuroraUXSparcV8TargetInfo(T);
5164    case llvm::Triple::Solaris:
5165      return new SolarisSparcV8TargetInfo(T);
5166    case llvm::Triple::NetBSD:
5167      return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
5168    case llvm::Triple::OpenBSD:
5169      return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
5170    case llvm::Triple::RTEMS:
5171      return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
5172    default:
5173      return new SparcV8TargetInfo(T);
5174    }
5175
5176  case llvm::Triple::tce:
5177    return new TCETargetInfo(T);
5178
5179  case llvm::Triple::x86:
5180    if (Triple.isOSDarwin())
5181      return new DarwinI386TargetInfo(T);
5182
5183    switch (os) {
5184    case llvm::Triple::AuroraUX:
5185      return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
5186    case llvm::Triple::Linux:
5187      return new LinuxTargetInfo<X86_32TargetInfo>(T);
5188    case llvm::Triple::DragonFly:
5189      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
5190    case llvm::Triple::NetBSD:
5191      return new NetBSDI386TargetInfo(T);
5192    case llvm::Triple::OpenBSD:
5193      return new OpenBSDI386TargetInfo(T);
5194    case llvm::Triple::Bitrig:
5195      return new BitrigI386TargetInfo(T);
5196    case llvm::Triple::FreeBSD:
5197      return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
5198    case llvm::Triple::Minix:
5199      return new MinixTargetInfo<X86_32TargetInfo>(T);
5200    case llvm::Triple::Solaris:
5201      return new SolarisTargetInfo<X86_32TargetInfo>(T);
5202    case llvm::Triple::Cygwin:
5203      return new CygwinX86_32TargetInfo(T);
5204    case llvm::Triple::MinGW32:
5205      return new MinGWX86_32TargetInfo(T);
5206    case llvm::Triple::Win32:
5207      return new VisualStudioWindowsX86_32TargetInfo(T);
5208    case llvm::Triple::Haiku:
5209      return new HaikuX86_32TargetInfo(T);
5210    case llvm::Triple::RTEMS:
5211      return new RTEMSX86_32TargetInfo(T);
5212    case llvm::Triple::NaCl:
5213      return new NaClTargetInfo<X86_32TargetInfo>(T);
5214    default:
5215      return new X86_32TargetInfo(T);
5216    }
5217
5218  case llvm::Triple::x86_64:
5219    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5220      return new DarwinX86_64TargetInfo(T);
5221
5222    switch (os) {
5223    case llvm::Triple::AuroraUX:
5224      return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
5225    case llvm::Triple::Linux:
5226      return new LinuxTargetInfo<X86_64TargetInfo>(T);
5227    case llvm::Triple::DragonFly:
5228      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
5229    case llvm::Triple::NetBSD:
5230      return new NetBSDTargetInfo<X86_64TargetInfo>(T);
5231    case llvm::Triple::OpenBSD:
5232      return new OpenBSDX86_64TargetInfo(T);
5233    case llvm::Triple::Bitrig:
5234      return new BitrigX86_64TargetInfo(T);
5235    case llvm::Triple::FreeBSD:
5236      return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
5237    case llvm::Triple::Solaris:
5238      return new SolarisTargetInfo<X86_64TargetInfo>(T);
5239    case llvm::Triple::MinGW32:
5240      return new MinGWX86_64TargetInfo(T);
5241    case llvm::Triple::Win32:   // This is what Triple.h supports now.
5242      return new VisualStudioWindowsX86_64TargetInfo(T);
5243    case llvm::Triple::NaCl:
5244      return new NaClTargetInfo<X86_64TargetInfo>(T);
5245    default:
5246      return new X86_64TargetInfo(T);
5247    }
5248
5249    case llvm::Triple::spir: {
5250      llvm::Triple Triple(T);
5251      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5252        Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5253        return NULL;
5254      return new SPIR32TargetInfo(T);
5255    }
5256    case llvm::Triple::spir64: {
5257      llvm::Triple Triple(T);
5258      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5259        Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5260        return NULL;
5261      return new SPIR64TargetInfo(T);
5262    }
5263  }
5264}
5265
5266/// CreateTargetInfo - Return the target info object for the specified target
5267/// triple.
5268TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5269                                         TargetOptions *Opts) {
5270  llvm::Triple Triple(Opts->Triple);
5271
5272  // Construct the target
5273  OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
5274  if (!Target) {
5275    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5276    return 0;
5277  }
5278  Target->setTargetOpts(Opts);
5279
5280  // Set the target CPU if specified.
5281  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5282    Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5283    return 0;
5284  }
5285
5286  // Set the target ABI if specified.
5287  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5288    Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5289    return 0;
5290  }
5291
5292  // Set the target C++ ABI.
5293  if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5294    Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5295    return 0;
5296  }
5297
5298  // Compute the default target features, we need the target to handle this
5299  // because features may have dependencies on one another.
5300  llvm::StringMap<bool> Features;
5301  Target->getDefaultFeatures(Features);
5302
5303  // Apply the user specified deltas.
5304  // First the enables.
5305  for (std::vector<std::string>::const_iterator
5306         it = Opts->FeaturesAsWritten.begin(),
5307         ie = Opts->FeaturesAsWritten.end();
5308       it != ie; ++it) {
5309    const char *Name = it->c_str();
5310
5311    if (Name[0] != '+')
5312      continue;
5313
5314    // Apply the feature via the target.
5315    if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5316      Diags.Report(diag::err_target_invalid_feature) << Name;
5317      return 0;
5318    }
5319  }
5320
5321  // Then the disables.
5322  for (std::vector<std::string>::const_iterator
5323         it = Opts->FeaturesAsWritten.begin(),
5324         ie = Opts->FeaturesAsWritten.end();
5325       it != ie; ++it) {
5326    const char *Name = it->c_str();
5327
5328    if (Name[0] == '+')
5329      continue;
5330
5331    // Apply the feature via the target.
5332    if (Name[0] != '-' ||
5333        !Target->setFeatureEnabled(Features, Name + 1, false)) {
5334      Diags.Report(diag::err_target_invalid_feature) << Name;
5335      return 0;
5336    }
5337  }
5338
5339  // Add the features to the compile options.
5340  //
5341  // FIXME: If we are completely confident that we have the right set, we only
5342  // need to pass the minuses.
5343  Opts->Features.clear();
5344  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5345         ie = Features.end(); it != ie; ++it)
5346    Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5347  Target->HandleTargetFeatures(Opts->Features);
5348
5349  return Target.take();
5350}
5351