SelectionDAGISel.h revision 014bf215c3457bb34fee348265e8f63a70b4d503 
1//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SelectionDAGISel class, which is used as the common
11// base class for SelectionDAG-based instruction selectors.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
17
18#include "llvm/BasicBlock.h"
19#include "llvm/Pass.h"
20#include "llvm/Constant.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23
24namespace llvm {
25  class FastISel;
26  class SelectionDAGBuilder;
27  class SDValue;
28  class MachineRegisterInfo;
29  class MachineBasicBlock;
30  class MachineFunction;
31  class MachineInstr;
32  class MachineModuleInfo;
33  class DwarfWriter;
34  class TargetLowering;
35  class TargetInstrInfo;
36  class FunctionLoweringInfo;
37  class ScheduleHazardRecognizer;
38  class GCFunctionInfo;
39  class ScheduleDAGSDNodes;
40
41/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
42/// pattern-matching instruction selectors.
43class SelectionDAGISel : public MachineFunctionPass {
44public:
45  const TargetMachine &TM;
46  TargetLowering &TLI;
47  FunctionLoweringInfo *FuncInfo;
48  MachineFunction *MF;
49  MachineRegisterInfo *RegInfo;
50  SelectionDAG *CurDAG;
51  SelectionDAGBuilder *SDB;
52  MachineBasicBlock *BB;
53  AliasAnalysis *AA;
54  GCFunctionInfo *GFI;
55  CodeGenOpt::Level OptLevel;
56  static char ID;
57
58  explicit SelectionDAGISel(TargetMachine &tm,
59                            CodeGenOpt::Level OL = CodeGenOpt::Default);
60  virtual ~SelectionDAGISel();
61
62  TargetLowering &getTargetLowering() { return TLI; }
63
64  virtual void getAnalysisUsage(AnalysisUsage &AU) const;
65
66  virtual bool runOnMachineFunction(MachineFunction &MF);
67
68  unsigned MakeReg(EVT VT);
69
70  virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
71  virtual void InstructionSelect() = 0;
72
73  void SelectRootInit() {
74    DAGSize = CurDAG->AssignTopologicalOrder();
75  }
76
77  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
78  /// addressing mode, according to the specified constraint code.  If this does
79  /// not match or is not implemented, return true.  The resultant operands
80  /// (which will appear in the machine instruction) should be added to the
81  /// OutOps vector.
82  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
83                                            char ConstraintCode,
84                                            std::vector<SDValue> &OutOps) {
85    return true;
86  }
87
88  /// IsProfitableToFold - Returns true if it's profitable to fold the specific
89  /// operand node N of U during instruction selection that starts at Root.
90  virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
91
92  /// IsLegalToFold - Returns true if the specific operand node N of
93  /// U can be folded during instruction selection that starts at Root.
94  virtual bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const;
95
96  /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
97  /// to use for this target when scheduling the DAG.
98  virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
99
100protected:
101  /// DAGSize - Size of DAG being instruction selected.
102  ///
103  unsigned DAGSize;
104
105  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
106  /// by tblgen.  Others should not call it.
107  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
108
109  // Calls to these predicates are generated by tblgen.
110  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
111                    int64_t DesiredMaskS) const;
112  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
113                    int64_t DesiredMaskS) const;
114
115  // Calls to these functions are generated by tblgen.
116  SDNode *Select_INLINEASM(SDNode *N);
117  SDNode *Select_UNDEF(SDNode *N);
118  SDNode *Select_EH_LABEL(SDNode *N);
119  void CannotYetSelect(SDNode *N);
120  void CannotYetSelectIntrinsic(SDNode *N);
121
122private:
123  void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
124                            MachineModuleInfo *MMI,
125                            DwarfWriter *DW,
126                            const TargetInstrInfo &TII);
127  void FinishBasicBlock();
128
129  void SelectBasicBlock(BasicBlock *LLVMBB,
130                        BasicBlock::iterator Begin,
131                        BasicBlock::iterator End,
132                        bool &HadTailCall);
133  void CodeGenAndEmitDAG();
134  void LowerArguments(BasicBlock *BB);
135
136  void ShrinkDemandedOps();
137  void ComputeLiveOutVRegInfo();
138
139  void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
140
141  bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
142
143  /// Create the scheduler. If a specific scheduler was specified
144  /// via the SchedulerRegistry, use it, otherwise select the
145  /// one preferred by the target.
146  ///
147  ScheduleDAGSDNodes *CreateScheduler();
148};
149
150}
151
152#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */
153