SelectionDAGISel.h revision 79ce276083ced01256a0eb7d80731e4948ca6e87 
1//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SelectionDAGISel class, which is used as the common
11// base class for SelectionDAG-based instruction selectors.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
17
18#include "llvm/BasicBlock.h"
19#include "llvm/Pass.h"
20#include "llvm/Constant.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22
23namespace llvm {
24  class FastISel;
25  class SelectionDAGLowering;
26  class SDValue;
27  class MachineRegisterInfo;
28  class MachineBasicBlock;
29  class MachineFunction;
30  class MachineInstr;
31  class MachineModuleInfo;
32  class DwarfWriter;
33  class TargetLowering;
34  class TargetInstrInfo;
35  class FunctionLoweringInfo;
36  class HazardRecognizer;
37  class GCFunctionInfo;
38  class ScheduleDAG;
39
40/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
41/// pattern-matching instruction selectors.
42class SelectionDAGISel : public FunctionPass {
43public:
44  const TargetMachine &TM;
45  TargetLowering &TLI;
46  FunctionLoweringInfo *FuncInfo;
47  MachineFunction *MF;
48  MachineRegisterInfo *RegInfo;
49  SelectionDAG *CurDAG;
50  SelectionDAGLowering *SDL;
51  MachineBasicBlock *BB;
52  AliasAnalysis *AA;
53  GCFunctionInfo *GFI;
54  bool Fast;
55  static char ID;
56
57  explicit SelectionDAGISel(TargetMachine &tm, bool fast = false);
58  virtual ~SelectionDAGISel();
59
60  TargetLowering &getTargetLowering() { return TLI; }
61
62  virtual void getAnalysisUsage(AnalysisUsage &AU) const;
63
64  virtual bool runOnFunction(Function &Fn);
65
66  unsigned MakeReg(MVT VT);
67
68  virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
69  virtual void InstructionSelect() = 0;
70
71  void SelectRootInit() {
72    DAGSize = CurDAG->AssignTopologicalOrder();
73  }
74
75  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
76  /// addressing mode, according to the specified constraint code.  If this does
77  /// not match or is not implemented, return true.  The resultant operands
78  /// (which will appear in the machine instruction) should be added to the
79  /// OutOps vector.
80  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
81                                            char ConstraintCode,
82                                            std::vector<SDValue> &OutOps) {
83    return true;
84  }
85
86  /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
87  /// U can be folded during instruction selection that starts at Root and
88  /// folding N is profitable.
89  virtual
90  bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const {
91    return true;
92  }
93
94  /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
95  /// to use for this target when scheduling the DAG.
96  virtual HazardRecognizer *CreateTargetHazardRecognizer();
97
98protected:
99  /// DAGSize - Size of DAG being instruction selected.
100  ///
101  unsigned DAGSize;
102
103  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
104  /// by tblgen.  Others should not call it.
105  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
106
107  // Calls to these predicates are generated by tblgen.
108  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
109                    int64_t DesiredMaskS) const;
110  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
111                    int64_t DesiredMaskS) const;
112
113private:
114  void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
115                            MachineModuleInfo *MMI,
116                            DwarfWriter *DW,
117                            const TargetInstrInfo &TII);
118  void FinishBasicBlock();
119
120  void SelectBasicBlock(BasicBlock *LLVMBB,
121                        BasicBlock::iterator Begin,
122                        BasicBlock::iterator End);
123  void CodeGenAndEmitDAG();
124  void LowerArguments(BasicBlock *BB);
125
126  void ComputeLiveOutVRegInfo();
127
128  void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
129
130  bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
131
132  /// Pick a safe ordering for instructions for each target node in the
133  /// graph.
134  ScheduleDAG *Schedule();
135};
136
137}
138
139#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */
140