SelectionDAGISel.h revision a4359be0328a91971c486b06892c742de1fa0f2b 
1//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SelectionDAGISel class, which is used as the common
11// base class for SelectionDAG-based instruction selectors.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
17
18#include "llvm/BasicBlock.h"
19#include "llvm/Pass.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include "llvm/CodeGen/MachineFunctionPass.h"
22
23namespace llvm {
24  class FastISel;
25  class SelectionDAGBuilder;
26  class SDValue;
27  class MachineRegisterInfo;
28  class MachineBasicBlock;
29  class MachineFunction;
30  class MachineInstr;
31  class TargetLowering;
32  class TargetInstrInfo;
33  class FunctionLoweringInfo;
34  class ScheduleHazardRecognizer;
35  class GCFunctionInfo;
36  class ScheduleDAGSDNodes;
37  class LoadInst;
38
39/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
40/// pattern-matching instruction selectors.
41class SelectionDAGISel : public MachineFunctionPass {
42public:
43  const TargetMachine &TM;
44  const TargetLowering &TLI;
45  FunctionLoweringInfo *FuncInfo;
46  MachineFunction *MF;
47  MachineRegisterInfo *RegInfo;
48  SelectionDAG *CurDAG;
49  SelectionDAGBuilder *SDB;
50  AliasAnalysis *AA;
51  GCFunctionInfo *GFI;
52  CodeGenOpt::Level OptLevel;
53  static char ID;
54
55  explicit SelectionDAGISel(const TargetMachine &tm,
56                            CodeGenOpt::Level OL = CodeGenOpt::Default);
57  virtual ~SelectionDAGISel();
58
59  const TargetLowering &getTargetLowering() { return TLI; }
60
61  virtual void getAnalysisUsage(AnalysisUsage &AU) const;
62
63  virtual bool runOnMachineFunction(MachineFunction &MF);
64
65  virtual void EmitFunctionEntryCode() {}
66
67  /// PreprocessISelDAG - This hook allows targets to hack on the graph before
68  /// instruction selection starts.
69  virtual void PreprocessISelDAG() {}
70
71  /// PostprocessISelDAG() - This hook allows the target to hack on the graph
72  /// right after selection.
73  virtual void PostprocessISelDAG() {}
74
75  /// Select - Main hook targets implement to select a node.
76  virtual SDNode *Select(SDNode *N) = 0;
77
78  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
79  /// addressing mode, according to the specified constraint code.  If this does
80  /// not match or is not implemented, return true.  The resultant operands
81  /// (which will appear in the machine instruction) should be added to the
82  /// OutOps vector.
83  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
84                                            char ConstraintCode,
85                                            std::vector<SDValue> &OutOps) {
86    return true;
87  }
88
89  /// IsProfitableToFold - Returns true if it's profitable to fold the specific
90  /// operand node N of U during instruction selection that starts at Root.
91  virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
92
93  /// IsLegalToFold - Returns true if the specific operand node N of
94  /// U can be folded during instruction selection that starts at Root.
95  /// FIXME: This is a static member function because the MSP430/SystemZ/X86
96  /// targets, which uses it during isel.  This could become a proper member.
97  static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
98                            CodeGenOpt::Level OptLevel,
99                            bool IgnoreChains = false);
100
101  /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
102  /// to use for this target when scheduling the DAG.
103  virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
104
105
106  // Opcodes used by the DAG state machine:
107  enum BuiltinOpcodes {
108    OPC_Scope,
109    OPC_RecordNode,
110    OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
111    OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
112    OPC_RecordMemRef,
113    OPC_CaptureFlagInput,
114    OPC_MoveChild,
115    OPC_MoveParent,
116    OPC_CheckSame,
117    OPC_CheckPatternPredicate,
118    OPC_CheckPredicate,
119    OPC_CheckOpcode,
120    OPC_SwitchOpcode,
121    OPC_CheckType,
122    OPC_SwitchType,
123    OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
124    OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
125    OPC_CheckChild6Type, OPC_CheckChild7Type,
126    OPC_CheckInteger,
127    OPC_CheckCondCode,
128    OPC_CheckValueType,
129    OPC_CheckComplexPat,
130    OPC_CheckAndImm, OPC_CheckOrImm,
131    OPC_CheckFoldableChainNode,
132
133    OPC_EmitInteger,
134    OPC_EmitRegister,
135    OPC_EmitConvertToTarget,
136    OPC_EmitMergeInputChains,
137    OPC_EmitMergeInputChains1_0,
138    OPC_EmitMergeInputChains1_1,
139    OPC_EmitCopyToReg,
140    OPC_EmitNodeXForm,
141    OPC_EmitNode,
142    OPC_MorphNodeTo,
143    OPC_MarkFlagResults,
144    OPC_CompleteMatch
145  };
146
147  enum {
148    OPFL_None       = 0,  // Node has no chain or flag input and isn't variadic.
149    OPFL_Chain      = 1,     // Node has a chain input.
150    OPFL_GlueInput  = 2,     // Node has a glue input.
151    OPFL_GlueOutput = 4,     // Node has a glue output.
152    OPFL_MemRefs    = 8,     // Node gets accumulated MemRefs.
153    OPFL_Variadic0  = 1<<4,  // Node is variadic, root has 0 fixed inputs.
154    OPFL_Variadic1  = 2<<4,  // Node is variadic, root has 1 fixed inputs.
155    OPFL_Variadic2  = 3<<4,  // Node is variadic, root has 2 fixed inputs.
156    OPFL_Variadic3  = 4<<4,  // Node is variadic, root has 3 fixed inputs.
157    OPFL_Variadic4  = 5<<4,  // Node is variadic, root has 4 fixed inputs.
158    OPFL_Variadic5  = 6<<4,  // Node is variadic, root has 5 fixed inputs.
159    OPFL_Variadic6  = 7<<4,  // Node is variadic, root has 6 fixed inputs.
160
161    OPFL_VariadicInfo = OPFL_Variadic6
162  };
163
164  /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
165  /// number of fixed arity values that should be skipped when copying from the
166  /// root.
167  static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
168    return ((Flags&OPFL_VariadicInfo) >> 4)-1;
169  }
170
171
172protected:
173  /// DAGSize - Size of DAG being instruction selected.
174  ///
175  unsigned DAGSize;
176
177  /// ISelPosition - Node iterator marking the current position of
178  /// instruction selection as it procedes through the topologically-sorted
179  /// node list.
180  SelectionDAG::allnodes_iterator ISelPosition;
181
182
183  /// ISelUpdater - helper class to handle updates of the
184  /// instruction selection graph.
185  class ISelUpdater : public SelectionDAG::DAGUpdateListener {
186    SelectionDAG::allnodes_iterator &ISelPosition;
187  public:
188    explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp)
189      : ISelPosition(isp) {}
190
191    /// NodeDeleted - Handle nodes deleted from the graph. If the
192    /// node being deleted is the current ISelPosition node, update
193    /// ISelPosition.
194    ///
195    virtual void NodeDeleted(SDNode *N, SDNode *E) {
196      if (ISelPosition == SelectionDAG::allnodes_iterator(N))
197        ++ISelPosition;
198    }
199
200    /// NodeUpdated - Ignore updates for now.
201    virtual void NodeUpdated(SDNode *N) {}
202  };
203
204  /// ReplaceUses - replace all uses of the old node F with the use
205  /// of the new node T.
206  void ReplaceUses(SDValue F, SDValue T) {
207    ISelUpdater ISU(ISelPosition);
208    CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISU);
209  }
210
211  /// ReplaceUses - replace all uses of the old nodes F with the use
212  /// of the new nodes T.
213  void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
214    ISelUpdater ISU(ISelPosition);
215    CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISU);
216  }
217
218  /// ReplaceUses - replace all uses of the old node F with the use
219  /// of the new node T.
220  void ReplaceUses(SDNode *F, SDNode *T) {
221    ISelUpdater ISU(ISelPosition);
222    CurDAG->ReplaceAllUsesWith(F, T, &ISU);
223  }
224
225
226  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
227  /// by tblgen.  Others should not call it.
228  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
229
230
231public:
232  // Calls to these predicates are generated by tblgen.
233  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
234                    int64_t DesiredMaskS) const;
235  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
236                    int64_t DesiredMaskS) const;
237
238
239  /// CheckPatternPredicate - This function is generated by tblgen in the
240  /// target.  It runs the specified pattern predicate and returns true if it
241  /// succeeds or false if it fails.  The number is a private implementation
242  /// detail to the code tblgen produces.
243  virtual bool CheckPatternPredicate(unsigned PredNo) const {
244    assert(0 && "Tblgen should generate the implementation of this!");
245    return 0;
246  }
247
248  /// CheckNodePredicate - This function is generated by tblgen in the target.
249  /// It runs node predicate number PredNo and returns true if it succeeds or
250  /// false if it fails.  The number is a private implementation
251  /// detail to the code tblgen produces.
252  virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
253    assert(0 && "Tblgen should generate the implementation of this!");
254    return 0;
255  }
256
257  virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
258                                   unsigned PatternNo,
259                        SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
260    assert(0 && "Tblgen should generate the implementation of this!");
261    return false;
262  }
263
264  virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
265    assert(0 && "Tblgen shoudl generate this!");
266    return SDValue();
267  }
268
269  SDNode *SelectCodeCommon(SDNode *NodeToMatch,
270                           const unsigned char *MatcherTable,
271                           unsigned TableSize);
272
273private:
274
275  // Calls to these functions are generated by tblgen.
276  SDNode *Select_INLINEASM(SDNode *N);
277  SDNode *Select_UNDEF(SDNode *N);
278  void CannotYetSelect(SDNode *N);
279
280private:
281  void DoInstructionSelection();
282  SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
283                    const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
284
285  void PrepareEHLandingPad();
286  void SelectAllBasicBlocks(const Function &Fn);
287  bool TryToFoldFastISelLoad(const LoadInst *LI, FastISel *FastIS);
288  void FinishBasicBlock();
289
290  void SelectBasicBlock(BasicBlock::const_iterator Begin,
291                        BasicBlock::const_iterator End,
292                        bool &HadTailCall);
293  void CodeGenAndEmitDAG();
294  void LowerArguments(const BasicBlock *BB);
295
296  void ComputeLiveOutVRegInfo();
297
298  /// Create the scheduler. If a specific scheduler was specified
299  /// via the SchedulerRegistry, use it, otherwise select the
300  /// one preferred by the target.
301  ///
302  ScheduleDAGSDNodes *CreateScheduler();
303
304  /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
305  /// state machines that start with a OPC_SwitchOpcode node.
306  std::vector<unsigned> OpcodeOffset;
307
308  void UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
309                           const SmallVectorImpl<SDNode*> &ChainNodesMatched,
310                           SDValue InputGlue, const SmallVectorImpl<SDNode*> &F,
311                           bool isMorphNodeTo);
312
313};
314
315}
316
317#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */
318