SelectionDAGISel.h revision c1c6ef8f74fc550f29cfec1f2fb699dd8c2fb94e 
1//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SelectionDAGISel class, which is used as the common
11// base class for SelectionDAG-based instruction selectors.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
17
18#include "llvm/BasicBlock.h"
19#include "llvm/Pass.h"
20#include "llvm/Constant.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22
23namespace llvm {
24  class FastISel;
25  class SelectionDAGLowering;
26  class SDValue;
27  class MachineRegisterInfo;
28  class MachineBasicBlock;
29  class MachineFunction;
30  class MachineInstr;
31  class MachineModuleInfo;
32  class DwarfWriter;
33  class TargetLowering;
34  class TargetInstrInfo;
35  class FunctionLoweringInfo;
36  class ScheduleHazardRecognizer;
37  class GCFunctionInfo;
38  class ScheduleDAGSDNodes;
39
40/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
41/// pattern-matching instruction selectors.
42class SelectionDAGISel : public FunctionPass {
43public:
44  const TargetMachine &TM;
45  TargetLowering &TLI;
46  FunctionLoweringInfo *FuncInfo;
47  MachineFunction *MF;
48  MachineRegisterInfo *RegInfo;
49  SelectionDAG *CurDAG;
50  SelectionDAGLowering *SDL;
51  MachineBasicBlock *BB;
52  AliasAnalysis *AA;
53  GCFunctionInfo *GFI;
54  CodeGenOpt::Level OptLevel;
55  static char ID;
56
57  explicit SelectionDAGISel(TargetMachine &tm,
58                            CodeGenOpt::Level OL = CodeGenOpt::Default);
59  virtual ~SelectionDAGISel();
60
61  TargetLowering &getTargetLowering() { return TLI; }
62
63  virtual void getAnalysisUsage(AnalysisUsage &AU) const;
64
65  virtual bool runOnFunction(Function &Fn);
66
67  unsigned MakeReg(MVT VT);
68
69  virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
70  virtual void InstructionSelect() = 0;
71
72  void SelectRootInit() {
73    DAGSize = CurDAG->AssignTopologicalOrder();
74  }
75
76  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
77  /// addressing mode, according to the specified constraint code.  If this does
78  /// not match or is not implemented, return true.  The resultant operands
79  /// (which will appear in the machine instruction) should be added to the
80  /// OutOps vector.
81  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
82                                            char ConstraintCode,
83                                            std::vector<SDValue> &OutOps) {
84    return true;
85  }
86
87  /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of
88  /// U can be folded during instruction selection that starts at Root and
89  /// folding N is profitable.
90  virtual
91  bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
92
93  /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
94  /// to use for this target when scheduling the DAG.
95  virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
96
97protected:
98  /// DAGSize - Size of DAG being instruction selected.
99  ///
100  unsigned DAGSize;
101
102  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
103  /// by tblgen.  Others should not call it.
104  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
105
106  // Calls to these predicates are generated by tblgen.
107  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
108                    int64_t DesiredMaskS) const;
109  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
110                    int64_t DesiredMaskS) const;
111
112private:
113  void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
114                            MachineModuleInfo *MMI,
115                            DwarfWriter *DW,
116                            const TargetInstrInfo &TII);
117  void FinishBasicBlock();
118
119  void SelectBasicBlock(BasicBlock *LLVMBB,
120                        BasicBlock::iterator Begin,
121                        BasicBlock::iterator End);
122  void CodeGenAndEmitDAG();
123  void LowerArguments(BasicBlock *BB);
124
125  void ComputeLiveOutVRegInfo();
126
127  void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
128
129  bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
130
131  /// Create the scheduler. If a specific scheduler was specified
132  /// via the SchedulerRegistry, use it, otherwise select the
133  /// one preferred by the target.
134  ///
135  ScheduleDAGSDNodes *CreateScheduler();
136};
137
138}
139
140#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */
141