SelectionDAGISel.h revision c6d7ad3c7d83e9af29bf3ba3bf3280e72a952f98 
1//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SelectionDAGISel class, which is used as the common
11// base class for SelectionDAG-based instruction selectors.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
17
18#include "llvm/BasicBlock.h"
19#include "llvm/Pass.h"
20#include "llvm/Constant.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23
24namespace llvm {
25  class FastISel;
26  class SelectionDAGBuilder;
27  class SDValue;
28  class MachineRegisterInfo;
29  class MachineBasicBlock;
30  class MachineFunction;
31  class MachineInstr;
32  class MachineModuleInfo;
33  class DwarfWriter;
34  class TargetLowering;
35  class TargetInstrInfo;
36  class FunctionLoweringInfo;
37  class ScheduleHazardRecognizer;
38  class GCFunctionInfo;
39  class ScheduleDAGSDNodes;
40
41/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
42/// pattern-matching instruction selectors.
43class SelectionDAGISel : public MachineFunctionPass {
44public:
45  const TargetMachine &TM;
46  TargetLowering &TLI;
47  FunctionLoweringInfo *FuncInfo;
48  MachineFunction *MF;
49  MachineRegisterInfo *RegInfo;
50  SelectionDAG *CurDAG;
51  SelectionDAGBuilder *SDB;
52  MachineBasicBlock *BB;
53  AliasAnalysis *AA;
54  GCFunctionInfo *GFI;
55  CodeGenOpt::Level OptLevel;
56  static char ID;
57
58  explicit SelectionDAGISel(TargetMachine &tm,
59                            CodeGenOpt::Level OL = CodeGenOpt::Default);
60  virtual ~SelectionDAGISel();
61
62  TargetLowering &getTargetLowering() { return TLI; }
63
64  virtual void getAnalysisUsage(AnalysisUsage &AU) const;
65
66  virtual bool runOnMachineFunction(MachineFunction &MF);
67
68  unsigned MakeReg(EVT VT);
69
70  virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
71  virtual void InstructionSelect() = 0;
72
73  void SelectRootInit() {
74    DAGSize = CurDAG->AssignTopologicalOrder();
75  }
76
77  /// SelectInlineAsmMemoryOperand - Select the specified address as a target
78  /// addressing mode, according to the specified constraint code.  If this does
79  /// not match or is not implemented, return true.  The resultant operands
80  /// (which will appear in the machine instruction) should be added to the
81  /// OutOps vector.
82  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
83                                            char ConstraintCode,
84                                            std::vector<SDValue> &OutOps) {
85    return true;
86  }
87
88  /// IsProfitableToFold - Returns true if it's profitable to fold the specific
89  /// operand node N of U during instruction selection that starts at Root.
90  virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
91
92  /// IsLegalToFold - Returns true if the specific operand node N of
93  /// U can be folded during instruction selection that starts at Root.
94  virtual bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const;
95
96  /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
97  /// to use for this target when scheduling the DAG.
98  virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
99
100
101  // Opcodes used by the DAG state machine:
102  enum BuiltinOpcodes {
103    OPC_Scope,
104    OPC_RecordNode,
105    OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
106    OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
107    OPC_RecordMemRef,
108    OPC_CaptureFlagInput,
109    OPC_MoveChild,
110    OPC_MoveParent,
111    OPC_CheckSame,
112    OPC_CheckPatternPredicate,
113    OPC_CheckPredicate,
114    OPC_CheckOpcode,
115    OPC_SwitchOpcode,
116    OPC_CheckType,
117    OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
118    OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
119    OPC_CheckChild6Type, OPC_CheckChild7Type,
120    OPC_CheckInteger,
121    OPC_CheckCondCode,
122    OPC_CheckValueType,
123    OPC_CheckComplexPat,
124    OPC_CheckAndImm, OPC_CheckOrImm,
125    OPC_CheckFoldableChainNode,
126
127    OPC_EmitInteger,
128    OPC_EmitRegister,
129    OPC_EmitConvertToTarget,
130    OPC_EmitMergeInputChains,
131    OPC_EmitCopyToReg,
132    OPC_EmitNodeXForm,
133    OPC_EmitNode,
134    OPC_MorphNodeTo,
135    OPC_MarkFlagResults,
136    OPC_CompleteMatch
137  };
138
139  enum {
140    OPFL_None       = 0,     // Node has no chain or flag input and isn't variadic.
141    OPFL_Chain      = 1,     // Node has a chain input.
142    OPFL_FlagInput  = 2,     // Node has a flag input.
143    OPFL_FlagOutput = 4,     // Node has a flag output.
144    OPFL_MemRefs    = 8,     // Node gets accumulated MemRefs.
145    OPFL_Variadic0  = 1<<4,  // Node is variadic, root has 0 fixed inputs.
146    OPFL_Variadic1  = 2<<4,  // Node is variadic, root has 1 fixed inputs.
147    OPFL_Variadic2  = 3<<4,  // Node is variadic, root has 2 fixed inputs.
148    OPFL_Variadic3  = 4<<4,  // Node is variadic, root has 3 fixed inputs.
149    OPFL_Variadic4  = 5<<4,  // Node is variadic, root has 4 fixed inputs.
150    OPFL_Variadic5  = 6<<4,  // Node is variadic, root has 5 fixed inputs.
151    OPFL_Variadic6  = 7<<4,  // Node is variadic, root has 6 fixed inputs.
152
153    OPFL_VariadicInfo = OPFL_Variadic6
154  };
155
156  /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
157  /// number of fixed arity values that should be skipped when copying from the
158  /// root.
159  static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
160    return ((Flags&OPFL_VariadicInfo) >> 4)-1;
161  }
162
163
164protected:
165  /// DAGSize - Size of DAG being instruction selected.
166  ///
167  unsigned DAGSize;
168
169  /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
170  /// by tblgen.  Others should not call it.
171  void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
172
173  // Calls to these predicates are generated by tblgen.
174  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
175                    int64_t DesiredMaskS) const;
176  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
177                    int64_t DesiredMaskS) const;
178
179
180  /// CheckPatternPredicate - This function is generated by tblgen in the
181  /// target.  It runs the specified pattern predicate and returns true if it
182  /// succeeds or false if it fails.  The number is a private implementation
183  /// detail to the code tblgen produces.
184  virtual bool CheckPatternPredicate(unsigned PredNo) const {
185    assert(0 && "Tblgen should generate the implementation of this!");
186    return 0;
187  }
188
189  /// CheckNodePredicate - This function is generated by tblgen in the target.
190  /// It runs node predicate number PredNo and returns true if it succeeds or
191  /// false if it fails.  The number is a private implementation
192  /// detail to the code tblgen produces.
193  virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
194    assert(0 && "Tblgen should generate the implementation of this!");
195    return 0;
196  }
197
198  virtual bool CheckComplexPattern(SDNode *Root, SDValue N, unsigned PatternNo,
199                                   SmallVectorImpl<SDValue> &Result) {
200    assert(0 && "Tblgen should generate the implementation of this!");
201    return false;
202  }
203
204  virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
205    assert(0 && "Tblgen shoudl generate this!");
206    return SDValue();
207  }
208
209
210  // Calls to these functions are generated by tblgen.
211  SDNode *Select_INLINEASM(SDNode *N);
212  SDNode *Select_UNDEF(SDNode *N);
213  SDNode *Select_EH_LABEL(SDNode *N);
214
215  SDNode *SelectCodeCommon(SDNode *NodeToMatch,
216                           const unsigned char *MatcherTable,
217                           unsigned TableSize);
218  void CannotYetSelect(SDNode *N);
219  void CannotYetSelectIntrinsic(SDNode *N);
220
221private:
222  void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
223                            MachineModuleInfo *MMI,
224                            DwarfWriter *DW,
225                            const TargetInstrInfo &TII);
226  void FinishBasicBlock();
227
228  void SelectBasicBlock(BasicBlock *LLVMBB,
229                        BasicBlock::iterator Begin,
230                        BasicBlock::iterator End,
231                        bool &HadTailCall);
232  void CodeGenAndEmitDAG();
233  void LowerArguments(BasicBlock *BB);
234
235  void ShrinkDemandedOps();
236  void ComputeLiveOutVRegInfo();
237
238  void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
239
240  bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
241
242  /// Create the scheduler. If a specific scheduler was specified
243  /// via the SchedulerRegistry, use it, otherwise select the
244  /// one preferred by the target.
245  ///
246  ScheduleDAGSDNodes *CreateScheduler();
247
248  /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
249  /// state machines that start with a OPC_SwitchOpcode node.
250  std::vector<unsigned> OpcodeOffset;
251};
252
253}
254
255#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */
256