SelectionDAGISel.h revision e1f188fe27050ec812e5b64cc996e6bb93300392
1//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAGISel class, which is used as the common 11// base class for SelectionDAG-based instruction selectors. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H 16#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H 17 18#include "llvm/BasicBlock.h" 19#include "llvm/Pass.h" 20#include "llvm/Constant.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/MachineFunctionPass.h" 23 24namespace llvm { 25 class FastISel; 26 class SelectionDAGLowering; 27 class SDValue; 28 class MachineRegisterInfo; 29 class MachineBasicBlock; 30 class MachineFunction; 31 class MachineInstr; 32 class MachineModuleInfo; 33 class DwarfWriter; 34 class TargetLowering; 35 class TargetInstrInfo; 36 class FunctionLoweringInfo; 37 class ScheduleHazardRecognizer; 38 class GCFunctionInfo; 39 class ScheduleDAGSDNodes; 40 41/// SelectionDAGISel - This is the common base class used for SelectionDAG-based 42/// pattern-matching instruction selectors. 43class SelectionDAGISel : public MachineFunctionPass { 44public: 45 const TargetMachine &TM; 46 TargetLowering &TLI; 47 FunctionLoweringInfo *FuncInfo; 48 MachineFunction *MF; 49 MachineRegisterInfo *RegInfo; 50 SelectionDAG *CurDAG; 51 SelectionDAGLowering *SDL; 52 MachineBasicBlock *BB; 53 AliasAnalysis *AA; 54 GCFunctionInfo *GFI; 55 CodeGenOpt::Level OptLevel; 56 static char ID; 57 58 explicit SelectionDAGISel(TargetMachine &tm, 59 CodeGenOpt::Level OL = CodeGenOpt::Default); 60 virtual ~SelectionDAGISel(); 61 62 TargetLowering &getTargetLowering() { return TLI; } 63 64 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 65 66 virtual bool runOnMachineFunction(MachineFunction &MF); 67 68 unsigned MakeReg(EVT VT); 69 70 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {} 71 virtual void InstructionSelect() = 0; 72 73 void SelectRootInit() { 74 DAGSize = CurDAG->AssignTopologicalOrder(); 75 } 76 77 /// SelectInlineAsmMemoryOperand - Select the specified address as a target 78 /// addressing mode, according to the specified constraint code. If this does 79 /// not match or is not implemented, return true. The resultant operands 80 /// (which will appear in the machine instruction) should be added to the 81 /// OutOps vector. 82 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 83 char ConstraintCode, 84 std::vector<SDValue> &OutOps) { 85 return true; 86 } 87 88 /// IsLegalAndProfitableToFold - Returns true if the specific operand node N of 89 /// U can be folded during instruction selection that starts at Root and 90 /// folding N is profitable. 91 virtual 92 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const; 93 94 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer 95 /// to use for this target when scheduling the DAG. 96 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer(); 97 98protected: 99 /// DAGSize - Size of DAG being instruction selected. 100 /// 101 unsigned DAGSize; 102 103 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 104 /// by tblgen. Others should not call it. 105 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops); 106 107 // Calls to these predicates are generated by tblgen. 108 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 109 int64_t DesiredMaskS) const; 110 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 111 int64_t DesiredMaskS) const; 112 113 // Calls to these functions are generated by tblgen. 114 SDNode *Select_INLINEASM(SDValue N); 115 SDNode *Select_UNDEF(const SDValue &N); 116 SDNode *Select_DBG_LABEL(const SDValue &N); 117 SDNode *Select_EH_LABEL(const SDValue &N); 118 void CannotYetSelect(SDValue N); 119 void CannotYetSelectIntrinsic(SDValue N); 120 121private: 122 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF, 123 MachineModuleInfo *MMI, 124 DwarfWriter *DW, 125 const TargetInstrInfo &TII); 126 void FinishBasicBlock(); 127 128 void SelectBasicBlock(BasicBlock *LLVMBB, 129 BasicBlock::iterator Begin, 130 BasicBlock::iterator End); 131 void CodeGenAndEmitDAG(); 132 void LowerArguments(BasicBlock *BB); 133 134 void ComputeLiveOutVRegInfo(); 135 136 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB); 137 138 bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F); 139 140 /// Create the scheduler. If a specific scheduler was specified 141 /// via the SchedulerRegistry, use it, otherwise select the 142 /// one preferred by the target. 143 /// 144 ScheduleDAGSDNodes *CreateScheduler(); 145}; 146 147} 148 149#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */ 150