16f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 93d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 103d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// This file describes an abstract interface used to get information about a 113d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// target machines register file. This information is used for a variety of 123d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// purposed, especially register allocation. 133d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 143d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner//===----------------------------------------------------------------------===// 153d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 166f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#define LLVM_TARGET_TARGETREGISTERINFO_H 183d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 1979c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen#include "llvm/ADT/ArrayRef.h" 20255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/CodeGen/MachineBasicBlock.h" 21255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/CodeGen/ValueTypes.h" 220b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/CallingConv.h" 23255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/MC/MCRegisterInfo.h" 244d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <cassert> 254d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <functional> 263d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 27d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 28d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 29171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass BitVector; 30198ab640bbb0b8e1cdda518b7f8b348764e4402cChris Lattnerclass MachineFunction; 31171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass RegScavenger; 32b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Chengtemplate<class T> class SmallVectorImpl; 337eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesenclass VirtRegMap; 34414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesenclass raw_ostream; 35282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 36f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramerclass TargetRegisterClass { 37282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukmanpublic: 38e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen typedef const MCPhysReg* iterator; 39e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen typedef const MCPhysReg* const_iterator; 402c6ae095b8a944c8355377498b9ad11bb94af2d5Benjamin Kramer typedef const MVT::SimpleValueType* vt_iterator; 413b0c0148ed9ec752b240dbea767ad4a9f0a682caEvan Cheng typedef const TargetRegisterClass* const * sc_iterator; 42ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer 43ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer // Instance variables filled by tablegen, do not use! 44f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer const MCRegisterClass *MC; 4516d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner const vt_iterator VTs; 461d61f283fad2e49d3e50a3585aac4cc9183a0d28Jakob Stoklund Olesen const uint32_t *SubClassMask; 471a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen const uint16_t *SuperRegIndices; 48c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng const sc_iterator SuperClasses; 49e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&); 50320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen 51f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getID() - Return the register class ID number. 52f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 53f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getID() const { return MC->getID(); } 54f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 55f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getName() - Return the register class name for debugging. 56f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 57f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer const char *getName() const { return MC->getName(); } 58f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 59f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// begin/end - Return all of the registers in this class. 60f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 61f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer iterator begin() const { return MC->begin(); } 62f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer iterator end() const { return MC->end(); } 63f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 64f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getNumRegs - Return the number of registers in this class. 65f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 66f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getNumRegs() const { return MC->getNumRegs(); } 67f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 68f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getRegister - Return the specified register in the class. 69f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 70f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getRegister(unsigned i) const { 71f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->getRegister(i); 72f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 73f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 74f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// contains - Return true if the specified register is included in this 75f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// register class. This does not include virtual registers. 76f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool contains(unsigned Reg) const { 77f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->contains(Reg); 78f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 79f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 80f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// contains - Return true if both registers are in this class. 81f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool contains(unsigned Reg1, unsigned Reg2) const { 82f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->contains(Reg1, Reg2); 83f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 84f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 85f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getSize - Return the size of the register in bytes, which is also the size 86f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// of a stack slot allocated to hold a spilled copy of this register. 87f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getSize() const { return MC->getSize(); } 88f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 89f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getAlignment - Return the minimum required alignment for a register of 90f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// this class. 91f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getAlignment() const { return MC->getAlignment(); } 92f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 93f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getCopyCost - Return the cost of copying a value between two registers in 94f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// this class. A negative number means the register class is very expensive 95f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// to copy e.g. status flag register classes. 96f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer int getCopyCost() const { return MC->getCopyCost(); } 97f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 98f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// isAllocatable - Return true if this register class may be used to create 99f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// virtual registers. 100f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool isAllocatable() const { return MC->isAllocatable(); } 101f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 1026510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman /// hasType - return true if this TargetRegisterClass has the ValueType vt. 1036510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman /// 104e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson bool hasType(EVT vt) const { 105cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands for(int i = 0; VTs[i] != MVT::Other; ++i) 1062c6ae095b8a944c8355377498b9ad11bb94af2d5Benjamin Kramer if (EVT(VTs[i]) == vt) 1076510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return true; 1086510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return false; 1096510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman } 11095923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 111696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// vt_begin / vt_end - Loop over all of the value types that can be 112696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// represented by values in this register class. 11316d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_begin() const { 11416d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return VTs; 11516d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 11616d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner 11716d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_end() const { 11816d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator I = VTs; 119cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands while (*I != MVT::Other) ++I; 12016d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return I; 12116d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 122696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 123f451cb870efcf9e0302d25ed05f4cac6bb494e42Dan Gohman /// hasSubClass - return true if the specified TargetRegisterClass 124c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// is a proper sub-class of this TargetRegisterClass. 125c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen bool hasSubClass(const TargetRegisterClass *RC) const { 126c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC != this && hasSubClassEq(RC); 127696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 128696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 129c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 1301f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// class. 1311f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSubClassEq(const TargetRegisterClass *RC) const { 132c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen unsigned ID = RC->getID(); 133c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 134696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 13595923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 1361367fd09cb021bae61e7dd2ee208f76574c8e789Christopher Lamb /// hasSuperClass - return true if the specified TargetRegisterClass is a 137c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// proper super-class of this TargetRegisterClass. 138c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen bool hasSuperClass(const TargetRegisterClass *RC) const { 139c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC->hasSubClass(this); 140c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 141c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng 142c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 1431f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// class. 1441f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSuperClassEq(const TargetRegisterClass *RC) const { 145c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC->hasSubClassEq(this); 1461f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen } 1471f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen 148c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// getSubClassMask - Returns a bit vector of subclasses, including this one. 149c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 150c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// use it. 1519ebfbf8b9fd5f982e0db9293808bd32168615ba9Craig Topper const uint32_t *getSubClassMask() const { 152c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return SubClassMask; 153c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 15495923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 1551a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// getSuperRegIndices - Returns a 0-terminated list of sub-register indices 156b7e22efa2b2a66b7d55c0297e45c217a465621ffEric Christopher /// that project some super-register class into this register class. The list 1571a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// has an entry for each Idx such that: 1581a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// 1591a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// There exists SuperRC where: 1601a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// For all Reg in SuperRC: 1611a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// this->contains(Reg:Idx) 1621a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// 1631a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen const uint16_t *getSuperRegIndices() const { 1641a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen return SuperRegIndices; 1651a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen } 1661a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen 167c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// getSuperClasses - Returns a NULL terminated list of super-classes. The 168c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// classes are ordered by ID which is also a topological ordering from large 169c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// to small classes. The list does NOT include the current class. 170c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen sc_iterator getSuperClasses() const { 171c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return SuperClasses; 172c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 1738c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng 174f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// isASubClass - return true if this TargetRegisterClass is a subset 175f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// class of at least one other TargetRegisterClass. 1768c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng bool isASubClass() const { 1778c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng return SuperClasses[0] != 0; 1788c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng } 17995923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 18079c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// getRawAllocationOrder - Returns the preferred order for allocating 18179c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// registers from this register class in MF. The raw order comes directly 18279c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// from the .td file and may include reserved registers that are not 18379c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// allocatable. Register allocators should also make sure to allocate 18479c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// callee-saved registers only after all the volatiles are used. The 18579c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// RegisterClassInfo class provides filtered allocation orders with 18679c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// callee-saved registers moved to the end. 18779c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 18879c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// The MachineFunction argument can be used to tune the allocatable 18979c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// registers based on the characteristics of the function, subtarget, or 19079c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// other criteria. 19179c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 19279c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// By default, this method returns all registers in the class. 19379c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 194e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const { 195ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 19679c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen } 197282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman}; 198282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 199a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 200a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// registers. These are used by codegen, not by MC. 201a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengstruct TargetRegisterInfoDesc { 202a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng unsigned CostPerUse; // Extra cost of instructions using register. 203a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng bool inAllocatableClass; // Register belongs to an allocatable regclass. 204a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng}; 205282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 206ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick/// Each TargetRegisterClass has a per register weight, and weight 207ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick/// limit which must be less than the limits of its pressure sets. 208ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trickstruct RegClassWeight { 20933d9e89e5f8d7656e50353b014d5bb1b52f15e13Andrew Trick unsigned RegWeight; 210ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick unsigned WeightLimit; 211ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick}; 212ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick 2136f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// TargetRegisterInfo base class - We assume that the target defines a static 2146f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// array of TargetRegisterDesc objects that represent all of the machine 2156f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// registers that the target has. As such, we simply have to track a pointer 2166f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// to this array so that we can turn register number into a register 2176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// descriptor. 2183d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// 219a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengclass TargetRegisterInfo : public MCRegisterInfo { 2208797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerpublic: 2218797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner typedef const TargetRegisterClass * const * regclass_iterator; 2228797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerprivate: 223a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 2241fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *const *SubRegIndexNames; // Names of subreg indexes. 225a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen // Pointer to array of lane masks, one per sub-reg index. 226a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen const unsigned *SubRegIndexLaneMasks; 227a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen 2288797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 229997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen unsigned CoveringLanes; 230b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene 2313d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerprotected: 232a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 2336f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassBegin, 2346f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassEnd, 235a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen const char *const *SRINames, 236997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen const unsigned *SRILaneMasks, 237997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen unsigned CoveringLanes); 2386f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman virtual ~TargetRegisterInfo(); 2393d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerpublic: 2403d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 241b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Register numbers can represent physical registers, virtual registers, and 242b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // sometimes stack slots. The unsigned values are divided into these ranges: 243b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 244b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 0 Not a register, can be used as a sentinel. 245b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [1;2^30) Physical registers assigned by TableGen. 246b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^30;2^31) Stack slots. (Rarely used.) 247b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 248b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 249b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Further sentinels can be allocated from the small negative integers. 250b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // DenseMapInfo<unsigned> uses -1u and -2u. 2513d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 252be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// isStackSlot - Sometimes it is useful the be able to store a non-negative 253be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// frame index in a variable that normally holds a register. isStackSlot() 254be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// returns true if Reg is in the range used for stack slots. 255be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 256da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 257da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// slots, so if a variable may contains a stack slot, always check 258da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// isStackSlot() first. 259be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 260be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static bool isStackSlot(unsigned Reg) { 261da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) >= (1 << 30); 262be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 263be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 264be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// stackSlot2Index - Compute the frame index from a register value 265be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// representing a stack slot. 266be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static int stackSlot2Index(unsigned Reg) { 267be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(isStackSlot(Reg) && "Not a stack slot"); 268da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg - (1u << 30)); 269be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 270be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 271be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// index2StackSlot - Convert a non-negative frame index to a stack slot 272be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// register value. 273be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static unsigned index2StackSlot(int FI) { 274be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(FI >= 0 && "Cannot hold a negative frame index."); 275da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return FI + (1u << 30); 276be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 277be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 278bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// isPhysicalRegister - Return true if the specified register number is in 279bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the physical register namespace. 280bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isPhysicalRegister(unsigned Reg) { 281da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 282da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) > 0; 283bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 284bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 285bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// isVirtualRegister - Return true if the specified register number is in 286bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the virtual register namespace. 287bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isVirtualRegister(unsigned Reg) { 288da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 289da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) < 0; 290bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 291bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 292c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen /// virtReg2Index - Convert a virtual register number to a 0-based index. 293c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen /// The first virtual register in a function will get the index 0. 294c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen static unsigned virtReg2Index(unsigned Reg) { 295da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(isVirtualRegister(Reg) && "Not a virtual register"); 296dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Reg & ~(1u << 31); 297c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen } 298c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen 299b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// index2VirtReg - Convert a 0-based index to a virtual register number. 300b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// This is the inverse operation of VirtReg2IndexFunctor below. 301b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen static unsigned index2VirtReg(unsigned Index) { 302dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Index | (1u << 31); 303b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen } 304b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 305ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola /// getMinimalPhysRegClass - Returns the Register Class of a physical 306c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman /// register of the given type, picking the most sub register class of 307c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman /// the right type that contains this physreg. 308d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola const TargetRegisterClass * 309d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 310ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 311f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick /// getAllocatableClass - Return the maximal subclass of the given register 312f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick /// class that is alloctable, or NULL. 313f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick const TargetRegisterClass * 314f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick getAllocatableClass(const TargetRegisterClass *RC) const; 315f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick 316bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos /// getAllocatableSet - Returns a bitset indexed by register number 317eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng /// indicating if a register is allocatable or not. If a register class is 318eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng /// specified, returns the subset for the class. 319769b7f89534caed11d7595b5c84aa47d3de30ad9Dan Gohman BitVector getAllocatableSet(const MachineFunction &MF, 320eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng const TargetRegisterClass *RC = NULL) const; 321bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos 3226bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen /// getCostPerUse - Return the additional cost of using this register instead 3236bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen /// of other registers in its class. 3246bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen unsigned getCostPerUse(unsigned RegNo) const { 325a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return InfoDesc[RegNo].CostPerUse; 3266bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen } 3276bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen 328a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// isInAllocatableClass - Return true if the register is in the allocation 329a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// of any register class. 330a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng bool isInAllocatableClass(unsigned RegNo) const { 331a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return InfoDesc[RegNo].inAllocatableClass; 33293aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos } 33393aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos 3341fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen /// getSubRegIndexName - Return the human-readable symbolic target-specific 3351fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen /// name for the specified SubRegIndex. 3361fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *getSubRegIndexName(unsigned SubIdx) const { 33759f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen assert(SubIdx && SubIdx < getNumSubRegIndices() && 33859f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen "This is not a subregister index"); 3391fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen return SubRegIndexNames[SubIdx-1]; 3401fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen } 3411fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen 342a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// getSubRegIndexLaneMask - Return a bitmask representing the parts of a 343a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// register that are covered by SubIdx. 344a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 345a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// Lane masks for sub-register indices are similar to register units for 346a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// physical registers. The individual bits in a lane mask can't be assigned 347a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// any specific meaning. They can be used to check if two sub-register 348a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// indices overlap. 349a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 350a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// If the target has a register such that: 351a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 352a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// getSubReg(Reg, A) overlaps getSubReg(Reg, B) 353a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 354a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// then: 355a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 356a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0 357a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 358a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// The converse is not necessarily true. If two lane masks have a common 359a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// bit, the corresponding sub-registers may not overlap, but it can be 360a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// assumed that they usually will. 361a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { 362a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen // SubIdx == 0 is allowed, it has the lane mask ~0u. 363a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); 364a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen return SubRegIndexLaneMasks[SubIdx]; 365a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen } 366a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen 367997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// The lane masks returned by getSubRegIndexLaneMask() above can only be 368997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// used to determine if sub-registers overlap - they can't be used to 369997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// determine if a set of sub-registers completely cover another 370997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// sub-register. 371997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// 372997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// The X86 general purpose registers have two lanes corresponding to the 373997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have 374997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the 375997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// sub_32bit sub-register. 376997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// 377997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// On the other hand, the ARM NEON lanes fully cover their registers: The 378997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. 379997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// This is related to the CoveredBySubRegs property on register definitions. 380997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// 381997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// This function returns a bit mask of lanes that completely cover their 382997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// sub-registers. More precisely, given: 383997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// 384997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// Covering = getCoveringLanes(); 385997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// MaskA = getSubRegIndexLaneMask(SubA); 386997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// MaskB = getSubRegIndexLaneMask(SubB); 387997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// 388997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by 389997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen /// SubB. 390997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen unsigned getCoveringLanes() const { return CoveringLanes; } 391997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen 3923f2f3f5341374c85955cfaffa71886724999762dLang Hames /// regsOverlap - Returns true if the two registers are equal or alias each 3933f2f3f5341374c85955cfaffa71886724999762dLang Hames /// other. The registers may be virtual register. 3943f2f3f5341374c85955cfaffa71886724999762dLang Hames bool regsOverlap(unsigned regA, unsigned regB) const { 3951e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (regA == regB) return true; 3963f2f3f5341374c85955cfaffa71886724999762dLang Hames if (isVirtualRegister(regA) || isVirtualRegister(regB)) 3973f2f3f5341374c85955cfaffa71886724999762dLang Hames return false; 39896feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen 39996feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen // Regunits are numerically ordered. Find a common unit. 40096feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen MCRegUnitIterator RUA(regA, this); 40196feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen MCRegUnitIterator RUB(regB, this); 40296feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen do { 40396feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen if (*RUA == *RUB) return true; 40496feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen if (*RUA < *RUB) ++RUA; 40596feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen else ++RUB; 40696feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen } while (RUA.isValid() && RUB.isValid()); 40704319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos return false; 40804319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos } 40904319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos 41028897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen /// hasRegUnit - Returns true if Reg contains RegUnit. 41128897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { 41228897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units) 41328897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen if (*Units == RegUnit) 41428897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen return true; 41528897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen return false; 41628897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen } 41728897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen 4180098b3e2b69e527ddcf2ebad7a3081898fa3b4f0Evan Cheng /// getCalleeSavedRegs - Return a null-terminated list of all of the 4190098b3e2b69e527ddcf2ebad7a3081898fa3b4f0Evan Cheng /// callee saved registers on this target. The register should be in the 42002569d7355b03155b32c1c0d0e46f6aa957f4802Evan Cheng /// order of desired callee-save stack frame offset. The first register is 421bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// closest to the incoming stack pointer if stack grows down, and vice versa. 422bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 423e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen virtual const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF = 0) 4242365f51ed03afe6993bae962fdc2e5a956a64cd5Anton Korobeynikov const = 0; 4258797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 426bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// getCallPreservedMask - Return a mask of call-preserved registers for the 427bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// given calling convention on the current sub-target. The mask should 428bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// include all call-preserved aliases. This is used by the register 429bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// allocator to determine which registers can be live across a call. 430bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 431bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 432bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// A set bit indicates that all bits of the corresponding register are 433bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// preserved across the function call. The bit mask is expected to be 434bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// sub-register complete, i.e. if A is preserved, so are all its 435bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// sub-registers. 436bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 437bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// Bits are numbered from the LSB, so the bit for physical register Reg can 438bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 439478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// 440478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// A NULL pointer means that no register mask will be used, and call 441478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// instructions should use implicit-def operands to indicate call clobbered 442478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// registers. 443bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 444bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { 445bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen // The default mask clobbers everything. All targets should override. 446bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen return 0; 447bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen } 4488797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 449b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng /// getReservedRegs - Returns a bitset indexed by physical register number 4501c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// indicating if a register is a special register that has particular uses 4511c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// and should be considered unavailable at all times, e.g. SP, RA. This is 4521c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// used by register scavenger to determine what registers are free. 453b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 454b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 4558a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng /// getMatchingSuperReg - Return a super-register of the specified register 4568a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng /// Reg so its sub-register of index SubIdx is Reg. 45795923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 4588a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng const TargetRegisterClass *RC) const { 45933ca87affb81b60c4d50214eb7458bd26d397d53Jim Grosbach return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 4608a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng } 4618a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng 4625248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// getMatchingSuperRegClass - Return a subclass of the specified register 4635248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// class A so that each register in it has a sub-register of the 4645248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// specified sub-register index which is in the specified register class B. 465570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// 466570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// TableGen will synthesize missing A sub-classes. 4675248468473f0488a652b545ad95f7abda302b7b5Evan Cheng virtual const TargetRegisterClass * 4685248468473f0488a652b545ad95f7abda302b7b5Evan Cheng getMatchingSuperRegClass(const TargetRegisterClass *A, 469dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen const TargetRegisterClass *B, unsigned Idx) const; 4705248468473f0488a652b545ad95f7abda302b7b5Evan Cheng 471845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 472845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// supports the sub-register index Idx. 473845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// If no such sub-class exists, return NULL. 474845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// If all registers in RC already have an Idx sub-register, return RC. 475845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// 476845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// TableGen generates a version of this function that is good enough in most 477845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// cases. Targets can override if they have constraints that TableGen 478845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// doesn't understand. For example, the x86 sub_8bit sub-register index is 479845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// supported by the full GR32 register class in 64-bit mode, but only by the 480845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// GR32_ABCD regiister class in 32-bit mode. 481845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// 482570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// TableGen will synthesize missing RC sub-classes. 483845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen virtual const TargetRegisterClass * 484309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 485309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen assert(Idx == 0 && "Target has no sub-registers"); 486309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen return RC; 487309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen } 488845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen 4892da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// composeSubRegIndices - Return the subregister index you get from composing 4902da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// two subregister indices. 4912da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 492ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen /// The special null sub-register index composes as the identity. 493ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen /// 4942da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 4952da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// returns c. Note that composeSubRegIndices does not tell you about illegal 4962da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// compositions. If R does not have a subreg a, or R:a does not have a subreg 4972da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// b, composeSubRegIndices doesn't tell you. 4982da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 4992da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 5002da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// ssub_0:S0 - ssub_3:S3 subregs. 5012da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 5022da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 503ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen unsigned composeSubRegIndices(unsigned a, unsigned b) const { 504ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen if (!a) return b; 505ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen if (!b) return a; 506ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen return composeSubRegIndicesImpl(a, b); 5072da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen } 5082da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen 509ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesenprotected: 510ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen /// Overridden by TableGen in targets that have sub-registers. 511ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const { 512ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen llvm_unreachable("Target has no sub-registers"); 513ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen } 514ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen 515ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesenpublic: 516fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// getCommonSuperRegClass - Find a common super-register class if it exists. 517fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 518fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// Find a register class, SuperRC and two sub-register indices, PreA and 519fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// PreB, such that: 520fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 521fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and 522fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 523fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and 524fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 525fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()). 526fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 527fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// SuperRC will be chosen such that no super-class of SuperRC satisfies the 528fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// requirements, and there is no register class with a smaller spill size 529fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// that satisfies the requirements. 530fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 531fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead. 532fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 533fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// Either of the PreA and PreB sub-register indices may be returned as 0. In 534fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// that case, the returned register class will be a sub-class of the 535fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// corresponding argument register class. 536fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 537fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// The function returns NULL if no register class can be found. 538fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 539fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterClass* 540fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 541fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterClass *RCB, unsigned SubB, 542fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned &PreA, unsigned &PreB) const; 543fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 5448797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner //===--------------------------------------------------------------------===// 5458797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // Register Class Information 5468797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // 5478797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 5488797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner /// Register class iterators 54992988ecdb6ca641ba39d1d1f8cbc57a89b63bbadChris Lattner /// 5508797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_begin() const { return RegClassBegin; } 5518797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_end() const { return RegClassEnd; } 5528797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 5538797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner unsigned getNumRegClasses() const { 55434cd4a484e532cc463fd5a4bf59b88d13c5467c1Evan Cheng return (unsigned)(regclass_end()-regclass_begin()); 5558797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner } 55695923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 55760f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// getRegClass - Returns the register class associated with the enumeration 558e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// value. See class MCOperandInfo. 55960f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey const TargetRegisterClass *getRegClass(unsigned i) const { 560a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman assert(i < getNumRegClasses() && "Register Class ID out of range"); 561a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman return RegClassBegin[i]; 56260f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey } 5638797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 564e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen /// getCommonSubClass - find the largest common subclass of A and B. Return 565e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen /// NULL if there is no common subclass. 566e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass * 567e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen getCommonSubClass(const TargetRegisterClass *A, 568e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass *B) const; 569e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen 570770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 5712cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner /// values. If a target supports multiple different pointer register classes, 5722cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner /// kind specifies which one is indicated. 573397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen virtual const TargetRegisterClass * 574397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const { 57550bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Target didn't implement getPointerRegClass!"); 576770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng } 5778797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 578ff110265753c19daf0468ee1facf357460497b7eEvan Cheng /// getCrossCopyRegClass - Returns a legal register class to copy a register 579b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// in the specified class to or from. If it is possible to copy the register 580b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// directly without using a cross register class copy, return the specified 581b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// RC. Returns NULL if it is not possible to copy between a two registers of 582b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// the specified class. 583ff110265753c19daf0468ee1facf357460497b7eEvan Cheng virtual const TargetRegisterClass * 584ff110265753c19daf0468ee1facf357460497b7eEvan Cheng getCrossCopyRegClass(const TargetRegisterClass *RC) const { 585b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng return RC; 586ff110265753c19daf0468ee1facf357460497b7eEvan Cheng } 587ff110265753c19daf0468ee1facf357460497b7eEvan Cheng 588c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// getLargestLegalSuperClass - Returns the largest super class of RC that is 589c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// legal to use in the current sub-target and has the same spill size. 590c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The returned register class can be used to create virtual registers which 591c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// means that all its registers can be copied and spilled. 592c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen virtual const TargetRegisterClass* 593c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 594c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The default implementation is very conservative and doesn't allow the 595c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// register allocator to inflate register classes. 596c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return RC; 597c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } 598c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen 599be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// getRegPressureLimit - Return the register pressure "high water mark" for 600be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// the specific register class. The scheduler is in high register pressure 601be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// mode (for the specific register class) if it goes over the limit. 602decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// 603decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Note: this is the old register pressure model that relies on a manually 604decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// specified representative register class per value type. 605be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 606be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich MachineFunction &MF) const { 607be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 0; 608be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 609be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 61083dbce2fc817fcb094a8958ca713fd3ba13758c5Andrew Trick /// Get the weight in units of pressure for this register class. 611ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick virtual const RegClassWeight &getRegClassWeight( 612ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick const TargetRegisterClass *RC) const = 0; 613decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 614eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick /// Get the weight in units of pressure for this register unit. 615eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0; 616eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick 617decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the number of dimensions of register pressure. 618decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual unsigned getNumRegPressureSets() const = 0; 619decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 620d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick /// Get the name of this register unit pressure set. 621d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick virtual const char *getRegPressureSetName(unsigned Idx) const = 0; 622d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick 623decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the register unit pressure limit for this dimension. 624decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// This limit must be adjusted dynamically for reserved registers. 625decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0; 626decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 627decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the dimensions of register pressure impacted by this register class. 628decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Returns a -1 terminated array of pressure set IDs. 629decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual const int *getRegClassPressureSets( 630decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick const TargetRegisterClass *RC) const = 0; 631decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 632eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick /// Get the dimensions of register pressure impacted by this register unit. 633eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick /// Returns a -1 terminated array of pressure set IDs. 634eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0; 635eca1fcf3d2d8246c45648fea59bd21a4091f9115Andrew Trick 6367eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// Get a list of 'hint' registers that the register allocator should try 6377eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// first when allocating a physical register for the virtual register 6387eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// VirtReg. These registers are effectively moved to the front of the 6397eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// allocation order. 6407eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// 6417eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// The Order argument is the allocation order for VirtReg's register class 6427eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// as returned from RegisterClassInfo::getOrder(). The hint registers must 6437eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// come from Order, and they must not be reserved. 6447eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// 6457eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// The default implementation of this function can resolve 6467eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// target-independent hints provided to MRI::setRegAllocationHint with 6477eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// HintType == 0. Targets that override this function should defer to the 6487eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// default implementation if they have no reason to change the allocation 6497eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen /// order for VirtReg. There may be target-independent hints. 6507eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen virtual void getRegAllocationHints(unsigned VirtReg, 6517eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen ArrayRef<MCPhysReg> Order, 6527eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen SmallVectorImpl<MCPhysReg> &Hints, 6537eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen const MachineFunction &MF, 6547eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen const VirtRegMap *VRM = 0) const; 6557eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen 656f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// avoidWriteAfterWrite - Return true if the register allocator should avoid 657f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// writing a register from RC in two consecutive instructions. 658f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// This can avoid pipeline stalls on certain architectures. 659f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// It does cause increased register pressure, though. 660f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 661f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return false; 662f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson } 663f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 664f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// UpdateRegAllocHint - A callback to allow target a chance to update 665f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// register allocation hints when a register is "changed" (e.g. coalesced) 666f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// to another register. e.g. On ARM, some virtual registers should target 667f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// register pairs, if one of pair is coalesced to another register, the 668f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// allocation hint of the other half of the pair should be changed to point 669f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// to the new register. 670f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 671f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng MachineFunction &MF) const { 672f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng // Do nothing. 673f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng } 674f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng 6751c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// requiresRegisterScavenging - returns true if the target requires (and can 6761c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// make use of) the register scavenger. 67736230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 67837f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng return false; 67937f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng } 68095923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 6810f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// useFPForScavengingIndex - returns true if the target wants to use 6820f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// frame pointer based accesses to spill to the scavenger emergency spill 6830f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// slot. 6840f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 6850f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach return true; 6860f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach } 6870f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach 68865c58daa8b8985d2116216043103009815a55e77Jim Grosbach /// requiresFrameIndexScavenging - returns true if the target requires post 68965c58daa8b8985d2116216043103009815a55e77Jim Grosbach /// PEI scavenging of registers for materializing frame index constants. 69065c58daa8b8985d2116216043103009815a55e77Jim Grosbach virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 69165c58daa8b8985d2116216043103009815a55e77Jim Grosbach return false; 69265c58daa8b8985d2116216043103009815a55e77Jim Grosbach } 69365c58daa8b8985d2116216043103009815a55e77Jim Grosbach 694a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// requiresVirtualBaseRegisters - Returns true if the target wants the 695a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// LocalStackAllocation pass to be run and virtual base registers 696a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// used for more efficient stack access. 697a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 698a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach return false; 699a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach } 700a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 701910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 702910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// the stack frame of the given function for the specified register. e.g. On 703910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// x86, if the frame register is required, the first fixed stack object is 704910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// reserved as its spill slot. This tells PEI not to create a new stack frame 705910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// object for the given register. It should be called only after 706910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// processFunctionBeforeCalleeSavedScan(). 70772852a8cfb605056d87b644d2e36b1346051413dEric Christopher virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 708910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng int &FrameIdx) const { 709910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng return false; 710910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng } 711910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng 7126a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd /// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked 7136a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd /// after register allocation. 7146a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 7156a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd return false; 7166a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd } 7176a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 718910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// needsStackRealignment - true if storage within the function requires the 719910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// stack pointer to be aligned more than the normal calling convention calls 720910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// for. 721b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen virtual bool needsStackRealignment(const MachineFunction &MF) const { 722b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen return false; 723b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen } 724b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen 725e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// getFrameIndexInstrOffset - Get the offset from the referenced frame 72663f8659d6936077c5e8e34eecb55ff1de0db5686Bob Wilson /// index in the instruction, if there is one. 7271ab3f16f06698596716593a30545799688acccd7Jim Grosbach virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 7281ab3f16f06698596716593a30545799688acccd7Jim Grosbach int Idx) const { 729e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return 0; 730e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 731e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 7328708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// needsFrameBaseReg - Returns true if the instruction's frame index 7338708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// reference would be better served by a base register other than FP 7348708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// or SP. Used by LocalStackFrameAllocation to determine which frame index 7358708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// references it should create new base registers for. 7363197380143cdc18837722129ac888528b9fbfc2bJim Grosbach virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 7378708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 7388708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 7398708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 740dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// materializeFrameBaseRegister - Insert defining instruction(s) for 741dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// BaseReg to be a pointer to FrameIdx before insertion point I. 742976ef86689ed065361a748f81c44ca3510af2202Bill Wendling virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 743e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned BaseReg, int FrameIdx, 744e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 74550bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("materializeFrameBaseRegister does not exist on this " 74650bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper "target"); 747dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 748dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 749dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// resolveFrameIndex - Resolve a frame index operand of an instruction 750dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// to reference the indicated base register plus offset instead. 751dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 752dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned BaseReg, int64_t Offset) const { 75350bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("resolveFrameIndex does not exist on this target"); 754dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 755dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 756e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// isFrameOffsetLegal - Determine whether a given offset immediate is 757e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// encodable to resolve a frame index. 758e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach virtual bool isFrameOffsetLegal(const MachineInstr *MI, 759e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 76050bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 76174d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach } 762dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 763f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 764d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// saveScavengerRegister - Spill the register so it can be used by the 765d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// register scavenger. Return true if the register was spilled, false 766d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// otherwise. If this function does not spill the register, the scavenger 767540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// will instead spill it to the emergency spill slot. 768540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// 769540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 770540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach MachineBasicBlock::iterator I, 771d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach MachineBasicBlock::iterator &UseMI, 772540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach const TargetRegisterClass *RC, 7731f8f4d2db734d9881467a5706acac73660842d43Evan Cheng unsigned Reg) const { 7741f8f4d2db734d9881467a5706acac73660842d43Evan Cheng return false; 7751f8f4d2db734d9881467a5706acac73660842d43Evan Cheng } 776540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach 777f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminateFrameIndex - This method must be overriden to eliminate abstract 778f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// frame indices from instructions which may use them. The instruction 779f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// referenced by the iterator contains an MO_FrameIndex operand which must be 780f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminated by this method. This method may modify or replace the 781c49a10aca1e31351c2e11b25ba636a23b93c46c8Dale Johannesen /// specified instruction, as long as it keeps the iterator pointing at the 782108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier /// finished product. SPAdj is the SP adjustment due to call frame setup 783108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier /// instruction. FIOperandNum is the FI operand number. 784fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 785108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int SPAdj, unsigned FIOperandNum, 786108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier RegScavenger *RS = NULL) const = 0; 787f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 788a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey //===--------------------------------------------------------------------===// 789a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// Debug information queries. 79095923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 791a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// getFrameRegister - This method should return the register used as a base 7924188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey /// for values allocated in the current stack frame. 793b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 79472bebb9205c1628601b052d25555aabe6e15e6f4Evan Cheng 7955cd2791513919ee7504c309151321e4e37a05a58Bill Wendling /// getCompactUnwindRegNum - This function maps the register to the number for 7965cd2791513919ee7504c309151321e4e37a05a58Bill Wendling /// compact unwind encoding. Return -1 if the register isn't valid. 797486dd90696545421c55346570b88fa03f6dd464fBill Wendling virtual int getCompactUnwindRegNum(unsigned, bool) const { 7985cd2791513919ee7504c309151321e4e37a05a58Bill Wendling return -1; 7995cd2791513919ee7504c309151321e4e37a05a58Bill Wendling } 8003d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner}; 8013d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 802c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng 80389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen//===----------------------------------------------------------------------===// 80489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// SuperRegClassIterator 80589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen//===----------------------------------------------------------------------===// 80689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 80789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// Iterate over the possible super-registers for a given register class. The 80889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// iterator will visit a list of pairs (Idx, Mask) corresponding to the 80989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// possible classes of super-registers. 81089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 81189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// Each bit mask will have at least one set bit, and each set bit in Mask 81289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// corresponds to a SuperRC such that: 81389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 81489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// For all Reg in SuperRC: Reg:Idx is in RC. 81589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 81689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// The iterator can include (O, RC->getSubClassMask()) as the first entry which 81789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// also satisfies the above requirement, assuming Reg:0 == Reg. 81889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 81989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesenclass SuperRegClassIterator { 82089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const unsigned RCMaskWords; 82189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen unsigned SubReg; 82289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const uint16_t *Idx; 82389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const uint32_t *Mask; 82489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 82589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesenpublic: 82689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Create a SuperRegClassIterator that visits all the super-register classes 82789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry. 82889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen SuperRegClassIterator(const TargetRegisterClass *RC, 82989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const TargetRegisterInfo *TRI, 83089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen bool IncludeSelf = false) 83189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen : RCMaskWords((TRI->getNumRegClasses() + 31) / 32), 83289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen SubReg(0), 83389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen Idx(RC->getSuperRegIndices()), 83489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen Mask(RC->getSubClassMask()) { 83589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen if (!IncludeSelf) 83689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen ++*this; 83789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen } 83889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 83989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Returns true if this iterator is still pointing at a valid entry. 84089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen bool isValid() const { return Idx; } 84189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 84289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Returns the current sub-register index. 84389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen unsigned getSubReg() const { return SubReg; } 84489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 84589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Returns the bit mask if register classes that getSubReg() projects into 84689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// RC. 84789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const uint32_t *getMask() const { return Mask; } 84889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 84989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Advance iterator to the next entry. 85089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen void operator++() { 85189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen assert(isValid() && "Cannot move iterator past end."); 85289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen Mask += RCMaskWords; 85389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen SubReg = *Idx++; 85489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen if (!SubReg) 85589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen Idx = 0; 85689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen } 85789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen}; 85889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 85994c002a190cd2e3a52b1510bc997e53d63af0b3bChris Lattner// This is useful when building IndexedMaps keyed on virtual registers 86059bf4fcc0680e75b408579064d1205a132361196Duncan Sandsstruct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 8614d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos unsigned operator()(unsigned Reg) const { 862c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen return TargetRegisterInfo::virtReg2Index(Reg); 8634d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos } 8644d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos}; 8654d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos 8664314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// PrintReg - Helper class for printing registers on a raw_ostream. 8674314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Prints virtual and physical registers with or without a TRI instance. 8684314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 8694314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// The format is: 87043a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %noreg - NoRegister 87143a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5 - a virtual register. 87243a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 87343a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %EAX - a physical register 87443a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %physreg17 - a physical register when no TRI instance given. 8754314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 8764314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 8774314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 8784314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenclass PrintReg { 8794314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen const TargetRegisterInfo *TRI; 8804314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen unsigned Reg; 8814314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen unsigned SubIdx; 8824314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenpublic: 883af87dae12cab8d2e5cab033a5ab60af98e1837feCraig Topper explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, 884af87dae12cab8d2e5cab033a5ab60af98e1837feCraig Topper unsigned subidx = 0) 8854314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen : TRI(tri), Reg(reg), SubIdx(subidx) {} 8864314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen void print(raw_ostream&) const; 8874314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen}; 8884314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen 8894314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenstatic inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 8904314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen PR.print(OS); 8914314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen return OS; 8924314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen} 8934314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen 8945ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// PrintRegUnit - Helper class for printing register units on a raw_ostream. 8955ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// 8965ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// Register units are named after their root registers: 8975ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// 8985ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// AL - Single root. 8995ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// FP0~ST7 - Dual roots. 9005ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// 9015ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n'; 9025ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// 9035ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesenclass PrintRegUnit { 9045ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen const TargetRegisterInfo *TRI; 9055ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen unsigned Unit; 9065ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesenpublic: 9075ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri) 9085ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen : TRI(tri), Unit(unit) {} 9095ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen void print(raw_ostream&) const; 9105ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen}; 9115ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen 9125ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesenstatic inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) { 9135ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen PR.print(OS); 9145ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen return OS; 9155ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen} 9165ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen 917d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 918d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 9193d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner#endif 920