TargetRegisterInfo.h revision 1e56a2a85fbafce5ceee72f72d41b84a71876844
16f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 93d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 103d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// This file describes an abstract interface used to get information about a 113d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// target machines register file. This information is used for a variety of 123d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// purposed, especially register allocation. 133d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 143d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner//===----------------------------------------------------------------------===// 153d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 166f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#define LLVM_TARGET_TARGETREGISTERINFO_H 183d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 19024126ee23e6e4430a77025b61d0e713180f03d3Alkis Evlogimenos#include "llvm/CodeGen/MachineBasicBlock.h" 20a385bf7b6dc9b71024aa4c7bb7026bab3c7ebe91Chris Lattner#include "llvm/CodeGen/ValueTypes.h" 21ddeed50d76e2ad52d3ccb3664d21dfe1463179c6Owen Anderson#include "llvm/ADT/DenseSet.h" 224d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <cassert> 234d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <functional> 243d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 25d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 26d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 27171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass BitVector; 28198ab640bbb0b8e1cdda518b7f8b348764e4402cChris Lattnerclass MachineFunction; 294188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskeyclass MachineMove; 30171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass RegScavenger; 31b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Chengtemplate<class T> class SmallVectorImpl; 32414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesenclass raw_ostream; 33282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 340f21fd5204a2627c613340269e2e39e2c8cca659Chris Lattner/// TargetRegisterDesc - This record contains all of the information known about 35b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen/// a particular register. The Overlaps field contains a pointer to a zero 36b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen/// terminated array of registers that this register aliases, starting with 37b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen/// itself. This is needed for architectures like X86 which have AL alias AX 38b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen/// alias EAX. The SubRegs field is a zero terminated array of registers that 39b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of 40b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen/// AX. The SuperRegs field is a zero terminated array of registers that are 412036835346ddf983d66b49505bd52db1d3f8b49dEvan Cheng/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 422036835346ddf983d66b49505bd52db1d3f8b49dEvan Cheng/// of AX. 433d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// 440f21fd5204a2627c613340269e2e39e2c8cca659Chris Lattnerstruct TargetRegisterDesc { 45e6d088acc90e422451e098555d383d4d65b6ce6bBill Wendling const char *Name; // Printable name for the reg (for debugging) 46b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen const unsigned *Overlaps; // Overlapping registers, described above 47a92d62c15fa2bf84453489716323b0159912c55dEvan Cheng const unsigned *SubRegs; // Sub-register set, described above 4850aadb96932a0f81ed69f73da6e7c8f8a453ee75Evan Cheng const unsigned *SuperRegs; // Super-register set, described above 496bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen unsigned CostPerUse; // Extra cost of instructions using register. 50f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen bool inAllocatableClass; // Register belongs to an allocatable regclass. 513d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner}; 523d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 53282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukmanclass TargetRegisterClass { 54282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukmanpublic: 550f24e33b73542bd7b280550aec6cff32d808e724Chris Lattner typedef const unsigned* iterator; 560f24e33b73542bd7b280550aec6cff32d808e724Chris Lattner typedef const unsigned* const_iterator; 57282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 58e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson typedef const EVT* vt_iterator; 593b0c0148ed9ec752b240dbea767ad4a9f0a682caEvan Cheng typedef const TargetRegisterClass* const * sc_iterator; 600f24e33b73542bd7b280550aec6cff32d808e724Chris Lattnerprivate: 6160f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey unsigned ID; 6241c90738e9e7e2111fbc31944b5ce2676830f267Chris Lattner const char *Name; 6316d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner const vt_iterator VTs; 64696736be8b80fe3946f73605b46359345afdf57aEvan Cheng const sc_iterator SubClasses; 65c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng const sc_iterator SuperClasses; 66f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const sc_iterator SubRegClasses; 67f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const sc_iterator SuperRegClasses; 68f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 69a3ca3149f2b59c512c50aab330b5a0d8efddeffaEvan Cheng const int CopyCost; 70f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen const bool Allocatable; 710f24e33b73542bd7b280550aec6cff32d808e724Chris Lattner const iterator RegsBegin, RegsEnd; 72ddeed50d76e2ad52d3ccb3664d21dfe1463179c6Owen Anderson DenseSet<unsigned> RegSet; 730f24e33b73542bd7b280550aec6cff32d808e724Chris Lattnerpublic: 7460f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey TargetRegisterClass(unsigned id, 7541c90738e9e7e2111fbc31944b5ce2676830f267Chris Lattner const char *name, 76e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson const EVT *vts, 773b0c0148ed9ec752b240dbea767ad4a9f0a682caEvan Cheng const TargetRegisterClass * const *subcs, 783b0c0148ed9ec752b240dbea767ad4a9f0a682caEvan Cheng const TargetRegisterClass * const *supcs, 79f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const TargetRegisterClass * const *subregcs, 80f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const TargetRegisterClass * const *superregcs, 81f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen unsigned RS, unsigned Al, int CC, bool Allocable, 82a3ca3149f2b59c512c50aab330b5a0d8efddeffaEvan Cheng iterator RB, iterator RE) 8341c90738e9e7e2111fbc31944b5ce2676830f267Chris Lattner : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 84f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman SubRegClasses(subregcs), SuperRegClasses(superregcs), 85f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen RegSize(RS), Alignment(Al), CopyCost(CC), Allocatable(Allocable), 86f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen RegsBegin(RB), RegsEnd(RE) { 87ddeed50d76e2ad52d3ccb3664d21dfe1463179c6Owen Anderson for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I) 88ddeed50d76e2ad52d3ccb3664d21dfe1463179c6Owen Anderson RegSet.insert(*I); 89ddeed50d76e2ad52d3ccb3664d21dfe1463179c6Owen Anderson } 900f24e33b73542bd7b280550aec6cff32d808e724Chris Lattner virtual ~TargetRegisterClass() {} // Allow subclasses 9195923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 926c8d90d65fa721d406c7a09a0045fa49254a9244Chris Lattner /// getID() - Return the register class ID number. 936c8d90d65fa721d406c7a09a0045fa49254a9244Chris Lattner /// 9460f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey unsigned getID() const { return ID; } 9541c90738e9e7e2111fbc31944b5ce2676830f267Chris Lattner 9641c90738e9e7e2111fbc31944b5ce2676830f267Chris Lattner /// getName() - Return the register class name for debugging. 9741c90738e9e7e2111fbc31944b5ce2676830f267Chris Lattner /// 9841c90738e9e7e2111fbc31944b5ce2676830f267Chris Lattner const char *getName() const { return Name; } 9941c90738e9e7e2111fbc31944b5ce2676830f267Chris Lattner 1006c8d90d65fa721d406c7a09a0045fa49254a9244Chris Lattner /// begin/end - Return all of the registers in this class. 1016c8d90d65fa721d406c7a09a0045fa49254a9244Chris Lattner /// 1020f24e33b73542bd7b280550aec6cff32d808e724Chris Lattner iterator begin() const { return RegsBegin; } 1030f24e33b73542bd7b280550aec6cff32d808e724Chris Lattner iterator end() const { return RegsEnd; } 104282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 1056c8d90d65fa721d406c7a09a0045fa49254a9244Chris Lattner /// getNumRegs - Return the number of registers in this class. 1066c8d90d65fa721d406c7a09a0045fa49254a9244Chris Lattner /// 10734cd4a484e532cc463fd5a4bf59b88d13c5467c1Evan Cheng unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } 108f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 1096c8d90d65fa721d406c7a09a0045fa49254a9244Chris Lattner /// getRegister - Return the specified register in the class. 1106c8d90d65fa721d406c7a09a0045fa49254a9244Chris Lattner /// 1110f24e33b73542bd7b280550aec6cff32d808e724Chris Lattner unsigned getRegister(unsigned i) const { 1120f24e33b73542bd7b280550aec6cff32d808e724Chris Lattner assert(i < getNumRegs() && "Register number out of range!"); 1130f24e33b73542bd7b280550aec6cff32d808e724Chris Lattner return RegsBegin[i]; 1140f24e33b73542bd7b280550aec6cff32d808e724Chris Lattner } 115282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 116f02b37da6f956dc9120a0da6ffa643b2753beb41Chris Lattner /// contains - Return true if the specified register is included in this 117e08b320f15b95eb3279fddba6ccb615eafbc4225Dan Gohman /// register class. This does not include virtual registers. 118f02b37da6f956dc9120a0da6ffa643b2753beb41Chris Lattner bool contains(unsigned Reg) const { 119ddeed50d76e2ad52d3ccb3664d21dfe1463179c6Owen Anderson return RegSet.count(Reg); 120f02b37da6f956dc9120a0da6ffa643b2753beb41Chris Lattner } 121f02b37da6f956dc9120a0da6ffa643b2753beb41Chris Lattner 122320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen /// contains - Return true if both registers are in this class. 123320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen bool contains(unsigned Reg1, unsigned Reg2) const { 124320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen return contains(Reg1) && contains(Reg2); 125320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen } 126320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen 1276510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman /// hasType - return true if this TargetRegisterClass has the ValueType vt. 1286510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman /// 129e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson bool hasType(EVT vt) const { 130cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands for(int i = 0; VTs[i] != MVT::Other; ++i) 1316510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman if (VTs[i] == vt) 1326510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return true; 1336510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return false; 1346510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman } 13595923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 136696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// vt_begin / vt_end - Loop over all of the value types that can be 137696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// represented by values in this register class. 13816d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_begin() const { 13916d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return VTs; 14016d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 14116d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner 14216d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_end() const { 14316d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator I = VTs; 144cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands while (*I != MVT::Other) ++I; 14516d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return I; 14616d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 147696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 148f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// subregclasses_begin / subregclasses_end - Loop over all of 149f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// the subreg register classes of this register class. 150f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator subregclasses_begin() const { 151f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return SubRegClasses; 152f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 153f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 154f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator subregclasses_end() const { 155f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator I = SubRegClasses; 156f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman while (*I != NULL) ++I; 157f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return I; 158f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 159f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 160fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen /// getSubRegisterRegClass - Return the register class of subregisters with 161fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen /// index SubIdx, or NULL if no such class exists. 162fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const { 163fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen assert(SubIdx>0 && "Invalid subregister index"); 164fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen return SubRegClasses[SubIdx-1]; 165fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen } 166fa4677b483b85217ac216f7e8d401c40cbe348aaJakob Stoklund Olesen 167f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// superregclasses_begin / superregclasses_end - Loop over all of 168f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// the superreg register classes of this register class. 169f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator superregclasses_begin() const { 170f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return SuperRegClasses; 171f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 172f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 173f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator superregclasses_end() const { 174f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator I = SuperRegClasses; 175f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman while (*I != NULL) ++I; 176f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return I; 177f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 178f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 179f451cb870efcf9e0302d25ed05f4cac6bb494e42Dan Gohman /// hasSubClass - return true if the specified TargetRegisterClass 180f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// is a proper subset of this TargetRegisterClass. 1811367fd09cb021bae61e7dd2ee208f76574c8e789Christopher Lamb bool hasSubClass(const TargetRegisterClass *cs) const { 18295923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach for (int i = 0; SubClasses[i] != NULL; ++i) 183696736be8b80fe3946f73605b46359345afdf57aEvan Cheng if (SubClasses[i] == cs) 184696736be8b80fe3946f73605b46359345afdf57aEvan Cheng return true; 185696736be8b80fe3946f73605b46359345afdf57aEvan Cheng return false; 186696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 187696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 1881f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// hasSubClassEq - Returns true if RC is a subclass of or equal to this 1891f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// class. 1901f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSubClassEq(const TargetRegisterClass *RC) const { 1911f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen return RC == this || hasSubClass(RC); 1921f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen } 1931f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen 194f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// subclasses_begin / subclasses_end - Loop over all of the classes 195f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// that are proper subsets of this register class. 196696736be8b80fe3946f73605b46359345afdf57aEvan Cheng sc_iterator subclasses_begin() const { 197696736be8b80fe3946f73605b46359345afdf57aEvan Cheng return SubClasses; 198696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 19995923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 200696736be8b80fe3946f73605b46359345afdf57aEvan Cheng sc_iterator subclasses_end() const { 201696736be8b80fe3946f73605b46359345afdf57aEvan Cheng sc_iterator I = SubClasses; 202696736be8b80fe3946f73605b46359345afdf57aEvan Cheng while (*I != NULL) ++I; 203696736be8b80fe3946f73605b46359345afdf57aEvan Cheng return I; 204696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 20595923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 2061367fd09cb021bae61e7dd2ee208f76574c8e789Christopher Lamb /// hasSuperClass - return true if the specified TargetRegisterClass is a 207f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// proper superset of this TargetRegisterClass. 2081367fd09cb021bae61e7dd2ee208f76574c8e789Christopher Lamb bool hasSuperClass(const TargetRegisterClass *cs) const { 20995923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach for (int i = 0; SuperClasses[i] != NULL; ++i) 210c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng if (SuperClasses[i] == cs) 211c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng return true; 212c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng return false; 213c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 214c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng 2151f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// hasSuperClassEq - Returns true if RC is a superclass of or equal to this 2161f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// class. 2171f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSuperClassEq(const TargetRegisterClass *RC) const { 2181f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen return RC == this || hasSuperClass(RC); 2191f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen } 2201f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen 221f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// superclasses_begin / superclasses_end - Loop over all of the classes 222f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// that are proper supersets of this register class. 223c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng sc_iterator superclasses_begin() const { 224c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng return SuperClasses; 225c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 22695923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 227c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng sc_iterator superclasses_end() const { 228c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng sc_iterator I = SuperClasses; 229c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng while (*I != NULL) ++I; 230c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng return I; 231c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 2328c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng 233f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// isASubClass - return true if this TargetRegisterClass is a subset 234f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// class of at least one other TargetRegisterClass. 2358c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng bool isASubClass() const { 2368c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng return SuperClasses[0] != 0; 2378c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng } 23895923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 239f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// allocation_order_begin/end - These methods define a range of registers 240f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// which specify the registers in this class that are valid to register 241f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// allocate, and the preferred order to allocate them in. For example, 242f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// callee saved registers should be at the end of the list, because it is 243f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// cheaper to allocate caller saved registers. 244f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// 245f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// These methods take a MachineFunction argument, which can be used to tune 246cc38399ea9aceb459a8d7e4bbc6deba9125ea869Jim Grosbach /// the allocatable registers based on the characteristics of the function, 247cc38399ea9aceb459a8d7e4bbc6deba9125ea869Jim Grosbach /// subtarget, or other criteria. 248cc38399ea9aceb459a8d7e4bbc6deba9125ea869Jim Grosbach /// 249cc38399ea9aceb459a8d7e4bbc6deba9125ea869Jim Grosbach /// Register allocators should account for the fact that an allocation 250cc38399ea9aceb459a8d7e4bbc6deba9125ea869Jim Grosbach /// order iterator may return a reserved register and always check 251cc38399ea9aceb459a8d7e4bbc6deba9125ea869Jim Grosbach /// if the register is allocatable (getAllocatableSet()) before using it. 252f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// 253f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// By default, these methods return all registers in the class. 254f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// 2555ea64fd9eb0027ad20a66ea29211eef79d8842a0Chris Lattner virtual iterator allocation_order_begin(const MachineFunction &MF) const { 256f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner return begin(); 257f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner } 2585ea64fd9eb0027ad20a66ea29211eef79d8842a0Chris Lattner virtual iterator allocation_order_end(const MachineFunction &MF) const { 259f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner return end(); 260f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner } 26134695381d626485a560594f162701088079589dfMisha Brukman 262f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// getSize - Return the size of the register in bytes, which is also the size 263f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// of a stack slot allocated to hold a spilled copy of this register. 264f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner unsigned getSize() const { return RegSize; } 265f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 266f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// getAlignment - Return the minimum required alignment for a register of 267f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// this class. 268f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner unsigned getAlignment() const { return Alignment; } 269a3ca3149f2b59c512c50aab330b5a0d8efddeffaEvan Cheng 270a3ca3149f2b59c512c50aab330b5a0d8efddeffaEvan Cheng /// getCopyCost - Return the cost of copying a value between two registers in 271b3a021cdb3d26ddb2985e326ba0cb96761b86f69Evan Cheng /// this class. A negative number means the register class is very expensive 272b3a021cdb3d26ddb2985e326ba0cb96761b86f69Evan Cheng /// to copy e.g. status flag register classes. 273a3ca3149f2b59c512c50aab330b5a0d8efddeffaEvan Cheng int getCopyCost() const { return CopyCost; } 274f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen 275f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen /// isAllocatable - Return true if this register class may be used to create 276f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen /// virtual registers. 277f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen bool isAllocatable() const { return Allocatable; } 278282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman}; 279282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 280282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 2816f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// TargetRegisterInfo base class - We assume that the target defines a static 2826f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// array of TargetRegisterDesc objects that represent all of the machine 2836f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// registers that the target has. As such, we simply have to track a pointer 2846f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// to this array so that we can turn register number into a register 2856f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// descriptor. 2863d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// 2876f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohmanclass TargetRegisterInfo { 2888797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerpublic: 2898797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner typedef const TargetRegisterClass * const * regclass_iterator; 2908797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerprivate: 2910f21fd5204a2627c613340269e2e39e2c8cca659Chris Lattner const TargetRegisterDesc *Desc; // Pointer to the descriptor array 2921fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *const *SubRegIndexNames; // Names of subreg indexes. 2938797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner unsigned NumRegs; // Number of entries in the array 2948797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 2958797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 2968797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 297f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner int CallFrameSetupOpcode, CallFrameDestroyOpcode; 298b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene 2993d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerprotected: 3006f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 3016f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassBegin, 3026f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassEnd, 3031fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *const *subregindexnames, 3046f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman int CallFrameSetupOpcode = -1, 3051e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson int CallFrameDestroyOpcode = -1); 3066f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman virtual ~TargetRegisterInfo(); 3073d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerpublic: 3083d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 309b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Register numbers can represent physical registers, virtual registers, and 310b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // sometimes stack slots. The unsigned values are divided into these ranges: 311b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 312b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 0 Not a register, can be used as a sentinel. 313b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [1;2^30) Physical registers assigned by TableGen. 314b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^30;2^31) Stack slots. (Rarely used.) 315b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 316b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 317b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Further sentinels can be allocated from the small negative integers. 318b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // DenseMapInfo<unsigned> uses -1u and -2u. 3193d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 320be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// isStackSlot - Sometimes it is useful the be able to store a non-negative 321be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// frame index in a variable that normally holds a register. isStackSlot() 322be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// returns true if Reg is in the range used for stack slots. 323be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 324da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 325da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// slots, so if a variable may contains a stack slot, always check 326da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// isStackSlot() first. 327be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 328be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static bool isStackSlot(unsigned Reg) { 329da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) >= (1 << 30); 330be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 331be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 332be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// stackSlot2Index - Compute the frame index from a register value 333be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// representing a stack slot. 334be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static int stackSlot2Index(unsigned Reg) { 335be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(isStackSlot(Reg) && "Not a stack slot"); 336da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg - (1u << 30)); 337be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 338be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 339be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// index2StackSlot - Convert a non-negative frame index to a stack slot 340be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// register value. 341be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static unsigned index2StackSlot(int FI) { 342be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(FI >= 0 && "Cannot hold a negative frame index."); 343da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return FI + (1u << 30); 344be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 345be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 346bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// isPhysicalRegister - Return true if the specified register number is in 347bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the physical register namespace. 348bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isPhysicalRegister(unsigned Reg) { 349da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 350da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) > 0; 351bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 352bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 353bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// isVirtualRegister - Return true if the specified register number is in 354bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the virtual register namespace. 355bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isVirtualRegister(unsigned Reg) { 356da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 357da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) < 0; 358bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 359bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 360c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen /// virtReg2Index - Convert a virtual register number to a 0-based index. 361c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen /// The first virtual register in a function will get the index 0. 362c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen static unsigned virtReg2Index(unsigned Reg) { 363da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(isVirtualRegister(Reg) && "Not a virtual register"); 364dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Reg & ~(1u << 31); 365c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen } 366c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen 367b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// index2VirtReg - Convert a 0-based index to a virtual register number. 368b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// This is the inverse operation of VirtReg2IndexFunctor below. 369b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen static unsigned index2VirtReg(unsigned Index) { 370dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Index | (1u << 31); 371b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen } 372b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 373ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola /// getMinimalPhysRegClass - Returns the Register Class of a physical 374c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman /// register of the given type, picking the most sub register class of 375c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman /// the right type that contains this physreg. 376d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola const TargetRegisterClass * 377d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 378ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 379bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos /// getAllocatableSet - Returns a bitset indexed by register number 380eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng /// indicating if a register is allocatable or not. If a register class is 381eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng /// specified, returns the subset for the class. 382769b7f89534caed11d7595b5c84aa47d3de30ad9Dan Gohman BitVector getAllocatableSet(const MachineFunction &MF, 383eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng const TargetRegisterClass *RC = NULL) const; 384bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos 3850f21fd5204a2627c613340269e2e39e2c8cca659Chris Lattner const TargetRegisterDesc &operator[](unsigned RegNo) const { 3863d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner assert(RegNo < NumRegs && 3873d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner "Attempting to access record for invalid register number!"); 3883d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner return Desc[RegNo]; 3893d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner } 3903d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 3913d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// Provide a get method, equivalent to [], but more useful if we have a 3923d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// pointer to this object. 3933d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// 3940f21fd5204a2627c613340269e2e39e2c8cca659Chris Lattner const TargetRegisterDesc &get(unsigned RegNo) const { 3950f21fd5204a2627c613340269e2e39e2c8cca659Chris Lattner return operator[](RegNo); 3960f21fd5204a2627c613340269e2e39e2c8cca659Chris Lattner } 3973d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 39800032bf6cc236b1fb534f74b1ac288f611a86804Chris Lattner /// getAliasSet - Return the set of registers aliased by the specified 39900032bf6cc236b1fb534f74b1ac288f611a86804Chris Lattner /// register, or a null list of there are none. The list returned is zero 40000032bf6cc236b1fb534f74b1ac288f611a86804Chris Lattner /// terminated. 40100032bf6cc236b1fb534f74b1ac288f611a86804Chris Lattner /// 40200032bf6cc236b1fb534f74b1ac288f611a86804Chris Lattner const unsigned *getAliasSet(unsigned RegNo) const { 403b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen // The Overlaps set always begins with Reg itself. 404b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen return get(RegNo).Overlaps + 1; 405b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen } 406b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen 407b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen /// getOverlaps - Return a list of registers that overlap Reg, including 408b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen /// itself. This is the same as the alias set except Reg is included in the 409b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen /// list. 410b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen /// These are exactly the registers in { x | regsOverlap(x, Reg) }. 411b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen /// 412b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen const unsigned *getOverlaps(unsigned RegNo) const { 413b83ff84193d44bb9aa75e1264ffaff55f468a303Jakob Stoklund Olesen return get(RegNo).Overlaps; 41400032bf6cc236b1fb534f74b1ac288f611a86804Chris Lattner } 415282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 4168102703d708e5d399926c6ba71ffa49bbd31fc8aEvan Cheng /// getSubRegisters - Return the list of registers that are sub-registers of 41750aadb96932a0f81ed69f73da6e7c8f8a453ee75Evan Cheng /// the specified register, or a null list of there are none. The list 4188102703d708e5d399926c6ba71ffa49bbd31fc8aEvan Cheng /// returned is zero terminated and sorted according to super-sub register 4198102703d708e5d399926c6ba71ffa49bbd31fc8aEvan Cheng /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 420e3e31c22bf7ebed9e8e00ede4f4aa87ce2225528Evan Cheng /// 421e3e31c22bf7ebed9e8e00ede4f4aa87ce2225528Evan Cheng const unsigned *getSubRegisters(unsigned RegNo) const { 422e3e31c22bf7ebed9e8e00ede4f4aa87ce2225528Evan Cheng return get(RegNo).SubRegs; 423e3e31c22bf7ebed9e8e00ede4f4aa87ce2225528Evan Cheng } 424e3e31c22bf7ebed9e8e00ede4f4aa87ce2225528Evan Cheng 4258102703d708e5d399926c6ba71ffa49bbd31fc8aEvan Cheng /// getSuperRegisters - Return the list of registers that are super-registers 42650aadb96932a0f81ed69f73da6e7c8f8a453ee75Evan Cheng /// of the specified register, or a null list of there are none. The list 4278102703d708e5d399926c6ba71ffa49bbd31fc8aEvan Cheng /// returned is zero terminated and sorted according to super-sub register 428026dc223aeef2579d63f395007491e37d6cde3a0Jakob Stoklund Olesen /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX. 42950aadb96932a0f81ed69f73da6e7c8f8a453ee75Evan Cheng /// 43050aadb96932a0f81ed69f73da6e7c8f8a453ee75Evan Cheng const unsigned *getSuperRegisters(unsigned RegNo) const { 43150aadb96932a0f81ed69f73da6e7c8f8a453ee75Evan Cheng return get(RegNo).SuperRegs; 43250aadb96932a0f81ed69f73da6e7c8f8a453ee75Evan Cheng } 43350aadb96932a0f81ed69f73da6e7c8f8a453ee75Evan Cheng 434e6d088acc90e422451e098555d383d4d65b6ce6bBill Wendling /// getName - Return the human-readable symbolic target-specific name for the 435e6d088acc90e422451e098555d383d4d65b6ce6bBill Wendling /// specified physical register. 436e6d088acc90e422451e098555d383d4d65b6ce6bBill Wendling const char *getName(unsigned RegNo) const { 437e6d088acc90e422451e098555d383d4d65b6ce6bBill Wendling return get(RegNo).Name; 438181eb737b28628adc4376b973610a02039385026Bill Wendling } 439181eb737b28628adc4376b973610a02039385026Bill Wendling 4406bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen /// getCostPerUse - Return the additional cost of using this register instead 4416bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen /// of other registers in its class. 4426bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen unsigned getCostPerUse(unsigned RegNo) const { 4436bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen return get(RegNo).CostPerUse; 4446bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen } 4456bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen 4461c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// getNumRegs - Return the number of registers this target has (useful for 4471c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// sizing arrays holding per register information) 44893aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos unsigned getNumRegs() const { 44993aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos return NumRegs; 45093aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos } 45193aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos 4521fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen /// getSubRegIndexName - Return the human-readable symbolic target-specific 4531fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen /// name for the specified SubRegIndex. 4541fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *getSubRegIndexName(unsigned SubIdx) const { 4551fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen assert(SubIdx && "This is not a subregister index"); 4561fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen return SubRegIndexNames[SubIdx-1]; 4571fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen } 4581fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen 4593f2f3f5341374c85955cfaffa71886724999762dLang Hames /// regsOverlap - Returns true if the two registers are equal or alias each 4603f2f3f5341374c85955cfaffa71886724999762dLang Hames /// other. The registers may be virtual register. 4613f2f3f5341374c85955cfaffa71886724999762dLang Hames bool regsOverlap(unsigned regA, unsigned regB) const { 4621e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (regA == regB) return true; 4633f2f3f5341374c85955cfaffa71886724999762dLang Hames if (isVirtualRegister(regA) || isVirtualRegister(regB)) 4643f2f3f5341374c85955cfaffa71886724999762dLang Hames return false; 4651e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) { 4661e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (*regList == regB) return true; 4673ca15c989ca0e09085648771db368d8c94ee1f19Owen Anderson } 46804319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos return false; 46904319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos } 47004319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos 471b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// isSubRegister - Returns true if regB is a sub-register of regA. 472b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// 473b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng bool isSubRegister(unsigned regA, unsigned regB) const { 4741e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson return isSuperRegister(regB, regA); 475b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng } 476b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng 477b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// isSuperRegister - Returns true if regB is a super-register of regA. 478b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// 479b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng bool isSuperRegister(unsigned regA, unsigned regB) const { 4801e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){ 4811e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (*regList == regB) return true; 4821e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson } 4831e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson return false; 484b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng } 485b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng 4860098b3e2b69e527ddcf2ebad7a3081898fa3b4f0Evan Cheng /// getCalleeSavedRegs - Return a null-terminated list of all of the 4870098b3e2b69e527ddcf2ebad7a3081898fa3b4f0Evan Cheng /// callee saved registers on this target. The register should be in the 48802569d7355b03155b32c1c0d0e46f6aa957f4802Evan Cheng /// order of desired callee-save stack frame offset. The first register is 48902569d7355b03155b32c1c0d0e46f6aa957f4802Evan Cheng /// closed to the incoming stack pointer if stack grows down, and vice versa. 4902365f51ed03afe6993bae962fdc2e5a956a64cd5Anton Korobeynikov virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 4912365f51ed03afe6993bae962fdc2e5a956a64cd5Anton Korobeynikov const = 0; 4928797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 4938797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 494b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng /// getReservedRegs - Returns a bitset indexed by physical register number 4951c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// indicating if a register is a special register that has particular uses 4961c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// and should be considered unavailable at all times, e.g. SP, RA. This is 4971c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// used by register scavenger to determine what registers are free. 498b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 499b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 5007bf1c272ab27297a7bbab329de3f17ddb26e02a3Nate Begeman /// getSubReg - Returns the physical register number of sub-register "Index" 501dd595c5998214c6ee07ed46f5db551b2abbfbbb3Evan Cheng /// for physical register RegNo. Return zero if the sub-register does not 502dd595c5998214c6ee07ed46f5db551b2abbfbbb3Evan Cheng /// exist. 5037bf1c272ab27297a7bbab329de3f17ddb26e02a3Nate Begeman virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 5047bf1c272ab27297a7bbab329de3f17ddb26e02a3Nate Begeman 505fae3e923452b85e72b2c03dd6eacc063f59d81b1Evan Cheng /// getSubRegIndex - For a given register pair, return the sub-register index 506754f680c1fcde09a3d36bb8562e1433fdb87018eBob Wilson /// if the second register is a sub-register of the first. Return zero 507fae3e923452b85e72b2c03dd6eacc063f59d81b1Evan Cheng /// otherwise. 508fae3e923452b85e72b2c03dd6eacc063f59d81b1Evan Cheng virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; 509fae3e923452b85e72b2c03dd6eacc063f59d81b1Evan Cheng 5108a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng /// getMatchingSuperReg - Return a super-register of the specified register 5118a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng /// Reg so its sub-register of index SubIdx is Reg. 51295923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 5138a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng const TargetRegisterClass *RC) const { 5148a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 5158a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 5168a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng return SR; 5178a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng return 0; 5188a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng } 5198a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng 52091a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// canCombineSubRegIndices - Given a register class and a list of 52191a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// subregister indices, return true if it's possible to combine the 52291a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// subregister indices into one that corresponds to a larger 52391a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// subregister. Return the new subregister index by reference. Note the 52491a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// new index may be zero if the given subregisters can be combined to 52591a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// form the whole register. 52691a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 52791a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson SmallVectorImpl<unsigned> &SubIndices, 52891a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson unsigned &NewSubIdx) const { 529b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return 0; 530b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 531b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 5325248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// getMatchingSuperRegClass - Return a subclass of the specified register 5335248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// class A so that each register in it has a sub-register of the 5345248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// specified sub-register index which is in the specified register class B. 5355248468473f0488a652b545ad95f7abda302b7b5Evan Cheng virtual const TargetRegisterClass * 5365248468473f0488a652b545ad95f7abda302b7b5Evan Cheng getMatchingSuperRegClass(const TargetRegisterClass *A, 5375248468473f0488a652b545ad95f7abda302b7b5Evan Cheng const TargetRegisterClass *B, unsigned Idx) const { 5385248468473f0488a652b545ad95f7abda302b7b5Evan Cheng return 0; 5395248468473f0488a652b545ad95f7abda302b7b5Evan Cheng } 5405248468473f0488a652b545ad95f7abda302b7b5Evan Cheng 5412da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// composeSubRegIndices - Return the subregister index you get from composing 5422da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// two subregister indices. 5432da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 5442da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 5452da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// returns c. Note that composeSubRegIndices does not tell you about illegal 5462da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// compositions. If R does not have a subreg a, or R:a does not have a subreg 5472da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// b, composeSubRegIndices doesn't tell you. 5482da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 5492da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 5502da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// ssub_0:S0 - ssub_3:S3 subregs. 5512da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 5522da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 5532da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 5542da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen // This default implementation is correct for most targets. 5552da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen return b; 5562da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen } 5572da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen 5588797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner //===--------------------------------------------------------------------===// 5598797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // Register Class Information 5608797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // 5618797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 5628797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner /// Register class iterators 56392988ecdb6ca641ba39d1d1f8cbc57a89b63bbadChris Lattner /// 5648797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_begin() const { return RegClassBegin; } 5658797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_end() const { return RegClassEnd; } 5668797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 5678797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner unsigned getNumRegClasses() const { 56834cd4a484e532cc463fd5a4bf59b88d13c5467c1Evan Cheng return (unsigned)(regclass_end()-regclass_begin()); 5698797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner } 57095923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 57160f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// getRegClass - Returns the register class associated with the enumeration 57260f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// value. See class TargetOperandInfo. 57360f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey const TargetRegisterClass *getRegClass(unsigned i) const { 574a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman assert(i < getNumRegClasses() && "Register Class ID out of range"); 575a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman return RegClassBegin[i]; 57660f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey } 5778797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 578770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 5792cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner /// values. If a target supports multiple different pointer register classes, 5802cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner /// kind specifies which one is indicated. 5812cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 582770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng assert(0 && "Target didn't implement getPointerRegClass!"); 583770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng return 0; // Must return a value in order to compile with VS 2005 584770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng } 5858797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 586ff110265753c19daf0468ee1facf357460497b7eEvan Cheng /// getCrossCopyRegClass - Returns a legal register class to copy a register 587b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// in the specified class to or from. If it is possible to copy the register 588b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// directly without using a cross register class copy, return the specified 589b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// RC. Returns NULL if it is not possible to copy between a two registers of 590b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// the specified class. 591ff110265753c19daf0468ee1facf357460497b7eEvan Cheng virtual const TargetRegisterClass * 592ff110265753c19daf0468ee1facf357460497b7eEvan Cheng getCrossCopyRegClass(const TargetRegisterClass *RC) const { 593b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng return RC; 594ff110265753c19daf0468ee1facf357460497b7eEvan Cheng } 595ff110265753c19daf0468ee1facf357460497b7eEvan Cheng 596c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// getLargestLegalSuperClass - Returns the largest super class of RC that is 597c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// legal to use in the current sub-target and has the same spill size. 598c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The returned register class can be used to create virtual registers which 599c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// means that all its registers can be copied and spilled. 600c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen virtual const TargetRegisterClass* 601c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 602c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The default implementation is very conservative and doesn't allow the 603c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// register allocator to inflate register classes. 604c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return RC; 605c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } 606c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen 607be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// getRegPressureLimit - Return the register pressure "high water mark" for 608be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// the specific register class. The scheduler is in high register pressure 609be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// mode (for the specific register class) if it goes over the limit. 610be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 611be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich MachineFunction &MF) const { 612be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 0; 613be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 614be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 615358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// getAllocationOrder - Returns the register allocation order for a specified 616358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// register class in the form of a pair of TargetRegisterClass iterators. 617358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 618358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng getAllocationOrder(const TargetRegisterClass *RC, 619f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng unsigned HintType, unsigned HintReg, 620358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng const MachineFunction &MF) const { 621358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng return std::make_pair(RC->allocation_order_begin(MF), 622358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng RC->allocation_order_end(MF)); 623358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng } 624358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng 625358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// ResolveRegAllocHint - Resolves the specified register allocation hint 626358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// to a physical register. Returns the physical register if it is successful. 627f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 628f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng const MachineFunction &MF) const { 629358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng if (Type == 0 && Reg && isPhysicalRegister(Reg)) 630358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng return Reg; 631358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng return 0; 632358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng } 633358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng 634f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// avoidWriteAfterWrite - Return true if the register allocator should avoid 635f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// writing a register from RC in two consecutive instructions. 636f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// This can avoid pipeline stalls on certain architectures. 637f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// It does cause increased register pressure, though. 638f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 639f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return false; 640f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson } 641f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 642f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// UpdateRegAllocHint - A callback to allow target a chance to update 643f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// register allocation hints when a register is "changed" (e.g. coalesced) 644f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// to another register. e.g. On ARM, some virtual registers should target 645f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// register pairs, if one of pair is coalesced to another register, the 646f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// allocation hint of the other half of the pair should be changed to point 647f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// to the new register. 648f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 649f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng MachineFunction &MF) const { 650f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng // Do nothing. 651f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng } 652f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng 6531c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// requiresRegisterScavenging - returns true if the target requires (and can 6541c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// make use of) the register scavenger. 65536230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 65637f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng return false; 65737f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng } 65895923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 6590f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// useFPForScavengingIndex - returns true if the target wants to use 6600f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// frame pointer based accesses to spill to the scavenger emergency spill 6610f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// slot. 6620f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 6630f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach return true; 6640f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach } 6650f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach 66665c58daa8b8985d2116216043103009815a55e77Jim Grosbach /// requiresFrameIndexScavenging - returns true if the target requires post 66765c58daa8b8985d2116216043103009815a55e77Jim Grosbach /// PEI scavenging of registers for materializing frame index constants. 66865c58daa8b8985d2116216043103009815a55e77Jim Grosbach virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 66965c58daa8b8985d2116216043103009815a55e77Jim Grosbach return false; 67065c58daa8b8985d2116216043103009815a55e77Jim Grosbach } 67165c58daa8b8985d2116216043103009815a55e77Jim Grosbach 672a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// requiresVirtualBaseRegisters - Returns true if the target wants the 673a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// LocalStackAllocation pass to be run and virtual base registers 674a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// used for more efficient stack access. 675a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 676a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach return false; 677a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach } 678a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 679910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 680910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// the stack frame of the given function for the specified register. e.g. On 681910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// x86, if the frame register is required, the first fixed stack object is 682910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// reserved as its spill slot. This tells PEI not to create a new stack frame 683910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// object for the given register. It should be called only after 684910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// processFunctionBeforeCalleeSavedScan(). 68572852a8cfb605056d87b644d2e36b1346051413dEric Christopher virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 686910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng int &FrameIdx) const { 687910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng return false; 688910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng } 689910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng 690910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// needsStackRealignment - true if storage within the function requires the 691910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// stack pointer to be aligned more than the normal calling convention calls 692910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// for. 693b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen virtual bool needsStackRealignment(const MachineFunction &MF) const { 694b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen return false; 695b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen } 696b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen 697e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// getFrameIndexInstrOffset - Get the offset from the referenced frame 69863f8659d6936077c5e8e34eecb55ff1de0db5686Bob Wilson /// index in the instruction, if there is one. 6991ab3f16f06698596716593a30545799688acccd7Jim Grosbach virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 7001ab3f16f06698596716593a30545799688acccd7Jim Grosbach int Idx) const { 701e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return 0; 702e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 703e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 7048708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// needsFrameBaseReg - Returns true if the instruction's frame index 7058708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// reference would be better served by a base register other than FP 7068708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// or SP. Used by LocalStackFrameAllocation to determine which frame index 7078708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// references it should create new base registers for. 7083197380143cdc18837722129ac888528b9fbfc2bJim Grosbach virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 7098708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 7108708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 7118708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 712dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// materializeFrameBaseRegister - Insert defining instruction(s) for 713dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// BaseReg to be a pointer to FrameIdx before insertion point I. 714976ef86689ed065361a748f81c44ca3510af2202Bill Wendling virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 715e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned BaseReg, int FrameIdx, 716e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 717dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(0 && "materializeFrameBaseRegister does not exist on this target"); 718dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 719dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 720dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// resolveFrameIndex - Resolve a frame index operand of an instruction 721dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// to reference the indicated base register plus offset instead. 722dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 723dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned BaseReg, int64_t Offset) const { 724dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(0 && "resolveFrameIndex does not exist on this target"); 725dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 726dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 727e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// isFrameOffsetLegal - Determine whether a given offset immediate is 728e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// encodable to resolve a frame index. 729e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach virtual bool isFrameOffsetLegal(const MachineInstr *MI, 730e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 731e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach assert(0 && "isFrameOffsetLegal does not exist on this target"); 73274d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach return false; // Must return a value in order to compile with VS 2005 73374d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach } 734dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 735f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 736f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// frame setup/destroy instructions if they exist (-1 otherwise). Some 737f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// targets use pseudo instructions in order to abstract away the difference 738f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// between operating with a frame pointer and operating without, through the 739f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// use of these two instructions. 740f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// 741f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 742f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 743f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 744f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 745f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// code insertion to eliminate call frame setup and destroy pseudo 746f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// instructions (but only if the Target is using them). It is responsible 747f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// for eliminating these instructions, replacing them with concrete 748f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// instructions. This method need only be implemented if using call frame 7498a1478b6d7aeaed8363316d2e0b90d9f53525c29Chris Lattner /// setup/destroy pseudo instructions. 750f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// 75134695381d626485a560594f162701088079589dfMisha Brukman virtual void 7528604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner eliminateCallFramePseudoInstr(MachineFunction &MF, 7538604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner MachineBasicBlock &MBB, 7548604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner MachineBasicBlock::iterator MI) const { 755f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 75600876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman "eliminateCallFramePseudoInstr must be implemented if using" 75700876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman " call frame setup/destroy pseudo instructions!"); 758f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 759f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner } 760f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 761f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 762d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// saveScavengerRegister - Spill the register so it can be used by the 763d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// register scavenger. Return true if the register was spilled, false 764d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// otherwise. If this function does not spill the register, the scavenger 765540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// will instead spill it to the emergency spill slot. 766540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// 767540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 768540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach MachineBasicBlock::iterator I, 769d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach MachineBasicBlock::iterator &UseMI, 770540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach const TargetRegisterClass *RC, 7711f8f4d2db734d9881467a5706acac73660842d43Evan Cheng unsigned Reg) const { 7721f8f4d2db734d9881467a5706acac73660842d43Evan Cheng return false; 7731f8f4d2db734d9881467a5706acac73660842d43Evan Cheng } 774540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach 775f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminateFrameIndex - This method must be overriden to eliminate abstract 776f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// frame indices from instructions which may use them. The instruction 777f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// referenced by the iterator contains an MO_FrameIndex operand which must be 778f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminated by this method. This method may modify or replace the 779c49a10aca1e31351c2e11b25ba636a23b93c46c8Dale Johannesen /// specified instruction, as long as it keeps the iterator pointing at the 78018b111bffe643b5ad52ae10a1d5728b0c1ac92f0Evan Cheng /// finished product. SPAdj is the SP adjustment due to call frame setup 7811ad70c09c890c3abcc147503f2e23082f683790cMatthijs Kooijman /// instruction. 782fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 783fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach int SPAdj, RegScavenger *RS=NULL) const = 0; 784f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 785a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey //===--------------------------------------------------------------------===// 786a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// Debug information queries. 78795923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 7884188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey /// getDwarfRegNum - Map a target register to an equivalent dwarf register 789b97aec663b1591e71c9ddee6dbb327d1b827eda5Dale Johannesen /// number. Returns -1 if there is no equivalent value. The second 790b97aec663b1591e71c9ddee6dbb327d1b827eda5Dale Johannesen /// parameter allows targets to use different numberings for EH info and 7912bbeccdee1937f6cef9f8762595246f447162a4fMatthijs Kooijman /// debugging info. 792b97aec663b1591e71c9ddee6dbb327d1b827eda5Dale Johannesen virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 793a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey 7946e032942cf58d1c41f88609a1cec74eb74940ecdRafael Espindola virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0; 7956e032942cf58d1c41f88609a1cec74eb74940ecdRafael Espindola 796a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// getFrameRegister - This method should return the register used as a base 7974188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey /// for values allocated in the current stack frame. 798b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 79972bebb9205c1628601b052d25555aabe6e15e6f4Evan Cheng 8004188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey /// getRARegister - This method should return the register where the return 8014188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey /// address can be found. 8024188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey virtual unsigned getRARegister() const = 0; 8036b918b84661687f7b5fc92dabd6d58e258bf39f2Charles Davis 8046b918b84661687f7b5fc92dabd6d58e258bf39f2Charles Davis /// getSEHRegNum - Map a target register to an equivalent SEH register 8056b918b84661687f7b5fc92dabd6d58e258bf39f2Charles Davis /// number. Returns -1 if there is no equivalent value. 8066b918b84661687f7b5fc92dabd6d58e258bf39f2Charles Davis virtual int getSEHRegNum(unsigned i) const { 8076b918b84661687f7b5fc92dabd6d58e258bf39f2Charles Davis return i; 8086b918b84661687f7b5fc92dabd6d58e258bf39f2Charles Davis } 8093d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner}; 8103d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 811c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng 81294c002a190cd2e3a52b1510bc997e53d63af0b3bChris Lattner// This is useful when building IndexedMaps keyed on virtual registers 81359bf4fcc0680e75b408579064d1205a132361196Duncan Sandsstruct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 8144d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos unsigned operator()(unsigned Reg) const { 815c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen return TargetRegisterInfo::virtReg2Index(Reg); 8164d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos } 8174d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos}; 8184d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos 819c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng/// getCommonSubClass - find the largest common subclass of A and B. Return NULL 820c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng/// if there is no common subclass. 821c781a243a3d17e7e763515794168d8fa6043f565Evan Chengconst TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A, 822c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng const TargetRegisterClass *B); 823c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng 8244314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// PrintReg - Helper class for printing registers on a raw_ostream. 8254314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Prints virtual and physical registers with or without a TRI instance. 8264314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 8274314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// The format is: 82843a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %noreg - NoRegister 82943a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5 - a virtual register. 83043a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 83143a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %EAX - a physical register 83243a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %physreg17 - a physical register when no TRI instance given. 8334314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 8344314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 8354314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 8364314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenclass PrintReg { 8374314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen const TargetRegisterInfo *TRI; 8384314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen unsigned Reg; 8394314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen unsigned SubIdx; 8404314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenpublic: 8414314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 8424314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen : TRI(tri), Reg(reg), SubIdx(subidx) {} 8434314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen void print(raw_ostream&) const; 8444314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen}; 8454314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen 8464314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenstatic inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 8474314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen PR.print(OS); 8484314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen return OS; 8494314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen} 8504314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen 851d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 852d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 8533d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner#endif 854