TargetRegisterInfo.h revision 255f89faee13dc491cb64fbeae3c763e7e2ea4e6
16f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 93d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 103d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// This file describes an abstract interface used to get information about a 113d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// target machines register file. This information is used for a variety of 123d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// purposed, especially register allocation. 133d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 143d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner//===----------------------------------------------------------------------===// 153d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 166f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#define LLVM_TARGET_TARGETREGISTERINFO_H 183d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 1979c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen#include "llvm/ADT/ArrayRef.h" 20bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen#include "llvm/CallingConv.h" 21255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/CodeGen/MachineBasicBlock.h" 22255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/CodeGen/ValueTypes.h" 23255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/MC/MCRegisterInfo.h" 244d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <cassert> 254d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <functional> 263d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 27d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 28d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 29171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass BitVector; 30198ab640bbb0b8e1cdda518b7f8b348764e4402cChris Lattnerclass MachineFunction; 31171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass RegScavenger; 32b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Chengtemplate<class T> class SmallVectorImpl; 33414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesenclass raw_ostream; 34282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 35f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramerclass TargetRegisterClass { 36282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukmanpublic: 37e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen typedef const MCPhysReg* iterator; 38e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen typedef const MCPhysReg* const_iterator; 392c6ae095b8a944c8355377498b9ad11bb94af2d5Benjamin Kramer typedef const MVT::SimpleValueType* vt_iterator; 403b0c0148ed9ec752b240dbea767ad4a9f0a682caEvan Cheng typedef const TargetRegisterClass* const * sc_iterator; 41ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer 42ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer // Instance variables filled by tablegen, do not use! 43f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer const MCRegisterClass *MC; 4416d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner const vt_iterator VTs; 451d61f283fad2e49d3e50a3585aac4cc9183a0d28Jakob Stoklund Olesen const uint32_t *SubClassMask; 461a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen const uint16_t *SuperRegIndices; 47c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng const sc_iterator SuperClasses; 48e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&); 49320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen 50f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getID() - Return the register class ID number. 51f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 52f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getID() const { return MC->getID(); } 53f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 54f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getName() - Return the register class name for debugging. 55f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 56f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer const char *getName() const { return MC->getName(); } 57f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 58f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// begin/end - Return all of the registers in this class. 59f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 60f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer iterator begin() const { return MC->begin(); } 61f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer iterator end() const { return MC->end(); } 62f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 63f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getNumRegs - Return the number of registers in this class. 64f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 65f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getNumRegs() const { return MC->getNumRegs(); } 66f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 67f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getRegister - Return the specified register in the class. 68f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 69f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getRegister(unsigned i) const { 70f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->getRegister(i); 71f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 72f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 73f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// contains - Return true if the specified register is included in this 74f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// register class. This does not include virtual registers. 75f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool contains(unsigned Reg) const { 76f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->contains(Reg); 77f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 78f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 79f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// contains - Return true if both registers are in this class. 80f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool contains(unsigned Reg1, unsigned Reg2) const { 81f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->contains(Reg1, Reg2); 82f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 83f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 84f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getSize - Return the size of the register in bytes, which is also the size 85f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// of a stack slot allocated to hold a spilled copy of this register. 86f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getSize() const { return MC->getSize(); } 87f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 88f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getAlignment - Return the minimum required alignment for a register of 89f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// this class. 90f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getAlignment() const { return MC->getAlignment(); } 91f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 92f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getCopyCost - Return the cost of copying a value between two registers in 93f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// this class. A negative number means the register class is very expensive 94f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// to copy e.g. status flag register classes. 95f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer int getCopyCost() const { return MC->getCopyCost(); } 96f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 97f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// isAllocatable - Return true if this register class may be used to create 98f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// virtual registers. 99f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool isAllocatable() const { return MC->isAllocatable(); } 100f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 1016510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman /// hasType - return true if this TargetRegisterClass has the ValueType vt. 1026510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman /// 103e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson bool hasType(EVT vt) const { 104cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands for(int i = 0; VTs[i] != MVT::Other; ++i) 1052c6ae095b8a944c8355377498b9ad11bb94af2d5Benjamin Kramer if (EVT(VTs[i]) == vt) 1066510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return true; 1076510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return false; 1086510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman } 10995923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 110696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// vt_begin / vt_end - Loop over all of the value types that can be 111696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// represented by values in this register class. 11216d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_begin() const { 11316d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return VTs; 11416d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 11516d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner 11616d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_end() const { 11716d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator I = VTs; 118cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands while (*I != MVT::Other) ++I; 11916d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return I; 12016d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 121696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 122f451cb870efcf9e0302d25ed05f4cac6bb494e42Dan Gohman /// hasSubClass - return true if the specified TargetRegisterClass 123c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// is a proper sub-class of this TargetRegisterClass. 124c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen bool hasSubClass(const TargetRegisterClass *RC) const { 125c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC != this && hasSubClassEq(RC); 126696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 127696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 128c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 1291f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// class. 1301f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSubClassEq(const TargetRegisterClass *RC) const { 131c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen unsigned ID = RC->getID(); 132c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 133696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 13495923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 1351367fd09cb021bae61e7dd2ee208f76574c8e789Christopher Lamb /// hasSuperClass - return true if the specified TargetRegisterClass is a 136c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// proper super-class of this TargetRegisterClass. 137c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen bool hasSuperClass(const TargetRegisterClass *RC) const { 138c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC->hasSubClass(this); 139c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 140c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng 141c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 1421f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// class. 1431f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSuperClassEq(const TargetRegisterClass *RC) const { 144c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC->hasSubClassEq(this); 1451f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen } 1461f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen 147c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// getSubClassMask - Returns a bit vector of subclasses, including this one. 148c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 149c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// use it. 1509ebfbf8b9fd5f982e0db9293808bd32168615ba9Craig Topper const uint32_t *getSubClassMask() const { 151c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return SubClassMask; 152c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 15395923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 1541a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// getSuperRegIndices - Returns a 0-terminated list of sub-register indices 155b7e22efa2b2a66b7d55c0297e45c217a465621ffEric Christopher /// that project some super-register class into this register class. The list 1561a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// has an entry for each Idx such that: 1571a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// 1581a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// There exists SuperRC where: 1591a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// For all Reg in SuperRC: 1601a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// this->contains(Reg:Idx) 1611a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// 1621a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen const uint16_t *getSuperRegIndices() const { 1631a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen return SuperRegIndices; 1641a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen } 1651a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen 166c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// getSuperClasses - Returns a NULL terminated list of super-classes. The 167c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// classes are ordered by ID which is also a topological ordering from large 168c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// to small classes. The list does NOT include the current class. 169c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen sc_iterator getSuperClasses() const { 170c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return SuperClasses; 171c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 1728c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng 173f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// isASubClass - return true if this TargetRegisterClass is a subset 174f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// class of at least one other TargetRegisterClass. 1758c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng bool isASubClass() const { 1768c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng return SuperClasses[0] != 0; 1778c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng } 17895923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 17979c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// getRawAllocationOrder - Returns the preferred order for allocating 18079c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// registers from this register class in MF. The raw order comes directly 18179c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// from the .td file and may include reserved registers that are not 18279c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// allocatable. Register allocators should also make sure to allocate 18379c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// callee-saved registers only after all the volatiles are used. The 18479c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// RegisterClassInfo class provides filtered allocation orders with 18579c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// callee-saved registers moved to the end. 18679c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 18779c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// The MachineFunction argument can be used to tune the allocatable 18879c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// registers based on the characteristics of the function, subtarget, or 18979c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// other criteria. 19079c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 19179c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// By default, this method returns all registers in the class. 19279c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 193e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const { 194ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 19579c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen } 196282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman}; 197282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 198a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 199a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// registers. These are used by codegen, not by MC. 200a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengstruct TargetRegisterInfoDesc { 201a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng unsigned CostPerUse; // Extra cost of instructions using register. 202a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng bool inAllocatableClass; // Register belongs to an allocatable regclass. 203a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng}; 204282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 205ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick/// Each TargetRegisterClass has a per register weight, and weight 206ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick/// limit which must be less than the limits of its pressure sets. 207ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trickstruct RegClassWeight { 20833d9e89e5f8d7656e50353b014d5bb1b52f15e13Andrew Trick unsigned RegWeight; 209ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick unsigned WeightLimit; 210ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick}; 211ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick 2126f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// TargetRegisterInfo base class - We assume that the target defines a static 2136f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// array of TargetRegisterDesc objects that represent all of the machine 2146f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// registers that the target has. As such, we simply have to track a pointer 2156f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// to this array so that we can turn register number into a register 2166f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// descriptor. 2173d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// 218a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengclass TargetRegisterInfo : public MCRegisterInfo { 2198797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerpublic: 2208797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner typedef const TargetRegisterClass * const * regclass_iterator; 2218797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerprivate: 222a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 2231fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *const *SubRegIndexNames; // Names of subreg indexes. 224a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen // Pointer to array of lane masks, one per sub-reg index. 225a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen const unsigned *SubRegIndexLaneMasks; 226a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen 2278797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 228b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene 2293d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerprotected: 230a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 2316f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassBegin, 2326f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassEnd, 233a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen const char *const *SRINames, 234a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen const unsigned *SRILaneMasks); 2356f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman virtual ~TargetRegisterInfo(); 2363d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerpublic: 2373d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 238b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Register numbers can represent physical registers, virtual registers, and 239b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // sometimes stack slots. The unsigned values are divided into these ranges: 240b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 241b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 0 Not a register, can be used as a sentinel. 242b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [1;2^30) Physical registers assigned by TableGen. 243b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^30;2^31) Stack slots. (Rarely used.) 244b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 245b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 246b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Further sentinels can be allocated from the small negative integers. 247b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // DenseMapInfo<unsigned> uses -1u and -2u. 2483d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 249be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// isStackSlot - Sometimes it is useful the be able to store a non-negative 250be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// frame index in a variable that normally holds a register. isStackSlot() 251be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// returns true if Reg is in the range used for stack slots. 252be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 253da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 254da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// slots, so if a variable may contains a stack slot, always check 255da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// isStackSlot() first. 256be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 257be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static bool isStackSlot(unsigned Reg) { 258da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) >= (1 << 30); 259be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 260be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 261be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// stackSlot2Index - Compute the frame index from a register value 262be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// representing a stack slot. 263be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static int stackSlot2Index(unsigned Reg) { 264be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(isStackSlot(Reg) && "Not a stack slot"); 265da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg - (1u << 30)); 266be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 267be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 268be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// index2StackSlot - Convert a non-negative frame index to a stack slot 269be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// register value. 270be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static unsigned index2StackSlot(int FI) { 271be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(FI >= 0 && "Cannot hold a negative frame index."); 272da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return FI + (1u << 30); 273be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 274be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 275bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// isPhysicalRegister - Return true if the specified register number is in 276bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the physical register namespace. 277bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isPhysicalRegister(unsigned Reg) { 278da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 279da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) > 0; 280bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 281bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 282bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// isVirtualRegister - Return true if the specified register number is in 283bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the virtual register namespace. 284bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isVirtualRegister(unsigned Reg) { 285da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 286da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) < 0; 287bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 288bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 289c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen /// virtReg2Index - Convert a virtual register number to a 0-based index. 290c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen /// The first virtual register in a function will get the index 0. 291c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen static unsigned virtReg2Index(unsigned Reg) { 292da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(isVirtualRegister(Reg) && "Not a virtual register"); 293dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Reg & ~(1u << 31); 294c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen } 295c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen 296b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// index2VirtReg - Convert a 0-based index to a virtual register number. 297b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// This is the inverse operation of VirtReg2IndexFunctor below. 298b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen static unsigned index2VirtReg(unsigned Index) { 299dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Index | (1u << 31); 300b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen } 301b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 302ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola /// getMinimalPhysRegClass - Returns the Register Class of a physical 303c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman /// register of the given type, picking the most sub register class of 304c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman /// the right type that contains this physreg. 305d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola const TargetRegisterClass * 306d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 307ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 308f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick /// getAllocatableClass - Return the maximal subclass of the given register 309f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick /// class that is alloctable, or NULL. 310f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick const TargetRegisterClass * 311f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick getAllocatableClass(const TargetRegisterClass *RC) const; 312f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick 313bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos /// getAllocatableSet - Returns a bitset indexed by register number 314eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng /// indicating if a register is allocatable or not. If a register class is 315eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng /// specified, returns the subset for the class. 316769b7f89534caed11d7595b5c84aa47d3de30ad9Dan Gohman BitVector getAllocatableSet(const MachineFunction &MF, 317eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng const TargetRegisterClass *RC = NULL) const; 318bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos 3196bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen /// getCostPerUse - Return the additional cost of using this register instead 3206bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen /// of other registers in its class. 3216bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen unsigned getCostPerUse(unsigned RegNo) const { 322a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return InfoDesc[RegNo].CostPerUse; 3236bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen } 3246bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen 325a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// isInAllocatableClass - Return true if the register is in the allocation 326a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// of any register class. 327a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng bool isInAllocatableClass(unsigned RegNo) const { 328a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return InfoDesc[RegNo].inAllocatableClass; 32993aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos } 33093aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos 3311fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen /// getSubRegIndexName - Return the human-readable symbolic target-specific 3321fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen /// name for the specified SubRegIndex. 3331fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *getSubRegIndexName(unsigned SubIdx) const { 33459f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen assert(SubIdx && SubIdx < getNumSubRegIndices() && 33559f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen "This is not a subregister index"); 3361fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen return SubRegIndexNames[SubIdx-1]; 3371fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen } 3381fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen 339a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// getSubRegIndexLaneMask - Return a bitmask representing the parts of a 340a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// register that are covered by SubIdx. 341a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 342a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// Lane masks for sub-register indices are similar to register units for 343a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// physical registers. The individual bits in a lane mask can't be assigned 344a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// any specific meaning. They can be used to check if two sub-register 345a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// indices overlap. 346a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 347a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// If the target has a register such that: 348a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 349a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// getSubReg(Reg, A) overlaps getSubReg(Reg, B) 350a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 351a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// then: 352a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 353a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0 354a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// 355a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// The converse is not necessarily true. If two lane masks have a common 356a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// bit, the corresponding sub-registers may not overlap, but it can be 357a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen /// assumed that they usually will. 358a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { 359a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen // SubIdx == 0 is allowed, it has the lane mask ~0u. 360a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); 361a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen return SubRegIndexLaneMasks[SubIdx]; 362a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen } 363a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen 3643f2f3f5341374c85955cfaffa71886724999762dLang Hames /// regsOverlap - Returns true if the two registers are equal or alias each 3653f2f3f5341374c85955cfaffa71886724999762dLang Hames /// other. The registers may be virtual register. 3663f2f3f5341374c85955cfaffa71886724999762dLang Hames bool regsOverlap(unsigned regA, unsigned regB) const { 3671e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (regA == regB) return true; 3683f2f3f5341374c85955cfaffa71886724999762dLang Hames if (isVirtualRegister(regA) || isVirtualRegister(regB)) 3693f2f3f5341374c85955cfaffa71886724999762dLang Hames return false; 37096feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen 37196feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen // Regunits are numerically ordered. Find a common unit. 37296feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen MCRegUnitIterator RUA(regA, this); 37396feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen MCRegUnitIterator RUB(regB, this); 37496feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen do { 37596feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen if (*RUA == *RUB) return true; 37696feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen if (*RUA < *RUB) ++RUA; 37796feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen else ++RUB; 37896feada378dc9769644333ca9670b265fd15a2efJakob Stoklund Olesen } while (RUA.isValid() && RUB.isValid()); 37904319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos return false; 38004319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos } 38104319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos 38228897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen /// hasRegUnit - Returns true if Reg contains RegUnit. 38328897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { 38428897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units) 38528897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen if (*Units == RegUnit) 38628897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen return true; 38728897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen return false; 38828897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen } 38928897ca434892340f2e188a0331db92d5899409bJakob Stoklund Olesen 390b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// isSubRegister - Returns true if regB is a sub-register of regA. 391b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// 392b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng bool isSubRegister(unsigned regA, unsigned regB) const { 3931e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson return isSuperRegister(regB, regA); 394b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng } 395b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng 396b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// isSuperRegister - Returns true if regB is a super-register of regA. 397b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// 398cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen bool isSuperRegister(unsigned RegA, unsigned RegB) const { 399cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I) 400cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen if (*I == RegB) 401cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen return true; 4021e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson return false; 403b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng } 404b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng 4050098b3e2b69e527ddcf2ebad7a3081898fa3b4f0Evan Cheng /// getCalleeSavedRegs - Return a null-terminated list of all of the 4060098b3e2b69e527ddcf2ebad7a3081898fa3b4f0Evan Cheng /// callee saved registers on this target. The register should be in the 40702569d7355b03155b32c1c0d0e46f6aa957f4802Evan Cheng /// order of desired callee-save stack frame offset. The first register is 408bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// closest to the incoming stack pointer if stack grows down, and vice versa. 409bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 410e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen virtual const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF = 0) 4112365f51ed03afe6993bae962fdc2e5a956a64cd5Anton Korobeynikov const = 0; 4128797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 413bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// getCallPreservedMask - Return a mask of call-preserved registers for the 414bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// given calling convention on the current sub-target. The mask should 415bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// include all call-preserved aliases. This is used by the register 416bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// allocator to determine which registers can be live across a call. 417bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 418bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 419bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// A set bit indicates that all bits of the corresponding register are 420bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// preserved across the function call. The bit mask is expected to be 421bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// sub-register complete, i.e. if A is preserved, so are all its 422bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// sub-registers. 423bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 424bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// Bits are numbered from the LSB, so the bit for physical register Reg can 425bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 426478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// 427478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// A NULL pointer means that no register mask will be used, and call 428478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// instructions should use implicit-def operands to indicate call clobbered 429478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// registers. 430bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 431bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { 432bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen // The default mask clobbers everything. All targets should override. 433bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen return 0; 434bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen } 4358797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 436b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng /// getReservedRegs - Returns a bitset indexed by physical register number 4371c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// indicating if a register is a special register that has particular uses 4381c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// and should be considered unavailable at all times, e.g. SP, RA. This is 4391c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// used by register scavenger to determine what registers are free. 440b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 441b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 4428a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng /// getMatchingSuperReg - Return a super-register of the specified register 4438a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng /// Reg so its sub-register of index SubIdx is Reg. 44495923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 4458a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng const TargetRegisterClass *RC) const { 44633ca87affb81b60c4d50214eb7458bd26d397d53Jim Grosbach return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 4478a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng } 4488a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng 4495248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// getMatchingSuperRegClass - Return a subclass of the specified register 4505248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// class A so that each register in it has a sub-register of the 4515248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// specified sub-register index which is in the specified register class B. 452570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// 453570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// TableGen will synthesize missing A sub-classes. 4545248468473f0488a652b545ad95f7abda302b7b5Evan Cheng virtual const TargetRegisterClass * 4555248468473f0488a652b545ad95f7abda302b7b5Evan Cheng getMatchingSuperRegClass(const TargetRegisterClass *A, 456dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen const TargetRegisterClass *B, unsigned Idx) const; 4575248468473f0488a652b545ad95f7abda302b7b5Evan Cheng 458845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 459845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// supports the sub-register index Idx. 460845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// If no such sub-class exists, return NULL. 461845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// If all registers in RC already have an Idx sub-register, return RC. 462845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// 463845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// TableGen generates a version of this function that is good enough in most 464845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// cases. Targets can override if they have constraints that TableGen 465845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// doesn't understand. For example, the x86 sub_8bit sub-register index is 466845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// supported by the full GR32 register class in 64-bit mode, but only by the 467845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// GR32_ABCD regiister class in 32-bit mode. 468845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// 469570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// TableGen will synthesize missing RC sub-classes. 470845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen virtual const TargetRegisterClass * 471309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 472309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen assert(Idx == 0 && "Target has no sub-registers"); 473309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen return RC; 474309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen } 475845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen 4762da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// composeSubRegIndices - Return the subregister index you get from composing 4772da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// two subregister indices. 4782da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 479ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen /// The special null sub-register index composes as the identity. 480ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen /// 4812da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 4822da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// returns c. Note that composeSubRegIndices does not tell you about illegal 4832da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// compositions. If R does not have a subreg a, or R:a does not have a subreg 4842da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// b, composeSubRegIndices doesn't tell you. 4852da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 4862da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 4872da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// ssub_0:S0 - ssub_3:S3 subregs. 4882da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 4892da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 490ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen unsigned composeSubRegIndices(unsigned a, unsigned b) const { 491ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen if (!a) return b; 492ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen if (!b) return a; 493ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen return composeSubRegIndicesImpl(a, b); 4942da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen } 4952da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen 496ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesenprotected: 497ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen /// Overridden by TableGen in targets that have sub-registers. 498ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const { 499ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen llvm_unreachable("Target has no sub-registers"); 500ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen } 501ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesen 502ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cfJakob Stoklund Olesenpublic: 503fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// getCommonSuperRegClass - Find a common super-register class if it exists. 504fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 505fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// Find a register class, SuperRC and two sub-register indices, PreA and 506fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// PreB, such that: 507fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 508fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and 509fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 510fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and 511fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 512fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()). 513fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 514fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// SuperRC will be chosen such that no super-class of SuperRC satisfies the 515fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// requirements, and there is no register class with a smaller spill size 516fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// that satisfies the requirements. 517fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 518fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead. 519fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 520fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// Either of the PreA and PreB sub-register indices may be returned as 0. In 521fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// that case, the returned register class will be a sub-class of the 522fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// corresponding argument register class. 523fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 524fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// The function returns NULL if no register class can be found. 525fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen /// 526fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterClass* 527fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 528fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterClass *RCB, unsigned SubB, 529fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned &PreA, unsigned &PreB) const; 530fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 5318797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner //===--------------------------------------------------------------------===// 5328797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // Register Class Information 5338797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // 5348797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 5358797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner /// Register class iterators 53692988ecdb6ca641ba39d1d1f8cbc57a89b63bbadChris Lattner /// 5378797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_begin() const { return RegClassBegin; } 5388797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_end() const { return RegClassEnd; } 5398797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 5408797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner unsigned getNumRegClasses() const { 54134cd4a484e532cc463fd5a4bf59b88d13c5467c1Evan Cheng return (unsigned)(regclass_end()-regclass_begin()); 5428797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner } 54395923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 54460f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// getRegClass - Returns the register class associated with the enumeration 545e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// value. See class MCOperandInfo. 54660f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey const TargetRegisterClass *getRegClass(unsigned i) const { 547a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman assert(i < getNumRegClasses() && "Register Class ID out of range"); 548a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman return RegClassBegin[i]; 54960f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey } 5508797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 551e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen /// getCommonSubClass - find the largest common subclass of A and B. Return 552e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen /// NULL if there is no common subclass. 553e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass * 554e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen getCommonSubClass(const TargetRegisterClass *A, 555e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass *B) const; 556e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen 557770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 5582cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner /// values. If a target supports multiple different pointer register classes, 5592cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner /// kind specifies which one is indicated. 560397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen virtual const TargetRegisterClass * 561397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const { 56250bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Target didn't implement getPointerRegClass!"); 563770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng } 5648797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 565ff110265753c19daf0468ee1facf357460497b7eEvan Cheng /// getCrossCopyRegClass - Returns a legal register class to copy a register 566b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// in the specified class to or from. If it is possible to copy the register 567b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// directly without using a cross register class copy, return the specified 568b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// RC. Returns NULL if it is not possible to copy between a two registers of 569b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// the specified class. 570ff110265753c19daf0468ee1facf357460497b7eEvan Cheng virtual const TargetRegisterClass * 571ff110265753c19daf0468ee1facf357460497b7eEvan Cheng getCrossCopyRegClass(const TargetRegisterClass *RC) const { 572b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng return RC; 573ff110265753c19daf0468ee1facf357460497b7eEvan Cheng } 574ff110265753c19daf0468ee1facf357460497b7eEvan Cheng 575c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// getLargestLegalSuperClass - Returns the largest super class of RC that is 576c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// legal to use in the current sub-target and has the same spill size. 577c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The returned register class can be used to create virtual registers which 578c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// means that all its registers can be copied and spilled. 579c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen virtual const TargetRegisterClass* 580c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 581c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The default implementation is very conservative and doesn't allow the 582c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// register allocator to inflate register classes. 583c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return RC; 584c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } 585c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen 586be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// getRegPressureLimit - Return the register pressure "high water mark" for 587be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// the specific register class. The scheduler is in high register pressure 588be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// mode (for the specific register class) if it goes over the limit. 589decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// 590decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Note: this is the old register pressure model that relies on a manually 591decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// specified representative register class per value type. 592be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 593be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich MachineFunction &MF) const { 594be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 0; 595be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 596be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 597d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick// Get the weight in units of pressure for this register class. 598ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick virtual const RegClassWeight &getRegClassWeight( 599ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick const TargetRegisterClass *RC) const = 0; 600decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 601decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the number of dimensions of register pressure. 602decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual unsigned getNumRegPressureSets() const = 0; 603decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 604d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick /// Get the name of this register unit pressure set. 605d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick virtual const char *getRegPressureSetName(unsigned Idx) const = 0; 606d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick 607decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the register unit pressure limit for this dimension. 608decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// This limit must be adjusted dynamically for reserved registers. 609decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0; 610decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 611decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the dimensions of register pressure impacted by this register class. 612decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Returns a -1 terminated array of pressure set IDs. 613decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual const int *getRegClassPressureSets( 614decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick const TargetRegisterClass *RC) const = 0; 615decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 616dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// getRawAllocationOrder - Returns the register allocation order for a 617dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// specified register class with a target-dependent hint. The returned list 618dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// may contain reserved registers that cannot be allocated. 619dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// 620dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// Register allocators need only call this function to resolve 621dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// target-dependent hints, but it should work without hinting as well. 622e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen virtual ArrayRef<MCPhysReg> 623dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen getRawAllocationOrder(const TargetRegisterClass *RC, 624dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen unsigned HintType, unsigned HintReg, 625dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen const MachineFunction &MF) const { 626dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen return RC->getRawAllocationOrder(MF); 627358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng } 628358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng 629358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// ResolveRegAllocHint - Resolves the specified register allocation hint 630358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// to a physical register. Returns the physical register if it is successful. 631f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 632f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng const MachineFunction &MF) const { 633358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng if (Type == 0 && Reg && isPhysicalRegister(Reg)) 634358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng return Reg; 635358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng return 0; 636358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng } 637358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng 638f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// avoidWriteAfterWrite - Return true if the register allocator should avoid 639f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// writing a register from RC in two consecutive instructions. 640f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// This can avoid pipeline stalls on certain architectures. 641f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// It does cause increased register pressure, though. 642f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 643f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return false; 644f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson } 645f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 646f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// UpdateRegAllocHint - A callback to allow target a chance to update 647f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// register allocation hints when a register is "changed" (e.g. coalesced) 648f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// to another register. e.g. On ARM, some virtual registers should target 649f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// register pairs, if one of pair is coalesced to another register, the 650f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// allocation hint of the other half of the pair should be changed to point 651f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// to the new register. 652f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 653f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng MachineFunction &MF) const { 654f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng // Do nothing. 655f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng } 656f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng 6571c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// requiresRegisterScavenging - returns true if the target requires (and can 6581c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// make use of) the register scavenger. 65936230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 66037f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng return false; 66137f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng } 66295923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 6630f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// useFPForScavengingIndex - returns true if the target wants to use 6640f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// frame pointer based accesses to spill to the scavenger emergency spill 6650f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// slot. 6660f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 6670f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach return true; 6680f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach } 6690f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach 67065c58daa8b8985d2116216043103009815a55e77Jim Grosbach /// requiresFrameIndexScavenging - returns true if the target requires post 67165c58daa8b8985d2116216043103009815a55e77Jim Grosbach /// PEI scavenging of registers for materializing frame index constants. 67265c58daa8b8985d2116216043103009815a55e77Jim Grosbach virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 67365c58daa8b8985d2116216043103009815a55e77Jim Grosbach return false; 67465c58daa8b8985d2116216043103009815a55e77Jim Grosbach } 67565c58daa8b8985d2116216043103009815a55e77Jim Grosbach 676a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// requiresVirtualBaseRegisters - Returns true if the target wants the 677a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// LocalStackAllocation pass to be run and virtual base registers 678a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// used for more efficient stack access. 679a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 680a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach return false; 681a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach } 682a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 683910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 684910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// the stack frame of the given function for the specified register. e.g. On 685910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// x86, if the frame register is required, the first fixed stack object is 686910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// reserved as its spill slot. This tells PEI not to create a new stack frame 687910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// object for the given register. It should be called only after 688910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// processFunctionBeforeCalleeSavedScan(). 68972852a8cfb605056d87b644d2e36b1346051413dEric Christopher virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 690910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng int &FrameIdx) const { 691910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng return false; 692910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng } 693910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng 6946a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd /// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked 6956a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd /// after register allocation. 6966a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 6976a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd return false; 6986a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd } 6996a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 700910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// needsStackRealignment - true if storage within the function requires the 701910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// stack pointer to be aligned more than the normal calling convention calls 702910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// for. 703b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen virtual bool needsStackRealignment(const MachineFunction &MF) const { 704b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen return false; 705b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen } 706b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen 707e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// getFrameIndexInstrOffset - Get the offset from the referenced frame 70863f8659d6936077c5e8e34eecb55ff1de0db5686Bob Wilson /// index in the instruction, if there is one. 7091ab3f16f06698596716593a30545799688acccd7Jim Grosbach virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 7101ab3f16f06698596716593a30545799688acccd7Jim Grosbach int Idx) const { 711e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return 0; 712e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 713e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 7148708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// needsFrameBaseReg - Returns true if the instruction's frame index 7158708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// reference would be better served by a base register other than FP 7168708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// or SP. Used by LocalStackFrameAllocation to determine which frame index 7178708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// references it should create new base registers for. 7183197380143cdc18837722129ac888528b9fbfc2bJim Grosbach virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 7198708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 7208708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 7218708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 722dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// materializeFrameBaseRegister - Insert defining instruction(s) for 723dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// BaseReg to be a pointer to FrameIdx before insertion point I. 724976ef86689ed065361a748f81c44ca3510af2202Bill Wendling virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 725e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned BaseReg, int FrameIdx, 726e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 72750bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("materializeFrameBaseRegister does not exist on this " 72850bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper "target"); 729dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 730dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 731dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// resolveFrameIndex - Resolve a frame index operand of an instruction 732dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// to reference the indicated base register plus offset instead. 733dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 734dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned BaseReg, int64_t Offset) const { 73550bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("resolveFrameIndex does not exist on this target"); 736dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 737dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 738e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// isFrameOffsetLegal - Determine whether a given offset immediate is 739e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// encodable to resolve a frame index. 740e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach virtual bool isFrameOffsetLegal(const MachineInstr *MI, 741e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 74250bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 74374d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach } 744dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 745f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 746f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// code insertion to eliminate call frame setup and destroy pseudo 747f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// instructions (but only if the Target is using them). It is responsible 748f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// for eliminating these instructions, replacing them with concrete 749f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// instructions. This method need only be implemented if using call frame 7508a1478b6d7aeaed8363316d2e0b90d9f53525c29Chris Lattner /// setup/destroy pseudo instructions. 751f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// 75234695381d626485a560594f162701088079589dfMisha Brukman virtual void 7538604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner eliminateCallFramePseudoInstr(MachineFunction &MF, 7548604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner MachineBasicBlock &MBB, 7558604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner MachineBasicBlock::iterator MI) const { 75650bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Call Frame Pseudo Instructions do not exist on this " 75750bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper "target!"); 758f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner } 759f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 760f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 761d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// saveScavengerRegister - Spill the register so it can be used by the 762d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// register scavenger. Return true if the register was spilled, false 763d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// otherwise. If this function does not spill the register, the scavenger 764540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// will instead spill it to the emergency spill slot. 765540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// 766540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 767540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach MachineBasicBlock::iterator I, 768d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach MachineBasicBlock::iterator &UseMI, 769540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach const TargetRegisterClass *RC, 7701f8f4d2db734d9881467a5706acac73660842d43Evan Cheng unsigned Reg) const { 7711f8f4d2db734d9881467a5706acac73660842d43Evan Cheng return false; 7721f8f4d2db734d9881467a5706acac73660842d43Evan Cheng } 773540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach 774f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminateFrameIndex - This method must be overriden to eliminate abstract 775f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// frame indices from instructions which may use them. The instruction 776f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// referenced by the iterator contains an MO_FrameIndex operand which must be 777f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminated by this method. This method may modify or replace the 778c49a10aca1e31351c2e11b25ba636a23b93c46c8Dale Johannesen /// specified instruction, as long as it keeps the iterator pointing at the 77918b111bffe643b5ad52ae10a1d5728b0c1ac92f0Evan Cheng /// finished product. SPAdj is the SP adjustment due to call frame setup 7801ad70c09c890c3abcc147503f2e23082f683790cMatthijs Kooijman /// instruction. 781fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 782fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach int SPAdj, RegScavenger *RS=NULL) const = 0; 783f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 784a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey //===--------------------------------------------------------------------===// 785a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// Debug information queries. 78695923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 787a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// getFrameRegister - This method should return the register used as a base 7884188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey /// for values allocated in the current stack frame. 789b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 79072bebb9205c1628601b052d25555aabe6e15e6f4Evan Cheng 7915cd2791513919ee7504c309151321e4e37a05a58Bill Wendling /// getCompactUnwindRegNum - This function maps the register to the number for 7925cd2791513919ee7504c309151321e4e37a05a58Bill Wendling /// compact unwind encoding. Return -1 if the register isn't valid. 793486dd90696545421c55346570b88fa03f6dd464fBill Wendling virtual int getCompactUnwindRegNum(unsigned, bool) const { 7945cd2791513919ee7504c309151321e4e37a05a58Bill Wendling return -1; 7955cd2791513919ee7504c309151321e4e37a05a58Bill Wendling } 7963d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner}; 7973d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 798c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng 79989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen//===----------------------------------------------------------------------===// 80089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// SuperRegClassIterator 80189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen//===----------------------------------------------------------------------===// 80289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 80389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// Iterate over the possible super-registers for a given register class. The 80489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// iterator will visit a list of pairs (Idx, Mask) corresponding to the 80589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// possible classes of super-registers. 80689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 80789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// Each bit mask will have at least one set bit, and each set bit in Mask 80889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// corresponds to a SuperRC such that: 80989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 81089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// For all Reg in SuperRC: Reg:Idx is in RC. 81189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 81289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// The iterator can include (O, RC->getSubClassMask()) as the first entry which 81389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// also satisfies the above requirement, assuming Reg:0 == Reg. 81489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen// 81589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesenclass SuperRegClassIterator { 81689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const unsigned RCMaskWords; 81789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen unsigned SubReg; 81889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const uint16_t *Idx; 81989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const uint32_t *Mask; 82089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 82189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesenpublic: 82289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Create a SuperRegClassIterator that visits all the super-register classes 82389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry. 82489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen SuperRegClassIterator(const TargetRegisterClass *RC, 82589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const TargetRegisterInfo *TRI, 82689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen bool IncludeSelf = false) 82789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen : RCMaskWords((TRI->getNumRegClasses() + 31) / 32), 82889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen SubReg(0), 82989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen Idx(RC->getSuperRegIndices()), 83089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen Mask(RC->getSubClassMask()) { 83189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen if (!IncludeSelf) 83289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen ++*this; 83389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen } 83489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 83589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Returns true if this iterator is still pointing at a valid entry. 83689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen bool isValid() const { return Idx; } 83789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 83889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Returns the current sub-register index. 83989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen unsigned getSubReg() const { return SubReg; } 84089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 84189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Returns the bit mask if register classes that getSubReg() projects into 84289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// RC. 84389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen const uint32_t *getMask() const { return Mask; } 84489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 84589e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen /// Advance iterator to the next entry. 84689e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen void operator++() { 84789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen assert(isValid() && "Cannot move iterator past end."); 84889e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen Mask += RCMaskWords; 84989e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen SubReg = *Idx++; 85089e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen if (!SubReg) 85189e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen Idx = 0; 85289e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen } 85389e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen}; 85489e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen 85594c002a190cd2e3a52b1510bc997e53d63af0b3bChris Lattner// This is useful when building IndexedMaps keyed on virtual registers 85659bf4fcc0680e75b408579064d1205a132361196Duncan Sandsstruct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 8574d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos unsigned operator()(unsigned Reg) const { 858c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen return TargetRegisterInfo::virtReg2Index(Reg); 8594d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos } 8604d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos}; 8614d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos 8624314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// PrintReg - Helper class for printing registers on a raw_ostream. 8634314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Prints virtual and physical registers with or without a TRI instance. 8644314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 8654314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// The format is: 86643a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %noreg - NoRegister 86743a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5 - a virtual register. 86843a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 86943a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %EAX - a physical register 87043a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %physreg17 - a physical register when no TRI instance given. 8714314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 8724314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 8734314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 8744314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenclass PrintReg { 8754314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen const TargetRegisterInfo *TRI; 8764314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen unsigned Reg; 8774314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen unsigned SubIdx; 8784314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenpublic: 879af87dae12cab8d2e5cab033a5ab60af98e1837feCraig Topper explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, 880af87dae12cab8d2e5cab033a5ab60af98e1837feCraig Topper unsigned subidx = 0) 8814314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen : TRI(tri), Reg(reg), SubIdx(subidx) {} 8824314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen void print(raw_ostream&) const; 8834314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen}; 8844314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen 8854314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenstatic inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 8864314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen PR.print(OS); 8874314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen return OS; 8884314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen} 8894314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen 8905ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// PrintRegUnit - Helper class for printing register units on a raw_ostream. 8915ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// 8925ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// Register units are named after their root registers: 8935ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// 8945ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// AL - Single root. 8955ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// FP0~ST7 - Dual roots. 8965ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// 8975ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n'; 8985ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen/// 8995ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesenclass PrintRegUnit { 9005ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen const TargetRegisterInfo *TRI; 9015ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen unsigned Unit; 9025ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesenpublic: 9035ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri) 9045ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen : TRI(tri), Unit(unit) {} 9055ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen void print(raw_ostream&) const; 9065ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen}; 9075ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen 9085ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesenstatic inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) { 9095ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen PR.print(OS); 9105ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen return OS; 9115ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen} 9125ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen 913d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 914d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 9153d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner#endif 916