TargetRegisterInfo.h revision 282ec57c4cdd4574103922487b6f1563b5034fb4
13d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner//===- Target/MRegisterInfo.h - Target Register Information -------*-C++-*-===// 23d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 33d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// This file describes an abstract interface used to get information about a 43d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// target machines register file. This information is used for a variety of 53d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// purposed, especially register allocation. 63d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 73d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner//===----------------------------------------------------------------------===// 83d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 9282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman#ifndef LLVM_TARGET_MREGISTERINFO_H 10282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman#define LLVM_TARGET_MREGISTERINFO_H 113d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 12282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman#include "llvm/CodeGen/MachineBasicBlock.h" 133d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner#include <assert.h> 143d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 15282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukmanclass Type; 16282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 173d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// MRegisterDesc - This record contains all of the information known about a 183d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// particular register. 193d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// 203d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerstruct MRegisterDesc { 213d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner const char *Name; // Assembly language name for the register 223d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner unsigned Flags; // Flags identifying register properties (defined below) 233d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner unsigned TSFlags; // Target Specific Flags 243d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner}; 253d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 263d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// MRF namespace - This namespace contains flags that pertain to machine 273d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// registers 283d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// 293d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnernamespace MRF { // MRF = Machine Register Flags 303d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner enum { 313d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner INT8 = 1 << 0, // This is an 8 bit integer register 323d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner INT16 = 1 << 1, // This is a 16 bit integer register 333d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner INT32 = 1 << 2, // This is a 32 bit integer register 343d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner INT64 = 1 << 3, // This is a 64 bit integer register 353d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner INT128 = 1 << 4, // This is a 128 bit integer register 363d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 373d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner FP32 = 1 << 5, // This is a 32 bit floating point register 383d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner FP64 = 1 << 6, // This is a 64 bit floating point register 393d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner FP80 = 1 << 7, // This is a 80 bit floating point register 403d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner FP128 = 1 << 8, // This is a 128 bit floating point register 413d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner }; 423d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner}; 433d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 44282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukmanclass TargetRegisterClass { 45282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukmanprotected: 46282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman TargetRegisterClass() {} 47282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 48282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukmanpublic: 49282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 50282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman typedef unsigned* iterator; 51282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman typedef unsigned* const_iterator; 52282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 53282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman iterator begin(); 54282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman iterator end(); 55282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman const_iterator begin() const; 56282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman const_iterator end() const; 57282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 58282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman virtual unsigned getNumRegs() const { return 0; } 59282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman virtual unsigned getRegister(unsigned idx) const { return 0; } 60282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 61282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman virtual unsigned getDataSize() const { return 0; } 62282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 63282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman //const std::vector<unsigned> &getRegsInClass(void) { return Regs; } 64282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman //void getAliases(void); 65282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman}; 66282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 67282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 683d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// MRegisterInfo base class - We assume that the target defines a static array 693d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// of MRegisterDesc objects that represent all of the machine registers that 703d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// the target has. As such, we simply have to track a pointer to this array so 713d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// that we can turn register number into a register descriptor. 723d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// 733d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerclass MRegisterInfo { 743d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner const MRegisterDesc *Desc; // Pointer to the descriptor array 753d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner unsigned NumRegs; // Number of entries in the array 763d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerprotected: 773d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner MRegisterInfo(const MRegisterDesc *D, unsigned NR) : Desc(D), NumRegs(NR) {} 783d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerpublic: 793d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 803d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner enum { // Define some target independant constants 813d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// NoRegister - This 'hard' register is a 'noop' register for all backends. 823d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// This is used as the destination register for instructions that do not 833d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// produce a value. Some frontends may use this as an operand register to 843d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// mean special things, for example, the Sparc backend uses R0 to mean %g0 853d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// which always PRODUCES the value 0. The X86 backend does not use this 863d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// value as an operand register. 873d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// 883d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner NoRegister = 0, 893d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 903d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// FirstVirtualRegister - This is the first register number that is 913d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// considered to be a 'virtual' register, which is part of the SSA 923d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// namespace. This must be the same for all targets, which means that each 933d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// target is limited to 1024 registers. 943d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// 953d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner FirstVirtualRegister = 1024, 963d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner }; 973d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 983d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner const MRegisterDesc &operator[](unsigned RegNo) const { 993d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner assert(RegNo < NumRegs && 1003d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner "Attempting to access record for invalid register number!"); 1013d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner return Desc[RegNo]; 1023d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner } 1033d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 1043d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// Provide a get method, equivalent to [], but more useful if we have a 1053d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// pointer to this object. 1063d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner /// 1073d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); } 1083d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 109282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 110282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman virtual void copyReg2PCRel(MachineBasicBlock *MBB, 111282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman MachineBasicBlock::iterator &MBBI, 112282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman unsigned SrcReg, unsigned ImmOffset, 113282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman unsigned dataSize) const = 0; 114282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 115282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman virtual void copyPCRel2Reg(MachineBasicBlock *MBB, 116282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman MachineBasicBlock::iterator &MBBI, 117282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman unsigned ImmOffset, unsigned DestReg, 118282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman unsigned dataSize) const = 0; 119282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 120282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman /// Register class iterators 121282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman typedef const TargetRegisterClass* const_iterator; 122282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 123282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman virtual const_iterator const_regclass_begin() const = 0; 124282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman virtual const_iterator const_regclass_end() const = 0; 125282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 126282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman virtual unsigned getNumRegClasses() const = 0; 127282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman virtual const TargetRegisterClass* getRegClassForType(const Type* Ty) const=0; 1283d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner}; 1293d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 1303d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner#endif 131