TargetRegisterInfo.h revision 309076ff76c61e03ddd3a0fbbfded3042d2da2e5
16f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 93d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 103d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// This file describes an abstract interface used to get information about a 113d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// target machines register file. This information is used for a variety of 123d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// purposed, especially register allocation. 133d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 143d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner//===----------------------------------------------------------------------===// 153d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 166f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#define LLVM_TARGET_TARGETREGISTERINFO_H 183d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 19a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include "llvm/MC/MCRegisterInfo.h" 20024126ee23e6e4430a77025b61d0e713180f03d3Alkis Evlogimenos#include "llvm/CodeGen/MachineBasicBlock.h" 21a385bf7b6dc9b71024aa4c7bb7026bab3c7ebe91Chris Lattner#include "llvm/CodeGen/ValueTypes.h" 2279c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen#include "llvm/ADT/ArrayRef.h" 23bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen#include "llvm/CallingConv.h" 244d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <cassert> 254d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <functional> 263d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 27d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 28d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 29171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass BitVector; 30198ab640bbb0b8e1cdda518b7f8b348764e4402cChris Lattnerclass MachineFunction; 31171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass RegScavenger; 32b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Chengtemplate<class T> class SmallVectorImpl; 33414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesenclass raw_ostream; 34282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 35f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramerclass TargetRegisterClass { 36282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukmanpublic: 37b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper typedef const uint16_t* iterator; 38b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper typedef const uint16_t* const_iterator; 392c6ae095b8a944c8355377498b9ad11bb94af2d5Benjamin Kramer typedef const MVT::SimpleValueType* vt_iterator; 403b0c0148ed9ec752b240dbea767ad4a9f0a682caEvan Cheng typedef const TargetRegisterClass* const * sc_iterator; 41ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer 42ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer // Instance variables filled by tablegen, do not use! 43f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer const MCRegisterClass *MC; 4416d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner const vt_iterator VTs; 45c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen const unsigned *SubClassMask; 46c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng const sc_iterator SuperClasses; 47f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const sc_iterator SuperRegClasses; 48b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper ArrayRef<uint16_t> (*OrderFunc)(const MachineFunction&); 49320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen 50f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getID() - Return the register class ID number. 51f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 52f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getID() const { return MC->getID(); } 53f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 54f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getName() - Return the register class name for debugging. 55f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 56f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer const char *getName() const { return MC->getName(); } 57f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 58f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// begin/end - Return all of the registers in this class. 59f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 60f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer iterator begin() const { return MC->begin(); } 61f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer iterator end() const { return MC->end(); } 62f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 63f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getNumRegs - Return the number of registers in this class. 64f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 65f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getNumRegs() const { return MC->getNumRegs(); } 66f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 67f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getRegister - Return the specified register in the class. 68f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 69f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getRegister(unsigned i) const { 70f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->getRegister(i); 71f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 72f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 73f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// contains - Return true if the specified register is included in this 74f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// register class. This does not include virtual registers. 75f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool contains(unsigned Reg) const { 76f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->contains(Reg); 77f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 78f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 79f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// contains - Return true if both registers are in this class. 80f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool contains(unsigned Reg1, unsigned Reg2) const { 81f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->contains(Reg1, Reg2); 82f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 83f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 84f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getSize - Return the size of the register in bytes, which is also the size 85f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// of a stack slot allocated to hold a spilled copy of this register. 86f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getSize() const { return MC->getSize(); } 87f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 88f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getAlignment - Return the minimum required alignment for a register of 89f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// this class. 90f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getAlignment() const { return MC->getAlignment(); } 91f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 92f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getCopyCost - Return the cost of copying a value between two registers in 93f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// this class. A negative number means the register class is very expensive 94f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// to copy e.g. status flag register classes. 95f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer int getCopyCost() const { return MC->getCopyCost(); } 96f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 97f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// isAllocatable - Return true if this register class may be used to create 98f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// virtual registers. 99f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool isAllocatable() const { return MC->isAllocatable(); } 100f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 1016510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman /// hasType - return true if this TargetRegisterClass has the ValueType vt. 1026510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman /// 103e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson bool hasType(EVT vt) const { 104cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands for(int i = 0; VTs[i] != MVT::Other; ++i) 1052c6ae095b8a944c8355377498b9ad11bb94af2d5Benjamin Kramer if (EVT(VTs[i]) == vt) 1066510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return true; 1076510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return false; 1086510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman } 10995923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 110696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// vt_begin / vt_end - Loop over all of the value types that can be 111696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// represented by values in this register class. 11216d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_begin() const { 11316d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return VTs; 11416d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 11516d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner 11616d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_end() const { 11716d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator I = VTs; 118cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands while (*I != MVT::Other) ++I; 11916d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return I; 12016d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 121696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 122f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// superregclasses_begin / superregclasses_end - Loop over all of 123f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// the superreg register classes of this register class. 124f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator superregclasses_begin() const { 125f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return SuperRegClasses; 126f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 127f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 128f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator superregclasses_end() const { 129f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator I = SuperRegClasses; 130f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman while (*I != NULL) ++I; 131f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return I; 132f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 133f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 134f451cb870efcf9e0302d25ed05f4cac6bb494e42Dan Gohman /// hasSubClass - return true if the specified TargetRegisterClass 135c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// is a proper sub-class of this TargetRegisterClass. 136c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen bool hasSubClass(const TargetRegisterClass *RC) const { 137c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC != this && hasSubClassEq(RC); 138696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 139696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 140c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 1411f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// class. 1421f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSubClassEq(const TargetRegisterClass *RC) const { 143c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen unsigned ID = RC->getID(); 144c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 145696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 14695923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 1471367fd09cb021bae61e7dd2ee208f76574c8e789Christopher Lamb /// hasSuperClass - return true if the specified TargetRegisterClass is a 148c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// proper super-class of this TargetRegisterClass. 149c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen bool hasSuperClass(const TargetRegisterClass *RC) const { 150c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC->hasSubClass(this); 151c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 152c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng 153c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 1541f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// class. 1551f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSuperClassEq(const TargetRegisterClass *RC) const { 156c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC->hasSubClassEq(this); 1571f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen } 1581f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen 159c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// getSubClassMask - Returns a bit vector of subclasses, including this one. 160c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 161c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// use it. 1629ebfbf8b9fd5f982e0db9293808bd32168615ba9Craig Topper const uint32_t *getSubClassMask() const { 163c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return SubClassMask; 164c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 16595923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 166c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// getSuperClasses - Returns a NULL terminated list of super-classes. The 167c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// classes are ordered by ID which is also a topological ordering from large 168c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// to small classes. The list does NOT include the current class. 169c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen sc_iterator getSuperClasses() const { 170c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return SuperClasses; 171c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 1728c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng 173f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// isASubClass - return true if this TargetRegisterClass is a subset 174f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// class of at least one other TargetRegisterClass. 1758c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng bool isASubClass() const { 1768c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng return SuperClasses[0] != 0; 1778c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng } 17895923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 17979c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// getRawAllocationOrder - Returns the preferred order for allocating 18079c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// registers from this register class in MF. The raw order comes directly 18179c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// from the .td file and may include reserved registers that are not 18279c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// allocatable. Register allocators should also make sure to allocate 18379c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// callee-saved registers only after all the volatiles are used. The 18479c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// RegisterClassInfo class provides filtered allocation orders with 18579c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// callee-saved registers moved to the end. 18679c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 18779c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// The MachineFunction argument can be used to tune the allocatable 18879c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// registers based on the characteristics of the function, subtarget, or 18979c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// other criteria. 19079c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 19179c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// By default, this method returns all registers in the class. 19279c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 193b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper ArrayRef<uint16_t> getRawAllocationOrder(const MachineFunction &MF) const { 194ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 19579c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen } 196282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman}; 197282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 198a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 199a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// registers. These are used by codegen, not by MC. 200a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengstruct TargetRegisterInfoDesc { 201a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng unsigned CostPerUse; // Extra cost of instructions using register. 202a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng bool inAllocatableClass; // Register belongs to an allocatable regclass. 203a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng}; 204282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 205ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick/// Each TargetRegisterClass has a per register weight, and weight 206ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick/// limit which must be less than the limits of its pressure sets. 207ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trickstruct RegClassWeight { 20833d9e89e5f8d7656e50353b014d5bb1b52f15e13Andrew Trick unsigned RegWeight; 209ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick unsigned WeightLimit; 210ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick}; 211ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick 2126f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// TargetRegisterInfo base class - We assume that the target defines a static 2136f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// array of TargetRegisterDesc objects that represent all of the machine 2146f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// registers that the target has. As such, we simply have to track a pointer 2156f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// to this array so that we can turn register number into a register 2166f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// descriptor. 2173d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// 218a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengclass TargetRegisterInfo : public MCRegisterInfo { 2198797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerpublic: 2208797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner typedef const TargetRegisterClass * const * regclass_iterator; 2218797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerprivate: 222a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 2231fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *const *SubRegIndexNames; // Names of subreg indexes. 2248797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 225b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene 2263d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerprotected: 227a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 2286f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassBegin, 2296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassEnd, 230d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng const char *const *subregindexnames); 2316f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman virtual ~TargetRegisterInfo(); 2323d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerpublic: 2333d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 234b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Register numbers can represent physical registers, virtual registers, and 235b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // sometimes stack slots. The unsigned values are divided into these ranges: 236b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 237b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 0 Not a register, can be used as a sentinel. 238b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [1;2^30) Physical registers assigned by TableGen. 239b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^30;2^31) Stack slots. (Rarely used.) 240b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 241b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 242b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Further sentinels can be allocated from the small negative integers. 243b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // DenseMapInfo<unsigned> uses -1u and -2u. 2443d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 245be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// isStackSlot - Sometimes it is useful the be able to store a non-negative 246be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// frame index in a variable that normally holds a register. isStackSlot() 247be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// returns true if Reg is in the range used for stack slots. 248be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 249da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 250da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// slots, so if a variable may contains a stack slot, always check 251da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// isStackSlot() first. 252be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 253be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static bool isStackSlot(unsigned Reg) { 254da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) >= (1 << 30); 255be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 256be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 257be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// stackSlot2Index - Compute the frame index from a register value 258be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// representing a stack slot. 259be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static int stackSlot2Index(unsigned Reg) { 260be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(isStackSlot(Reg) && "Not a stack slot"); 261da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg - (1u << 30)); 262be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 263be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 264be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// index2StackSlot - Convert a non-negative frame index to a stack slot 265be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// register value. 266be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static unsigned index2StackSlot(int FI) { 267be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(FI >= 0 && "Cannot hold a negative frame index."); 268da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return FI + (1u << 30); 269be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 270be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 271bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// isPhysicalRegister - Return true if the specified register number is in 272bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the physical register namespace. 273bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isPhysicalRegister(unsigned Reg) { 274da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 275da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) > 0; 276bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 277bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 278bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// isVirtualRegister - Return true if the specified register number is in 279bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the virtual register namespace. 280bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isVirtualRegister(unsigned Reg) { 281da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 282da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) < 0; 283bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 284bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 285c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen /// virtReg2Index - Convert a virtual register number to a 0-based index. 286c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen /// The first virtual register in a function will get the index 0. 287c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen static unsigned virtReg2Index(unsigned Reg) { 288da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(isVirtualRegister(Reg) && "Not a virtual register"); 289dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Reg & ~(1u << 31); 290c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen } 291c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen 292b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// index2VirtReg - Convert a 0-based index to a virtual register number. 293b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// This is the inverse operation of VirtReg2IndexFunctor below. 294b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen static unsigned index2VirtReg(unsigned Index) { 295dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Index | (1u << 31); 296b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen } 297b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 298ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola /// getMinimalPhysRegClass - Returns the Register Class of a physical 299c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman /// register of the given type, picking the most sub register class of 300c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman /// the right type that contains this physreg. 301d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola const TargetRegisterClass * 302d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 303ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 304f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick /// getAllocatableClass - Return the maximal subclass of the given register 305f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick /// class that is alloctable, or NULL. 306f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick const TargetRegisterClass * 307f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick getAllocatableClass(const TargetRegisterClass *RC) const; 308f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick 309bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos /// getAllocatableSet - Returns a bitset indexed by register number 310eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng /// indicating if a register is allocatable or not. If a register class is 311eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng /// specified, returns the subset for the class. 312769b7f89534caed11d7595b5c84aa47d3de30ad9Dan Gohman BitVector getAllocatableSet(const MachineFunction &MF, 313eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng const TargetRegisterClass *RC = NULL) const; 314bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos 3156bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen /// getCostPerUse - Return the additional cost of using this register instead 3166bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen /// of other registers in its class. 3176bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen unsigned getCostPerUse(unsigned RegNo) const { 318a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return InfoDesc[RegNo].CostPerUse; 3196bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen } 3206bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen 321a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// isInAllocatableClass - Return true if the register is in the allocation 322a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// of any register class. 323a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng bool isInAllocatableClass(unsigned RegNo) const { 324a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return InfoDesc[RegNo].inAllocatableClass; 32593aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos } 32693aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos 3271fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen /// getSubRegIndexName - Return the human-readable symbolic target-specific 3281fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen /// name for the specified SubRegIndex. 3291fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *getSubRegIndexName(unsigned SubIdx) const { 3301fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen assert(SubIdx && "This is not a subregister index"); 3311fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen return SubRegIndexNames[SubIdx-1]; 3321fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen } 3331fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen 3343f2f3f5341374c85955cfaffa71886724999762dLang Hames /// regsOverlap - Returns true if the two registers are equal or alias each 3353f2f3f5341374c85955cfaffa71886724999762dLang Hames /// other. The registers may be virtual register. 3363f2f3f5341374c85955cfaffa71886724999762dLang Hames bool regsOverlap(unsigned regA, unsigned regB) const { 3371e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (regA == regB) return true; 3383f2f3f5341374c85955cfaffa71886724999762dLang Hames if (isVirtualRegister(regA) || isVirtualRegister(regB)) 3393f2f3f5341374c85955cfaffa71886724999762dLang Hames return false; 340e4fd907e72a599eddfa7a81eac4366b5b82523e3Craig Topper for (const uint16_t *regList = getOverlaps(regA)+1; *regList; ++regList) { 3411e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (*regList == regB) return true; 3423ca15c989ca0e09085648771db368d8c94ee1f19Owen Anderson } 34304319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos return false; 34404319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos } 34504319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos 346b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// isSubRegister - Returns true if regB is a sub-register of regA. 347b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// 348b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng bool isSubRegister(unsigned regA, unsigned regB) const { 3491e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson return isSuperRegister(regB, regA); 350b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng } 351b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng 352b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// isSuperRegister - Returns true if regB is a super-register of regA. 353b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// 354b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng bool isSuperRegister(unsigned regA, unsigned regB) const { 3559ebfbf8b9fd5f982e0db9293808bd32168615ba9Craig Topper for (const uint16_t *regList = getSuperRegisters(regA); *regList;++regList){ 3561e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (*regList == regB) return true; 3571e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson } 3581e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson return false; 359b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng } 360b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng 3610098b3e2b69e527ddcf2ebad7a3081898fa3b4f0Evan Cheng /// getCalleeSavedRegs - Return a null-terminated list of all of the 3620098b3e2b69e527ddcf2ebad7a3081898fa3b4f0Evan Cheng /// callee saved registers on this target. The register should be in the 36302569d7355b03155b32c1c0d0e46f6aa957f4802Evan Cheng /// order of desired callee-save stack frame offset. The first register is 364bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// closest to the incoming stack pointer if stack grows down, and vice versa. 365bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 366015f228861ef9b337366f92f637d4e8d624bb006Craig Topper virtual const uint16_t* getCalleeSavedRegs(const MachineFunction *MF = 0) 3672365f51ed03afe6993bae962fdc2e5a956a64cd5Anton Korobeynikov const = 0; 3688797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 369bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// getCallPreservedMask - Return a mask of call-preserved registers for the 370bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// given calling convention on the current sub-target. The mask should 371bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// include all call-preserved aliases. This is used by the register 372bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// allocator to determine which registers can be live across a call. 373bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 374bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 375bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// A set bit indicates that all bits of the corresponding register are 376bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// preserved across the function call. The bit mask is expected to be 377bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// sub-register complete, i.e. if A is preserved, so are all its 378bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// sub-registers. 379bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 380bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// Bits are numbered from the LSB, so the bit for physical register Reg can 381bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 382478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// 383478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// A NULL pointer means that no register mask will be used, and call 384478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// instructions should use implicit-def operands to indicate call clobbered 385478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// registers. 386bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 387bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { 388bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen // The default mask clobbers everything. All targets should override. 389bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen return 0; 390bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen } 3918797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 392b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng /// getReservedRegs - Returns a bitset indexed by physical register number 3931c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// indicating if a register is a special register that has particular uses 3941c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// and should be considered unavailable at all times, e.g. SP, RA. This is 3951c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// used by register scavenger to determine what registers are free. 396b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 397b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 3988a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng /// getMatchingSuperReg - Return a super-register of the specified register 3998a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng /// Reg so its sub-register of index SubIdx is Reg. 40095923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 4018a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng const TargetRegisterClass *RC) const { 40233ca87affb81b60c4d50214eb7458bd26d397d53Jim Grosbach return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 4038a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng } 4048a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng 40591a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// canCombineSubRegIndices - Given a register class and a list of 40691a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// subregister indices, return true if it's possible to combine the 40791a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// subregister indices into one that corresponds to a larger 40891a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// subregister. Return the new subregister index by reference. Note the 40991a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// new index may be zero if the given subregisters can be combined to 41091a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// form the whole register. 41191a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 41291a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson SmallVectorImpl<unsigned> &SubIndices, 41391a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson unsigned &NewSubIdx) const { 414b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return 0; 415b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 416b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 4175248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// getMatchingSuperRegClass - Return a subclass of the specified register 4185248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// class A so that each register in it has a sub-register of the 4195248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// specified sub-register index which is in the specified register class B. 420570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// 421570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// TableGen will synthesize missing A sub-classes. 4225248468473f0488a652b545ad95f7abda302b7b5Evan Cheng virtual const TargetRegisterClass * 4235248468473f0488a652b545ad95f7abda302b7b5Evan Cheng getMatchingSuperRegClass(const TargetRegisterClass *A, 424309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen const TargetRegisterClass *B, unsigned Idx) const { 425309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen llvm_unreachable("Target has no sub-registers"); 426309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen } 4275248468473f0488a652b545ad95f7abda302b7b5Evan Cheng 428845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 429845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// supports the sub-register index Idx. 430845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// If no such sub-class exists, return NULL. 431845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// If all registers in RC already have an Idx sub-register, return RC. 432845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// 433845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// TableGen generates a version of this function that is good enough in most 434845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// cases. Targets can override if they have constraints that TableGen 435845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// doesn't understand. For example, the x86 sub_8bit sub-register index is 436845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// supported by the full GR32 register class in 64-bit mode, but only by the 437845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// GR32_ABCD regiister class in 32-bit mode. 438845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// 439570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// TableGen will synthesize missing RC sub-classes. 440845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen virtual const TargetRegisterClass * 441309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 442309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen assert(Idx == 0 && "Target has no sub-registers"); 443309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen return RC; 444309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen } 445845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen 4462da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// composeSubRegIndices - Return the subregister index you get from composing 4472da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// two subregister indices. 4482da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 4492da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 4502da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// returns c. Note that composeSubRegIndices does not tell you about illegal 4512da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// compositions. If R does not have a subreg a, or R:a does not have a subreg 4522da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// b, composeSubRegIndices doesn't tell you. 4532da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 4542da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 4552da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// ssub_0:S0 - ssub_3:S3 subregs. 4562da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 4572da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 4582da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 4592da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen // This default implementation is correct for most targets. 4602da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen return b; 4612da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen } 4622da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen 4638797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner //===--------------------------------------------------------------------===// 4648797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // Register Class Information 4658797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // 4668797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 4678797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner /// Register class iterators 46892988ecdb6ca641ba39d1d1f8cbc57a89b63bbadChris Lattner /// 4698797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_begin() const { return RegClassBegin; } 4708797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_end() const { return RegClassEnd; } 4718797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 4728797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner unsigned getNumRegClasses() const { 47334cd4a484e532cc463fd5a4bf59b88d13c5467c1Evan Cheng return (unsigned)(regclass_end()-regclass_begin()); 4748797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner } 47595923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 47660f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// getRegClass - Returns the register class associated with the enumeration 477e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// value. See class MCOperandInfo. 47860f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey const TargetRegisterClass *getRegClass(unsigned i) const { 479a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman assert(i < getNumRegClasses() && "Register Class ID out of range"); 480a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman return RegClassBegin[i]; 48160f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey } 4828797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 483e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen /// getCommonSubClass - find the largest common subclass of A and B. Return 484e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen /// NULL if there is no common subclass. 485e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass * 486e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen getCommonSubClass(const TargetRegisterClass *A, 487e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass *B) const; 488e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen 489770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 4902cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner /// values. If a target supports multiple different pointer register classes, 4912cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner /// kind specifies which one is indicated. 4922cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 49350bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Target didn't implement getPointerRegClass!"); 494770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng } 4958797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 496ff110265753c19daf0468ee1facf357460497b7eEvan Cheng /// getCrossCopyRegClass - Returns a legal register class to copy a register 497b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// in the specified class to or from. If it is possible to copy the register 498b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// directly without using a cross register class copy, return the specified 499b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// RC. Returns NULL if it is not possible to copy between a two registers of 500b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// the specified class. 501ff110265753c19daf0468ee1facf357460497b7eEvan Cheng virtual const TargetRegisterClass * 502ff110265753c19daf0468ee1facf357460497b7eEvan Cheng getCrossCopyRegClass(const TargetRegisterClass *RC) const { 503b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng return RC; 504ff110265753c19daf0468ee1facf357460497b7eEvan Cheng } 505ff110265753c19daf0468ee1facf357460497b7eEvan Cheng 506c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// getLargestLegalSuperClass - Returns the largest super class of RC that is 507c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// legal to use in the current sub-target and has the same spill size. 508c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The returned register class can be used to create virtual registers which 509c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// means that all its registers can be copied and spilled. 510c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen virtual const TargetRegisterClass* 511c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 512c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The default implementation is very conservative and doesn't allow the 513c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// register allocator to inflate register classes. 514c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return RC; 515c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } 516c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen 517be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// getRegPressureLimit - Return the register pressure "high water mark" for 518be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// the specific register class. The scheduler is in high register pressure 519be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// mode (for the specific register class) if it goes over the limit. 520decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// 521decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Note: this is the old register pressure model that relies on a manually 522decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// specified representative register class per value type. 523be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 524be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich MachineFunction &MF) const { 525be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 0; 526be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 527be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 528d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick// Get the weight in units of pressure for this register class. 529ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick virtual const RegClassWeight &getRegClassWeight( 530ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick const TargetRegisterClass *RC) const = 0; 531decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 532decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the number of dimensions of register pressure. 533decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual unsigned getNumRegPressureSets() const = 0; 534decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 535d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick /// Get the name of this register unit pressure set. 536d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick virtual const char *getRegPressureSetName(unsigned Idx) const = 0; 537d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick 538decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the register unit pressure limit for this dimension. 539decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// This limit must be adjusted dynamically for reserved registers. 540decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0; 541decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 542decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the dimensions of register pressure impacted by this register class. 543decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Returns a -1 terminated array of pressure set IDs. 544decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual const int *getRegClassPressureSets( 545decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick const TargetRegisterClass *RC) const = 0; 546decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 547dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// getRawAllocationOrder - Returns the register allocation order for a 548dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// specified register class with a target-dependent hint. The returned list 549dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// may contain reserved registers that cannot be allocated. 550dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// 551dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// Register allocators need only call this function to resolve 552dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// target-dependent hints, but it should work without hinting as well. 553b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper virtual ArrayRef<uint16_t> 554dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen getRawAllocationOrder(const TargetRegisterClass *RC, 555dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen unsigned HintType, unsigned HintReg, 556dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen const MachineFunction &MF) const { 557dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen return RC->getRawAllocationOrder(MF); 558358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng } 559358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng 560358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// ResolveRegAllocHint - Resolves the specified register allocation hint 561358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// to a physical register. Returns the physical register if it is successful. 562f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 563f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng const MachineFunction &MF) const { 564358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng if (Type == 0 && Reg && isPhysicalRegister(Reg)) 565358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng return Reg; 566358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng return 0; 567358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng } 568358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng 569f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// avoidWriteAfterWrite - Return true if the register allocator should avoid 570f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// writing a register from RC in two consecutive instructions. 571f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// This can avoid pipeline stalls on certain architectures. 572f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// It does cause increased register pressure, though. 573f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 574f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return false; 575f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson } 576f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 577f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// UpdateRegAllocHint - A callback to allow target a chance to update 578f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// register allocation hints when a register is "changed" (e.g. coalesced) 579f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// to another register. e.g. On ARM, some virtual registers should target 580f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// register pairs, if one of pair is coalesced to another register, the 581f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// allocation hint of the other half of the pair should be changed to point 582f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// to the new register. 583f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 584f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng MachineFunction &MF) const { 585f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng // Do nothing. 586f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng } 587f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng 5881c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// requiresRegisterScavenging - returns true if the target requires (and can 5891c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// make use of) the register scavenger. 59036230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 59137f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng return false; 59237f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng } 59395923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 5940f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// useFPForScavengingIndex - returns true if the target wants to use 5950f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// frame pointer based accesses to spill to the scavenger emergency spill 5960f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// slot. 5970f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 5980f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach return true; 5990f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach } 6000f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach 60165c58daa8b8985d2116216043103009815a55e77Jim Grosbach /// requiresFrameIndexScavenging - returns true if the target requires post 60265c58daa8b8985d2116216043103009815a55e77Jim Grosbach /// PEI scavenging of registers for materializing frame index constants. 60365c58daa8b8985d2116216043103009815a55e77Jim Grosbach virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 60465c58daa8b8985d2116216043103009815a55e77Jim Grosbach return false; 60565c58daa8b8985d2116216043103009815a55e77Jim Grosbach } 60665c58daa8b8985d2116216043103009815a55e77Jim Grosbach 607a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// requiresVirtualBaseRegisters - Returns true if the target wants the 608a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// LocalStackAllocation pass to be run and virtual base registers 609a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// used for more efficient stack access. 610a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 611a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach return false; 612a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach } 613a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 614910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 615910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// the stack frame of the given function for the specified register. e.g. On 616910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// x86, if the frame register is required, the first fixed stack object is 617910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// reserved as its spill slot. This tells PEI not to create a new stack frame 618910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// object for the given register. It should be called only after 619910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// processFunctionBeforeCalleeSavedScan(). 62072852a8cfb605056d87b644d2e36b1346051413dEric Christopher virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 621910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng int &FrameIdx) const { 622910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng return false; 623910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng } 624910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng 6256a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd /// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked 6266a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd /// after register allocation. 6276a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 6286a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd return false; 6296a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd } 6306a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 631910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// needsStackRealignment - true if storage within the function requires the 632910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// stack pointer to be aligned more than the normal calling convention calls 633910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// for. 634b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen virtual bool needsStackRealignment(const MachineFunction &MF) const { 635b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen return false; 636b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen } 637b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen 638e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// getFrameIndexInstrOffset - Get the offset from the referenced frame 63963f8659d6936077c5e8e34eecb55ff1de0db5686Bob Wilson /// index in the instruction, if there is one. 6401ab3f16f06698596716593a30545799688acccd7Jim Grosbach virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 6411ab3f16f06698596716593a30545799688acccd7Jim Grosbach int Idx) const { 642e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return 0; 643e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 644e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 6458708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// needsFrameBaseReg - Returns true if the instruction's frame index 6468708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// reference would be better served by a base register other than FP 6478708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// or SP. Used by LocalStackFrameAllocation to determine which frame index 6488708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// references it should create new base registers for. 6493197380143cdc18837722129ac888528b9fbfc2bJim Grosbach virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 6508708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 6518708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 6528708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 653dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// materializeFrameBaseRegister - Insert defining instruction(s) for 654dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// BaseReg to be a pointer to FrameIdx before insertion point I. 655976ef86689ed065361a748f81c44ca3510af2202Bill Wendling virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 656e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned BaseReg, int FrameIdx, 657e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 65850bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("materializeFrameBaseRegister does not exist on this " 65950bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper "target"); 660dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 661dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 662dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// resolveFrameIndex - Resolve a frame index operand of an instruction 663dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// to reference the indicated base register plus offset instead. 664dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 665dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned BaseReg, int64_t Offset) const { 66650bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("resolveFrameIndex does not exist on this target"); 667dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 668dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 669e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// isFrameOffsetLegal - Determine whether a given offset immediate is 670e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// encodable to resolve a frame index. 671e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach virtual bool isFrameOffsetLegal(const MachineInstr *MI, 672e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 67350bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 67474d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach } 675dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 676f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 677f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// code insertion to eliminate call frame setup and destroy pseudo 678f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// instructions (but only if the Target is using them). It is responsible 679f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// for eliminating these instructions, replacing them with concrete 680f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// instructions. This method need only be implemented if using call frame 6818a1478b6d7aeaed8363316d2e0b90d9f53525c29Chris Lattner /// setup/destroy pseudo instructions. 682f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// 68334695381d626485a560594f162701088079589dfMisha Brukman virtual void 6848604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner eliminateCallFramePseudoInstr(MachineFunction &MF, 6858604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner MachineBasicBlock &MBB, 6868604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner MachineBasicBlock::iterator MI) const { 68750bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Call Frame Pseudo Instructions do not exist on this " 68850bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper "target!"); 689f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner } 690f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 691f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 692d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// saveScavengerRegister - Spill the register so it can be used by the 693d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// register scavenger. Return true if the register was spilled, false 694d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// otherwise. If this function does not spill the register, the scavenger 695540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// will instead spill it to the emergency spill slot. 696540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// 697540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 698540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach MachineBasicBlock::iterator I, 699d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach MachineBasicBlock::iterator &UseMI, 700540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach const TargetRegisterClass *RC, 7011f8f4d2db734d9881467a5706acac73660842d43Evan Cheng unsigned Reg) const { 7021f8f4d2db734d9881467a5706acac73660842d43Evan Cheng return false; 7031f8f4d2db734d9881467a5706acac73660842d43Evan Cheng } 704540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach 705f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminateFrameIndex - This method must be overriden to eliminate abstract 706f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// frame indices from instructions which may use them. The instruction 707f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// referenced by the iterator contains an MO_FrameIndex operand which must be 708f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminated by this method. This method may modify or replace the 709c49a10aca1e31351c2e11b25ba636a23b93c46c8Dale Johannesen /// specified instruction, as long as it keeps the iterator pointing at the 71018b111bffe643b5ad52ae10a1d5728b0c1ac92f0Evan Cheng /// finished product. SPAdj is the SP adjustment due to call frame setup 7111ad70c09c890c3abcc147503f2e23082f683790cMatthijs Kooijman /// instruction. 712fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 713fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach int SPAdj, RegScavenger *RS=NULL) const = 0; 714f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 715a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey //===--------------------------------------------------------------------===// 716a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// Debug information queries. 71795923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 718a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// getFrameRegister - This method should return the register used as a base 7194188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey /// for values allocated in the current stack frame. 720b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 72172bebb9205c1628601b052d25555aabe6e15e6f4Evan Cheng 7225cd2791513919ee7504c309151321e4e37a05a58Bill Wendling /// getCompactUnwindRegNum - This function maps the register to the number for 7235cd2791513919ee7504c309151321e4e37a05a58Bill Wendling /// compact unwind encoding. Return -1 if the register isn't valid. 724486dd90696545421c55346570b88fa03f6dd464fBill Wendling virtual int getCompactUnwindRegNum(unsigned, bool) const { 7255cd2791513919ee7504c309151321e4e37a05a58Bill Wendling return -1; 7265cd2791513919ee7504c309151321e4e37a05a58Bill Wendling } 7273d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner}; 7283d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 729c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng 73094c002a190cd2e3a52b1510bc997e53d63af0b3bChris Lattner// This is useful when building IndexedMaps keyed on virtual registers 73159bf4fcc0680e75b408579064d1205a132361196Duncan Sandsstruct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 7324d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos unsigned operator()(unsigned Reg) const { 733c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen return TargetRegisterInfo::virtReg2Index(Reg); 7344d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos } 7354d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos}; 7364d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos 7374314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// PrintReg - Helper class for printing registers on a raw_ostream. 7384314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Prints virtual and physical registers with or without a TRI instance. 7394314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 7404314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// The format is: 74143a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %noreg - NoRegister 74243a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5 - a virtual register. 74343a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 74443a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %EAX - a physical register 74543a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %physreg17 - a physical register when no TRI instance given. 7464314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 7474314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 7484314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 7494314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenclass PrintReg { 7504314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen const TargetRegisterInfo *TRI; 7514314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen unsigned Reg; 7524314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen unsigned SubIdx; 7534314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenpublic: 7544314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 7554314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen : TRI(tri), Reg(reg), SubIdx(subidx) {} 7564314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen void print(raw_ostream&) const; 7574314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen}; 7584314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen 7594314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenstatic inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 7604314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen PR.print(OS); 7614314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen return OS; 7624314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen} 7634314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen 764d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 765d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 7663d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner#endif 767