TargetRegisterInfo.h revision dd63a063e2df0d0bc52b50732e3462fd58a636c0
16f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 93d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 103d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// This file describes an abstract interface used to get information about a 113d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// target machines register file. This information is used for a variety of 123d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// purposed, especially register allocation. 133d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner// 143d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner//===----------------------------------------------------------------------===// 153d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 166f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#define LLVM_TARGET_TARGETREGISTERINFO_H 183d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 19a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include "llvm/MC/MCRegisterInfo.h" 20024126ee23e6e4430a77025b61d0e713180f03d3Alkis Evlogimenos#include "llvm/CodeGen/MachineBasicBlock.h" 21a385bf7b6dc9b71024aa4c7bb7026bab3c7ebe91Chris Lattner#include "llvm/CodeGen/ValueTypes.h" 2279c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen#include "llvm/ADT/ArrayRef.h" 23bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen#include "llvm/CallingConv.h" 244d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <cassert> 254d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos#include <functional> 263d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 27d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 28d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 29171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass BitVector; 30198ab640bbb0b8e1cdda518b7f8b348764e4402cChris Lattnerclass MachineFunction; 31171eed533408a23de0b141af17475fd6b4da72e0Evan Chengclass RegScavenger; 32b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Chengtemplate<class T> class SmallVectorImpl; 33414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesenclass raw_ostream; 34282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 35f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramerclass TargetRegisterClass { 36282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukmanpublic: 37b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper typedef const uint16_t* iterator; 38b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper typedef const uint16_t* const_iterator; 392c6ae095b8a944c8355377498b9ad11bb94af2d5Benjamin Kramer typedef const MVT::SimpleValueType* vt_iterator; 403b0c0148ed9ec752b240dbea767ad4a9f0a682caEvan Cheng typedef const TargetRegisterClass* const * sc_iterator; 41ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer 42ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer // Instance variables filled by tablegen, do not use! 43f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer const MCRegisterClass *MC; 4416d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner const vt_iterator VTs; 451d61f283fad2e49d3e50a3585aac4cc9183a0d28Jakob Stoklund Olesen const uint32_t *SubClassMask; 461a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen const uint16_t *SuperRegIndices; 47c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng const sc_iterator SuperClasses; 48f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman const sc_iterator SuperRegClasses; 49b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper ArrayRef<uint16_t> (*OrderFunc)(const MachineFunction&); 50320bdcbfe2691021702085f718db1617b1d4df49Jakob Stoklund Olesen 51f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getID() - Return the register class ID number. 52f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 53f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getID() const { return MC->getID(); } 54f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 55f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getName() - Return the register class name for debugging. 56f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 57f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer const char *getName() const { return MC->getName(); } 58f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 59f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// begin/end - Return all of the registers in this class. 60f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 61f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer iterator begin() const { return MC->begin(); } 62f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer iterator end() const { return MC->end(); } 63f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 64f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getNumRegs - Return the number of registers in this class. 65f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 66f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getNumRegs() const { return MC->getNumRegs(); } 67f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 68f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getRegister - Return the specified register in the class. 69f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// 70f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getRegister(unsigned i) const { 71f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->getRegister(i); 72f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 73f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 74f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// contains - Return true if the specified register is included in this 75f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// register class. This does not include virtual registers. 76f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool contains(unsigned Reg) const { 77f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->contains(Reg); 78f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 79f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 80f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// contains - Return true if both registers are in this class. 81f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool contains(unsigned Reg1, unsigned Reg2) const { 82f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer return MC->contains(Reg1, Reg2); 83f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer } 84f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 85f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getSize - Return the size of the register in bytes, which is also the size 86f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// of a stack slot allocated to hold a spilled copy of this register. 87f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getSize() const { return MC->getSize(); } 88f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 89f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getAlignment - Return the minimum required alignment for a register of 90f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// this class. 91f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer unsigned getAlignment() const { return MC->getAlignment(); } 92f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 93f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// getCopyCost - Return the cost of copying a value between two registers in 94f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// this class. A negative number means the register class is very expensive 95f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// to copy e.g. status flag register classes. 96f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer int getCopyCost() const { return MC->getCopyCost(); } 97f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 98f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// isAllocatable - Return true if this register class may be used to create 99f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer /// virtual registers. 100f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer bool isAllocatable() const { return MC->isAllocatable(); } 101f496d68493acf8d178afbbe8c3146ea09bd7776bBenjamin Kramer 1026510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman /// hasType - return true if this TargetRegisterClass has the ValueType vt. 1036510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman /// 104e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson bool hasType(EVT vt) const { 105cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands for(int i = 0; VTs[i] != MVT::Other; ++i) 1062c6ae095b8a944c8355377498b9ad11bb94af2d5Benjamin Kramer if (EVT(VTs[i]) == vt) 1076510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return true; 1086510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman return false; 1096510b22cec7de4f0acc9965ec24c3668a6a8a87eNate Begeman } 11095923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 111696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// vt_begin / vt_end - Loop over all of the value types that can be 112696736be8b80fe3946f73605b46359345afdf57aEvan Cheng /// represented by values in this register class. 11316d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_begin() const { 11416d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return VTs; 11516d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 11616d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner 11716d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator vt_end() const { 11816d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner vt_iterator I = VTs; 119cdfad36b401be6fc709ea4051f9de58e1a30bcc9Duncan Sands while (*I != MVT::Other) ++I; 12016d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner return I; 12116d597a20d405d8cb13f89f15b8c1fed20428808Chris Lattner } 122696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 123f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// superregclasses_begin / superregclasses_end - Loop over all of 124f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// the superreg register classes of this register class. 125f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator superregclasses_begin() const { 126f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return SuperRegClasses; 127f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 128f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 129f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator superregclasses_end() const { 130f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman sc_iterator I = SuperRegClasses; 131f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman while (*I != NULL) ++I; 132f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman return I; 133f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman } 134f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman 135f451cb870efcf9e0302d25ed05f4cac6bb494e42Dan Gohman /// hasSubClass - return true if the specified TargetRegisterClass 136c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// is a proper sub-class of this TargetRegisterClass. 137c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen bool hasSubClass(const TargetRegisterClass *RC) const { 138c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC != this && hasSubClassEq(RC); 139696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 140696736be8b80fe3946f73605b46359345afdf57aEvan Cheng 141c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 1421f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// class. 1431f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSubClassEq(const TargetRegisterClass *RC) const { 144c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen unsigned ID = RC->getID(); 145c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 146696736be8b80fe3946f73605b46359345afdf57aEvan Cheng } 14795923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 1481367fd09cb021bae61e7dd2ee208f76574c8e789Christopher Lamb /// hasSuperClass - return true if the specified TargetRegisterClass is a 149c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// proper super-class of this TargetRegisterClass. 150c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen bool hasSuperClass(const TargetRegisterClass *RC) const { 151c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC->hasSubClass(this); 152c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 153c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng 154c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 1551f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen /// class. 1561f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen bool hasSuperClassEq(const TargetRegisterClass *RC) const { 157c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return RC->hasSubClassEq(this); 1581f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen } 1591f9a09c61489a83360238032b6756395bd69b620Jakob Stoklund Olesen 160c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// getSubClassMask - Returns a bit vector of subclasses, including this one. 161c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 162c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// use it. 1639ebfbf8b9fd5f982e0db9293808bd32168615ba9Craig Topper const uint32_t *getSubClassMask() const { 164c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return SubClassMask; 165c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 16695923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 1671a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// getSuperRegIndices - Returns a 0-terminated list of sub-register indices 1681a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// that projec some super-register class into this register class. The list 1691a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// has an entry for each Idx such that: 1701a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// 1711a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// There exists SuperRC where: 1721a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// For all Reg in SuperRC: 1731a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// this->contains(Reg:Idx) 1741a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen /// 1751a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen const uint16_t *getSuperRegIndices() const { 1761a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen return SuperRegIndices; 1771a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen } 1781a2a19dd3ce2b163837b5f0a1ea474c72527cad6Jakob Stoklund Olesen 179c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// getSuperClasses - Returns a NULL terminated list of super-classes. The 180c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// classes are ordered by ID which is also a topological ordering from large 181c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen /// to small classes. The list does NOT include the current class. 182c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen sc_iterator getSuperClasses() const { 183c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen return SuperClasses; 184c3580cace271b0f7d35a25eb285a1cc0d644c30cEvan Cheng } 1858c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng 186f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// isASubClass - return true if this TargetRegisterClass is a subset 187f8c7394781f7cf27ac52ca087e289436d36844daDan Gohman /// class of at least one other TargetRegisterClass. 1888c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng bool isASubClass() const { 1898c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng return SuperClasses[0] != 0; 1908c08d8c77c45d4721e7d3ef746cca9e39b28e379Evan Cheng } 19195923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 19279c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// getRawAllocationOrder - Returns the preferred order for allocating 19379c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// registers from this register class in MF. The raw order comes directly 19479c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// from the .td file and may include reserved registers that are not 19579c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// allocatable. Register allocators should also make sure to allocate 19679c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// callee-saved registers only after all the volatiles are used. The 19779c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// RegisterClassInfo class provides filtered allocation orders with 19879c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// callee-saved registers moved to the end. 19979c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 20079c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// The MachineFunction argument can be used to tune the allocatable 20179c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// registers based on the characteristics of the function, subtarget, or 20279c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// other criteria. 20379c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 20479c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// By default, this method returns all registers in the class. 20579c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen /// 206b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper ArrayRef<uint16_t> getRawAllocationOrder(const MachineFunction &MF) const { 207ccc8d3ba06408feff0ca6e58973c20d15010e3fcBenjamin Kramer return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 20879c890f64f3b67f9b11341aa452c4302b75184aaJakob Stoklund Olesen } 209282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman}; 210282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 211a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 212a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// registers. These are used by codegen, not by MC. 213a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengstruct TargetRegisterInfoDesc { 214a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng unsigned CostPerUse; // Extra cost of instructions using register. 215a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng bool inAllocatableClass; // Register belongs to an allocatable regclass. 216a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng}; 217282ec57c4cdd4574103922487b6f1563b5034fb4Misha Brukman 218ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick/// Each TargetRegisterClass has a per register weight, and weight 219ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick/// limit which must be less than the limits of its pressure sets. 220ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trickstruct RegClassWeight { 22133d9e89e5f8d7656e50353b014d5bb1b52f15e13Andrew Trick unsigned RegWeight; 222ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick unsigned WeightLimit; 223ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick}; 224ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick 2256f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// TargetRegisterInfo base class - We assume that the target defines a static 2266f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// array of TargetRegisterDesc objects that represent all of the machine 2276f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// registers that the target has. As such, we simply have to track a pointer 2286f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// to this array so that we can turn register number into a register 2296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman/// descriptor. 2303d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner/// 231a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengclass TargetRegisterInfo : public MCRegisterInfo { 2328797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerpublic: 2338797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner typedef const TargetRegisterClass * const * regclass_iterator; 2348797caac84c3012416e933c9c05ad34d75bf4029Chris Lattnerprivate: 235a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 2361fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *const *SubRegIndexNames; // Names of subreg indexes. 2378797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 238b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene 2393d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerprotected: 240a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 2416f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassBegin, 2426f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman regclass_iterator RegClassEnd, 243d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng const char *const *subregindexnames); 2446f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman virtual ~TargetRegisterInfo(); 2453d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattnerpublic: 2463d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 247b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Register numbers can represent physical registers, virtual registers, and 248b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // sometimes stack slots. The unsigned values are divided into these ranges: 249b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 250b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 0 Not a register, can be used as a sentinel. 251b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [1;2^30) Physical registers assigned by TableGen. 252b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^30;2^31) Stack slots. (Rarely used.) 253b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 254b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // 255b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // Further sentinels can be allocated from the small negative integers. 256b79cb79a46fd4d870897f5e2fd0c50beb96dc30aJakob Stoklund Olesen // DenseMapInfo<unsigned> uses -1u and -2u. 2573d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 258be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// isStackSlot - Sometimes it is useful the be able to store a non-negative 259be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// frame index in a variable that normally holds a register. isStackSlot() 260be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// returns true if Reg is in the range used for stack slots. 261be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 262da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 263da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// slots, so if a variable may contains a stack slot, always check 264da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen /// isStackSlot() first. 265be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// 266be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static bool isStackSlot(unsigned Reg) { 267da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) >= (1 << 30); 268be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 269be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 270be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// stackSlot2Index - Compute the frame index from a register value 271be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// representing a stack slot. 272be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static int stackSlot2Index(unsigned Reg) { 273be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(isStackSlot(Reg) && "Not a stack slot"); 274da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg - (1u << 30)); 275be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 276be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 277be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// index2StackSlot - Convert a non-negative frame index to a stack slot 278be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen /// register value. 279be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen static unsigned index2StackSlot(int FI) { 280be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen assert(FI >= 0 && "Cannot hold a negative frame index."); 281da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return FI + (1u << 30); 282be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen } 283be97e906e03dd9b22e14f6749157c9d5f9701dd5Jakob Stoklund Olesen 284bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// isPhysicalRegister - Return true if the specified register number is in 285bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the physical register namespace. 286bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isPhysicalRegister(unsigned Reg) { 287da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 288da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) > 0; 289bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 290bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 291bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// isVirtualRegister - Return true if the specified register number is in 292bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner /// the virtual register namespace. 293bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner static bool isVirtualRegister(unsigned Reg) { 294da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 295da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen return int(Reg) < 0; 296bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner } 297bd490d919bd36d2ab956031b524a55dd8519eb64Chris Lattner 298c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen /// virtReg2Index - Convert a virtual register number to a 0-based index. 299c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen /// The first virtual register in a function will get the index 0. 300c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen static unsigned virtReg2Index(unsigned Reg) { 301da1f1f495066f95957fd1c19ad44d4453e47aff4Jakob Stoklund Olesen assert(isVirtualRegister(Reg) && "Not a virtual register"); 302dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Reg & ~(1u << 31); 303c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen } 304c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen 305b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// index2VirtReg - Convert a 0-based index to a virtual register number. 306b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// This is the inverse operation of VirtReg2IndexFunctor below. 307b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen static unsigned index2VirtReg(unsigned Index) { 308dfa178bc2a21667aab745ba9a182cd3e702fec3bJakob Stoklund Olesen return Index | (1u << 31); 309b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen } 310b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 311ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola /// getMinimalPhysRegClass - Returns the Register Class of a physical 312c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman /// register of the given type, picking the most sub register class of 313c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman /// the right type that contains this physreg. 314d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola const TargetRegisterClass * 315d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 316ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 317f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick /// getAllocatableClass - Return the maximal subclass of the given register 318f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick /// class that is alloctable, or NULL. 319f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick const TargetRegisterClass * 320f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick getAllocatableClass(const TargetRegisterClass *RC) const; 321f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick 322bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos /// getAllocatableSet - Returns a bitset indexed by register number 323eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng /// indicating if a register is allocatable or not. If a register class is 324eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng /// specified, returns the subset for the class. 325769b7f89534caed11d7595b5c84aa47d3de30ad9Dan Gohman BitVector getAllocatableSet(const MachineFunction &MF, 326eff03db46d5d1df315cf2aa020ccd7f50ab3848eEvan Cheng const TargetRegisterClass *RC = NULL) const; 327bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos 3286bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen /// getCostPerUse - Return the additional cost of using this register instead 3296bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen /// of other registers in its class. 3306bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen unsigned getCostPerUse(unsigned RegNo) const { 331a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return InfoDesc[RegNo].CostPerUse; 3326bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen } 3336bfba2e5af163442a1c6b11fe14aa9df9101cfd7Jakob Stoklund Olesen 334a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// isInAllocatableClass - Return true if the register is in the allocation 335a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// of any register class. 336a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng bool isInAllocatableClass(unsigned RegNo) const { 337a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return InfoDesc[RegNo].inAllocatableClass; 33893aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos } 33993aa52a8a96c036454be9318bb1c78c9bfb5f390Alkis Evlogimenos 3401fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen /// getSubRegIndexName - Return the human-readable symbolic target-specific 3411fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen /// name for the specified SubRegIndex. 3421fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen const char *getSubRegIndexName(unsigned SubIdx) const { 3431fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen assert(SubIdx && "This is not a subregister index"); 3441fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen return SubRegIndexNames[SubIdx-1]; 3451fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen } 3461fc8e759a767077726f9be35b93767e68bdf101fJakob Stoklund Olesen 3473f2f3f5341374c85955cfaffa71886724999762dLang Hames /// regsOverlap - Returns true if the two registers are equal or alias each 3483f2f3f5341374c85955cfaffa71886724999762dLang Hames /// other. The registers may be virtual register. 3493f2f3f5341374c85955cfaffa71886724999762dLang Hames bool regsOverlap(unsigned regA, unsigned regB) const { 3501e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (regA == regB) return true; 3513f2f3f5341374c85955cfaffa71886724999762dLang Hames if (isVirtualRegister(regA) || isVirtualRegister(regB)) 3523f2f3f5341374c85955cfaffa71886724999762dLang Hames return false; 353e4fd907e72a599eddfa7a81eac4366b5b82523e3Craig Topper for (const uint16_t *regList = getOverlaps(regA)+1; *regList; ++regList) { 3541e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (*regList == regB) return true; 3553ca15c989ca0e09085648771db368d8c94ee1f19Owen Anderson } 35604319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos return false; 35704319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos } 35804319bb2bda50d2ae7cc284cb1c4e742b44a466bAlkis Evlogimenos 359b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// isSubRegister - Returns true if regB is a sub-register of regA. 360b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// 361b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng bool isSubRegister(unsigned regA, unsigned regB) const { 3621e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson return isSuperRegister(regB, regA); 363b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng } 364b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng 365b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// isSuperRegister - Returns true if regB is a super-register of regA. 366b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng /// 367b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng bool isSuperRegister(unsigned regA, unsigned regB) const { 3689ebfbf8b9fd5f982e0db9293808bd32168615ba9Craig Topper for (const uint16_t *regList = getSuperRegisters(regA); *regList;++regList){ 3691e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson if (*regList == regB) return true; 3701e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson } 3711e56a2a85fbafce5ceee72f72d41b84a71876844Owen Anderson return false; 372b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng } 373b2f2e64c0790db11aea7eb52e2d056527204ee9aEvan Cheng 3740098b3e2b69e527ddcf2ebad7a3081898fa3b4f0Evan Cheng /// getCalleeSavedRegs - Return a null-terminated list of all of the 3750098b3e2b69e527ddcf2ebad7a3081898fa3b4f0Evan Cheng /// callee saved registers on this target. The register should be in the 37602569d7355b03155b32c1c0d0e46f6aa957f4802Evan Cheng /// order of desired callee-save stack frame offset. The first register is 377bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// closest to the incoming stack pointer if stack grows down, and vice versa. 378bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 379015f228861ef9b337366f92f637d4e8d624bb006Craig Topper virtual const uint16_t* getCalleeSavedRegs(const MachineFunction *MF = 0) 3802365f51ed03afe6993bae962fdc2e5a956a64cd5Anton Korobeynikov const = 0; 3818797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 382bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// getCallPreservedMask - Return a mask of call-preserved registers for the 383bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// given calling convention on the current sub-target. The mask should 384bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// include all call-preserved aliases. This is used by the register 385bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// allocator to determine which registers can be live across a call. 386bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 387bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 388bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// A set bit indicates that all bits of the corresponding register are 389bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// preserved across the function call. The bit mask is expected to be 390bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// sub-register complete, i.e. if A is preserved, so are all its 391bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// sub-registers. 392bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 393bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// Bits are numbered from the LSB, so the bit for physical register Reg can 394bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 395478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// 396478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// A NULL pointer means that no register mask will be used, and call 397478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// instructions should use implicit-def operands to indicate call clobbered 398478a8a02bc0f2e739ed8f4240152e99837e480b9Jakob Stoklund Olesen /// registers. 399bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen /// 400bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { 401bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen // The default mask clobbers everything. All targets should override. 402bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen return 0; 403bd6dc3be1dac2d153f29927cad517af9e579b204Jakob Stoklund Olesen } 4048797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 405b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng /// getReservedRegs - Returns a bitset indexed by physical register number 4061c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// indicating if a register is a special register that has particular uses 4071c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// and should be considered unavailable at all times, e.g. SP, RA. This is 4081c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// used by register scavenger to determine what registers are free. 409b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 410b371f457b0ea4a652a9f526ba4375c80ae542252Evan Cheng 4118a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng /// getMatchingSuperReg - Return a super-register of the specified register 4128a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng /// Reg so its sub-register of index SubIdx is Reg. 41395923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 4148a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng const TargetRegisterClass *RC) const { 41533ca87affb81b60c4d50214eb7458bd26d397d53Jim Grosbach return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 4168a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng } 4178a8a0dfc3b200e193db14ea1e6f1a18bf4187866Evan Cheng 41891a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// canCombineSubRegIndices - Given a register class and a list of 41991a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// subregister indices, return true if it's possible to combine the 42091a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// subregister indices into one that corresponds to a larger 42191a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// subregister. Return the new subregister index by reference. Note the 42291a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// new index may be zero if the given subregisters can be combined to 42391a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson /// form the whole register. 42491a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 42591a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson SmallVectorImpl<unsigned> &SubIndices, 42691a74da036d3a9442953ae1de3e797a50da4ccf0Bob Wilson unsigned &NewSubIdx) const { 427b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return 0; 428b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 429b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 4305248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// getMatchingSuperRegClass - Return a subclass of the specified register 4315248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// class A so that each register in it has a sub-register of the 4325248468473f0488a652b545ad95f7abda302b7b5Evan Cheng /// specified sub-register index which is in the specified register class B. 433570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// 434570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// TableGen will synthesize missing A sub-classes. 4355248468473f0488a652b545ad95f7abda302b7b5Evan Cheng virtual const TargetRegisterClass * 4365248468473f0488a652b545ad95f7abda302b7b5Evan Cheng getMatchingSuperRegClass(const TargetRegisterClass *A, 437dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen const TargetRegisterClass *B, unsigned Idx) const; 4385248468473f0488a652b545ad95f7abda302b7b5Evan Cheng 439845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 440845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// supports the sub-register index Idx. 441845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// If no such sub-class exists, return NULL. 442845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// If all registers in RC already have an Idx sub-register, return RC. 443845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// 444845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// TableGen generates a version of this function that is good enough in most 445845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// cases. Targets can override if they have constraints that TableGen 446845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// doesn't understand. For example, the x86 sub_8bit sub-register index is 447845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// supported by the full GR32 register class in 64-bit mode, but only by the 448845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// GR32_ABCD regiister class in 32-bit mode. 449845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen /// 450570f9a972e02830d1ca223743dd6b4cc4fdf9549Jakob Stoklund Olesen /// TableGen will synthesize missing RC sub-classes. 451845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen virtual const TargetRegisterClass * 452309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 453309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen assert(Idx == 0 && "Target has no sub-registers"); 454309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen return RC; 455309076ff76c61e03ddd3a0fbbfded3042d2da2e5Jakob Stoklund Olesen } 456845d2c0c776abce551d16f7b1b7dc1f4d4df1a27Jakob Stoklund Olesen 4572da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// composeSubRegIndices - Return the subregister index you get from composing 4582da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// two subregister indices. 4592da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 4602da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 4612da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// returns c. Note that composeSubRegIndices does not tell you about illegal 4622da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// compositions. If R does not have a subreg a, or R:a does not have a subreg 4632da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// b, composeSubRegIndices doesn't tell you. 4642da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 4652da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 4662da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// ssub_0:S0 - ssub_3:S3 subregs. 4672da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 4682da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen /// 4692da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 4702da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen // This default implementation is correct for most targets. 4712da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen return b; 4722da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen } 4732da53370241fdd1b5c291483311b34e609f06c73Jakob Stoklund Olesen 4748797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner //===--------------------------------------------------------------------===// 4758797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // Register Class Information 4768797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner // 4778797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 4788797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner /// Register class iterators 47992988ecdb6ca641ba39d1d1f8cbc57a89b63bbadChris Lattner /// 4808797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_begin() const { return RegClassBegin; } 4818797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner regclass_iterator regclass_end() const { return RegClassEnd; } 4828797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 4838797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner unsigned getNumRegClasses() const { 48434cd4a484e532cc463fd5a4bf59b88d13c5467c1Evan Cheng return (unsigned)(regclass_end()-regclass_begin()); 4858797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner } 48695923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 48760f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// getRegClass - Returns the register class associated with the enumeration 488e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// value. See class MCOperandInfo. 48960f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey const TargetRegisterClass *getRegClass(unsigned i) const { 490a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman assert(i < getNumRegClasses() && "Register Class ID out of range"); 491a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman return RegClassBegin[i]; 49260f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey } 4938797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 494e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen /// getCommonSubClass - find the largest common subclass of A and B. Return 495e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen /// NULL if there is no common subclass. 496e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass * 497e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen getCommonSubClass(const TargetRegisterClass *A, 498e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterClass *B) const; 499e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen 500770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 5012cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner /// values. If a target supports multiple different pointer register classes, 5022cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner /// kind specifies which one is indicated. 5032cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 50450bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Target didn't implement getPointerRegClass!"); 505770bcc7b15adbc978800db70dbb1c3c22913b52cEvan Cheng } 5068797caac84c3012416e933c9c05ad34d75bf4029Chris Lattner 507ff110265753c19daf0468ee1facf357460497b7eEvan Cheng /// getCrossCopyRegClass - Returns a legal register class to copy a register 508b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// in the specified class to or from. If it is possible to copy the register 509b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// directly without using a cross register class copy, return the specified 510b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// RC. Returns NULL if it is not possible to copy between a two registers of 511b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng /// the specified class. 512ff110265753c19daf0468ee1facf357460497b7eEvan Cheng virtual const TargetRegisterClass * 513ff110265753c19daf0468ee1facf357460497b7eEvan Cheng getCrossCopyRegClass(const TargetRegisterClass *RC) const { 514b0519e15f70cef7ba16b712f258d4782ade17e13Evan Cheng return RC; 515ff110265753c19daf0468ee1facf357460497b7eEvan Cheng } 516ff110265753c19daf0468ee1facf357460497b7eEvan Cheng 517c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// getLargestLegalSuperClass - Returns the largest super class of RC that is 518c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// legal to use in the current sub-target and has the same spill size. 519c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The returned register class can be used to create virtual registers which 520c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// means that all its registers can be copied and spilled. 521c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen virtual const TargetRegisterClass* 522c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 523c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// The default implementation is very conservative and doesn't allow the 524c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen /// register allocator to inflate register classes. 525c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return RC; 526c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } 527c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen 528be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// getRegPressureLimit - Return the register pressure "high water mark" for 529be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// the specific register class. The scheduler is in high register pressure 530be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich /// mode (for the specific register class) if it goes over the limit. 531decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// 532decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Note: this is the old register pressure model that relies on a manually 533decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// specified representative register class per value type. 534be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 535be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich MachineFunction &MF) const { 536be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 0; 537be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 538be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 539d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick// Get the weight in units of pressure for this register class. 540ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick virtual const RegClassWeight &getRegClassWeight( 541ec14cd7ddc66d47cd7927f18d8c11844c400367eAndrew Trick const TargetRegisterClass *RC) const = 0; 542decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 543decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the number of dimensions of register pressure. 544decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual unsigned getNumRegPressureSets() const = 0; 545decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 546d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick /// Get the name of this register unit pressure set. 547d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick virtual const char *getRegPressureSetName(unsigned Idx) const = 0; 548d06c2decc2f5c296dfe914509ff841a639eb2a61Andrew Trick 549decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the register unit pressure limit for this dimension. 550decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// This limit must be adjusted dynamically for reserved registers. 551decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0; 552decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 553decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Get the dimensions of register pressure impacted by this register class. 554decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick /// Returns a -1 terminated array of pressure set IDs. 555decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick virtual const int *getRegClassPressureSets( 556decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick const TargetRegisterClass *RC) const = 0; 557decb37eb2b56643cd3d1ebf1af2b7a9c04e1b2f2Andrew Trick 558dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// getRawAllocationOrder - Returns the register allocation order for a 559dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// specified register class with a target-dependent hint. The returned list 560dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// may contain reserved registers that cannot be allocated. 561dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// 562dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// Register allocators need only call this function to resolve 563dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen /// target-dependent hints, but it should work without hinting as well. 564b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper virtual ArrayRef<uint16_t> 565dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen getRawAllocationOrder(const TargetRegisterClass *RC, 566dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen unsigned HintType, unsigned HintReg, 567dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen const MachineFunction &MF) const { 568dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen return RC->getRawAllocationOrder(MF); 569358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng } 570358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng 571358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// ResolveRegAllocHint - Resolves the specified register allocation hint 572358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// to a physical register. Returns the physical register if it is successful. 573f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 574f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng const MachineFunction &MF) const { 575358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng if (Type == 0 && Reg && isPhysicalRegister(Reg)) 576358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng return Reg; 577358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng return 0; 578358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng } 579358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng 580f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// avoidWriteAfterWrite - Return true if the register allocator should avoid 581f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// writing a register from RC in two consecutive instructions. 582f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// This can avoid pipeline stalls on certain architectures. 583f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson /// It does cause increased register pressure, though. 584f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 585f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return false; 586f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson } 587f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 588f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// UpdateRegAllocHint - A callback to allow target a chance to update 589f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// register allocation hints when a register is "changed" (e.g. coalesced) 590f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// to another register. e.g. On ARM, some virtual registers should target 591f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// register pairs, if one of pair is coalesced to another register, the 592f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// allocation hint of the other half of the pair should be changed to point 593f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng /// to the new register. 594f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 595f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng MachineFunction &MF) const { 596f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng // Do nothing. 597f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng } 598f9f1da17f8bd6ffb2df62ce3cb933f0ee63f8da4Evan Cheng 5991c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// requiresRegisterScavenging - returns true if the target requires (and can 6001c08eba3fb44d59176ca1e3bfefce42e7f47d5ecBill Wendling /// make use of) the register scavenger. 60136230cdda48edf6c634f2dcf69f9d78ac5a17377Evan Cheng virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 60237f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng return false; 60337f15a6d488d256d371f6c39ab83837bc9c0772dEvan Cheng } 60495923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 6050f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// useFPForScavengingIndex - returns true if the target wants to use 6060f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// frame pointer based accesses to spill to the scavenger emergency spill 6070f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach /// slot. 6080f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 6090f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach return true; 6100f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach } 6110f657b156f3d0890584bedda7294932a20b2ea16Jim Grosbach 61265c58daa8b8985d2116216043103009815a55e77Jim Grosbach /// requiresFrameIndexScavenging - returns true if the target requires post 61365c58daa8b8985d2116216043103009815a55e77Jim Grosbach /// PEI scavenging of registers for materializing frame index constants. 61465c58daa8b8985d2116216043103009815a55e77Jim Grosbach virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 61565c58daa8b8985d2116216043103009815a55e77Jim Grosbach return false; 61665c58daa8b8985d2116216043103009815a55e77Jim Grosbach } 61765c58daa8b8985d2116216043103009815a55e77Jim Grosbach 618a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// requiresVirtualBaseRegisters - Returns true if the target wants the 619a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// LocalStackAllocation pass to be run and virtual base registers 620a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach /// used for more efficient stack access. 621a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 622a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach return false; 623a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach } 624a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 625910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 626910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// the stack frame of the given function for the specified register. e.g. On 627910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// x86, if the frame register is required, the first fixed stack object is 628910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// reserved as its spill slot. This tells PEI not to create a new stack frame 629910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// object for the given register. It should be called only after 630910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// processFunctionBeforeCalleeSavedScan(). 63172852a8cfb605056d87b644d2e36b1346051413dEric Christopher virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 632910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng int &FrameIdx) const { 633910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng return false; 634910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng } 635910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng 6366a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd /// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked 6376a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd /// after register allocation. 6386a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 6396a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd return false; 6406a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd } 6416a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 642910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// needsStackRealignment - true if storage within the function requires the 643910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// stack pointer to be aligned more than the normal calling convention calls 644910139f9ca53fc20a680d51ae61bb1e072095141Evan Cheng /// for. 645b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen virtual bool needsStackRealignment(const MachineFunction &MF) const { 646b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen return false; 647b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen } 648b5dae003252d8e650a32bfdf33cba5aed8e41e40Dale Johannesen 649e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// getFrameIndexInstrOffset - Get the offset from the referenced frame 65063f8659d6936077c5e8e34eecb55ff1de0db5686Bob Wilson /// index in the instruction, if there is one. 6511ab3f16f06698596716593a30545799688acccd7Jim Grosbach virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 6521ab3f16f06698596716593a30545799688acccd7Jim Grosbach int Idx) const { 653e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return 0; 654e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 655e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 6568708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// needsFrameBaseReg - Returns true if the instruction's frame index 6578708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// reference would be better served by a base register other than FP 6588708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// or SP. Used by LocalStackFrameAllocation to determine which frame index 6598708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach /// references it should create new base registers for. 6603197380143cdc18837722129ac888528b9fbfc2bJim Grosbach virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 6618708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 6628708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 6638708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 664dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// materializeFrameBaseRegister - Insert defining instruction(s) for 665dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// BaseReg to be a pointer to FrameIdx before insertion point I. 666976ef86689ed065361a748f81c44ca3510af2202Bill Wendling virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 667e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned BaseReg, int FrameIdx, 668e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 66950bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("materializeFrameBaseRegister does not exist on this " 67050bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper "target"); 671dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 672dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 673dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// resolveFrameIndex - Resolve a frame index operand of an instruction 674dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach /// to reference the indicated base register plus offset instead. 675dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 676dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned BaseReg, int64_t Offset) const { 67750bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("resolveFrameIndex does not exist on this target"); 678dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 679dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 680e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// isFrameOffsetLegal - Determine whether a given offset immediate is 681e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach /// encodable to resolve a frame index. 682e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach virtual bool isFrameOffsetLegal(const MachineInstr *MI, 683e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 68450bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 68574d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach } 686dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 687f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 688f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// code insertion to eliminate call frame setup and destroy pseudo 689f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// instructions (but only if the Target is using them). It is responsible 690f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// for eliminating these instructions, replacing them with concrete 691f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// instructions. This method need only be implemented if using call frame 6928a1478b6d7aeaed8363316d2e0b90d9f53525c29Chris Lattner /// setup/destroy pseudo instructions. 693f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// 69434695381d626485a560594f162701088079589dfMisha Brukman virtual void 6958604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner eliminateCallFramePseudoInstr(MachineFunction &MF, 6968604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner MachineBasicBlock &MBB, 6978604e7572132e8728a1e20d53965bc4ab6986818Chris Lattner MachineBasicBlock::iterator MI) const { 69850bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Call Frame Pseudo Instructions do not exist on this " 69950bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper "target!"); 700f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner } 701f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 702f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 703d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// saveScavengerRegister - Spill the register so it can be used by the 704d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// register scavenger. Return true if the register was spilled, false 705d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach /// otherwise. If this function does not spill the register, the scavenger 706540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// will instead spill it to the emergency spill slot. 707540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach /// 708540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 709540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach MachineBasicBlock::iterator I, 710d482f55af135081aee7f7ab972bb8973f189c88fJim Grosbach MachineBasicBlock::iterator &UseMI, 711540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach const TargetRegisterClass *RC, 7121f8f4d2db734d9881467a5706acac73660842d43Evan Cheng unsigned Reg) const { 7131f8f4d2db734d9881467a5706acac73660842d43Evan Cheng return false; 7141f8f4d2db734d9881467a5706acac73660842d43Evan Cheng } 715540b05d227a79443b2a7b07d5152a35cb6392abfJim Grosbach 716f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminateFrameIndex - This method must be overriden to eliminate abstract 717f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// frame indices from instructions which may use them. The instruction 718f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// referenced by the iterator contains an MO_FrameIndex operand which must be 719f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner /// eliminated by this method. This method may modify or replace the 720c49a10aca1e31351c2e11b25ba636a23b93c46c8Dale Johannesen /// specified instruction, as long as it keeps the iterator pointing at the 72118b111bffe643b5ad52ae10a1d5728b0c1ac92f0Evan Cheng /// finished product. SPAdj is the SP adjustment due to call frame setup 7221ad70c09c890c3abcc147503f2e23082f683790cMatthijs Kooijman /// instruction. 723fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 724fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach int SPAdj, RegScavenger *RS=NULL) const = 0; 725f9b332b59d1c008268551572557dca6ab6028a4dChris Lattner 726a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey //===--------------------------------------------------------------------===// 727a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// Debug information queries. 72895923d70d90e0b9901d63ec3e35bf94be260e4f0Jim Grosbach 729a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey /// getFrameRegister - This method should return the register used as a base 7304188699f80c233a20b6ddc61570a8a8c1804cb85Jim Laskey /// for values allocated in the current stack frame. 731b9c2fd964ee7dd7823ac71db8443055e4d0f1c15David Greene virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 73272bebb9205c1628601b052d25555aabe6e15e6f4Evan Cheng 7335cd2791513919ee7504c309151321e4e37a05a58Bill Wendling /// getCompactUnwindRegNum - This function maps the register to the number for 7345cd2791513919ee7504c309151321e4e37a05a58Bill Wendling /// compact unwind encoding. Return -1 if the register isn't valid. 735486dd90696545421c55346570b88fa03f6dd464fBill Wendling virtual int getCompactUnwindRegNum(unsigned, bool) const { 7365cd2791513919ee7504c309151321e4e37a05a58Bill Wendling return -1; 7375cd2791513919ee7504c309151321e4e37a05a58Bill Wendling } 7383d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner}; 7393d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner 740c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng 74194c002a190cd2e3a52b1510bc997e53d63af0b3bChris Lattner// This is useful when building IndexedMaps keyed on virtual registers 74259bf4fcc0680e75b408579064d1205a132361196Duncan Sandsstruct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 7434d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos unsigned operator()(unsigned Reg) const { 744c7d67f90d36375f1ff512a3857c887b7e4246adbJakob Stoklund Olesen return TargetRegisterInfo::virtReg2Index(Reg); 7454d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos } 7464d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos}; 7474d0d864be3d9a698c4edfe36961a22126f041298Alkis Evlogimenos 7484314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// PrintReg - Helper class for printing registers on a raw_ostream. 7494314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Prints virtual and physical registers with or without a TRI instance. 7504314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 7514314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// The format is: 75243a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %noreg - NoRegister 75343a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5 - a virtual register. 75443a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 75543a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %EAX - a physical register 75643a566519b85ddffa482695d6a5a3dc4a02e267fJakob Stoklund Olesen/// %physreg17 - a physical register when no TRI instance given. 7574314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 7584314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 7594314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen/// 7604314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenclass PrintReg { 7614314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen const TargetRegisterInfo *TRI; 7624314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen unsigned Reg; 7634314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen unsigned SubIdx; 7644314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenpublic: 7654314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 7664314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen : TRI(tri), Reg(reg), SubIdx(subidx) {} 7674314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen void print(raw_ostream&) const; 7684314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen}; 7694314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen 7704314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesenstatic inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 7714314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen PR.print(OS); 7724314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen return OS; 7734314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen} 7744314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen 775d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 776d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 7773d7771a387d9476cfb25451ab95b72ce7b3e2532Chris Lattner#endif 778