MachineInstr.cpp revision 0d7585839540abb9ab661a741dc3e0c2c860bceb
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineInstr.h" 15#include "llvm/Constants.h" 16#include "llvm/DebugInfo.h" 17#include "llvm/Function.h" 18#include "llvm/InlineAsm.h" 19#include "llvm/LLVMContext.h" 20#include "llvm/Metadata.h" 21#include "llvm/Module.h" 22#include "llvm/Type.h" 23#include "llvm/Value.h" 24#include "llvm/Assembly/Writer.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineMemOperand.h" 28#include "llvm/CodeGen/MachineModuleInfo.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/CodeGen/PseudoSourceValue.h" 31#include "llvm/MC/MCInstrDesc.h" 32#include "llvm/MC/MCSymbol.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/Target/TargetInstrInfo.h" 35#include "llvm/Target/TargetRegisterInfo.h" 36#include "llvm/Analysis/AliasAnalysis.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Support/LeakDetector.h" 40#include "llvm/Support/MathExtras.h" 41#include "llvm/Support/raw_ostream.h" 42#include "llvm/ADT/FoldingSet.h" 43#include "llvm/ADT/Hashing.h" 44using namespace llvm; 45 46//===----------------------------------------------------------------------===// 47// MachineOperand Implementation 48//===----------------------------------------------------------------------===// 49 50void MachineOperand::setReg(unsigned Reg) { 51 if (getReg() == Reg) return; // No change. 52 53 // Otherwise, we have to change the register. If this operand is embedded 54 // into a machine function, we need to update the old and new register's 55 // use/def lists. 56 if (MachineInstr *MI = getParent()) 57 if (MachineBasicBlock *MBB = MI->getParent()) 58 if (MachineFunction *MF = MBB->getParent()) { 59 MachineRegisterInfo &MRI = MF->getRegInfo(); 60 MRI.removeRegOperandFromUseList(this); 61 SmallContents.RegNo = Reg; 62 MRI.addRegOperandToUseList(this); 63 return; 64 } 65 66 // Otherwise, just change the register, no problem. :) 67 SmallContents.RegNo = Reg; 68} 69 70void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, 71 const TargetRegisterInfo &TRI) { 72 assert(TargetRegisterInfo::isVirtualRegister(Reg)); 73 if (SubIdx && getSubReg()) 74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 75 setReg(Reg); 76 if (SubIdx) 77 setSubReg(SubIdx); 78} 79 80void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { 81 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 82 if (getSubReg()) { 83 Reg = TRI.getSubReg(Reg, getSubReg()); 84 // Note that getSubReg() may return 0 if the sub-register doesn't exist. 85 // That won't happen in legal code. 86 setSubReg(0); 87 } 88 setReg(Reg); 89} 90 91/// Change a def to a use, or a use to a def. 92void MachineOperand::setIsDef(bool Val) { 93 assert(isReg() && "Wrong MachineOperand accessor"); 94 assert((!Val || !isDebug()) && "Marking a debug operation as def"); 95 if (IsDef == Val) 96 return; 97 // MRI may keep uses and defs in different list positions. 98 if (MachineInstr *MI = getParent()) 99 if (MachineBasicBlock *MBB = MI->getParent()) 100 if (MachineFunction *MF = MBB->getParent()) { 101 MachineRegisterInfo &MRI = MF->getRegInfo(); 102 MRI.removeRegOperandFromUseList(this); 103 IsDef = Val; 104 MRI.addRegOperandToUseList(this); 105 return; 106 } 107 IsDef = Val; 108} 109 110/// ChangeToImmediate - Replace this operand with a new immediate operand of 111/// the specified value. If an operand is known to be an immediate already, 112/// the setImm method should be used. 113void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 114 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); 115 // If this operand is currently a register operand, and if this is in a 116 // function, deregister the operand from the register's use/def list. 117 if (isReg() && isOnRegUseList()) 118 if (MachineInstr *MI = getParent()) 119 if (MachineBasicBlock *MBB = MI->getParent()) 120 if (MachineFunction *MF = MBB->getParent()) 121 MF->getRegInfo().removeRegOperandFromUseList(this); 122 123 OpKind = MO_Immediate; 124 Contents.ImmVal = ImmVal; 125} 126 127/// ChangeToRegister - Replace this operand with a new register operand of 128/// the specified value. If an operand is known to be an register already, 129/// the setReg method should be used. 130void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 131 bool isKill, bool isDead, bool isUndef, 132 bool isDebug) { 133 MachineRegisterInfo *RegInfo = 0; 134 if (MachineInstr *MI = getParent()) 135 if (MachineBasicBlock *MBB = MI->getParent()) 136 if (MachineFunction *MF = MBB->getParent()) 137 RegInfo = &MF->getRegInfo(); 138 // If this operand is already a register operand, remove it from the 139 // register's use/def lists. 140 bool WasReg = isReg(); 141 if (RegInfo && WasReg) 142 RegInfo->removeRegOperandFromUseList(this); 143 144 // Change this to a register and set the reg#. 145 OpKind = MO_Register; 146 SmallContents.RegNo = Reg; 147 SubReg = 0; 148 IsDef = isDef; 149 IsImp = isImp; 150 IsKill = isKill; 151 IsDead = isDead; 152 IsUndef = isUndef; 153 IsInternalRead = false; 154 IsEarlyClobber = false; 155 IsDebug = isDebug; 156 // Ensure isOnRegUseList() returns false. 157 Contents.Reg.Prev = 0; 158 // Preserve the tie bit when the operand was already a register. 159 if (!WasReg) 160 IsTied = false; 161 162 // If this operand is embedded in a function, add the operand to the 163 // register's use/def list. 164 if (RegInfo) 165 RegInfo->addRegOperandToUseList(this); 166} 167 168/// isIdenticalTo - Return true if this operand is identical to the specified 169/// operand. Note that this should stay in sync with the hash_value overload 170/// below. 171bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 172 if (getType() != Other.getType() || 173 getTargetFlags() != Other.getTargetFlags()) 174 return false; 175 176 switch (getType()) { 177 case MachineOperand::MO_Register: 178 return getReg() == Other.getReg() && isDef() == Other.isDef() && 179 getSubReg() == Other.getSubReg(); 180 case MachineOperand::MO_Immediate: 181 return getImm() == Other.getImm(); 182 case MachineOperand::MO_CImmediate: 183 return getCImm() == Other.getCImm(); 184 case MachineOperand::MO_FPImmediate: 185 return getFPImm() == Other.getFPImm(); 186 case MachineOperand::MO_MachineBasicBlock: 187 return getMBB() == Other.getMBB(); 188 case MachineOperand::MO_FrameIndex: 189 return getIndex() == Other.getIndex(); 190 case MachineOperand::MO_ConstantPoolIndex: 191 case MachineOperand::MO_TargetIndex: 192 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 193 case MachineOperand::MO_JumpTableIndex: 194 return getIndex() == Other.getIndex(); 195 case MachineOperand::MO_GlobalAddress: 196 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 197 case MachineOperand::MO_ExternalSymbol: 198 return !strcmp(getSymbolName(), Other.getSymbolName()) && 199 getOffset() == Other.getOffset(); 200 case MachineOperand::MO_BlockAddress: 201 return getBlockAddress() == Other.getBlockAddress(); 202 case MO_RegisterMask: 203 return getRegMask() == Other.getRegMask(); 204 case MachineOperand::MO_MCSymbol: 205 return getMCSymbol() == Other.getMCSymbol(); 206 case MachineOperand::MO_Metadata: 207 return getMetadata() == Other.getMetadata(); 208 } 209 llvm_unreachable("Invalid machine operand type"); 210} 211 212// Note: this must stay exactly in sync with isIdenticalTo above. 213hash_code llvm::hash_value(const MachineOperand &MO) { 214 switch (MO.getType()) { 215 case MachineOperand::MO_Register: 216 // Register operands don't have target flags. 217 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); 218 case MachineOperand::MO_Immediate: 219 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm()); 220 case MachineOperand::MO_CImmediate: 221 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm()); 222 case MachineOperand::MO_FPImmediate: 223 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm()); 224 case MachineOperand::MO_MachineBasicBlock: 225 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB()); 226 case MachineOperand::MO_FrameIndex: 227 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 228 case MachineOperand::MO_ConstantPoolIndex: 229 case MachineOperand::MO_TargetIndex: 230 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(), 231 MO.getOffset()); 232 case MachineOperand::MO_JumpTableIndex: 233 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 234 case MachineOperand::MO_ExternalSymbol: 235 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(), 236 MO.getSymbolName()); 237 case MachineOperand::MO_GlobalAddress: 238 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(), 239 MO.getOffset()); 240 case MachineOperand::MO_BlockAddress: 241 return hash_combine(MO.getType(), MO.getTargetFlags(), 242 MO.getBlockAddress()); 243 case MachineOperand::MO_RegisterMask: 244 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask()); 245 case MachineOperand::MO_Metadata: 246 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata()); 247 case MachineOperand::MO_MCSymbol: 248 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol()); 249 } 250 llvm_unreachable("Invalid machine operand type"); 251} 252 253/// print - Print the specified machine operand. 254/// 255void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 256 // If the instruction is embedded into a basic block, we can find the 257 // target info for the instruction. 258 if (!TM) 259 if (const MachineInstr *MI = getParent()) 260 if (const MachineBasicBlock *MBB = MI->getParent()) 261 if (const MachineFunction *MF = MBB->getParent()) 262 TM = &MF->getTarget(); 263 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; 264 265 switch (getType()) { 266 case MachineOperand::MO_Register: 267 OS << PrintReg(getReg(), TRI, getSubReg()); 268 269 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 270 isInternalRead() || isEarlyClobber() || isTied()) { 271 OS << '<'; 272 bool NeedComma = false; 273 if (isDef()) { 274 if (NeedComma) OS << ','; 275 if (isEarlyClobber()) 276 OS << "earlyclobber,"; 277 if (isImplicit()) 278 OS << "imp-"; 279 OS << "def"; 280 NeedComma = true; 281 // <def,read-undef> only makes sense when getSubReg() is set. 282 // Don't clutter the output otherwise. 283 if (isUndef() && getSubReg()) 284 OS << ",read-undef"; 285 } else if (isImplicit()) { 286 OS << "imp-use"; 287 NeedComma = true; 288 } 289 290 if (isKill()) { 291 if (NeedComma) OS << ','; 292 OS << "kill"; 293 NeedComma = true; 294 } 295 if (isDead()) { 296 if (NeedComma) OS << ','; 297 OS << "dead"; 298 NeedComma = true; 299 } 300 if (isUndef() && isUse()) { 301 if (NeedComma) OS << ','; 302 OS << "undef"; 303 NeedComma = true; 304 } 305 if (isInternalRead()) { 306 if (NeedComma) OS << ','; 307 OS << "internal"; 308 NeedComma = true; 309 } 310 if (isTied()) { 311 if (NeedComma) OS << ','; 312 OS << "tied"; 313 NeedComma = true; 314 } 315 OS << '>'; 316 } 317 break; 318 case MachineOperand::MO_Immediate: 319 OS << getImm(); 320 break; 321 case MachineOperand::MO_CImmediate: 322 getCImm()->getValue().print(OS, false); 323 break; 324 case MachineOperand::MO_FPImmediate: 325 if (getFPImm()->getType()->isFloatTy()) 326 OS << getFPImm()->getValueAPF().convertToFloat(); 327 else 328 OS << getFPImm()->getValueAPF().convertToDouble(); 329 break; 330 case MachineOperand::MO_MachineBasicBlock: 331 OS << "<BB#" << getMBB()->getNumber() << ">"; 332 break; 333 case MachineOperand::MO_FrameIndex: 334 OS << "<fi#" << getIndex() << '>'; 335 break; 336 case MachineOperand::MO_ConstantPoolIndex: 337 OS << "<cp#" << getIndex(); 338 if (getOffset()) OS << "+" << getOffset(); 339 OS << '>'; 340 break; 341 case MachineOperand::MO_TargetIndex: 342 OS << "<ti#" << getIndex(); 343 if (getOffset()) OS << "+" << getOffset(); 344 OS << '>'; 345 break; 346 case MachineOperand::MO_JumpTableIndex: 347 OS << "<jt#" << getIndex() << '>'; 348 break; 349 case MachineOperand::MO_GlobalAddress: 350 OS << "<ga:"; 351 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 352 if (getOffset()) OS << "+" << getOffset(); 353 OS << '>'; 354 break; 355 case MachineOperand::MO_ExternalSymbol: 356 OS << "<es:" << getSymbolName(); 357 if (getOffset()) OS << "+" << getOffset(); 358 OS << '>'; 359 break; 360 case MachineOperand::MO_BlockAddress: 361 OS << '<'; 362 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 363 OS << '>'; 364 break; 365 case MachineOperand::MO_RegisterMask: 366 OS << "<regmask>"; 367 break; 368 case MachineOperand::MO_Metadata: 369 OS << '<'; 370 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 371 OS << '>'; 372 break; 373 case MachineOperand::MO_MCSymbol: 374 OS << "<MCSym=" << *getMCSymbol() << '>'; 375 break; 376 } 377 378 if (unsigned TF = getTargetFlags()) 379 OS << "[TF=" << TF << ']'; 380} 381 382//===----------------------------------------------------------------------===// 383// MachineMemOperand Implementation 384//===----------------------------------------------------------------------===// 385 386/// getAddrSpace - Return the LLVM IR address space number that this pointer 387/// points into. 388unsigned MachinePointerInfo::getAddrSpace() const { 389 if (V == 0) return 0; 390 return cast<PointerType>(V->getType())->getAddressSpace(); 391} 392 393/// getConstantPool - Return a MachinePointerInfo record that refers to the 394/// constant pool. 395MachinePointerInfo MachinePointerInfo::getConstantPool() { 396 return MachinePointerInfo(PseudoSourceValue::getConstantPool()); 397} 398 399/// getFixedStack - Return a MachinePointerInfo record that refers to the 400/// the specified FrameIndex. 401MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) { 402 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset); 403} 404 405MachinePointerInfo MachinePointerInfo::getJumpTable() { 406 return MachinePointerInfo(PseudoSourceValue::getJumpTable()); 407} 408 409MachinePointerInfo MachinePointerInfo::getGOT() { 410 return MachinePointerInfo(PseudoSourceValue::getGOT()); 411} 412 413MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) { 414 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset); 415} 416 417MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f, 418 uint64_t s, unsigned int a, 419 const MDNode *TBAAInfo, 420 const MDNode *Ranges) 421 : PtrInfo(ptrinfo), Size(s), 422 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)), 423 TBAAInfo(TBAAInfo), Ranges(Ranges) { 424 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) && 425 "invalid pointer value"); 426 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 427 assert((isLoad() || isStore()) && "Not a load/store!"); 428} 429 430/// Profile - Gather unique data for the object. 431/// 432void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 433 ID.AddInteger(getOffset()); 434 ID.AddInteger(Size); 435 ID.AddPointer(getValue()); 436 ID.AddInteger(Flags); 437} 438 439void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 440 // The Value and Offset may differ due to CSE. But the flags and size 441 // should be the same. 442 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 443 assert(MMO->getSize() == getSize() && "Size mismatch!"); 444 445 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 446 // Update the alignment value. 447 Flags = (Flags & ((1 << MOMaxBits) - 1)) | 448 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); 449 // Also update the base and offset, because the new alignment may 450 // not be applicable with the old ones. 451 PtrInfo = MMO->PtrInfo; 452 } 453} 454 455/// getAlignment - Return the minimum known alignment in bytes of the 456/// actual memory reference. 457uint64_t MachineMemOperand::getAlignment() const { 458 return MinAlign(getBaseAlignment(), getOffset()); 459} 460 461raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 462 assert((MMO.isLoad() || MMO.isStore()) && 463 "SV has to be a load, store or both."); 464 465 if (MMO.isVolatile()) 466 OS << "Volatile "; 467 468 if (MMO.isLoad()) 469 OS << "LD"; 470 if (MMO.isStore()) 471 OS << "ST"; 472 OS << MMO.getSize(); 473 474 // Print the address information. 475 OS << "["; 476 if (!MMO.getValue()) 477 OS << "<unknown>"; 478 else 479 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 480 481 // If the alignment of the memory reference itself differs from the alignment 482 // of the base pointer, print the base alignment explicitly, next to the base 483 // pointer. 484 if (MMO.getBaseAlignment() != MMO.getAlignment()) 485 OS << "(align=" << MMO.getBaseAlignment() << ")"; 486 487 if (MMO.getOffset() != 0) 488 OS << "+" << MMO.getOffset(); 489 OS << "]"; 490 491 // Print the alignment of the reference. 492 if (MMO.getBaseAlignment() != MMO.getAlignment() || 493 MMO.getBaseAlignment() != MMO.getSize()) 494 OS << "(align=" << MMO.getAlignment() << ")"; 495 496 // Print TBAA info. 497 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) { 498 OS << "(tbaa="; 499 if (TBAAInfo->getNumOperands() > 0) 500 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false); 501 else 502 OS << "<unknown>"; 503 OS << ")"; 504 } 505 506 // Print nontemporal info. 507 if (MMO.isNonTemporal()) 508 OS << "(nontemporal)"; 509 510 return OS; 511} 512 513//===----------------------------------------------------------------------===// 514// MachineInstr Implementation 515//===----------------------------------------------------------------------===// 516 517/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 518/// MCID NULL and no operands. 519MachineInstr::MachineInstr() 520 : MCID(0), Flags(0), AsmPrinterFlags(0), 521 NumMemRefs(0), MemRefs(0), 522 Parent(0) { 523 // Make sure that we get added to a machine basicblock 524 LeakDetector::addGarbageObject(this); 525} 526 527void MachineInstr::addImplicitDefUseOperands() { 528 if (MCID->ImplicitDefs) 529 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 530 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 531 if (MCID->ImplicitUses) 532 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) 533 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 534} 535 536/// MachineInstr ctor - This constructor creates a MachineInstr and adds the 537/// implicit operands. It reserves space for the number of operands specified by 538/// the MCInstrDesc. 539MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp) 540 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 541 NumMemRefs(0), MemRefs(0), Parent(0) { 542 unsigned NumImplicitOps = 0; 543 if (!NoImp) 544 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 545 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 546 if (!NoImp) 547 addImplicitDefUseOperands(); 548 // Make sure that we get added to a machine basicblock 549 LeakDetector::addGarbageObject(this); 550} 551 552/// MachineInstr ctor - As above, but with a DebugLoc. 553MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl, 554 bool NoImp) 555 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 556 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) { 557 unsigned NumImplicitOps = 0; 558 if (!NoImp) 559 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 560 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 561 if (!NoImp) 562 addImplicitDefUseOperands(); 563 // Make sure that we get added to a machine basicblock 564 LeakDetector::addGarbageObject(this); 565} 566 567/// MachineInstr ctor - Work exactly the same as the ctor two above, except 568/// that the MachineInstr is created and added to the end of the specified 569/// basic block. 570MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid) 571 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 572 NumMemRefs(0), MemRefs(0), Parent(0) { 573 assert(MBB && "Cannot use inserting ctor with null basic block!"); 574 unsigned NumImplicitOps = 575 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 576 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 577 addImplicitDefUseOperands(); 578 // Make sure that we get added to a machine basicblock 579 LeakDetector::addGarbageObject(this); 580 MBB->push_back(this); // Add instruction to end of basic block! 581} 582 583/// MachineInstr ctor - As above, but with a DebugLoc. 584/// 585MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 586 const MCInstrDesc &tid) 587 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 588 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) { 589 assert(MBB && "Cannot use inserting ctor with null basic block!"); 590 unsigned NumImplicitOps = 591 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 592 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 593 addImplicitDefUseOperands(); 594 // Make sure that we get added to a machine basicblock 595 LeakDetector::addGarbageObject(this); 596 MBB->push_back(this); // Add instruction to end of basic block! 597} 598 599/// MachineInstr ctor - Copies MachineInstr arg exactly 600/// 601MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 602 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0), 603 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs), 604 Parent(0), debugLoc(MI.getDebugLoc()) { 605 Operands.reserve(MI.getNumOperands()); 606 607 // Add operands 608 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 609 addOperand(MI.getOperand(i)); 610 611 // Copy all the flags. 612 Flags = MI.Flags; 613 614 // Set parent to null. 615 Parent = 0; 616 617 LeakDetector::addGarbageObject(this); 618} 619 620MachineInstr::~MachineInstr() { 621 LeakDetector::removeGarbageObject(this); 622#ifndef NDEBUG 623 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 624 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 625 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 626 "Reg operand def/use list corrupted"); 627 } 628#endif 629} 630 631/// getRegInfo - If this instruction is embedded into a MachineFunction, 632/// return the MachineRegisterInfo object for the current function, otherwise 633/// return null. 634MachineRegisterInfo *MachineInstr::getRegInfo() { 635 if (MachineBasicBlock *MBB = getParent()) 636 return &MBB->getParent()->getRegInfo(); 637 return 0; 638} 639 640/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 641/// this instruction from their respective use lists. This requires that the 642/// operands already be on their use lists. 643void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { 644 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 645 if (Operands[i].isReg()) 646 MRI.removeRegOperandFromUseList(&Operands[i]); 647} 648 649/// AddRegOperandsToUseLists - Add all of the register operands in 650/// this instruction from their respective use lists. This requires that the 651/// operands not be on their use lists yet. 652void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { 653 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 654 if (Operands[i].isReg()) 655 MRI.addRegOperandToUseList(&Operands[i]); 656} 657 658/// addOperand - Add the specified operand to the instruction. If it is an 659/// implicit operand, it is added to the end of the operand list. If it is 660/// an explicit operand it is added at the end of the explicit operand list 661/// (before the first implicit operand). 662void MachineInstr::addOperand(const MachineOperand &Op) { 663 assert(MCID && "Cannot add operands before providing an instr descriptor"); 664 bool isImpReg = Op.isReg() && Op.isImplicit(); 665 MachineRegisterInfo *RegInfo = getRegInfo(); 666 667 // If the Operands backing store is reallocated, all register operands must 668 // be removed and re-added to RegInfo. It is storing pointers to operands. 669 bool Reallocate = RegInfo && 670 !Operands.empty() && Operands.size() == Operands.capacity(); 671 672 // Find the insert location for the new operand. Implicit registers go at 673 // the end, everything goes before the implicit regs. 674 unsigned OpNo = Operands.size(); 675 676 // Remove all the implicit operands from RegInfo if they need to be shifted. 677 // FIXME: Allow mixed explicit and implicit operands on inline asm. 678 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as 679 // implicit-defs, but they must not be moved around. See the FIXME in 680 // InstrEmitter.cpp. 681 if (!isImpReg && !isInlineAsm()) { 682 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { 683 --OpNo; 684 if (RegInfo) 685 RegInfo->removeRegOperandFromUseList(&Operands[OpNo]); 686 } 687 } 688 689 // OpNo now points as the desired insertion point. Unless this is a variadic 690 // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). 691 // RegMask operands go between the explicit and implicit operands. 692 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || 693 OpNo < MCID->getNumOperands()) && 694 "Trying to add an operand to a machine instr that is already done!"); 695 696 // All operands from OpNo have been removed from RegInfo. If the Operands 697 // backing store needs to be reallocated, we also need to remove any other 698 // register operands. 699 if (Reallocate) 700 for (unsigned i = 0; i != OpNo; ++i) 701 if (Operands[i].isReg()) 702 RegInfo->removeRegOperandFromUseList(&Operands[i]); 703 704 // Insert the new operand at OpNo. 705 Operands.insert(Operands.begin() + OpNo, Op); 706 Operands[OpNo].ParentMI = this; 707 708 // The Operands backing store has now been reallocated, so we can re-add the 709 // operands before OpNo. 710 if (Reallocate) 711 for (unsigned i = 0; i != OpNo; ++i) 712 if (Operands[i].isReg()) 713 RegInfo->addRegOperandToUseList(&Operands[i]); 714 715 // When adding a register operand, tell RegInfo about it. 716 if (Operands[OpNo].isReg()) { 717 // Ensure isOnRegUseList() returns false, regardless of Op's status. 718 Operands[OpNo].Contents.Reg.Prev = 0; 719 // Ignore existing IsTied bit. This is not a property that can be copied. 720 Operands[OpNo].IsTied = false; 721 // Add the new operand to RegInfo. 722 if (RegInfo) 723 RegInfo->addRegOperandToUseList(&Operands[OpNo]); 724 // Set the IsTied bit if MC indicates this use is tied to a def. 725 if (Operands[OpNo].isUse()) { 726 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); 727 if (DefIdx != -1) { 728 MachineOperand &DefMO = getOperand(DefIdx); 729 assert(DefMO.isDef() && "Use tied to operand that isn't a def"); 730 DefMO.IsTied = true; 731 Operands[OpNo].IsTied = true; 732 } 733 } 734 // If the register operand is flagged as early, mark the operand as such. 735 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 736 Operands[OpNo].setIsEarlyClobber(true); 737 } 738 739 // Re-add all the implicit ops. 740 if (RegInfo) { 741 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) { 742 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 743 RegInfo->addRegOperandToUseList(&Operands[i]); 744 } 745 } 746} 747 748/// RemoveOperand - Erase an operand from an instruction, leaving it with one 749/// fewer operand than it started with. 750/// 751void MachineInstr::RemoveOperand(unsigned OpNo) { 752 assert(OpNo < Operands.size() && "Invalid operand number"); 753 untieRegOperand(OpNo); 754 MachineRegisterInfo *RegInfo = getRegInfo(); 755 756 // Special case removing the last one. 757 if (OpNo == Operands.size()-1) { 758 // If needed, remove from the reg def/use list. 759 if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList()) 760 RegInfo->removeRegOperandFromUseList(&Operands.back()); 761 762 Operands.pop_back(); 763 return; 764 } 765 766 // Otherwise, we are removing an interior operand. If we have reginfo to 767 // update, remove all operands that will be shifted down from their reg lists, 768 // move everything down, then re-add them. 769 if (RegInfo) { 770 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 771 if (Operands[i].isReg()) 772 RegInfo->removeRegOperandFromUseList(&Operands[i]); 773 } 774 } 775 776 Operands.erase(Operands.begin()+OpNo); 777 778 if (RegInfo) { 779 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 780 if (Operands[i].isReg()) 781 RegInfo->addRegOperandToUseList(&Operands[i]); 782 } 783 } 784} 785 786/// addMemOperand - Add a MachineMemOperand to the machine instruction. 787/// This function should be used only occasionally. The setMemRefs function 788/// is the primary method for setting up a MachineInstr's MemRefs list. 789void MachineInstr::addMemOperand(MachineFunction &MF, 790 MachineMemOperand *MO) { 791 mmo_iterator OldMemRefs = MemRefs; 792 uint16_t OldNumMemRefs = NumMemRefs; 793 794 uint16_t NewNum = NumMemRefs + 1; 795 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 796 797 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs); 798 NewMemRefs[NewNum - 1] = MO; 799 800 MemRefs = NewMemRefs; 801 NumMemRefs = NewNum; 802} 803 804bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const { 805 const MachineBasicBlock *MBB = getParent(); 806 MachineBasicBlock::const_instr_iterator MII = *this; ++MII; 807 while (MII != MBB->end() && MII->isInsideBundle()) { 808 if (MII->getDesc().getFlags() & Mask) { 809 if (Type == AnyInBundle) 810 return true; 811 } else { 812 if (Type == AllInBundle) 813 return false; 814 } 815 ++MII; 816 } 817 818 return Type == AllInBundle; 819} 820 821bool MachineInstr::isIdenticalTo(const MachineInstr *Other, 822 MICheckType Check) const { 823 // If opcodes or number of operands are not the same then the two 824 // instructions are obviously not identical. 825 if (Other->getOpcode() != getOpcode() || 826 Other->getNumOperands() != getNumOperands()) 827 return false; 828 829 if (isBundle()) { 830 // Both instructions are bundles, compare MIs inside the bundle. 831 MachineBasicBlock::const_instr_iterator I1 = *this; 832 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end(); 833 MachineBasicBlock::const_instr_iterator I2 = *Other; 834 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end(); 835 while (++I1 != E1 && I1->isInsideBundle()) { 836 ++I2; 837 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check)) 838 return false; 839 } 840 } 841 842 // Check operands to make sure they match. 843 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 844 const MachineOperand &MO = getOperand(i); 845 const MachineOperand &OMO = Other->getOperand(i); 846 if (!MO.isReg()) { 847 if (!MO.isIdenticalTo(OMO)) 848 return false; 849 continue; 850 } 851 852 // Clients may or may not want to ignore defs when testing for equality. 853 // For example, machine CSE pass only cares about finding common 854 // subexpressions, so it's safe to ignore virtual register defs. 855 if (MO.isDef()) { 856 if (Check == IgnoreDefs) 857 continue; 858 else if (Check == IgnoreVRegDefs) { 859 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 860 TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) 861 if (MO.getReg() != OMO.getReg()) 862 return false; 863 } else { 864 if (!MO.isIdenticalTo(OMO)) 865 return false; 866 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) 867 return false; 868 } 869 } else { 870 if (!MO.isIdenticalTo(OMO)) 871 return false; 872 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) 873 return false; 874 } 875 } 876 // If DebugLoc does not match then two dbg.values are not identical. 877 if (isDebugValue()) 878 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown() 879 && getDebugLoc() != Other->getDebugLoc()) 880 return false; 881 return true; 882} 883 884/// removeFromParent - This method unlinks 'this' from the containing basic 885/// block, and returns it, but does not delete it. 886MachineInstr *MachineInstr::removeFromParent() { 887 assert(getParent() && "Not embedded in a basic block!"); 888 889 // If it's a bundle then remove the MIs inside the bundle as well. 890 if (isBundle()) { 891 MachineBasicBlock *MBB = getParent(); 892 MachineBasicBlock::instr_iterator MII = *this; ++MII; 893 MachineBasicBlock::instr_iterator E = MBB->instr_end(); 894 while (MII != E && MII->isInsideBundle()) { 895 MachineInstr *MI = &*MII; 896 ++MII; 897 MBB->remove(MI); 898 } 899 } 900 getParent()->remove(this); 901 return this; 902} 903 904 905/// eraseFromParent - This method unlinks 'this' from the containing basic 906/// block, and deletes it. 907void MachineInstr::eraseFromParent() { 908 assert(getParent() && "Not embedded in a basic block!"); 909 // If it's a bundle then remove the MIs inside the bundle as well. 910 if (isBundle()) { 911 MachineBasicBlock *MBB = getParent(); 912 MachineBasicBlock::instr_iterator MII = *this; ++MII; 913 MachineBasicBlock::instr_iterator E = MBB->instr_end(); 914 while (MII != E && MII->isInsideBundle()) { 915 MachineInstr *MI = &*MII; 916 ++MII; 917 MBB->erase(MI); 918 } 919 } 920 // Erase the individual instruction, which may itself be inside a bundle. 921 getParent()->erase_instr(this); 922} 923 924 925/// getNumExplicitOperands - Returns the number of non-implicit operands. 926/// 927unsigned MachineInstr::getNumExplicitOperands() const { 928 unsigned NumOperands = MCID->getNumOperands(); 929 if (!MCID->isVariadic()) 930 return NumOperands; 931 932 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 933 const MachineOperand &MO = getOperand(i); 934 if (!MO.isReg() || !MO.isImplicit()) 935 NumOperands++; 936 } 937 return NumOperands; 938} 939 940/// isBundled - Return true if this instruction part of a bundle. This is true 941/// if either itself or its following instruction is marked "InsideBundle". 942bool MachineInstr::isBundled() const { 943 if (isInsideBundle()) 944 return true; 945 MachineBasicBlock::const_instr_iterator nextMI = this; 946 ++nextMI; 947 return nextMI != Parent->instr_end() && nextMI->isInsideBundle(); 948} 949 950bool MachineInstr::isStackAligningInlineAsm() const { 951 if (isInlineAsm()) { 952 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 953 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 954 return true; 955 } 956 return false; 957} 958 959int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, 960 unsigned *GroupNo) const { 961 assert(isInlineAsm() && "Expected an inline asm instruction"); 962 assert(OpIdx < getNumOperands() && "OpIdx out of range"); 963 964 // Ignore queries about the initial operands. 965 if (OpIdx < InlineAsm::MIOp_FirstOperand) 966 return -1; 967 968 unsigned Group = 0; 969 unsigned NumOps; 970 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 971 i += NumOps) { 972 const MachineOperand &FlagMO = getOperand(i); 973 // If we reach the implicit register operands, stop looking. 974 if (!FlagMO.isImm()) 975 return -1; 976 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 977 if (i + NumOps > OpIdx) { 978 if (GroupNo) 979 *GroupNo = Group; 980 return i; 981 } 982 ++Group; 983 } 984 return -1; 985} 986 987const TargetRegisterClass* 988MachineInstr::getRegClassConstraint(unsigned OpIdx, 989 const TargetInstrInfo *TII, 990 const TargetRegisterInfo *TRI) const { 991 assert(getParent() && "Can't have an MBB reference here!"); 992 assert(getParent()->getParent() && "Can't have an MF reference here!"); 993 const MachineFunction &MF = *getParent()->getParent(); 994 995 // Most opcodes have fixed constraints in their MCInstrDesc. 996 if (!isInlineAsm()) 997 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); 998 999 if (!getOperand(OpIdx).isReg()) 1000 return NULL; 1001 1002 // For tied uses on inline asm, get the constraint from the def. 1003 unsigned DefIdx; 1004 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 1005 OpIdx = DefIdx; 1006 1007 // Inline asm stores register class constraints in the flag word. 1008 int FlagIdx = findInlineAsmFlagIdx(OpIdx); 1009 if (FlagIdx < 0) 1010 return NULL; 1011 1012 unsigned Flag = getOperand(FlagIdx).getImm(); 1013 unsigned RCID; 1014 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) 1015 return TRI->getRegClass(RCID); 1016 1017 // Assume that all registers in a memory operand are pointers. 1018 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem) 1019 return TRI->getPointerRegClass(MF); 1020 1021 return NULL; 1022} 1023 1024/// getBundleSize - Return the number of instructions inside the MI bundle. 1025unsigned MachineInstr::getBundleSize() const { 1026 assert(isBundle() && "Expecting a bundle"); 1027 1028 MachineBasicBlock::const_instr_iterator I = *this; 1029 unsigned Size = 0; 1030 while ((++I)->isInsideBundle()) { 1031 ++Size; 1032 } 1033 assert(Size > 1 && "Malformed bundle"); 1034 1035 return Size; 1036} 1037 1038/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 1039/// the specific register or -1 if it is not found. It further tightens 1040/// the search criteria to a use that kills the register if isKill is true. 1041int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 1042 const TargetRegisterInfo *TRI) const { 1043 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1044 const MachineOperand &MO = getOperand(i); 1045 if (!MO.isReg() || !MO.isUse()) 1046 continue; 1047 unsigned MOReg = MO.getReg(); 1048 if (!MOReg) 1049 continue; 1050 if (MOReg == Reg || 1051 (TRI && 1052 TargetRegisterInfo::isPhysicalRegister(MOReg) && 1053 TargetRegisterInfo::isPhysicalRegister(Reg) && 1054 TRI->isSubRegister(MOReg, Reg))) 1055 if (!isKill || MO.isKill()) 1056 return i; 1057 } 1058 return -1; 1059} 1060 1061/// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 1062/// indicating if this instruction reads or writes Reg. This also considers 1063/// partial defines. 1064std::pair<bool,bool> 1065MachineInstr::readsWritesVirtualRegister(unsigned Reg, 1066 SmallVectorImpl<unsigned> *Ops) const { 1067 bool PartDef = false; // Partial redefine. 1068 bool FullDef = false; // Full define. 1069 bool Use = false; 1070 1071 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1072 const MachineOperand &MO = getOperand(i); 1073 if (!MO.isReg() || MO.getReg() != Reg) 1074 continue; 1075 if (Ops) 1076 Ops->push_back(i); 1077 if (MO.isUse()) 1078 Use |= !MO.isUndef(); 1079 else if (MO.getSubReg() && !MO.isUndef()) 1080 // A partial <def,undef> doesn't count as reading the register. 1081 PartDef = true; 1082 else 1083 FullDef = true; 1084 } 1085 // A partial redefine uses Reg unless there is also a full define. 1086 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); 1087} 1088 1089/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 1090/// the specified register or -1 if it is not found. If isDead is true, defs 1091/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 1092/// also checks if there is a def of a super-register. 1093int 1094MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, 1095 const TargetRegisterInfo *TRI) const { 1096 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg); 1097 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1098 const MachineOperand &MO = getOperand(i); 1099 // Accept regmask operands when Overlap is set. 1100 // Ignore them when looking for a specific def operand (Overlap == false). 1101 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) 1102 return i; 1103 if (!MO.isReg() || !MO.isDef()) 1104 continue; 1105 unsigned MOReg = MO.getReg(); 1106 bool Found = (MOReg == Reg); 1107 if (!Found && TRI && isPhys && 1108 TargetRegisterInfo::isPhysicalRegister(MOReg)) { 1109 if (Overlap) 1110 Found = TRI->regsOverlap(MOReg, Reg); 1111 else 1112 Found = TRI->isSubRegister(MOReg, Reg); 1113 } 1114 if (Found && (!isDead || MO.isDead())) 1115 return i; 1116 } 1117 return -1; 1118} 1119 1120/// findFirstPredOperandIdx() - Find the index of the first operand in the 1121/// operand list that is used to represent the predicate. It returns -1 if 1122/// none is found. 1123int MachineInstr::findFirstPredOperandIdx() const { 1124 // Don't call MCID.findFirstPredOperandIdx() because this variant 1125 // is sometimes called on an instruction that's not yet complete, and 1126 // so the number of operands is less than the MCID indicates. In 1127 // particular, the PTX target does this. 1128 const MCInstrDesc &MCID = getDesc(); 1129 if (MCID.isPredicable()) { 1130 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 1131 if (MCID.OpInfo[i].isPredicate()) 1132 return i; 1133 } 1134 1135 return -1; 1136} 1137 1138/// Given the index of a tied register operand, find the operand it is tied to. 1139/// Defs are tied to uses and vice versa. Returns the index of the tied operand 1140/// which must exist. 1141unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const { 1142 // It doesn't usually happen, but an instruction can have multiple pairs of 1143 // tied operands. 1144 SmallVector<unsigned, 4> Uses, Defs; 1145 unsigned PairNo = ~0u; 1146 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1147 const MachineOperand &MO = getOperand(i); 1148 if (!MO.isReg() || !MO.isTied()) 1149 continue; 1150 if (MO.isUse()) { 1151 if (i == OpIdx) 1152 PairNo = Uses.size(); 1153 Uses.push_back(i); 1154 } else { 1155 if (i == OpIdx) 1156 PairNo = Defs.size(); 1157 Defs.push_back(i); 1158 } 1159 } 1160 // For each tied use there must be a tied def and vice versa. 1161 assert(Uses.size() == Defs.size() && "Tied uses and defs don't match"); 1162 assert(PairNo < Uses.size() && "OpIdx must be a tied register operand"); 1163 1164 // Find the matching operand. 1165 return (getOperand(OpIdx).isDef() ? Uses : Defs)[PairNo]; 1166} 1167 1168/// isRegTiedToUseOperand - Given the index of a register def operand, 1169/// check if the register def is tied to a source operand, due to either 1170/// two-address elimination or inline assembly constraints. Returns the 1171/// first tied use operand index by reference is UseOpIdx is not null. 1172bool MachineInstr:: 1173isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const { 1174 if (isInlineAsm()) { 1175 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand); 1176 const MachineOperand &MO = getOperand(DefOpIdx); 1177 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) 1178 return false; 1179 // Determine the actual operand index that corresponds to this index. 1180 unsigned DefNo = 0; 1181 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo); 1182 if (FlagIdx < 0) 1183 return false; 1184 1185 // Which part of the group is DefOpIdx? 1186 unsigned DefPart = DefOpIdx - (FlagIdx + 1); 1187 1188 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); 1189 i != e; ++i) { 1190 const MachineOperand &FMO = getOperand(i); 1191 if (!FMO.isImm()) 1192 continue; 1193 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) 1194 continue; 1195 unsigned Idx; 1196 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 1197 Idx == DefNo) { 1198 if (UseOpIdx) 1199 *UseOpIdx = (unsigned)i + 1 + DefPart; 1200 return true; 1201 } 1202 } 1203 return false; 1204 } 1205 1206 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); 1207 const MCInstrDesc &MCID = getDesc(); 1208 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { 1209 const MachineOperand &MO = getOperand(i); 1210 if (MO.isReg() && MO.isUse() && 1211 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) { 1212 if (UseOpIdx) 1213 *UseOpIdx = (unsigned)i; 1214 return true; 1215 } 1216 } 1217 return false; 1218} 1219 1220/// isRegTiedToDefOperand - Return true if the operand of the specified index 1221/// is a register use and it is tied to an def operand. It also returns the def 1222/// operand index by reference. 1223bool MachineInstr:: 1224isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { 1225 if (isInlineAsm()) { 1226 const MachineOperand &MO = getOperand(UseOpIdx); 1227 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) 1228 return false; 1229 1230 // Find the flag operand corresponding to UseOpIdx 1231 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx); 1232 if (FlagIdx < 0) 1233 return false; 1234 1235 const MachineOperand &UFMO = getOperand(FlagIdx); 1236 unsigned DefNo; 1237 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { 1238 if (!DefOpIdx) 1239 return true; 1240 1241 unsigned DefIdx = InlineAsm::MIOp_FirstOperand; 1242 // Remember to adjust the index. First operand is asm string, second is 1243 // the HasSideEffects and AlignStack bits, then there is a flag for each. 1244 while (DefNo) { 1245 const MachineOperand &FMO = getOperand(DefIdx); 1246 assert(FMO.isImm()); 1247 // Skip over this def. 1248 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; 1249 --DefNo; 1250 } 1251 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; 1252 return true; 1253 } 1254 return false; 1255 } 1256 1257 const MCInstrDesc &MCID = getDesc(); 1258 if (UseOpIdx >= MCID.getNumOperands()) 1259 return false; 1260 const MachineOperand &MO = getOperand(UseOpIdx); 1261 if (!MO.isReg() || !MO.isUse()) 1262 return false; 1263 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO); 1264 if (DefIdx == -1) 1265 return false; 1266 if (DefOpIdx) 1267 *DefOpIdx = (unsigned)DefIdx; 1268 return true; 1269} 1270 1271/// clearKillInfo - Clears kill flags on all operands. 1272/// 1273void MachineInstr::clearKillInfo() { 1274 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1275 MachineOperand &MO = getOperand(i); 1276 if (MO.isReg() && MO.isUse()) 1277 MO.setIsKill(false); 1278 } 1279} 1280 1281/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 1282/// 1283void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 1284 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1285 const MachineOperand &MO = MI->getOperand(i); 1286 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 1287 continue; 1288 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 1289 MachineOperand &MOp = getOperand(j); 1290 if (!MOp.isIdenticalTo(MO)) 1291 continue; 1292 if (MO.isKill()) 1293 MOp.setIsKill(); 1294 else 1295 MOp.setIsDead(); 1296 break; 1297 } 1298 } 1299} 1300 1301/// copyPredicates - Copies predicate operand(s) from MI. 1302void MachineInstr::copyPredicates(const MachineInstr *MI) { 1303 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles"); 1304 1305 const MCInstrDesc &MCID = MI->getDesc(); 1306 if (!MCID.isPredicable()) 1307 return; 1308 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1309 if (MCID.OpInfo[i].isPredicate()) { 1310 // Predicated operands must be last operands. 1311 addOperand(MI->getOperand(i)); 1312 } 1313 } 1314} 1315 1316void MachineInstr::substituteRegister(unsigned FromReg, 1317 unsigned ToReg, 1318 unsigned SubIdx, 1319 const TargetRegisterInfo &RegInfo) { 1320 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) { 1321 if (SubIdx) 1322 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1323 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1324 MachineOperand &MO = getOperand(i); 1325 if (!MO.isReg() || MO.getReg() != FromReg) 1326 continue; 1327 MO.substPhysReg(ToReg, RegInfo); 1328 } 1329 } else { 1330 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1331 MachineOperand &MO = getOperand(i); 1332 if (!MO.isReg() || MO.getReg() != FromReg) 1333 continue; 1334 MO.substVirtReg(ToReg, SubIdx, RegInfo); 1335 } 1336 } 1337} 1338 1339/// isSafeToMove - Return true if it is safe to move this instruction. If 1340/// SawStore is set to true, it means that there is a store (or call) between 1341/// the instruction's location and its intended destination. 1342bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 1343 AliasAnalysis *AA, 1344 bool &SawStore) const { 1345 // Ignore stuff that we obviously can't move. 1346 // 1347 // Treat volatile loads as stores. This is not strictly necessary for 1348 // volatiles, but it is required for atomic loads. It is now allowed to move 1349 // a load across an atomic load with Ordering > Monotonic. 1350 if (mayStore() || isCall() || 1351 (mayLoad() && hasVolatileMemoryRef())) { 1352 SawStore = true; 1353 return false; 1354 } 1355 1356 if (isLabel() || isDebugValue() || 1357 isTerminator() || hasUnmodeledSideEffects()) 1358 return false; 1359 1360 // See if this instruction does a load. If so, we have to guarantee that the 1361 // loaded value doesn't change between the load and the its intended 1362 // destination. The check for isInvariantLoad gives the targe the chance to 1363 // classify the load as always returning a constant, e.g. a constant pool 1364 // load. 1365 if (mayLoad() && !isInvariantLoad(AA)) 1366 // Otherwise, this is a real load. If there is a store between the load and 1367 // end of block, we can't move it. 1368 return !SawStore; 1369 1370 return true; 1371} 1372 1373/// isSafeToReMat - Return true if it's safe to rematerialize the specified 1374/// instruction which defined the specified register instead of copying it. 1375bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 1376 AliasAnalysis *AA, 1377 unsigned DstReg) const { 1378 bool SawStore = false; 1379 if (!TII->isTriviallyReMaterializable(this, AA) || 1380 !isSafeToMove(TII, AA, SawStore)) 1381 return false; 1382 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1383 const MachineOperand &MO = getOperand(i); 1384 if (!MO.isReg()) 1385 continue; 1386 // FIXME: For now, do not remat any instruction with register operands. 1387 // Later on, we can loosen the restriction is the register operands have 1388 // not been modified between the def and use. Note, this is different from 1389 // MachineSink because the code is no longer in two-address form (at least 1390 // partially). 1391 if (MO.isUse()) 1392 return false; 1393 else if (!MO.isDead() && MO.getReg() != DstReg) 1394 return false; 1395 } 1396 return true; 1397} 1398 1399/// hasVolatileMemoryRef - Return true if this instruction may have a 1400/// volatile memory reference, or if the information describing the 1401/// memory reference is not available. Return false if it is known to 1402/// have no volatile memory references. 1403bool MachineInstr::hasVolatileMemoryRef() const { 1404 // An instruction known never to access memory won't have a volatile access. 1405 if (!mayStore() && 1406 !mayLoad() && 1407 !isCall() && 1408 !hasUnmodeledSideEffects()) 1409 return false; 1410 1411 // Otherwise, if the instruction has no memory reference information, 1412 // conservatively assume it wasn't preserved. 1413 if (memoperands_empty()) 1414 return true; 1415 1416 // Check the memory reference information for volatile references. 1417 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1418 if ((*I)->isVolatile()) 1419 return true; 1420 1421 return false; 1422} 1423 1424/// isInvariantLoad - Return true if this instruction is loading from a 1425/// location whose value is invariant across the function. For example, 1426/// loading a value from the constant pool or from the argument area 1427/// of a function if it does not change. This should only return true of 1428/// *all* loads the instruction does are invariant (if it does multiple loads). 1429bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1430 // If the instruction doesn't load at all, it isn't an invariant load. 1431 if (!mayLoad()) 1432 return false; 1433 1434 // If the instruction has lost its memoperands, conservatively assume that 1435 // it may not be an invariant load. 1436 if (memoperands_empty()) 1437 return false; 1438 1439 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1440 1441 for (mmo_iterator I = memoperands_begin(), 1442 E = memoperands_end(); I != E; ++I) { 1443 if ((*I)->isVolatile()) return false; 1444 if ((*I)->isStore()) return false; 1445 if ((*I)->isInvariant()) return true; 1446 1447 if (const Value *V = (*I)->getValue()) { 1448 // A load from a constant PseudoSourceValue is invariant. 1449 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1450 if (PSV->isConstant(MFI)) 1451 continue; 1452 // If we have an AliasAnalysis, ask it whether the memory is constant. 1453 if (AA && AA->pointsToConstantMemory( 1454 AliasAnalysis::Location(V, (*I)->getSize(), 1455 (*I)->getTBAAInfo()))) 1456 continue; 1457 } 1458 1459 // Otherwise assume conservatively. 1460 return false; 1461 } 1462 1463 // Everything checks out. 1464 return true; 1465} 1466 1467/// isConstantValuePHI - If the specified instruction is a PHI that always 1468/// merges together the same virtual register, return the register, otherwise 1469/// return 0. 1470unsigned MachineInstr::isConstantValuePHI() const { 1471 if (!isPHI()) 1472 return 0; 1473 assert(getNumOperands() >= 3 && 1474 "It's illegal to have a PHI without source operands"); 1475 1476 unsigned Reg = getOperand(1).getReg(); 1477 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1478 if (getOperand(i).getReg() != Reg) 1479 return 0; 1480 return Reg; 1481} 1482 1483bool MachineInstr::hasUnmodeledSideEffects() const { 1484 if (hasProperty(MCID::UnmodeledSideEffects)) 1485 return true; 1486 if (isInlineAsm()) { 1487 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1488 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1489 return true; 1490 } 1491 1492 return false; 1493} 1494 1495/// allDefsAreDead - Return true if all the defs of this instruction are dead. 1496/// 1497bool MachineInstr::allDefsAreDead() const { 1498 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { 1499 const MachineOperand &MO = getOperand(i); 1500 if (!MO.isReg() || MO.isUse()) 1501 continue; 1502 if (!MO.isDead()) 1503 return false; 1504 } 1505 return true; 1506} 1507 1508/// copyImplicitOps - Copy implicit register operands from specified 1509/// instruction to this instruction. 1510void MachineInstr::copyImplicitOps(const MachineInstr *MI) { 1511 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands(); 1512 i != e; ++i) { 1513 const MachineOperand &MO = MI->getOperand(i); 1514 if (MO.isReg() && MO.isImplicit()) 1515 addOperand(MO); 1516 } 1517} 1518 1519void MachineInstr::dump() const { 1520 dbgs() << " " << *this; 1521} 1522 1523static void printDebugLoc(DebugLoc DL, const MachineFunction *MF, 1524 raw_ostream &CommentOS) { 1525 const LLVMContext &Ctx = MF->getFunction()->getContext(); 1526 if (!DL.isUnknown()) { // Print source line info. 1527 DIScope Scope(DL.getScope(Ctx)); 1528 // Omit the directory, because it's likely to be long and uninteresting. 1529 if (Scope.Verify()) 1530 CommentOS << Scope.getFilename(); 1531 else 1532 CommentOS << "<unknown>"; 1533 CommentOS << ':' << DL.getLine(); 1534 if (DL.getCol() != 0) 1535 CommentOS << ':' << DL.getCol(); 1536 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx)); 1537 if (!InlinedAtDL.isUnknown()) { 1538 CommentOS << " @[ "; 1539 printDebugLoc(InlinedAtDL, MF, CommentOS); 1540 CommentOS << " ]"; 1541 } 1542 } 1543} 1544 1545void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1546 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1547 const MachineFunction *MF = 0; 1548 const MachineRegisterInfo *MRI = 0; 1549 if (const MachineBasicBlock *MBB = getParent()) { 1550 MF = MBB->getParent(); 1551 if (!TM && MF) 1552 TM = &MF->getTarget(); 1553 if (MF) 1554 MRI = &MF->getRegInfo(); 1555 } 1556 1557 // Save a list of virtual registers. 1558 SmallVector<unsigned, 8> VirtRegs; 1559 1560 // Print explicitly defined operands on the left of an assignment syntax. 1561 unsigned StartOp = 0, e = getNumOperands(); 1562 for (; StartOp < e && getOperand(StartOp).isReg() && 1563 getOperand(StartOp).isDef() && 1564 !getOperand(StartOp).isImplicit(); 1565 ++StartOp) { 1566 if (StartOp != 0) OS << ", "; 1567 getOperand(StartOp).print(OS, TM); 1568 unsigned Reg = getOperand(StartOp).getReg(); 1569 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1570 VirtRegs.push_back(Reg); 1571 } 1572 1573 if (StartOp != 0) 1574 OS << " = "; 1575 1576 // Print the opcode name. 1577 if (TM && TM->getInstrInfo()) 1578 OS << TM->getInstrInfo()->getName(getOpcode()); 1579 else 1580 OS << "UNKNOWN"; 1581 1582 // Print the rest of the operands. 1583 bool OmittedAnyCallClobbers = false; 1584 bool FirstOp = true; 1585 unsigned AsmDescOp = ~0u; 1586 unsigned AsmOpCount = 0; 1587 1588 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { 1589 // Print asm string. 1590 OS << " "; 1591 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM); 1592 1593 // Print HasSideEffects, IsAlignStack 1594 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1595 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1596 OS << " [sideeffect]"; 1597 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 1598 OS << " [alignstack]"; 1599 1600 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; 1601 FirstOp = false; 1602 } 1603 1604 1605 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1606 const MachineOperand &MO = getOperand(i); 1607 1608 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1609 VirtRegs.push_back(MO.getReg()); 1610 1611 // Omit call-clobbered registers which aren't used anywhere. This makes 1612 // call instructions much less noisy on targets where calls clobber lots 1613 // of registers. Don't rely on MO.isDead() because we may be called before 1614 // LiveVariables is run, or we may be looking at a non-allocatable reg. 1615 if (MF && isCall() && 1616 MO.isReg() && MO.isImplicit() && MO.isDef()) { 1617 unsigned Reg = MO.getReg(); 1618 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 1619 const MachineRegisterInfo &MRI = MF->getRegInfo(); 1620 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1621 bool HasAliasLive = false; 1622 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true); 1623 AI.isValid(); ++AI) { 1624 unsigned AliasReg = *AI; 1625 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1626 HasAliasLive = true; 1627 break; 1628 } 1629 } 1630 if (!HasAliasLive) { 1631 OmittedAnyCallClobbers = true; 1632 continue; 1633 } 1634 } 1635 } 1636 } 1637 1638 if (FirstOp) FirstOp = false; else OS << ","; 1639 OS << " "; 1640 if (i < getDesc().NumOperands) { 1641 const MCOperandInfo &MCOI = getDesc().OpInfo[i]; 1642 if (MCOI.isPredicate()) 1643 OS << "pred:"; 1644 if (MCOI.isOptionalDef()) 1645 OS << "opt:"; 1646 } 1647 if (isDebugValue() && MO.isMetadata()) { 1648 // Pretty print DBG_VALUE instructions. 1649 const MDNode *MD = MO.getMetadata(); 1650 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2))) 1651 OS << "!\"" << MDS->getString() << '\"'; 1652 else 1653 MO.print(OS, TM); 1654 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { 1655 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm()); 1656 } else if (i == AsmDescOp && MO.isImm()) { 1657 // Pretty print the inline asm operand descriptor. 1658 OS << '$' << AsmOpCount++; 1659 unsigned Flag = MO.getImm(); 1660 switch (InlineAsm::getKind(Flag)) { 1661 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break; 1662 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break; 1663 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; 1664 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break; 1665 case InlineAsm::Kind_Imm: OS << ":[imm"; break; 1666 case InlineAsm::Kind_Mem: OS << ":[mem"; break; 1667 default: OS << ":[??" << InlineAsm::getKind(Flag); break; 1668 } 1669 1670 unsigned RCID = 0; 1671 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { 1672 if (TM) 1673 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName(); 1674 else 1675 OS << ":RC" << RCID; 1676 } 1677 1678 unsigned TiedTo = 0; 1679 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) 1680 OS << " tiedto:$" << TiedTo; 1681 1682 OS << ']'; 1683 1684 // Compute the index of the next operand descriptor. 1685 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); 1686 } else 1687 MO.print(OS, TM); 1688 } 1689 1690 // Briefly indicate whether any call clobbers were omitted. 1691 if (OmittedAnyCallClobbers) { 1692 if (!FirstOp) OS << ","; 1693 OS << " ..."; 1694 } 1695 1696 bool HaveSemi = false; 1697 if (Flags) { 1698 if (!HaveSemi) OS << ";"; HaveSemi = true; 1699 OS << " flags: "; 1700 1701 if (Flags & FrameSetup) 1702 OS << "FrameSetup"; 1703 } 1704 1705 if (!memoperands_empty()) { 1706 if (!HaveSemi) OS << ";"; HaveSemi = true; 1707 1708 OS << " mem:"; 1709 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1710 i != e; ++i) { 1711 OS << **i; 1712 if (llvm::next(i) != e) 1713 OS << " "; 1714 } 1715 } 1716 1717 // Print the regclass of any virtual registers encountered. 1718 if (MRI && !VirtRegs.empty()) { 1719 if (!HaveSemi) OS << ";"; HaveSemi = true; 1720 for (unsigned i = 0; i != VirtRegs.size(); ++i) { 1721 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]); 1722 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]); 1723 for (unsigned j = i+1; j != VirtRegs.size();) { 1724 if (MRI->getRegClass(VirtRegs[j]) != RC) { 1725 ++j; 1726 continue; 1727 } 1728 if (VirtRegs[i] != VirtRegs[j]) 1729 OS << "," << PrintReg(VirtRegs[j]); 1730 VirtRegs.erase(VirtRegs.begin()+j); 1731 } 1732 } 1733 } 1734 1735 // Print debug location information. 1736 if (isDebugValue() && getOperand(e - 1).isMetadata()) { 1737 if (!HaveSemi) OS << ";"; HaveSemi = true; 1738 DIVariable DV(getOperand(e - 1).getMetadata()); 1739 OS << " line no:" << DV.getLineNumber(); 1740 if (MDNode *InlinedAt = DV.getInlinedAt()) { 1741 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt); 1742 if (!InlinedAtDL.isUnknown()) { 1743 OS << " inlined @[ "; 1744 printDebugLoc(InlinedAtDL, MF, OS); 1745 OS << " ]"; 1746 } 1747 } 1748 } else if (!debugLoc.isUnknown() && MF) { 1749 if (!HaveSemi) OS << ";"; HaveSemi = true; 1750 OS << " dbg:"; 1751 printDebugLoc(debugLoc, MF, OS); 1752 } 1753 1754 OS << '\n'; 1755} 1756 1757bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1758 const TargetRegisterInfo *RegInfo, 1759 bool AddIfNotFound) { 1760 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1761 bool hasAliases = isPhysReg && 1762 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1763 bool Found = false; 1764 SmallVector<unsigned,4> DeadOps; 1765 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1766 MachineOperand &MO = getOperand(i); 1767 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1768 continue; 1769 unsigned Reg = MO.getReg(); 1770 if (!Reg) 1771 continue; 1772 1773 if (Reg == IncomingReg) { 1774 if (!Found) { 1775 if (MO.isKill()) 1776 // The register is already marked kill. 1777 return true; 1778 if (isPhysReg && isRegTiedToDefOperand(i)) 1779 // Two-address uses of physregs must not be marked kill. 1780 return true; 1781 MO.setIsKill(); 1782 Found = true; 1783 } 1784 } else if (hasAliases && MO.isKill() && 1785 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1786 // A super-register kill already exists. 1787 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1788 return true; 1789 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1790 DeadOps.push_back(i); 1791 } 1792 } 1793 1794 // Trim unneeded kill operands. 1795 while (!DeadOps.empty()) { 1796 unsigned OpIdx = DeadOps.back(); 1797 if (getOperand(OpIdx).isImplicit()) 1798 RemoveOperand(OpIdx); 1799 else 1800 getOperand(OpIdx).setIsKill(false); 1801 DeadOps.pop_back(); 1802 } 1803 1804 // If not found, this means an alias of one of the operands is killed. Add a 1805 // new implicit operand if required. 1806 if (!Found && AddIfNotFound) { 1807 addOperand(MachineOperand::CreateReg(IncomingReg, 1808 false /*IsDef*/, 1809 true /*IsImp*/, 1810 true /*IsKill*/)); 1811 return true; 1812 } 1813 return Found; 1814} 1815 1816void MachineInstr::clearRegisterKills(unsigned Reg, 1817 const TargetRegisterInfo *RegInfo) { 1818 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) 1819 RegInfo = 0; 1820 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1821 MachineOperand &MO = getOperand(i); 1822 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) 1823 continue; 1824 unsigned OpReg = MO.getReg(); 1825 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg))) 1826 MO.setIsKill(false); 1827 } 1828} 1829 1830bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1831 const TargetRegisterInfo *RegInfo, 1832 bool AddIfNotFound) { 1833 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1834 bool hasAliases = isPhysReg && 1835 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1836 bool Found = false; 1837 SmallVector<unsigned,4> DeadOps; 1838 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1839 MachineOperand &MO = getOperand(i); 1840 if (!MO.isReg() || !MO.isDef()) 1841 continue; 1842 unsigned Reg = MO.getReg(); 1843 if (!Reg) 1844 continue; 1845 1846 if (Reg == IncomingReg) { 1847 MO.setIsDead(); 1848 Found = true; 1849 } else if (hasAliases && MO.isDead() && 1850 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1851 // There exists a super-register that's marked dead. 1852 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1853 return true; 1854 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1855 DeadOps.push_back(i); 1856 } 1857 } 1858 1859 // Trim unneeded dead operands. 1860 while (!DeadOps.empty()) { 1861 unsigned OpIdx = DeadOps.back(); 1862 if (getOperand(OpIdx).isImplicit()) 1863 RemoveOperand(OpIdx); 1864 else 1865 getOperand(OpIdx).setIsDead(false); 1866 DeadOps.pop_back(); 1867 } 1868 1869 // If not found, this means an alias of one of the operands is dead. Add a 1870 // new implicit operand if required. 1871 if (Found || !AddIfNotFound) 1872 return Found; 1873 1874 addOperand(MachineOperand::CreateReg(IncomingReg, 1875 true /*IsDef*/, 1876 true /*IsImp*/, 1877 false /*IsKill*/, 1878 true /*IsDead*/)); 1879 return true; 1880} 1881 1882void MachineInstr::addRegisterDefined(unsigned IncomingReg, 1883 const TargetRegisterInfo *RegInfo) { 1884 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { 1885 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1886 if (MO) 1887 return; 1888 } else { 1889 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1890 const MachineOperand &MO = getOperand(i); 1891 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() && 1892 MO.getSubReg() == 0) 1893 return; 1894 } 1895 } 1896 addOperand(MachineOperand::CreateReg(IncomingReg, 1897 true /*IsDef*/, 1898 true /*IsImp*/)); 1899} 1900 1901void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, 1902 const TargetRegisterInfo &TRI) { 1903 bool HasRegMask = false; 1904 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1905 MachineOperand &MO = getOperand(i); 1906 if (MO.isRegMask()) { 1907 HasRegMask = true; 1908 continue; 1909 } 1910 if (!MO.isReg() || !MO.isDef()) continue; 1911 unsigned Reg = MO.getReg(); 1912 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 1913 bool Dead = true; 1914 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 1915 I != E; ++I) 1916 if (TRI.regsOverlap(*I, Reg)) { 1917 Dead = false; 1918 break; 1919 } 1920 // If there are no uses, including partial uses, the def is dead. 1921 if (Dead) MO.setIsDead(); 1922 } 1923 1924 // This is a call with a register mask operand. 1925 // Mask clobbers are always dead, so add defs for the non-dead defines. 1926 if (HasRegMask) 1927 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 1928 I != E; ++I) 1929 addRegisterDefined(*I, &TRI); 1930} 1931 1932unsigned 1933MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { 1934 // Build up a buffer of hash code components. 1935 SmallVector<size_t, 8> HashComponents; 1936 HashComponents.reserve(MI->getNumOperands() + 1); 1937 HashComponents.push_back(MI->getOpcode()); 1938 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1939 const MachineOperand &MO = MI->getOperand(i); 1940 if (MO.isReg() && MO.isDef() && 1941 TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1942 continue; // Skip virtual register defs. 1943 1944 HashComponents.push_back(hash_value(MO)); 1945 } 1946 return hash_combine_range(HashComponents.begin(), HashComponents.end()); 1947} 1948 1949void MachineInstr::emitError(StringRef Msg) const { 1950 // Find the source location cookie. 1951 unsigned LocCookie = 0; 1952 const MDNode *LocMD = 0; 1953 for (unsigned i = getNumOperands(); i != 0; --i) { 1954 if (getOperand(i-1).isMetadata() && 1955 (LocMD = getOperand(i-1).getMetadata()) && 1956 LocMD->getNumOperands() != 0) { 1957 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) { 1958 LocCookie = CI->getZExtValue(); 1959 break; 1960 } 1961 } 1962 } 1963 1964 if (const MachineBasicBlock *MBB = getParent()) 1965 if (const MachineFunction *MF = MBB->getParent()) 1966 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); 1967 report_fatal_error(Msg); 1968} 1969