MachineInstr.cpp revision 25377c8c6dafd094f17833f2c37daff0b77a16fc 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/ADT/FoldingSet.h"
16#include "llvm/ADT/Hashing.h"
17#include "llvm/Analysis/AliasAnalysis.h"
18#include "llvm/Assembly/Writer.h"
19#include "llvm/CodeGen/MachineConstantPool.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/CodeGen/MachineModuleInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/PseudoSourceValue.h"
25#include "llvm/DebugInfo.h"
26#include "llvm/IR/Constants.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/IR/LLVMContext.h"
30#include "llvm/IR/Metadata.h"
31#include "llvm/IR/Module.h"
32#include "llvm/IR/Type.h"
33#include "llvm/IR/Value.h"
34#include "llvm/MC/MCInstrDesc.h"
35#include "llvm/MC/MCSymbol.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/MathExtras.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/Target/TargetInstrInfo.h"
41#include "llvm/Target/TargetMachine.h"
42#include "llvm/Target/TargetRegisterInfo.h"
43using namespace llvm;
44
45//===----------------------------------------------------------------------===//
46// MachineOperand Implementation
47//===----------------------------------------------------------------------===//
48
49void MachineOperand::setReg(unsigned Reg) {
50  if (getReg() == Reg) return; // No change.
51
52  // Otherwise, we have to change the register.  If this operand is embedded
53  // into a machine function, we need to update the old and new register's
54  // use/def lists.
55  if (MachineInstr *MI = getParent())
56    if (MachineBasicBlock *MBB = MI->getParent())
57      if (MachineFunction *MF = MBB->getParent()) {
58        MachineRegisterInfo &MRI = MF->getRegInfo();
59        MRI.removeRegOperandFromUseList(this);
60        SmallContents.RegNo = Reg;
61        MRI.addRegOperandToUseList(this);
62        return;
63      }
64
65  // Otherwise, just change the register, no problem.  :)
66  SmallContents.RegNo = Reg;
67}
68
69void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
70                                  const TargetRegisterInfo &TRI) {
71  assert(TargetRegisterInfo::isVirtualRegister(Reg));
72  if (SubIdx && getSubReg())
73    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
74  setReg(Reg);
75  if (SubIdx)
76    setSubReg(SubIdx);
77}
78
79void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
80  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
81  if (getSubReg()) {
82    Reg = TRI.getSubReg(Reg, getSubReg());
83    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
84    // That won't happen in legal code.
85    setSubReg(0);
86  }
87  setReg(Reg);
88}
89
90/// Change a def to a use, or a use to a def.
91void MachineOperand::setIsDef(bool Val) {
92  assert(isReg() && "Wrong MachineOperand accessor");
93  assert((!Val || !isDebug()) && "Marking a debug operation as def");
94  if (IsDef == Val)
95    return;
96  // MRI may keep uses and defs in different list positions.
97  if (MachineInstr *MI = getParent())
98    if (MachineBasicBlock *MBB = MI->getParent())
99      if (MachineFunction *MF = MBB->getParent()) {
100        MachineRegisterInfo &MRI = MF->getRegInfo();
101        MRI.removeRegOperandFromUseList(this);
102        IsDef = Val;
103        MRI.addRegOperandToUseList(this);
104        return;
105      }
106  IsDef = Val;
107}
108
109/// ChangeToImmediate - Replace this operand with a new immediate operand of
110/// the specified value.  If an operand is known to be an immediate already,
111/// the setImm method should be used.
112void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
113  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
114  // If this operand is currently a register operand, and if this is in a
115  // function, deregister the operand from the register's use/def list.
116  if (isReg() && isOnRegUseList())
117    if (MachineInstr *MI = getParent())
118      if (MachineBasicBlock *MBB = MI->getParent())
119        if (MachineFunction *MF = MBB->getParent())
120          MF->getRegInfo().removeRegOperandFromUseList(this);
121
122  OpKind = MO_Immediate;
123  Contents.ImmVal = ImmVal;
124}
125
126/// ChangeToRegister - Replace this operand with a new register operand of
127/// the specified value.  If an operand is known to be an register already,
128/// the setReg method should be used.
129void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
130                                      bool isKill, bool isDead, bool isUndef,
131                                      bool isDebug) {
132  MachineRegisterInfo *RegInfo = 0;
133  if (MachineInstr *MI = getParent())
134    if (MachineBasicBlock *MBB = MI->getParent())
135      if (MachineFunction *MF = MBB->getParent())
136        RegInfo = &MF->getRegInfo();
137  // If this operand is already a register operand, remove it from the
138  // register's use/def lists.
139  bool WasReg = isReg();
140  if (RegInfo && WasReg)
141    RegInfo->removeRegOperandFromUseList(this);
142
143  // Change this to a register and set the reg#.
144  OpKind = MO_Register;
145  SmallContents.RegNo = Reg;
146  SubReg_TargetFlags = 0;
147  IsDef = isDef;
148  IsImp = isImp;
149  IsKill = isKill;
150  IsDead = isDead;
151  IsUndef = isUndef;
152  IsInternalRead = false;
153  IsEarlyClobber = false;
154  IsDebug = isDebug;
155  // Ensure isOnRegUseList() returns false.
156  Contents.Reg.Prev = 0;
157  // Preserve the tie when the operand was already a register.
158  if (!WasReg)
159    TiedTo = 0;
160
161  // If this operand is embedded in a function, add the operand to the
162  // register's use/def list.
163  if (RegInfo)
164    RegInfo->addRegOperandToUseList(this);
165}
166
167/// isIdenticalTo - Return true if this operand is identical to the specified
168/// operand. Note that this should stay in sync with the hash_value overload
169/// below.
170bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
171  if (getType() != Other.getType() ||
172      getTargetFlags() != Other.getTargetFlags())
173    return false;
174
175  switch (getType()) {
176  case MachineOperand::MO_Register:
177    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
178           getSubReg() == Other.getSubReg();
179  case MachineOperand::MO_Immediate:
180    return getImm() == Other.getImm();
181  case MachineOperand::MO_CImmediate:
182    return getCImm() == Other.getCImm();
183  case MachineOperand::MO_FPImmediate:
184    return getFPImm() == Other.getFPImm();
185  case MachineOperand::MO_MachineBasicBlock:
186    return getMBB() == Other.getMBB();
187  case MachineOperand::MO_FrameIndex:
188    return getIndex() == Other.getIndex();
189  case MachineOperand::MO_ConstantPoolIndex:
190  case MachineOperand::MO_TargetIndex:
191    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
192  case MachineOperand::MO_JumpTableIndex:
193    return getIndex() == Other.getIndex();
194  case MachineOperand::MO_GlobalAddress:
195    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
196  case MachineOperand::MO_ExternalSymbol:
197    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
198           getOffset() == Other.getOffset();
199  case MachineOperand::MO_BlockAddress:
200    return getBlockAddress() == Other.getBlockAddress() &&
201           getOffset() == Other.getOffset();
202  case MO_RegisterMask:
203    return getRegMask() == Other.getRegMask();
204  case MachineOperand::MO_MCSymbol:
205    return getMCSymbol() == Other.getMCSymbol();
206  case MachineOperand::MO_Metadata:
207    return getMetadata() == Other.getMetadata();
208  }
209  llvm_unreachable("Invalid machine operand type");
210}
211
212// Note: this must stay exactly in sync with isIdenticalTo above.
213hash_code llvm::hash_value(const MachineOperand &MO) {
214  switch (MO.getType()) {
215  case MachineOperand::MO_Register:
216    // Register operands don't have target flags.
217    return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
218  case MachineOperand::MO_Immediate:
219    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
220  case MachineOperand::MO_CImmediate:
221    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
222  case MachineOperand::MO_FPImmediate:
223    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
224  case MachineOperand::MO_MachineBasicBlock:
225    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
226  case MachineOperand::MO_FrameIndex:
227    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
228  case MachineOperand::MO_ConstantPoolIndex:
229  case MachineOperand::MO_TargetIndex:
230    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
231                        MO.getOffset());
232  case MachineOperand::MO_JumpTableIndex:
233    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
234  case MachineOperand::MO_ExternalSymbol:
235    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
236                        MO.getSymbolName());
237  case MachineOperand::MO_GlobalAddress:
238    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
239                        MO.getOffset());
240  case MachineOperand::MO_BlockAddress:
241    return hash_combine(MO.getType(), MO.getTargetFlags(),
242                        MO.getBlockAddress(), MO.getOffset());
243  case MachineOperand::MO_RegisterMask:
244    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
245  case MachineOperand::MO_Metadata:
246    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
247  case MachineOperand::MO_MCSymbol:
248    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
249  }
250  llvm_unreachable("Invalid machine operand type");
251}
252
253/// print - Print the specified machine operand.
254///
255void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
256  // If the instruction is embedded into a basic block, we can find the
257  // target info for the instruction.
258  if (!TM)
259    if (const MachineInstr *MI = getParent())
260      if (const MachineBasicBlock *MBB = MI->getParent())
261        if (const MachineFunction *MF = MBB->getParent())
262          TM = &MF->getTarget();
263  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
264
265  switch (getType()) {
266  case MachineOperand::MO_Register:
267    OS << PrintReg(getReg(), TRI, getSubReg());
268
269    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
270        isInternalRead() || isEarlyClobber() || isTied()) {
271      OS << '<';
272      bool NeedComma = false;
273      if (isDef()) {
274        if (NeedComma) OS << ',';
275        if (isEarlyClobber())
276          OS << "earlyclobber,";
277        if (isImplicit())
278          OS << "imp-";
279        OS << "def";
280        NeedComma = true;
281        // <def,read-undef> only makes sense when getSubReg() is set.
282        // Don't clutter the output otherwise.
283        if (isUndef() && getSubReg())
284          OS << ",read-undef";
285      } else if (isImplicit()) {
286          OS << "imp-use";
287          NeedComma = true;
288      }
289
290      if (isKill()) {
291        if (NeedComma) OS << ',';
292        OS << "kill";
293        NeedComma = true;
294      }
295      if (isDead()) {
296        if (NeedComma) OS << ',';
297        OS << "dead";
298        NeedComma = true;
299      }
300      if (isUndef() && isUse()) {
301        if (NeedComma) OS << ',';
302        OS << "undef";
303        NeedComma = true;
304      }
305      if (isInternalRead()) {
306        if (NeedComma) OS << ',';
307        OS << "internal";
308        NeedComma = true;
309      }
310      if (isTied()) {
311        if (NeedComma) OS << ',';
312        OS << "tied";
313        if (TiedTo != 15)
314          OS << unsigned(TiedTo - 1);
315        NeedComma = true;
316      }
317      OS << '>';
318    }
319    break;
320  case MachineOperand::MO_Immediate:
321    OS << getImm();
322    break;
323  case MachineOperand::MO_CImmediate:
324    getCImm()->getValue().print(OS, false);
325    break;
326  case MachineOperand::MO_FPImmediate:
327    if (getFPImm()->getType()->isFloatTy())
328      OS << getFPImm()->getValueAPF().convertToFloat();
329    else
330      OS << getFPImm()->getValueAPF().convertToDouble();
331    break;
332  case MachineOperand::MO_MachineBasicBlock:
333    OS << "<BB#" << getMBB()->getNumber() << ">";
334    break;
335  case MachineOperand::MO_FrameIndex:
336    OS << "<fi#" << getIndex() << '>';
337    break;
338  case MachineOperand::MO_ConstantPoolIndex:
339    OS << "<cp#" << getIndex();
340    if (getOffset()) OS << "+" << getOffset();
341    OS << '>';
342    break;
343  case MachineOperand::MO_TargetIndex:
344    OS << "<ti#" << getIndex();
345    if (getOffset()) OS << "+" << getOffset();
346    OS << '>';
347    break;
348  case MachineOperand::MO_JumpTableIndex:
349    OS << "<jt#" << getIndex() << '>';
350    break;
351  case MachineOperand::MO_GlobalAddress:
352    OS << "<ga:";
353    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
354    if (getOffset()) OS << "+" << getOffset();
355    OS << '>';
356    break;
357  case MachineOperand::MO_ExternalSymbol:
358    OS << "<es:" << getSymbolName();
359    if (getOffset()) OS << "+" << getOffset();
360    OS << '>';
361    break;
362  case MachineOperand::MO_BlockAddress:
363    OS << '<';
364    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
365    if (getOffset()) OS << "+" << getOffset();
366    OS << '>';
367    break;
368  case MachineOperand::MO_RegisterMask:
369    OS << "<regmask>";
370    break;
371  case MachineOperand::MO_Metadata:
372    OS << '<';
373    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
374    OS << '>';
375    break;
376  case MachineOperand::MO_MCSymbol:
377    OS << "<MCSym=" << *getMCSymbol() << '>';
378    break;
379  }
380
381  if (unsigned TF = getTargetFlags())
382    OS << "[TF=" << TF << ']';
383}
384
385//===----------------------------------------------------------------------===//
386// MachineMemOperand Implementation
387//===----------------------------------------------------------------------===//
388
389/// getAddrSpace - Return the LLVM IR address space number that this pointer
390/// points into.
391unsigned MachinePointerInfo::getAddrSpace() const {
392  if (V == 0) return 0;
393  return cast<PointerType>(V->getType())->getAddressSpace();
394}
395
396/// getConstantPool - Return a MachinePointerInfo record that refers to the
397/// constant pool.
398MachinePointerInfo MachinePointerInfo::getConstantPool() {
399  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
400}
401
402/// getFixedStack - Return a MachinePointerInfo record that refers to the
403/// the specified FrameIndex.
404MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
405  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
406}
407
408MachinePointerInfo MachinePointerInfo::getJumpTable() {
409  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
410}
411
412MachinePointerInfo MachinePointerInfo::getGOT() {
413  return MachinePointerInfo(PseudoSourceValue::getGOT());
414}
415
416MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
417  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
418}
419
420MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
421                                     uint64_t s, unsigned int a,
422                                     const MDNode *TBAAInfo,
423                                     const MDNode *Ranges)
424  : PtrInfo(ptrinfo), Size(s),
425    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
426    TBAAInfo(TBAAInfo), Ranges(Ranges) {
427  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
428         "invalid pointer value");
429  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
430  assert((isLoad() || isStore()) && "Not a load/store!");
431}
432
433/// Profile - Gather unique data for the object.
434///
435void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
436  ID.AddInteger(getOffset());
437  ID.AddInteger(Size);
438  ID.AddPointer(getValue());
439  ID.AddInteger(Flags);
440}
441
442void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
443  // The Value and Offset may differ due to CSE. But the flags and size
444  // should be the same.
445  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
446  assert(MMO->getSize() == getSize() && "Size mismatch!");
447
448  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
449    // Update the alignment value.
450    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
451      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
452    // Also update the base and offset, because the new alignment may
453    // not be applicable with the old ones.
454    PtrInfo = MMO->PtrInfo;
455  }
456}
457
458/// getAlignment - Return the minimum known alignment in bytes of the
459/// actual memory reference.
460uint64_t MachineMemOperand::getAlignment() const {
461  return MinAlign(getBaseAlignment(), getOffset());
462}
463
464raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
465  assert((MMO.isLoad() || MMO.isStore()) &&
466         "SV has to be a load, store or both.");
467
468  if (MMO.isVolatile())
469    OS << "Volatile ";
470
471  if (MMO.isLoad())
472    OS << "LD";
473  if (MMO.isStore())
474    OS << "ST";
475  OS << MMO.getSize();
476
477  // Print the address information.
478  OS << "[";
479  if (!MMO.getValue())
480    OS << "<unknown>";
481  else
482    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
483
484  // If the alignment of the memory reference itself differs from the alignment
485  // of the base pointer, print the base alignment explicitly, next to the base
486  // pointer.
487  if (MMO.getBaseAlignment() != MMO.getAlignment())
488    OS << "(align=" << MMO.getBaseAlignment() << ")";
489
490  if (MMO.getOffset() != 0)
491    OS << "+" << MMO.getOffset();
492  OS << "]";
493
494  // Print the alignment of the reference.
495  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
496      MMO.getBaseAlignment() != MMO.getSize())
497    OS << "(align=" << MMO.getAlignment() << ")";
498
499  // Print TBAA info.
500  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
501    OS << "(tbaa=";
502    if (TBAAInfo->getNumOperands() > 0)
503      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
504    else
505      OS << "<unknown>";
506    OS << ")";
507  }
508
509  // Print nontemporal info.
510  if (MMO.isNonTemporal())
511    OS << "(nontemporal)";
512
513  return OS;
514}
515
516//===----------------------------------------------------------------------===//
517// MachineInstr Implementation
518//===----------------------------------------------------------------------===//
519
520void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
521  if (MCID->ImplicitDefs)
522    for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
523      addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
524  if (MCID->ImplicitUses)
525    for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
526      addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
527}
528
529/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
530/// implicit operands. It reserves space for the number of operands specified by
531/// the MCInstrDesc.
532MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
533                           const DebugLoc dl, bool NoImp)
534  : MCID(&tid), Parent(0), Operands(0), NumOperands(0),
535    Flags(0), AsmPrinterFlags(0),
536    NumMemRefs(0), MemRefs(0), debugLoc(dl) {
537  // Reserve space for the expected number of operands.
538  if (unsigned NumOps = MCID->getNumOperands() +
539    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
540    CapOperands = OperandCapacity::get(NumOps);
541    Operands = MF.allocateOperandArray(CapOperands);
542  }
543
544  if (!NoImp)
545    addImplicitDefUseOperands(MF);
546}
547
548/// MachineInstr ctor - Copies MachineInstr arg exactly
549///
550MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
551  : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0),
552    Flags(0), AsmPrinterFlags(0),
553    NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
554    debugLoc(MI.getDebugLoc()) {
555  CapOperands = OperandCapacity::get(MI.getNumOperands());
556  Operands = MF.allocateOperandArray(CapOperands);
557
558  // Copy operands.
559  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
560    addOperand(MF, MI.getOperand(i));
561
562  // Copy all the sensible flags.
563  setFlags(MI.Flags);
564}
565
566/// getRegInfo - If this instruction is embedded into a MachineFunction,
567/// return the MachineRegisterInfo object for the current function, otherwise
568/// return null.
569MachineRegisterInfo *MachineInstr::getRegInfo() {
570  if (MachineBasicBlock *MBB = getParent())
571    return &MBB->getParent()->getRegInfo();
572  return 0;
573}
574
575/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
576/// this instruction from their respective use lists.  This requires that the
577/// operands already be on their use lists.
578void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
579  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
580    if (Operands[i].isReg())
581      MRI.removeRegOperandFromUseList(&Operands[i]);
582}
583
584/// AddRegOperandsToUseLists - Add all of the register operands in
585/// this instruction from their respective use lists.  This requires that the
586/// operands not be on their use lists yet.
587void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
588  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
589    if (Operands[i].isReg())
590      MRI.addRegOperandToUseList(&Operands[i]);
591}
592
593void MachineInstr::addOperand(const MachineOperand &Op) {
594  MachineBasicBlock *MBB = getParent();
595  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
596  MachineFunction *MF = MBB->getParent();
597  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
598  addOperand(*MF, Op);
599}
600
601/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
602/// ranges. If MRI is non-null also update use-def chains.
603static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
604                         unsigned NumOps, MachineRegisterInfo *MRI) {
605  if (MRI)
606    return MRI->moveOperands(Dst, Src, NumOps);
607
608  // Here it would be convenient to call memmove, so that isn't allowed because
609  // MachineOperand has a constructor and so isn't a POD type.
610  if (Dst < Src)
611    for (unsigned i = 0; i != NumOps; ++i)
612      new (Dst + i) MachineOperand(Src[i]);
613  else
614    for (unsigned i = NumOps; i ; --i)
615      new (Dst + i - 1) MachineOperand(Src[i - 1]);
616}
617
618/// addOperand - Add the specified operand to the instruction.  If it is an
619/// implicit operand, it is added to the end of the operand list.  If it is
620/// an explicit operand it is added at the end of the explicit operand list
621/// (before the first implicit operand).
622void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
623  assert(MCID && "Cannot add operands before providing an instr descriptor");
624
625  // Check if we're adding one of our existing operands.
626  if (&Op >= Operands && &Op < Operands + NumOperands) {
627    // This is unusual: MI->addOperand(MI->getOperand(i)).
628    // If adding Op requires reallocating or moving existing operands around,
629    // the Op reference could go stale. Support it by copying Op.
630    MachineOperand CopyOp(Op);
631    return addOperand(MF, CopyOp);
632  }
633
634  // Find the insert location for the new operand.  Implicit registers go at
635  // the end, everything else goes before the implicit regs.
636  //
637  // FIXME: Allow mixed explicit and implicit operands on inline asm.
638  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
639  // implicit-defs, but they must not be moved around.  See the FIXME in
640  // InstrEmitter.cpp.
641  unsigned OpNo = getNumOperands();
642  bool isImpReg = Op.isReg() && Op.isImplicit();
643  if (!isImpReg && !isInlineAsm()) {
644    while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
645      --OpNo;
646      assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
647    }
648  }
649
650  // OpNo now points as the desired insertion point.  Unless this is a variadic
651  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
652  // RegMask operands go between the explicit and implicit operands.
653  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
654          OpNo < MCID->getNumOperands()) &&
655         "Trying to add an operand to a machine instr that is already done!");
656
657  MachineRegisterInfo *MRI = getRegInfo();
658
659  // Determine if the Operands array needs to be reallocated.
660  // Save the old capacity and operand array.
661  OperandCapacity OldCap = CapOperands;
662  MachineOperand *OldOperands = Operands;
663  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
664    CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
665    Operands = MF.allocateOperandArray(CapOperands);
666    // Move the operands before the insertion point.
667    if (OpNo)
668      moveOperands(Operands, OldOperands, OpNo, MRI);
669  }
670
671  // Move the operands following the insertion point.
672  if (OpNo != NumOperands)
673    moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
674                 MRI);
675  ++NumOperands;
676
677  // Deallocate the old operand array.
678  if (OldOperands != Operands && OldOperands)
679    MF.deallocateOperandArray(OldCap, OldOperands);
680
681  // Copy Op into place. It still needs to be inserted into the MRI use lists.
682  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
683  NewMO->ParentMI = this;
684
685  // When adding a register operand, tell MRI about it.
686  if (NewMO->isReg()) {
687    // Ensure isOnRegUseList() returns false, regardless of Op's status.
688    NewMO->Contents.Reg.Prev = 0;
689    // Ignore existing ties. This is not a property that can be copied.
690    NewMO->TiedTo = 0;
691    // Add the new operand to MRI, but only for instructions in an MBB.
692    if (MRI)
693      MRI->addRegOperandToUseList(NewMO);
694    // The MCID operand information isn't accurate until we start adding
695    // explicit operands. The implicit operands are added first, then the
696    // explicits are inserted before them.
697    if (!isImpReg) {
698      // Tie uses to defs as indicated in MCInstrDesc.
699      if (NewMO->isUse()) {
700        int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
701        if (DefIdx != -1)
702          tieOperands(DefIdx, OpNo);
703      }
704      // If the register operand is flagged as early, mark the operand as such.
705      if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
706        NewMO->setIsEarlyClobber(true);
707    }
708  }
709}
710
711/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
712/// fewer operand than it started with.
713///
714void MachineInstr::RemoveOperand(unsigned OpNo) {
715  assert(OpNo < getNumOperands() && "Invalid operand number");
716  untieRegOperand(OpNo);
717
718#ifndef NDEBUG
719  // Moving tied operands would break the ties.
720  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
721    if (Operands[i].isReg())
722      assert(!Operands[i].isTied() && "Cannot move tied operands");
723#endif
724
725  MachineRegisterInfo *MRI = getRegInfo();
726  if (MRI && Operands[OpNo].isReg())
727    MRI->removeRegOperandFromUseList(Operands + OpNo);
728
729  // Don't call the MachineOperand destructor. A lot of this code depends on
730  // MachineOperand having a trivial destructor anyway, and adding a call here
731  // wouldn't make it 'destructor-correct'.
732
733  if (unsigned N = NumOperands - 1 - OpNo)
734    moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
735  --NumOperands;
736}
737
738/// addMemOperand - Add a MachineMemOperand to the machine instruction.
739/// This function should be used only occasionally. The setMemRefs function
740/// is the primary method for setting up a MachineInstr's MemRefs list.
741void MachineInstr::addMemOperand(MachineFunction &MF,
742                                 MachineMemOperand *MO) {
743  mmo_iterator OldMemRefs = MemRefs;
744  unsigned OldNumMemRefs = NumMemRefs;
745
746  unsigned NewNum = NumMemRefs + 1;
747  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
748
749  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
750  NewMemRefs[NewNum - 1] = MO;
751  setMemRefs(NewMemRefs, NewMemRefs + NewNum);
752}
753
754bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
755  const MachineBasicBlock *MBB = getParent();
756  MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
757  while (MII != MBB->end() && MII->isInsideBundle()) {
758    if (MII->getDesc().getFlags() & Mask) {
759      if (Type == AnyInBundle)
760        return true;
761    } else {
762      if (Type == AllInBundle)
763        return false;
764    }
765    ++MII;
766  }
767
768  return Type == AllInBundle;
769}
770
771bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
772                                 MICheckType Check) const {
773  // If opcodes or number of operands are not the same then the two
774  // instructions are obviously not identical.
775  if (Other->getOpcode() != getOpcode() ||
776      Other->getNumOperands() != getNumOperands())
777    return false;
778
779  if (isBundle()) {
780    // Both instructions are bundles, compare MIs inside the bundle.
781    MachineBasicBlock::const_instr_iterator I1 = *this;
782    MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
783    MachineBasicBlock::const_instr_iterator I2 = *Other;
784    MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
785    while (++I1 != E1 && I1->isInsideBundle()) {
786      ++I2;
787      if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
788        return false;
789    }
790  }
791
792  // Check operands to make sure they match.
793  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
794    const MachineOperand &MO = getOperand(i);
795    const MachineOperand &OMO = Other->getOperand(i);
796    if (!MO.isReg()) {
797      if (!MO.isIdenticalTo(OMO))
798        return false;
799      continue;
800    }
801
802    // Clients may or may not want to ignore defs when testing for equality.
803    // For example, machine CSE pass only cares about finding common
804    // subexpressions, so it's safe to ignore virtual register defs.
805    if (MO.isDef()) {
806      if (Check == IgnoreDefs)
807        continue;
808      else if (Check == IgnoreVRegDefs) {
809        if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
810            TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
811          if (MO.getReg() != OMO.getReg())
812            return false;
813      } else {
814        if (!MO.isIdenticalTo(OMO))
815          return false;
816        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
817          return false;
818      }
819    } else {
820      if (!MO.isIdenticalTo(OMO))
821        return false;
822      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
823        return false;
824    }
825  }
826  // If DebugLoc does not match then two dbg.values are not identical.
827  if (isDebugValue())
828    if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
829        && getDebugLoc() != Other->getDebugLoc())
830      return false;
831  return true;
832}
833
834MachineInstr *MachineInstr::removeFromParent() {
835  assert(getParent() && "Not embedded in a basic block!");
836  return getParent()->remove(this);
837}
838
839MachineInstr *MachineInstr::removeFromBundle() {
840  assert(getParent() && "Not embedded in a basic block!");
841  return getParent()->remove_instr(this);
842}
843
844void MachineInstr::eraseFromParent() {
845  assert(getParent() && "Not embedded in a basic block!");
846  getParent()->erase(this);
847}
848
849void MachineInstr::eraseFromBundle() {
850  assert(getParent() && "Not embedded in a basic block!");
851  getParent()->erase_instr(this);
852}
853
854/// getNumExplicitOperands - Returns the number of non-implicit operands.
855///
856unsigned MachineInstr::getNumExplicitOperands() const {
857  unsigned NumOperands = MCID->getNumOperands();
858  if (!MCID->isVariadic())
859    return NumOperands;
860
861  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
862    const MachineOperand &MO = getOperand(i);
863    if (!MO.isReg() || !MO.isImplicit())
864      NumOperands++;
865  }
866  return NumOperands;
867}
868
869void MachineInstr::bundleWithPred() {
870  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
871  setFlag(BundledPred);
872  MachineBasicBlock::instr_iterator Pred = this;
873  --Pred;
874  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
875  Pred->setFlag(BundledSucc);
876}
877
878void MachineInstr::bundleWithSucc() {
879  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
880  setFlag(BundledSucc);
881  MachineBasicBlock::instr_iterator Succ = this;
882  ++Succ;
883  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
884  Succ->setFlag(BundledPred);
885}
886
887void MachineInstr::unbundleFromPred() {
888  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
889  clearFlag(BundledPred);
890  MachineBasicBlock::instr_iterator Pred = this;
891  --Pred;
892  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
893  Pred->clearFlag(BundledSucc);
894}
895
896void MachineInstr::unbundleFromSucc() {
897  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
898  clearFlag(BundledSucc);
899  MachineBasicBlock::instr_iterator Succ = this;
900  ++Succ;
901  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
902  Succ->clearFlag(BundledPred);
903}
904
905bool MachineInstr::isStackAligningInlineAsm() const {
906  if (isInlineAsm()) {
907    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
908    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
909      return true;
910  }
911  return false;
912}
913
914InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
915  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
916  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
917  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
918}
919
920int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
921                                       unsigned *GroupNo) const {
922  assert(isInlineAsm() && "Expected an inline asm instruction");
923  assert(OpIdx < getNumOperands() && "OpIdx out of range");
924
925  // Ignore queries about the initial operands.
926  if (OpIdx < InlineAsm::MIOp_FirstOperand)
927    return -1;
928
929  unsigned Group = 0;
930  unsigned NumOps;
931  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
932       i += NumOps) {
933    const MachineOperand &FlagMO = getOperand(i);
934    // If we reach the implicit register operands, stop looking.
935    if (!FlagMO.isImm())
936      return -1;
937    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
938    if (i + NumOps > OpIdx) {
939      if (GroupNo)
940        *GroupNo = Group;
941      return i;
942    }
943    ++Group;
944  }
945  return -1;
946}
947
948const TargetRegisterClass*
949MachineInstr::getRegClassConstraint(unsigned OpIdx,
950                                    const TargetInstrInfo *TII,
951                                    const TargetRegisterInfo *TRI) const {
952  assert(getParent() && "Can't have an MBB reference here!");
953  assert(getParent()->getParent() && "Can't have an MF reference here!");
954  const MachineFunction &MF = *getParent()->getParent();
955
956  // Most opcodes have fixed constraints in their MCInstrDesc.
957  if (!isInlineAsm())
958    return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
959
960  if (!getOperand(OpIdx).isReg())
961    return NULL;
962
963  // For tied uses on inline asm, get the constraint from the def.
964  unsigned DefIdx;
965  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
966    OpIdx = DefIdx;
967
968  // Inline asm stores register class constraints in the flag word.
969  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
970  if (FlagIdx < 0)
971    return NULL;
972
973  unsigned Flag = getOperand(FlagIdx).getImm();
974  unsigned RCID;
975  if (InlineAsm::hasRegClassConstraint(Flag, RCID))
976    return TRI->getRegClass(RCID);
977
978  // Assume that all registers in a memory operand are pointers.
979  if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
980    return TRI->getPointerRegClass(MF);
981
982  return NULL;
983}
984
985/// Return the number of instructions inside the MI bundle, not counting the
986/// header instruction.
987unsigned MachineInstr::getBundleSize() const {
988  MachineBasicBlock::const_instr_iterator I = this;
989  unsigned Size = 0;
990  while (I->isBundledWithSucc())
991    ++Size, ++I;
992  return Size;
993}
994
995/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
996/// the specific register or -1 if it is not found. It further tightens
997/// the search criteria to a use that kills the register if isKill is true.
998int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
999                                          const TargetRegisterInfo *TRI) const {
1000  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1001    const MachineOperand &MO = getOperand(i);
1002    if (!MO.isReg() || !MO.isUse())
1003      continue;
1004    unsigned MOReg = MO.getReg();
1005    if (!MOReg)
1006      continue;
1007    if (MOReg == Reg ||
1008        (TRI &&
1009         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1010         TargetRegisterInfo::isPhysicalRegister(Reg) &&
1011         TRI->isSubRegister(MOReg, Reg)))
1012      if (!isKill || MO.isKill())
1013        return i;
1014  }
1015  return -1;
1016}
1017
1018/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1019/// indicating if this instruction reads or writes Reg. This also considers
1020/// partial defines.
1021std::pair<bool,bool>
1022MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1023                                         SmallVectorImpl<unsigned> *Ops) const {
1024  bool PartDef = false; // Partial redefine.
1025  bool FullDef = false; // Full define.
1026  bool Use = false;
1027
1028  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1029    const MachineOperand &MO = getOperand(i);
1030    if (!MO.isReg() || MO.getReg() != Reg)
1031      continue;
1032    if (Ops)
1033      Ops->push_back(i);
1034    if (MO.isUse())
1035      Use |= !MO.isUndef();
1036    else if (MO.getSubReg() && !MO.isUndef())
1037      // A partial <def,undef> doesn't count as reading the register.
1038      PartDef = true;
1039    else
1040      FullDef = true;
1041  }
1042  // A partial redefine uses Reg unless there is also a full define.
1043  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1044}
1045
1046/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1047/// the specified register or -1 if it is not found. If isDead is true, defs
1048/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1049/// also checks if there is a def of a super-register.
1050int
1051MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1052                                        const TargetRegisterInfo *TRI) const {
1053  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1054  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1055    const MachineOperand &MO = getOperand(i);
1056    // Accept regmask operands when Overlap is set.
1057    // Ignore them when looking for a specific def operand (Overlap == false).
1058    if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1059      return i;
1060    if (!MO.isReg() || !MO.isDef())
1061      continue;
1062    unsigned MOReg = MO.getReg();
1063    bool Found = (MOReg == Reg);
1064    if (!Found && TRI && isPhys &&
1065        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1066      if (Overlap)
1067        Found = TRI->regsOverlap(MOReg, Reg);
1068      else
1069        Found = TRI->isSubRegister(MOReg, Reg);
1070    }
1071    if (Found && (!isDead || MO.isDead()))
1072      return i;
1073  }
1074  return -1;
1075}
1076
1077/// findFirstPredOperandIdx() - Find the index of the first operand in the
1078/// operand list that is used to represent the predicate. It returns -1 if
1079/// none is found.
1080int MachineInstr::findFirstPredOperandIdx() const {
1081  // Don't call MCID.findFirstPredOperandIdx() because this variant
1082  // is sometimes called on an instruction that's not yet complete, and
1083  // so the number of operands is less than the MCID indicates. In
1084  // particular, the PTX target does this.
1085  const MCInstrDesc &MCID = getDesc();
1086  if (MCID.isPredicable()) {
1087    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1088      if (MCID.OpInfo[i].isPredicate())
1089        return i;
1090  }
1091
1092  return -1;
1093}
1094
1095// MachineOperand::TiedTo is 4 bits wide.
1096const unsigned TiedMax = 15;
1097
1098/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1099///
1100/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1101/// field. TiedTo can have these values:
1102///
1103/// 0:              Operand is not tied to anything.
1104/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1105/// TiedMax:        Tied to an operand >= TiedMax-1.
1106///
1107/// The tied def must be one of the first TiedMax operands on a normal
1108/// instruction. INLINEASM instructions allow more tied defs.
1109///
1110void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1111  MachineOperand &DefMO = getOperand(DefIdx);
1112  MachineOperand &UseMO = getOperand(UseIdx);
1113  assert(DefMO.isDef() && "DefIdx must be a def operand");
1114  assert(UseMO.isUse() && "UseIdx must be a use operand");
1115  assert(!DefMO.isTied() && "Def is already tied to another use");
1116  assert(!UseMO.isTied() && "Use is already tied to another def");
1117
1118  if (DefIdx < TiedMax)
1119    UseMO.TiedTo = DefIdx + 1;
1120  else {
1121    // Inline asm can use the group descriptors to find tied operands, but on
1122    // normal instruction, the tied def must be within the first TiedMax
1123    // operands.
1124    assert(isInlineAsm() && "DefIdx out of range");
1125    UseMO.TiedTo = TiedMax;
1126  }
1127
1128  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1129  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1130}
1131
1132/// Given the index of a tied register operand, find the operand it is tied to.
1133/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1134/// which must exist.
1135unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1136  const MachineOperand &MO = getOperand(OpIdx);
1137  assert(MO.isTied() && "Operand isn't tied");
1138
1139  // Normally TiedTo is in range.
1140  if (MO.TiedTo < TiedMax)
1141    return MO.TiedTo - 1;
1142
1143  // Uses on normal instructions can be out of range.
1144  if (!isInlineAsm()) {
1145    // Normal tied defs must be in the 0..TiedMax-1 range.
1146    if (MO.isUse())
1147      return TiedMax - 1;
1148    // MO is a def. Search for the tied use.
1149    for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1150      const MachineOperand &UseMO = getOperand(i);
1151      if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1152        return i;
1153    }
1154    llvm_unreachable("Can't find tied use");
1155  }
1156
1157  // Now deal with inline asm by parsing the operand group descriptor flags.
1158  // Find the beginning of each operand group.
1159  SmallVector<unsigned, 8> GroupIdx;
1160  unsigned OpIdxGroup = ~0u;
1161  unsigned NumOps;
1162  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1163       i += NumOps) {
1164    const MachineOperand &FlagMO = getOperand(i);
1165    assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1166    unsigned CurGroup = GroupIdx.size();
1167    GroupIdx.push_back(i);
1168    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1169    // OpIdx belongs to this operand group.
1170    if (OpIdx > i && OpIdx < i + NumOps)
1171      OpIdxGroup = CurGroup;
1172    unsigned TiedGroup;
1173    if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1174      continue;
1175    // Operands in this group are tied to operands in TiedGroup which must be
1176    // earlier. Find the number of operands between the two groups.
1177    unsigned Delta = i - GroupIdx[TiedGroup];
1178
1179    // OpIdx is a use tied to TiedGroup.
1180    if (OpIdxGroup == CurGroup)
1181      return OpIdx - Delta;
1182
1183    // OpIdx is a def tied to this use group.
1184    if (OpIdxGroup == TiedGroup)
1185      return OpIdx + Delta;
1186  }
1187  llvm_unreachable("Invalid tied operand on inline asm");
1188}
1189
1190/// clearKillInfo - Clears kill flags on all operands.
1191///
1192void MachineInstr::clearKillInfo() {
1193  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1194    MachineOperand &MO = getOperand(i);
1195    if (MO.isReg() && MO.isUse())
1196      MO.setIsKill(false);
1197  }
1198}
1199
1200void MachineInstr::substituteRegister(unsigned FromReg,
1201                                      unsigned ToReg,
1202                                      unsigned SubIdx,
1203                                      const TargetRegisterInfo &RegInfo) {
1204  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1205    if (SubIdx)
1206      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1207    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1208      MachineOperand &MO = getOperand(i);
1209      if (!MO.isReg() || MO.getReg() != FromReg)
1210        continue;
1211      MO.substPhysReg(ToReg, RegInfo);
1212    }
1213  } else {
1214    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1215      MachineOperand &MO = getOperand(i);
1216      if (!MO.isReg() || MO.getReg() != FromReg)
1217        continue;
1218      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1219    }
1220  }
1221}
1222
1223/// isSafeToMove - Return true if it is safe to move this instruction. If
1224/// SawStore is set to true, it means that there is a store (or call) between
1225/// the instruction's location and its intended destination.
1226bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1227                                AliasAnalysis *AA,
1228                                bool &SawStore) const {
1229  // Ignore stuff that we obviously can't move.
1230  //
1231  // Treat volatile loads as stores. This is not strictly necessary for
1232  // volatiles, but it is required for atomic loads. It is not allowed to move
1233  // a load across an atomic load with Ordering > Monotonic.
1234  if (mayStore() || isCall() ||
1235      (mayLoad() && hasOrderedMemoryRef())) {
1236    SawStore = true;
1237    return false;
1238  }
1239
1240  if (isLabel() || isDebugValue() ||
1241      isTerminator() || hasUnmodeledSideEffects())
1242    return false;
1243
1244  // See if this instruction does a load.  If so, we have to guarantee that the
1245  // loaded value doesn't change between the load and the its intended
1246  // destination. The check for isInvariantLoad gives the targe the chance to
1247  // classify the load as always returning a constant, e.g. a constant pool
1248  // load.
1249  if (mayLoad() && !isInvariantLoad(AA))
1250    // Otherwise, this is a real load.  If there is a store between the load and
1251    // end of block, we can't move it.
1252    return !SawStore;
1253
1254  return true;
1255}
1256
1257/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1258/// instruction which defined the specified register instead of copying it.
1259bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1260                                 AliasAnalysis *AA,
1261                                 unsigned DstReg) const {
1262  bool SawStore = false;
1263  if (!TII->isTriviallyReMaterializable(this, AA) ||
1264      !isSafeToMove(TII, AA, SawStore))
1265    return false;
1266  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1267    const MachineOperand &MO = getOperand(i);
1268    if (!MO.isReg())
1269      continue;
1270    // FIXME: For now, do not remat any instruction with register operands.
1271    // Later on, we can loosen the restriction is the register operands have
1272    // not been modified between the def and use. Note, this is different from
1273    // MachineSink because the code is no longer in two-address form (at least
1274    // partially).
1275    if (MO.isUse())
1276      return false;
1277    else if (!MO.isDead() && MO.getReg() != DstReg)
1278      return false;
1279  }
1280  return true;
1281}
1282
1283/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1284/// or volatile memory reference, or if the information describing the memory
1285/// reference is not available. Return false if it is known to have no ordered
1286/// memory references.
1287bool MachineInstr::hasOrderedMemoryRef() const {
1288  // An instruction known never to access memory won't have a volatile access.
1289  if (!mayStore() &&
1290      !mayLoad() &&
1291      !isCall() &&
1292      !hasUnmodeledSideEffects())
1293    return false;
1294
1295  // Otherwise, if the instruction has no memory reference information,
1296  // conservatively assume it wasn't preserved.
1297  if (memoperands_empty())
1298    return true;
1299
1300  // Check the memory reference information for ordered references.
1301  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1302    if (!(*I)->isUnordered())
1303      return true;
1304
1305  return false;
1306}
1307
1308/// isInvariantLoad - Return true if this instruction is loading from a
1309/// location whose value is invariant across the function.  For example,
1310/// loading a value from the constant pool or from the argument area
1311/// of a function if it does not change.  This should only return true of
1312/// *all* loads the instruction does are invariant (if it does multiple loads).
1313bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1314  // If the instruction doesn't load at all, it isn't an invariant load.
1315  if (!mayLoad())
1316    return false;
1317
1318  // If the instruction has lost its memoperands, conservatively assume that
1319  // it may not be an invariant load.
1320  if (memoperands_empty())
1321    return false;
1322
1323  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1324
1325  for (mmo_iterator I = memoperands_begin(),
1326       E = memoperands_end(); I != E; ++I) {
1327    if ((*I)->isVolatile()) return false;
1328    if ((*I)->isStore()) return false;
1329    if ((*I)->isInvariant()) return true;
1330
1331    if (const Value *V = (*I)->getValue()) {
1332      // A load from a constant PseudoSourceValue is invariant.
1333      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1334        if (PSV->isConstant(MFI))
1335          continue;
1336      // If we have an AliasAnalysis, ask it whether the memory is constant.
1337      if (AA && AA->pointsToConstantMemory(
1338                      AliasAnalysis::Location(V, (*I)->getSize(),
1339                                              (*I)->getTBAAInfo())))
1340        continue;
1341    }
1342
1343    // Otherwise assume conservatively.
1344    return false;
1345  }
1346
1347  // Everything checks out.
1348  return true;
1349}
1350
1351/// isConstantValuePHI - If the specified instruction is a PHI that always
1352/// merges together the same virtual register, return the register, otherwise
1353/// return 0.
1354unsigned MachineInstr::isConstantValuePHI() const {
1355  if (!isPHI())
1356    return 0;
1357  assert(getNumOperands() >= 3 &&
1358         "It's illegal to have a PHI without source operands");
1359
1360  unsigned Reg = getOperand(1).getReg();
1361  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1362    if (getOperand(i).getReg() != Reg)
1363      return 0;
1364  return Reg;
1365}
1366
1367bool MachineInstr::hasUnmodeledSideEffects() const {
1368  if (hasProperty(MCID::UnmodeledSideEffects))
1369    return true;
1370  if (isInlineAsm()) {
1371    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1372    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1373      return true;
1374  }
1375
1376  return false;
1377}
1378
1379/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1380///
1381bool MachineInstr::allDefsAreDead() const {
1382  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1383    const MachineOperand &MO = getOperand(i);
1384    if (!MO.isReg() || MO.isUse())
1385      continue;
1386    if (!MO.isDead())
1387      return false;
1388  }
1389  return true;
1390}
1391
1392/// copyImplicitOps - Copy implicit register operands from specified
1393/// instruction to this instruction.
1394void MachineInstr::copyImplicitOps(MachineFunction &MF,
1395                                   const MachineInstr *MI) {
1396  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1397       i != e; ++i) {
1398    const MachineOperand &MO = MI->getOperand(i);
1399    if (MO.isReg() && MO.isImplicit())
1400      addOperand(MF, MO);
1401  }
1402}
1403
1404void MachineInstr::dump() const {
1405#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1406  dbgs() << "  " << *this;
1407#endif
1408}
1409
1410static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1411                         raw_ostream &CommentOS) {
1412  const LLVMContext &Ctx = MF->getFunction()->getContext();
1413  if (!DL.isUnknown()) {          // Print source line info.
1414    DIScope Scope(DL.getScope(Ctx));
1415    // Omit the directory, because it's likely to be long and uninteresting.
1416    if (Scope.Verify())
1417      CommentOS << Scope.getFilename();
1418    else
1419      CommentOS << "<unknown>";
1420    CommentOS << ':' << DL.getLine();
1421    if (DL.getCol() != 0)
1422      CommentOS << ':' << DL.getCol();
1423    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1424    if (!InlinedAtDL.isUnknown()) {
1425      CommentOS << " @[ ";
1426      printDebugLoc(InlinedAtDL, MF, CommentOS);
1427      CommentOS << " ]";
1428    }
1429  }
1430}
1431
1432void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1433  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1434  const MachineFunction *MF = 0;
1435  const MachineRegisterInfo *MRI = 0;
1436  if (const MachineBasicBlock *MBB = getParent()) {
1437    MF = MBB->getParent();
1438    if (!TM && MF)
1439      TM = &MF->getTarget();
1440    if (MF)
1441      MRI = &MF->getRegInfo();
1442  }
1443
1444  // Save a list of virtual registers.
1445  SmallVector<unsigned, 8> VirtRegs;
1446
1447  // Print explicitly defined operands on the left of an assignment syntax.
1448  unsigned StartOp = 0, e = getNumOperands();
1449  for (; StartOp < e && getOperand(StartOp).isReg() &&
1450         getOperand(StartOp).isDef() &&
1451         !getOperand(StartOp).isImplicit();
1452       ++StartOp) {
1453    if (StartOp != 0) OS << ", ";
1454    getOperand(StartOp).print(OS, TM);
1455    unsigned Reg = getOperand(StartOp).getReg();
1456    if (TargetRegisterInfo::isVirtualRegister(Reg))
1457      VirtRegs.push_back(Reg);
1458  }
1459
1460  if (StartOp != 0)
1461    OS << " = ";
1462
1463  // Print the opcode name.
1464  if (TM && TM->getInstrInfo())
1465    OS << TM->getInstrInfo()->getName(getOpcode());
1466  else
1467    OS << "UNKNOWN";
1468
1469  // Print the rest of the operands.
1470  bool OmittedAnyCallClobbers = false;
1471  bool FirstOp = true;
1472  unsigned AsmDescOp = ~0u;
1473  unsigned AsmOpCount = 0;
1474
1475  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1476    // Print asm string.
1477    OS << " ";
1478    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1479
1480    // Print HasSideEffects, IsAlignStack
1481    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1482    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1483      OS << " [sideeffect]";
1484    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1485      OS << " [alignstack]";
1486    if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1487      OS << " [attdialect]";
1488    if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1489      OS << " [inteldialect]";
1490
1491    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1492    FirstOp = false;
1493  }
1494
1495
1496  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1497    const MachineOperand &MO = getOperand(i);
1498
1499    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1500      VirtRegs.push_back(MO.getReg());
1501
1502    // Omit call-clobbered registers which aren't used anywhere. This makes
1503    // call instructions much less noisy on targets where calls clobber lots
1504    // of registers. Don't rely on MO.isDead() because we may be called before
1505    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1506    if (MF && isCall() &&
1507        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1508      unsigned Reg = MO.getReg();
1509      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1510        const MachineRegisterInfo &MRI = MF->getRegInfo();
1511        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1512          bool HasAliasLive = false;
1513          for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1514               AI.isValid(); ++AI) {
1515            unsigned AliasReg = *AI;
1516            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1517              HasAliasLive = true;
1518              break;
1519            }
1520          }
1521          if (!HasAliasLive) {
1522            OmittedAnyCallClobbers = true;
1523            continue;
1524          }
1525        }
1526      }
1527    }
1528
1529    if (FirstOp) FirstOp = false; else OS << ",";
1530    OS << " ";
1531    if (i < getDesc().NumOperands) {
1532      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1533      if (MCOI.isPredicate())
1534        OS << "pred:";
1535      if (MCOI.isOptionalDef())
1536        OS << "opt:";
1537    }
1538    if (isDebugValue() && MO.isMetadata()) {
1539      // Pretty print DBG_VALUE instructions.
1540      const MDNode *MD = MO.getMetadata();
1541      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1542        OS << "!\"" << MDS->getString() << '\"';
1543      else
1544        MO.print(OS, TM);
1545    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1546      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1547    } else if (i == AsmDescOp && MO.isImm()) {
1548      // Pretty print the inline asm operand descriptor.
1549      OS << '$' << AsmOpCount++;
1550      unsigned Flag = MO.getImm();
1551      switch (InlineAsm::getKind(Flag)) {
1552      case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
1553      case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
1554      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1555      case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
1556      case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
1557      case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
1558      default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1559      }
1560
1561      unsigned RCID = 0;
1562      if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1563        if (TM)
1564          OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1565        else
1566          OS << ":RC" << RCID;
1567      }
1568
1569      unsigned TiedTo = 0;
1570      if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1571        OS << " tiedto:$" << TiedTo;
1572
1573      OS << ']';
1574
1575      // Compute the index of the next operand descriptor.
1576      AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1577    } else
1578      MO.print(OS, TM);
1579  }
1580
1581  // Briefly indicate whether any call clobbers were omitted.
1582  if (OmittedAnyCallClobbers) {
1583    if (!FirstOp) OS << ",";
1584    OS << " ...";
1585  }
1586
1587  bool HaveSemi = false;
1588  if (Flags) {
1589    if (!HaveSemi) OS << ";"; HaveSemi = true;
1590    OS << " flags: ";
1591
1592    if (Flags & FrameSetup)
1593      OS << "FrameSetup";
1594  }
1595
1596  if (!memoperands_empty()) {
1597    if (!HaveSemi) OS << ";"; HaveSemi = true;
1598
1599    OS << " mem:";
1600    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1601         i != e; ++i) {
1602      OS << **i;
1603      if (llvm::next(i) != e)
1604        OS << " ";
1605    }
1606  }
1607
1608  // Print the regclass of any virtual registers encountered.
1609  if (MRI && !VirtRegs.empty()) {
1610    if (!HaveSemi) OS << ";"; HaveSemi = true;
1611    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1612      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1613      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1614      for (unsigned j = i+1; j != VirtRegs.size();) {
1615        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1616          ++j;
1617          continue;
1618        }
1619        if (VirtRegs[i] != VirtRegs[j])
1620          OS << "," << PrintReg(VirtRegs[j]);
1621        VirtRegs.erase(VirtRegs.begin()+j);
1622      }
1623    }
1624  }
1625
1626  // Print debug location information.
1627  if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1628    if (!HaveSemi) OS << ";"; HaveSemi = true;
1629    DIVariable DV(getOperand(e - 1).getMetadata());
1630    OS << " line no:" <<  DV.getLineNumber();
1631    if (MDNode *InlinedAt = DV.getInlinedAt()) {
1632      DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1633      if (!InlinedAtDL.isUnknown()) {
1634        OS << " inlined @[ ";
1635        printDebugLoc(InlinedAtDL, MF, OS);
1636        OS << " ]";
1637      }
1638    }
1639  } else if (!debugLoc.isUnknown() && MF) {
1640    if (!HaveSemi) OS << ";"; HaveSemi = true;
1641    OS << " dbg:";
1642    printDebugLoc(debugLoc, MF, OS);
1643  }
1644
1645  OS << '\n';
1646}
1647
1648bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1649                                     const TargetRegisterInfo *RegInfo,
1650                                     bool AddIfNotFound) {
1651  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1652  bool hasAliases = isPhysReg &&
1653    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1654  bool Found = false;
1655  SmallVector<unsigned,4> DeadOps;
1656  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1657    MachineOperand &MO = getOperand(i);
1658    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1659      continue;
1660    unsigned Reg = MO.getReg();
1661    if (!Reg)
1662      continue;
1663
1664    if (Reg == IncomingReg) {
1665      if (!Found) {
1666        if (MO.isKill())
1667          // The register is already marked kill.
1668          return true;
1669        if (isPhysReg && isRegTiedToDefOperand(i))
1670          // Two-address uses of physregs must not be marked kill.
1671          return true;
1672        MO.setIsKill();
1673        Found = true;
1674      }
1675    } else if (hasAliases && MO.isKill() &&
1676               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1677      // A super-register kill already exists.
1678      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1679        return true;
1680      if (RegInfo->isSubRegister(IncomingReg, Reg))
1681        DeadOps.push_back(i);
1682    }
1683  }
1684
1685  // Trim unneeded kill operands.
1686  while (!DeadOps.empty()) {
1687    unsigned OpIdx = DeadOps.back();
1688    if (getOperand(OpIdx).isImplicit())
1689      RemoveOperand(OpIdx);
1690    else
1691      getOperand(OpIdx).setIsKill(false);
1692    DeadOps.pop_back();
1693  }
1694
1695  // If not found, this means an alias of one of the operands is killed. Add a
1696  // new implicit operand if required.
1697  if (!Found && AddIfNotFound) {
1698    addOperand(MachineOperand::CreateReg(IncomingReg,
1699                                         false /*IsDef*/,
1700                                         true  /*IsImp*/,
1701                                         true  /*IsKill*/));
1702    return true;
1703  }
1704  return Found;
1705}
1706
1707void MachineInstr::clearRegisterKills(unsigned Reg,
1708                                      const TargetRegisterInfo *RegInfo) {
1709  if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1710    RegInfo = 0;
1711  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1712    MachineOperand &MO = getOperand(i);
1713    if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1714      continue;
1715    unsigned OpReg = MO.getReg();
1716    if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1717      MO.setIsKill(false);
1718  }
1719}
1720
1721bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1722                                   const TargetRegisterInfo *RegInfo,
1723                                   bool AddIfNotFound) {
1724  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1725  bool hasAliases = isPhysReg &&
1726    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1727  bool Found = false;
1728  SmallVector<unsigned,4> DeadOps;
1729  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1730    MachineOperand &MO = getOperand(i);
1731    if (!MO.isReg() || !MO.isDef())
1732      continue;
1733    unsigned Reg = MO.getReg();
1734    if (!Reg)
1735      continue;
1736
1737    if (Reg == IncomingReg) {
1738      MO.setIsDead();
1739      Found = true;
1740    } else if (hasAliases && MO.isDead() &&
1741               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1742      // There exists a super-register that's marked dead.
1743      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1744        return true;
1745      if (RegInfo->isSubRegister(IncomingReg, Reg))
1746        DeadOps.push_back(i);
1747    }
1748  }
1749
1750  // Trim unneeded dead operands.
1751  while (!DeadOps.empty()) {
1752    unsigned OpIdx = DeadOps.back();
1753    if (getOperand(OpIdx).isImplicit())
1754      RemoveOperand(OpIdx);
1755    else
1756      getOperand(OpIdx).setIsDead(false);
1757    DeadOps.pop_back();
1758  }
1759
1760  // If not found, this means an alias of one of the operands is dead. Add a
1761  // new implicit operand if required.
1762  if (Found || !AddIfNotFound)
1763    return Found;
1764
1765  addOperand(MachineOperand::CreateReg(IncomingReg,
1766                                       true  /*IsDef*/,
1767                                       true  /*IsImp*/,
1768                                       false /*IsKill*/,
1769                                       true  /*IsDead*/));
1770  return true;
1771}
1772
1773void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1774                                      const TargetRegisterInfo *RegInfo) {
1775  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1776    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1777    if (MO)
1778      return;
1779  } else {
1780    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1781      const MachineOperand &MO = getOperand(i);
1782      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1783          MO.getSubReg() == 0)
1784        return;
1785    }
1786  }
1787  addOperand(MachineOperand::CreateReg(IncomingReg,
1788                                       true  /*IsDef*/,
1789                                       true  /*IsImp*/));
1790}
1791
1792void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1793                                         const TargetRegisterInfo &TRI) {
1794  bool HasRegMask = false;
1795  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1796    MachineOperand &MO = getOperand(i);
1797    if (MO.isRegMask()) {
1798      HasRegMask = true;
1799      continue;
1800    }
1801    if (!MO.isReg() || !MO.isDef()) continue;
1802    unsigned Reg = MO.getReg();
1803    if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1804    bool Dead = true;
1805    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1806         I != E; ++I)
1807      if (TRI.regsOverlap(*I, Reg)) {
1808        Dead = false;
1809        break;
1810      }
1811    // If there are no uses, including partial uses, the def is dead.
1812    if (Dead) MO.setIsDead();
1813  }
1814
1815  // This is a call with a register mask operand.
1816  // Mask clobbers are always dead, so add defs for the non-dead defines.
1817  if (HasRegMask)
1818    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1819         I != E; ++I)
1820      addRegisterDefined(*I, &TRI);
1821}
1822
1823unsigned
1824MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1825  // Build up a buffer of hash code components.
1826  SmallVector<size_t, 8> HashComponents;
1827  HashComponents.reserve(MI->getNumOperands() + 1);
1828  HashComponents.push_back(MI->getOpcode());
1829  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1830    const MachineOperand &MO = MI->getOperand(i);
1831    if (MO.isReg() && MO.isDef() &&
1832        TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1833      continue;  // Skip virtual register defs.
1834
1835    HashComponents.push_back(hash_value(MO));
1836  }
1837  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1838}
1839
1840void MachineInstr::emitError(StringRef Msg) const {
1841  // Find the source location cookie.
1842  unsigned LocCookie = 0;
1843  const MDNode *LocMD = 0;
1844  for (unsigned i = getNumOperands(); i != 0; --i) {
1845    if (getOperand(i-1).isMetadata() &&
1846        (LocMD = getOperand(i-1).getMetadata()) &&
1847        LocMD->getNumOperands() != 0) {
1848      if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1849        LocCookie = CI->getZExtValue();
1850        break;
1851      }
1852    }
1853  }
1854
1855  if (const MachineBasicBlock *MBB = getParent())
1856    if (const MachineFunction *MF = MBB->getParent())
1857      return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1858  report_fatal_error(Msg);
1859}
1860