MachineInstr.cpp revision 33a537a5c41e60507ac9a4ea987c1a395cbb74fe
172a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch// 3c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch// The LLVM Compiler Infrastructure 4c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch// 5c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch// This file is distributed under the University of Illinois Open Source 6c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch// License. See LICENSE.TXT for details. 772a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen// 872a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen//===----------------------------------------------------------------------===// 93345a6884c488ff3a535c2c9acdd33d74b37e311Iain Merrick// 10c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch// Methods common to all machine instructions. 11c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch// 12ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen//===----------------------------------------------------------------------===// 13c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch 1472a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen#include "llvm/CodeGen/MachineInstr.h" 1572a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen#include "llvm/Constants.h" 16dc0f95d653279beabeb9817299e2902918ba123eKristian Monsen#include "llvm/DebugInfo.h" 17dc0f95d653279beabeb9817299e2902918ba123eKristian Monsen#include "llvm/Function.h" 183f50c38dc070f4bb515c1b64450dae14f316474eKristian Monsen#include "llvm/InlineAsm.h" 1972a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen#include "llvm/LLVMContext.h" 2072a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen#include "llvm/Metadata.h" 2172a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen#include "llvm/Module.h" 2272a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen#include "llvm/Type.h" 23c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/Value.h" 24c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/Assembly/Writer.h" 25c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/CodeGen/MachineConstantPool.h" 26ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsen#include "llvm/CodeGen/MachineFunction.h" 27c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/CodeGen/MachineMemOperand.h" 28c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/CodeGen/MachineModuleInfo.h" 29c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/CodeGen/MachineRegisterInfo.h" 30c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/CodeGen/PseudoSourceValue.h" 313f50c38dc070f4bb515c1b64450dae14f316474eKristian Monsen#include "llvm/MC/MCInstrDesc.h" 323f50c38dc070f4bb515c1b64450dae14f316474eKristian Monsen#include "llvm/MC/MCSymbol.h" 33c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/Target/TargetMachine.h" 343f50c38dc070f4bb515c1b64450dae14f316474eKristian Monsen#include "llvm/Target/TargetInstrInfo.h" 35c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/Target/TargetRegisterInfo.h" 36c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/Analysis/AliasAnalysis.h" 37c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/Support/Debug.h" 38c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/Support/ErrorHandling.h" 39c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/Support/LeakDetector.h" 40c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/Support/MathExtras.h" 413f50c38dc070f4bb515c1b64450dae14f316474eKristian Monsen#include "llvm/Support/raw_ostream.h" 42c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/ADT/FoldingSet.h" 43c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch#include "llvm/ADT/Hashing.h" 4472a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsenusing namespace llvm; 45c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch 46c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch//===----------------------------------------------------------------------===// 47c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch// MachineOperand Implementation 48c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch//===----------------------------------------------------------------------===// 49c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch 50c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch/// AddRegOperandToRegInfo - Add this register operand to the specified 51c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch/// MachineRegisterInfo. If it is null, then the next/prev fields should be 5221d179b334e59e9a3bfcaed4c4430bef1bc5759dKristian Monsen/// explicitly nulled out. 53c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdochvoid MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 5472a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen assert(isReg() && "Can only add reg operand to use lists"); 5572a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen 5672a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen // If the reginfo pointer is null, just explicitly null out or next/prev 57c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch // pointers, to ensure they are not garbage. 58c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch if (RegInfo == 0) { 59c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch Contents.Reg.Prev = 0; 60c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch Contents.Reg.Next = 0; 61c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch return; 62c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch } 633f50c38dc070f4bb515c1b64450dae14f316474eKristian Monsen 643f50c38dc070f4bb515c1b64450dae14f316474eKristian Monsen // Otherwise, add this operand to the head of the registers use/def list. 65c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 66dc0f95d653279beabeb9817299e2902918ba123eKristian Monsen 67dc0f95d653279beabeb9817299e2902918ba123eKristian Monsen // For SSA values, we prefer to keep the definition at the start of the list. 68dc0f95d653279beabeb9817299e2902918ba123eKristian Monsen // we do this by skipping over the definition if it is at the head of the 69c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch // list. 70c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch if (*Head && (*Head)->isDef()) 71c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch Head = &(*Head)->Contents.Reg.Next; 72c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch 73c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch Contents.Reg.Next = *Head; 74c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch if (Contents.Reg.Next) { 75c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch assert(getReg() == Contents.Reg.Next->getReg() && 76c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch "Different regs on the same list!"); 77c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 78c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch } 79c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch 80c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch Contents.Reg.Prev = Head; 81c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch *Head = this; 82c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch} 83c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch 84c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch/// RemoveRegOperandFromRegInfo - Remove this register operand from the 85c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch/// MachineRegisterInfo it is linked with. 86c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdochvoid MachineOperand::RemoveRegOperandFromRegInfo() { 87c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch assert(isOnRegUseList() && "Reg operand is not on a use list"); 8872a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen // Unlink this from the doubly linked list of operands. 8972a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen MachineOperand *NextOp = Contents.Reg.Next; 903345a6884c488ff3a535c2c9acdd33d74b37e311Iain Merrick *Contents.Reg.Prev = NextOp; 91c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch if (NextOp) { 9272a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!"); 9372a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen NextOp->Contents.Reg.Prev = Contents.Reg.Prev; 94c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch } 95c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch Contents.Reg.Prev = 0; 96c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch Contents.Reg.Next = 0; 97c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch} 98c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch 99ddb351dbec246cf1fab5ec20d2d5520909041de1Kristian Monsenvoid MachineOperand::setReg(unsigned Reg) { 100c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch if (getReg() == Reg) return; // No change. 101c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch 102c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch // Otherwise, we have to change the register. If this operand is embedded 103c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch // into a machine function, we need to update the old and new register's 104c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch // use/def lists. 105c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch if (MachineInstr *MI = getParent()) 106c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch if (MachineBasicBlock *MBB = MI->getParent()) 107c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch if (MachineFunction *MF = MBB->getParent()) { 108c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch RemoveRegOperandFromRegInfo(); 109c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch SmallContents.RegNo = Reg; 110c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch AddRegOperandToRegInfo(&MF->getRegInfo()); 111c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch return; 112c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch } 113c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch 114c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch // Otherwise, just change the register, no problem. :) 115c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch SmallContents.RegNo = Reg; 116c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch} 117c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch 118c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdochvoid MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, 119c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch const TargetRegisterInfo &TRI) { 120c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch assert(TargetRegisterInfo::isVirtualRegister(Reg)); 121c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch if (SubIdx && getSubReg()) 122c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 1233f50c38dc070f4bb515c1b64450dae14f316474eKristian Monsen setReg(Reg); 124c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch if (SubIdx) 125c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch setSubReg(SubIdx); 126c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch} 127c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch 128c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdochvoid MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { 129c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 130c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch if (getSubReg()) { 131c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch Reg = TRI.getSubReg(Reg, getSubReg()); 132c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch // Note that getSubReg() may return 0 if the sub-register doesn't exist. 133c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch // That won't happen in legal code. 134c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch setSubReg(0); 13572a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen } 13672a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen setReg(Reg); 13772a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen} 13872a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen 13972a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen/// ChangeToImmediate - Replace this operand with a new immediate operand of 14072a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen/// the specified value. If an operand is known to be an immediate already, 141c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch/// the setImm method should be used. 142c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdochvoid MachineOperand::ChangeToImmediate(int64_t ImmVal) { 143c407dc5cd9bdc5668497f21b26b09d988ab439deBen Murdoch // If this operand is currently a register operand, and if this is in a 14472a454cd3513ac24fbdd0e0cb9ad70b86a99b801Kristian Monsen // function, deregister the operand from the register's use/def list. 145 if (isReg() && getParent() && getParent()->getParent() && 146 getParent()->getParent()->getParent()) 147 RemoveRegOperandFromRegInfo(); 148 149 OpKind = MO_Immediate; 150 Contents.ImmVal = ImmVal; 151} 152 153/// ChangeToRegister - Replace this operand with a new register operand of 154/// the specified value. If an operand is known to be an register already, 155/// the setReg method should be used. 156void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 157 bool isKill, bool isDead, bool isUndef, 158 bool isDebug) { 159 // If this operand is already a register operand, use setReg to update the 160 // register's use/def lists. 161 if (isReg()) { 162 assert(!isEarlyClobber()); 163 setReg(Reg); 164 } else { 165 // Otherwise, change this to a register and set the reg#. 166 OpKind = MO_Register; 167 SmallContents.RegNo = Reg; 168 169 // If this operand is embedded in a function, add the operand to the 170 // register's use/def list. 171 if (MachineInstr *MI = getParent()) 172 if (MachineBasicBlock *MBB = MI->getParent()) 173 if (MachineFunction *MF = MBB->getParent()) 174 AddRegOperandToRegInfo(&MF->getRegInfo()); 175 } 176 177 IsDef = isDef; 178 IsImp = isImp; 179 IsKill = isKill; 180 IsDead = isDead; 181 IsUndef = isUndef; 182 IsInternalRead = false; 183 IsEarlyClobber = false; 184 IsDebug = isDebug; 185 SubReg = 0; 186} 187 188/// isIdenticalTo - Return true if this operand is identical to the specified 189/// operand. 190bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 191 if (getType() != Other.getType() || 192 getTargetFlags() != Other.getTargetFlags()) 193 return false; 194 195 switch (getType()) { 196 case MachineOperand::MO_Register: 197 return getReg() == Other.getReg() && isDef() == Other.isDef() && 198 getSubReg() == Other.getSubReg(); 199 case MachineOperand::MO_Immediate: 200 return getImm() == Other.getImm(); 201 case MachineOperand::MO_CImmediate: 202 return getCImm() == Other.getCImm(); 203 case MachineOperand::MO_FPImmediate: 204 return getFPImm() == Other.getFPImm(); 205 case MachineOperand::MO_MachineBasicBlock: 206 return getMBB() == Other.getMBB(); 207 case MachineOperand::MO_FrameIndex: 208 return getIndex() == Other.getIndex(); 209 case MachineOperand::MO_ConstantPoolIndex: 210 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 211 case MachineOperand::MO_JumpTableIndex: 212 return getIndex() == Other.getIndex(); 213 case MachineOperand::MO_GlobalAddress: 214 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 215 case MachineOperand::MO_ExternalSymbol: 216 return !strcmp(getSymbolName(), Other.getSymbolName()) && 217 getOffset() == Other.getOffset(); 218 case MachineOperand::MO_BlockAddress: 219 return getBlockAddress() == Other.getBlockAddress(); 220 case MO_RegisterMask: 221 return getRegMask() == Other.getRegMask(); 222 case MachineOperand::MO_MCSymbol: 223 return getMCSymbol() == Other.getMCSymbol(); 224 case MachineOperand::MO_Metadata: 225 return getMetadata() == Other.getMetadata(); 226 } 227 llvm_unreachable("Invalid machine operand type"); 228} 229 230/// print - Print the specified machine operand. 231/// 232void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 233 // If the instruction is embedded into a basic block, we can find the 234 // target info for the instruction. 235 if (!TM) 236 if (const MachineInstr *MI = getParent()) 237 if (const MachineBasicBlock *MBB = MI->getParent()) 238 if (const MachineFunction *MF = MBB->getParent()) 239 TM = &MF->getTarget(); 240 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; 241 242 switch (getType()) { 243 case MachineOperand::MO_Register: 244 OS << PrintReg(getReg(), TRI, getSubReg()); 245 246 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 247 isInternalRead() || isEarlyClobber()) { 248 OS << '<'; 249 bool NeedComma = false; 250 if (isDef()) { 251 if (NeedComma) OS << ','; 252 if (isEarlyClobber()) 253 OS << "earlyclobber,"; 254 if (isImplicit()) 255 OS << "imp-"; 256 OS << "def"; 257 NeedComma = true; 258 // <def,read-undef> only makes sense when getSubReg() is set. 259 // Don't clutter the output otherwise. 260 if (isUndef() && getSubReg()) 261 OS << ",read-undef"; 262 } else if (isImplicit()) { 263 OS << "imp-use"; 264 NeedComma = true; 265 } 266 267 if (isKill() || isDead() || (isUndef() && isUse()) || isInternalRead()) { 268 if (NeedComma) OS << ','; 269 NeedComma = false; 270 if (isKill()) { 271 OS << "kill"; 272 NeedComma = true; 273 } 274 if (isDead()) { 275 OS << "dead"; 276 NeedComma = true; 277 } 278 if (isUndef() && isUse()) { 279 if (NeedComma) OS << ','; 280 OS << "undef"; 281 NeedComma = true; 282 } 283 if (isInternalRead()) { 284 if (NeedComma) OS << ','; 285 OS << "internal"; 286 NeedComma = true; 287 } 288 } 289 OS << '>'; 290 } 291 break; 292 case MachineOperand::MO_Immediate: 293 OS << getImm(); 294 break; 295 case MachineOperand::MO_CImmediate: 296 getCImm()->getValue().print(OS, false); 297 break; 298 case MachineOperand::MO_FPImmediate: 299 if (getFPImm()->getType()->isFloatTy()) 300 OS << getFPImm()->getValueAPF().convertToFloat(); 301 else 302 OS << getFPImm()->getValueAPF().convertToDouble(); 303 break; 304 case MachineOperand::MO_MachineBasicBlock: 305 OS << "<BB#" << getMBB()->getNumber() << ">"; 306 break; 307 case MachineOperand::MO_FrameIndex: 308 OS << "<fi#" << getIndex() << '>'; 309 break; 310 case MachineOperand::MO_ConstantPoolIndex: 311 OS << "<cp#" << getIndex(); 312 if (getOffset()) OS << "+" << getOffset(); 313 OS << '>'; 314 break; 315 case MachineOperand::MO_JumpTableIndex: 316 OS << "<jt#" << getIndex() << '>'; 317 break; 318 case MachineOperand::MO_GlobalAddress: 319 OS << "<ga:"; 320 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 321 if (getOffset()) OS << "+" << getOffset(); 322 OS << '>'; 323 break; 324 case MachineOperand::MO_ExternalSymbol: 325 OS << "<es:" << getSymbolName(); 326 if (getOffset()) OS << "+" << getOffset(); 327 OS << '>'; 328 break; 329 case MachineOperand::MO_BlockAddress: 330 OS << '<'; 331 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 332 OS << '>'; 333 break; 334 case MachineOperand::MO_RegisterMask: 335 OS << "<regmask>"; 336 break; 337 case MachineOperand::MO_Metadata: 338 OS << '<'; 339 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 340 OS << '>'; 341 break; 342 case MachineOperand::MO_MCSymbol: 343 OS << "<MCSym=" << *getMCSymbol() << '>'; 344 break; 345 } 346 347 if (unsigned TF = getTargetFlags()) 348 OS << "[TF=" << TF << ']'; 349} 350 351//===----------------------------------------------------------------------===// 352// MachineMemOperand Implementation 353//===----------------------------------------------------------------------===// 354 355/// getAddrSpace - Return the LLVM IR address space number that this pointer 356/// points into. 357unsigned MachinePointerInfo::getAddrSpace() const { 358 if (V == 0) return 0; 359 return cast<PointerType>(V->getType())->getAddressSpace(); 360} 361 362/// getConstantPool - Return a MachinePointerInfo record that refers to the 363/// constant pool. 364MachinePointerInfo MachinePointerInfo::getConstantPool() { 365 return MachinePointerInfo(PseudoSourceValue::getConstantPool()); 366} 367 368/// getFixedStack - Return a MachinePointerInfo record that refers to the 369/// the specified FrameIndex. 370MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) { 371 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset); 372} 373 374MachinePointerInfo MachinePointerInfo::getJumpTable() { 375 return MachinePointerInfo(PseudoSourceValue::getJumpTable()); 376} 377 378MachinePointerInfo MachinePointerInfo::getGOT() { 379 return MachinePointerInfo(PseudoSourceValue::getGOT()); 380} 381 382MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) { 383 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset); 384} 385 386MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f, 387 uint64_t s, unsigned int a, 388 const MDNode *TBAAInfo, 389 const MDNode *Ranges) 390 : PtrInfo(ptrinfo), Size(s), 391 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)), 392 TBAAInfo(TBAAInfo), Ranges(Ranges) { 393 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) && 394 "invalid pointer value"); 395 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 396 assert((isLoad() || isStore()) && "Not a load/store!"); 397} 398 399/// Profile - Gather unique data for the object. 400/// 401void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 402 ID.AddInteger(getOffset()); 403 ID.AddInteger(Size); 404 ID.AddPointer(getValue()); 405 ID.AddInteger(Flags); 406} 407 408void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 409 // The Value and Offset may differ due to CSE. But the flags and size 410 // should be the same. 411 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 412 assert(MMO->getSize() == getSize() && "Size mismatch!"); 413 414 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 415 // Update the alignment value. 416 Flags = (Flags & ((1 << MOMaxBits) - 1)) | 417 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); 418 // Also update the base and offset, because the new alignment may 419 // not be applicable with the old ones. 420 PtrInfo = MMO->PtrInfo; 421 } 422} 423 424/// getAlignment - Return the minimum known alignment in bytes of the 425/// actual memory reference. 426uint64_t MachineMemOperand::getAlignment() const { 427 return MinAlign(getBaseAlignment(), getOffset()); 428} 429 430raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 431 assert((MMO.isLoad() || MMO.isStore()) && 432 "SV has to be a load, store or both."); 433 434 if (MMO.isVolatile()) 435 OS << "Volatile "; 436 437 if (MMO.isLoad()) 438 OS << "LD"; 439 if (MMO.isStore()) 440 OS << "ST"; 441 OS << MMO.getSize(); 442 443 // Print the address information. 444 OS << "["; 445 if (!MMO.getValue()) 446 OS << "<unknown>"; 447 else 448 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 449 450 // If the alignment of the memory reference itself differs from the alignment 451 // of the base pointer, print the base alignment explicitly, next to the base 452 // pointer. 453 if (MMO.getBaseAlignment() != MMO.getAlignment()) 454 OS << "(align=" << MMO.getBaseAlignment() << ")"; 455 456 if (MMO.getOffset() != 0) 457 OS << "+" << MMO.getOffset(); 458 OS << "]"; 459 460 // Print the alignment of the reference. 461 if (MMO.getBaseAlignment() != MMO.getAlignment() || 462 MMO.getBaseAlignment() != MMO.getSize()) 463 OS << "(align=" << MMO.getAlignment() << ")"; 464 465 // Print TBAA info. 466 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) { 467 OS << "(tbaa="; 468 if (TBAAInfo->getNumOperands() > 0) 469 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false); 470 else 471 OS << "<unknown>"; 472 OS << ")"; 473 } 474 475 // Print nontemporal info. 476 if (MMO.isNonTemporal()) 477 OS << "(nontemporal)"; 478 479 return OS; 480} 481 482//===----------------------------------------------------------------------===// 483// MachineInstr Implementation 484//===----------------------------------------------------------------------===// 485 486/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 487/// MCID NULL and no operands. 488MachineInstr::MachineInstr() 489 : MCID(0), Flags(0), AsmPrinterFlags(0), 490 NumMemRefs(0), MemRefs(0), 491 Parent(0) { 492 // Make sure that we get added to a machine basicblock 493 LeakDetector::addGarbageObject(this); 494} 495 496void MachineInstr::addImplicitDefUseOperands() { 497 if (MCID->ImplicitDefs) 498 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 499 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 500 if (MCID->ImplicitUses) 501 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) 502 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 503} 504 505/// MachineInstr ctor - This constructor creates a MachineInstr and adds the 506/// implicit operands. It reserves space for the number of operands specified by 507/// the MCInstrDesc. 508MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp) 509 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 510 NumMemRefs(0), MemRefs(0), Parent(0) { 511 unsigned NumImplicitOps = 0; 512 if (!NoImp) 513 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 514 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 515 if (!NoImp) 516 addImplicitDefUseOperands(); 517 // Make sure that we get added to a machine basicblock 518 LeakDetector::addGarbageObject(this); 519} 520 521/// MachineInstr ctor - As above, but with a DebugLoc. 522MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl, 523 bool NoImp) 524 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 525 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) { 526 unsigned NumImplicitOps = 0; 527 if (!NoImp) 528 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 529 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 530 if (!NoImp) 531 addImplicitDefUseOperands(); 532 // Make sure that we get added to a machine basicblock 533 LeakDetector::addGarbageObject(this); 534} 535 536/// MachineInstr ctor - Work exactly the same as the ctor two above, except 537/// that the MachineInstr is created and added to the end of the specified 538/// basic block. 539MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid) 540 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 541 NumMemRefs(0), MemRefs(0), Parent(0) { 542 assert(MBB && "Cannot use inserting ctor with null basic block!"); 543 unsigned NumImplicitOps = 544 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 545 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 546 addImplicitDefUseOperands(); 547 // Make sure that we get added to a machine basicblock 548 LeakDetector::addGarbageObject(this); 549 MBB->push_back(this); // Add instruction to end of basic block! 550} 551 552/// MachineInstr ctor - As above, but with a DebugLoc. 553/// 554MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 555 const MCInstrDesc &tid) 556 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 557 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) { 558 assert(MBB && "Cannot use inserting ctor with null basic block!"); 559 unsigned NumImplicitOps = 560 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 561 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 562 addImplicitDefUseOperands(); 563 // Make sure that we get added to a machine basicblock 564 LeakDetector::addGarbageObject(this); 565 MBB->push_back(this); // Add instruction to end of basic block! 566} 567 568/// MachineInstr ctor - Copies MachineInstr arg exactly 569/// 570MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 571 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0), 572 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs), 573 Parent(0), debugLoc(MI.getDebugLoc()) { 574 Operands.reserve(MI.getNumOperands()); 575 576 // Add operands 577 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 578 addOperand(MI.getOperand(i)); 579 580 // Copy all the flags. 581 Flags = MI.Flags; 582 583 // Set parent to null. 584 Parent = 0; 585 586 LeakDetector::addGarbageObject(this); 587} 588 589MachineInstr::~MachineInstr() { 590 LeakDetector::removeGarbageObject(this); 591#ifndef NDEBUG 592 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 593 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 594 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 595 "Reg operand def/use list corrupted"); 596 } 597#endif 598} 599 600/// getRegInfo - If this instruction is embedded into a MachineFunction, 601/// return the MachineRegisterInfo object for the current function, otherwise 602/// return null. 603MachineRegisterInfo *MachineInstr::getRegInfo() { 604 if (MachineBasicBlock *MBB = getParent()) 605 return &MBB->getParent()->getRegInfo(); 606 return 0; 607} 608 609/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 610/// this instruction from their respective use lists. This requires that the 611/// operands already be on their use lists. 612void MachineInstr::RemoveRegOperandsFromUseLists() { 613 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 614 if (Operands[i].isReg()) 615 Operands[i].RemoveRegOperandFromRegInfo(); 616 } 617} 618 619/// AddRegOperandsToUseLists - Add all of the register operands in 620/// this instruction from their respective use lists. This requires that the 621/// operands not be on their use lists yet. 622void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 623 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 624 if (Operands[i].isReg()) 625 Operands[i].AddRegOperandToRegInfo(&RegInfo); 626 } 627} 628 629 630/// addOperand - Add the specified operand to the instruction. If it is an 631/// implicit operand, it is added to the end of the operand list. If it is 632/// an explicit operand it is added at the end of the explicit operand list 633/// (before the first implicit operand). 634void MachineInstr::addOperand(const MachineOperand &Op) { 635 assert(MCID && "Cannot add operands before providing an instr descriptor"); 636 bool isImpReg = Op.isReg() && Op.isImplicit(); 637 MachineRegisterInfo *RegInfo = getRegInfo(); 638 639 // If the Operands backing store is reallocated, all register operands must 640 // be removed and re-added to RegInfo. It is storing pointers to operands. 641 bool Reallocate = RegInfo && 642 !Operands.empty() && Operands.size() == Operands.capacity(); 643 644 // Find the insert location for the new operand. Implicit registers go at 645 // the end, everything goes before the implicit regs. 646 unsigned OpNo = Operands.size(); 647 648 // Remove all the implicit operands from RegInfo if they need to be shifted. 649 // FIXME: Allow mixed explicit and implicit operands on inline asm. 650 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as 651 // implicit-defs, but they must not be moved around. See the FIXME in 652 // InstrEmitter.cpp. 653 if (!isImpReg && !isInlineAsm()) { 654 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { 655 --OpNo; 656 if (RegInfo) 657 Operands[OpNo].RemoveRegOperandFromRegInfo(); 658 } 659 } 660 661 // OpNo now points as the desired insertion point. Unless this is a variadic 662 // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). 663 // RegMask operands go between the explicit and implicit operands. 664 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || 665 OpNo < MCID->getNumOperands()) && 666 "Trying to add an operand to a machine instr that is already done!"); 667 668 // All operands from OpNo have been removed from RegInfo. If the Operands 669 // backing store needs to be reallocated, we also need to remove any other 670 // register operands. 671 if (Reallocate) 672 for (unsigned i = 0; i != OpNo; ++i) 673 if (Operands[i].isReg()) 674 Operands[i].RemoveRegOperandFromRegInfo(); 675 676 // Insert the new operand at OpNo. 677 Operands.insert(Operands.begin() + OpNo, Op); 678 Operands[OpNo].ParentMI = this; 679 680 // The Operands backing store has now been reallocated, so we can re-add the 681 // operands before OpNo. 682 if (Reallocate) 683 for (unsigned i = 0; i != OpNo; ++i) 684 if (Operands[i].isReg()) 685 Operands[i].AddRegOperandToRegInfo(RegInfo); 686 687 // When adding a register operand, tell RegInfo about it. 688 if (Operands[OpNo].isReg()) { 689 // Add the new operand to RegInfo, even when RegInfo is NULL. 690 // This will initialize the linked list pointers. 691 Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 692 // If the register operand is flagged as early, mark the operand as such. 693 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 694 Operands[OpNo].setIsEarlyClobber(true); 695 } 696 697 // Re-add all the implicit ops. 698 if (RegInfo) { 699 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) { 700 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 701 Operands[i].AddRegOperandToRegInfo(RegInfo); 702 } 703 } 704} 705 706/// RemoveOperand - Erase an operand from an instruction, leaving it with one 707/// fewer operand than it started with. 708/// 709void MachineInstr::RemoveOperand(unsigned OpNo) { 710 assert(OpNo < Operands.size() && "Invalid operand number"); 711 712 // Special case removing the last one. 713 if (OpNo == Operands.size()-1) { 714 // If needed, remove from the reg def/use list. 715 if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 716 Operands.back().RemoveRegOperandFromRegInfo(); 717 718 Operands.pop_back(); 719 return; 720 } 721 722 // Otherwise, we are removing an interior operand. If we have reginfo to 723 // update, remove all operands that will be shifted down from their reg lists, 724 // move everything down, then re-add them. 725 MachineRegisterInfo *RegInfo = getRegInfo(); 726 if (RegInfo) { 727 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 728 if (Operands[i].isReg()) 729 Operands[i].RemoveRegOperandFromRegInfo(); 730 } 731 } 732 733 Operands.erase(Operands.begin()+OpNo); 734 735 if (RegInfo) { 736 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 737 if (Operands[i].isReg()) 738 Operands[i].AddRegOperandToRegInfo(RegInfo); 739 } 740 } 741} 742 743/// addMemOperand - Add a MachineMemOperand to the machine instruction. 744/// This function should be used only occasionally. The setMemRefs function 745/// is the primary method for setting up a MachineInstr's MemRefs list. 746void MachineInstr::addMemOperand(MachineFunction &MF, 747 MachineMemOperand *MO) { 748 mmo_iterator OldMemRefs = MemRefs; 749 uint16_t OldNumMemRefs = NumMemRefs; 750 751 uint16_t NewNum = NumMemRefs + 1; 752 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 753 754 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs); 755 NewMemRefs[NewNum - 1] = MO; 756 757 MemRefs = NewMemRefs; 758 NumMemRefs = NewNum; 759} 760 761bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const { 762 const MachineBasicBlock *MBB = getParent(); 763 MachineBasicBlock::const_instr_iterator MII = *this; ++MII; 764 while (MII != MBB->end() && MII->isInsideBundle()) { 765 if (MII->getDesc().getFlags() & Mask) { 766 if (Type == AnyInBundle) 767 return true; 768 } else { 769 if (Type == AllInBundle) 770 return false; 771 } 772 ++MII; 773 } 774 775 return Type == AllInBundle; 776} 777 778bool MachineInstr::isIdenticalTo(const MachineInstr *Other, 779 MICheckType Check) const { 780 // If opcodes or number of operands are not the same then the two 781 // instructions are obviously not identical. 782 if (Other->getOpcode() != getOpcode() || 783 Other->getNumOperands() != getNumOperands()) 784 return false; 785 786 if (isBundle()) { 787 // Both instructions are bundles, compare MIs inside the bundle. 788 MachineBasicBlock::const_instr_iterator I1 = *this; 789 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end(); 790 MachineBasicBlock::const_instr_iterator I2 = *Other; 791 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end(); 792 while (++I1 != E1 && I1->isInsideBundle()) { 793 ++I2; 794 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check)) 795 return false; 796 } 797 } 798 799 // Check operands to make sure they match. 800 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 801 const MachineOperand &MO = getOperand(i); 802 const MachineOperand &OMO = Other->getOperand(i); 803 if (!MO.isReg()) { 804 if (!MO.isIdenticalTo(OMO)) 805 return false; 806 continue; 807 } 808 809 // Clients may or may not want to ignore defs when testing for equality. 810 // For example, machine CSE pass only cares about finding common 811 // subexpressions, so it's safe to ignore virtual register defs. 812 if (MO.isDef()) { 813 if (Check == IgnoreDefs) 814 continue; 815 else if (Check == IgnoreVRegDefs) { 816 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 817 TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) 818 if (MO.getReg() != OMO.getReg()) 819 return false; 820 } else { 821 if (!MO.isIdenticalTo(OMO)) 822 return false; 823 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) 824 return false; 825 } 826 } else { 827 if (!MO.isIdenticalTo(OMO)) 828 return false; 829 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) 830 return false; 831 } 832 } 833 // If DebugLoc does not match then two dbg.values are not identical. 834 if (isDebugValue()) 835 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown() 836 && getDebugLoc() != Other->getDebugLoc()) 837 return false; 838 return true; 839} 840 841/// removeFromParent - This method unlinks 'this' from the containing basic 842/// block, and returns it, but does not delete it. 843MachineInstr *MachineInstr::removeFromParent() { 844 assert(getParent() && "Not embedded in a basic block!"); 845 846 // If it's a bundle then remove the MIs inside the bundle as well. 847 if (isBundle()) { 848 MachineBasicBlock *MBB = getParent(); 849 MachineBasicBlock::instr_iterator MII = *this; ++MII; 850 MachineBasicBlock::instr_iterator E = MBB->instr_end(); 851 while (MII != E && MII->isInsideBundle()) { 852 MachineInstr *MI = &*MII; 853 ++MII; 854 MBB->remove(MI); 855 } 856 } 857 getParent()->remove(this); 858 return this; 859} 860 861 862/// eraseFromParent - This method unlinks 'this' from the containing basic 863/// block, and deletes it. 864void MachineInstr::eraseFromParent() { 865 assert(getParent() && "Not embedded in a basic block!"); 866 // If it's a bundle then remove the MIs inside the bundle as well. 867 if (isBundle()) { 868 MachineBasicBlock *MBB = getParent(); 869 MachineBasicBlock::instr_iterator MII = *this; ++MII; 870 MachineBasicBlock::instr_iterator E = MBB->instr_end(); 871 while (MII != E && MII->isInsideBundle()) { 872 MachineInstr *MI = &*MII; 873 ++MII; 874 MBB->erase(MI); 875 } 876 } 877 // Erase the individual instruction, which may itself be inside a bundle. 878 getParent()->erase_instr(this); 879} 880 881 882/// getNumExplicitOperands - Returns the number of non-implicit operands. 883/// 884unsigned MachineInstr::getNumExplicitOperands() const { 885 unsigned NumOperands = MCID->getNumOperands(); 886 if (!MCID->isVariadic()) 887 return NumOperands; 888 889 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 890 const MachineOperand &MO = getOperand(i); 891 if (!MO.isReg() || !MO.isImplicit()) 892 NumOperands++; 893 } 894 return NumOperands; 895} 896 897/// isBundled - Return true if this instruction part of a bundle. This is true 898/// if either itself or its following instruction is marked "InsideBundle". 899bool MachineInstr::isBundled() const { 900 if (isInsideBundle()) 901 return true; 902 MachineBasicBlock::const_instr_iterator nextMI = this; 903 ++nextMI; 904 return nextMI != Parent->instr_end() && nextMI->isInsideBundle(); 905} 906 907bool MachineInstr::isStackAligningInlineAsm() const { 908 if (isInlineAsm()) { 909 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 910 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 911 return true; 912 } 913 return false; 914} 915 916int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, 917 unsigned *GroupNo) const { 918 assert(isInlineAsm() && "Expected an inline asm instruction"); 919 assert(OpIdx < getNumOperands() && "OpIdx out of range"); 920 921 // Ignore queries about the initial operands. 922 if (OpIdx < InlineAsm::MIOp_FirstOperand) 923 return -1; 924 925 unsigned Group = 0; 926 unsigned NumOps; 927 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 928 i += NumOps) { 929 const MachineOperand &FlagMO = getOperand(i); 930 // If we reach the implicit register operands, stop looking. 931 if (!FlagMO.isImm()) 932 return -1; 933 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 934 if (i + NumOps > OpIdx) { 935 if (GroupNo) 936 *GroupNo = Group; 937 return i; 938 } 939 ++Group; 940 } 941 return -1; 942} 943 944const TargetRegisterClass* 945MachineInstr::getRegClassConstraint(unsigned OpIdx, 946 const TargetInstrInfo *TII, 947 const TargetRegisterInfo *TRI) const { 948 assert(getParent() && "Can't have an MBB reference here!"); 949 assert(getParent()->getParent() && "Can't have an MF reference here!"); 950 const MachineFunction &MF = *getParent()->getParent(); 951 952 // Most opcodes have fixed constraints in their MCInstrDesc. 953 if (!isInlineAsm()) 954 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); 955 956 if (!getOperand(OpIdx).isReg()) 957 return NULL; 958 959 // For tied uses on inline asm, get the constraint from the def. 960 unsigned DefIdx; 961 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 962 OpIdx = DefIdx; 963 964 // Inline asm stores register class constraints in the flag word. 965 int FlagIdx = findInlineAsmFlagIdx(OpIdx); 966 if (FlagIdx < 0) 967 return NULL; 968 969 unsigned Flag = getOperand(FlagIdx).getImm(); 970 unsigned RCID; 971 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) 972 return TRI->getRegClass(RCID); 973 974 // Assume that all registers in a memory operand are pointers. 975 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem) 976 return TRI->getPointerRegClass(MF); 977 978 return NULL; 979} 980 981/// getBundleSize - Return the number of instructions inside the MI bundle. 982unsigned MachineInstr::getBundleSize() const { 983 assert(isBundle() && "Expecting a bundle"); 984 985 MachineBasicBlock::const_instr_iterator I = *this; 986 unsigned Size = 0; 987 while ((++I)->isInsideBundle()) { 988 ++Size; 989 } 990 assert(Size > 1 && "Malformed bundle"); 991 992 return Size; 993} 994 995/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 996/// the specific register or -1 if it is not found. It further tightens 997/// the search criteria to a use that kills the register if isKill is true. 998int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 999 const TargetRegisterInfo *TRI) const { 1000 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1001 const MachineOperand &MO = getOperand(i); 1002 if (!MO.isReg() || !MO.isUse()) 1003 continue; 1004 unsigned MOReg = MO.getReg(); 1005 if (!MOReg) 1006 continue; 1007 if (MOReg == Reg || 1008 (TRI && 1009 TargetRegisterInfo::isPhysicalRegister(MOReg) && 1010 TargetRegisterInfo::isPhysicalRegister(Reg) && 1011 TRI->isSubRegister(MOReg, Reg))) 1012 if (!isKill || MO.isKill()) 1013 return i; 1014 } 1015 return -1; 1016} 1017 1018/// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 1019/// indicating if this instruction reads or writes Reg. This also considers 1020/// partial defines. 1021std::pair<bool,bool> 1022MachineInstr::readsWritesVirtualRegister(unsigned Reg, 1023 SmallVectorImpl<unsigned> *Ops) const { 1024 bool PartDef = false; // Partial redefine. 1025 bool FullDef = false; // Full define. 1026 bool Use = false; 1027 1028 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1029 const MachineOperand &MO = getOperand(i); 1030 if (!MO.isReg() || MO.getReg() != Reg) 1031 continue; 1032 if (Ops) 1033 Ops->push_back(i); 1034 if (MO.isUse()) 1035 Use |= !MO.isUndef(); 1036 else if (MO.getSubReg() && !MO.isUndef()) 1037 // A partial <def,undef> doesn't count as reading the register. 1038 PartDef = true; 1039 else 1040 FullDef = true; 1041 } 1042 // A partial redefine uses Reg unless there is also a full define. 1043 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); 1044} 1045 1046/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 1047/// the specified register or -1 if it is not found. If isDead is true, defs 1048/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 1049/// also checks if there is a def of a super-register. 1050int 1051MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, 1052 const TargetRegisterInfo *TRI) const { 1053 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg); 1054 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1055 const MachineOperand &MO = getOperand(i); 1056 // Accept regmask operands when Overlap is set. 1057 // Ignore them when looking for a specific def operand (Overlap == false). 1058 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) 1059 return i; 1060 if (!MO.isReg() || !MO.isDef()) 1061 continue; 1062 unsigned MOReg = MO.getReg(); 1063 bool Found = (MOReg == Reg); 1064 if (!Found && TRI && isPhys && 1065 TargetRegisterInfo::isPhysicalRegister(MOReg)) { 1066 if (Overlap) 1067 Found = TRI->regsOverlap(MOReg, Reg); 1068 else 1069 Found = TRI->isSubRegister(MOReg, Reg); 1070 } 1071 if (Found && (!isDead || MO.isDead())) 1072 return i; 1073 } 1074 return -1; 1075} 1076 1077/// findFirstPredOperandIdx() - Find the index of the first operand in the 1078/// operand list that is used to represent the predicate. It returns -1 if 1079/// none is found. 1080int MachineInstr::findFirstPredOperandIdx() const { 1081 // Don't call MCID.findFirstPredOperandIdx() because this variant 1082 // is sometimes called on an instruction that's not yet complete, and 1083 // so the number of operands is less than the MCID indicates. In 1084 // particular, the PTX target does this. 1085 const MCInstrDesc &MCID = getDesc(); 1086 if (MCID.isPredicable()) { 1087 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 1088 if (MCID.OpInfo[i].isPredicate()) 1089 return i; 1090 } 1091 1092 return -1; 1093} 1094 1095/// isRegTiedToUseOperand - Given the index of a register def operand, 1096/// check if the register def is tied to a source operand, due to either 1097/// two-address elimination or inline assembly constraints. Returns the 1098/// first tied use operand index by reference is UseOpIdx is not null. 1099bool MachineInstr:: 1100isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const { 1101 if (isInlineAsm()) { 1102 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand); 1103 const MachineOperand &MO = getOperand(DefOpIdx); 1104 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) 1105 return false; 1106 // Determine the actual operand index that corresponds to this index. 1107 unsigned DefNo = 0; 1108 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo); 1109 if (FlagIdx < 0) 1110 return false; 1111 1112 // Which part of the group is DefOpIdx? 1113 unsigned DefPart = DefOpIdx - (FlagIdx + 1); 1114 1115 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); 1116 i != e; ++i) { 1117 const MachineOperand &FMO = getOperand(i); 1118 if (!FMO.isImm()) 1119 continue; 1120 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) 1121 continue; 1122 unsigned Idx; 1123 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 1124 Idx == DefNo) { 1125 if (UseOpIdx) 1126 *UseOpIdx = (unsigned)i + 1 + DefPart; 1127 return true; 1128 } 1129 } 1130 return false; 1131 } 1132 1133 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); 1134 const MCInstrDesc &MCID = getDesc(); 1135 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { 1136 const MachineOperand &MO = getOperand(i); 1137 if (MO.isReg() && MO.isUse() && 1138 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) { 1139 if (UseOpIdx) 1140 *UseOpIdx = (unsigned)i; 1141 return true; 1142 } 1143 } 1144 return false; 1145} 1146 1147/// isRegTiedToDefOperand - Return true if the operand of the specified index 1148/// is a register use and it is tied to an def operand. It also returns the def 1149/// operand index by reference. 1150bool MachineInstr:: 1151isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { 1152 if (isInlineAsm()) { 1153 const MachineOperand &MO = getOperand(UseOpIdx); 1154 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) 1155 return false; 1156 1157 // Find the flag operand corresponding to UseOpIdx 1158 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx); 1159 if (FlagIdx < 0) 1160 return false; 1161 1162 const MachineOperand &UFMO = getOperand(FlagIdx); 1163 unsigned DefNo; 1164 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { 1165 if (!DefOpIdx) 1166 return true; 1167 1168 unsigned DefIdx = InlineAsm::MIOp_FirstOperand; 1169 // Remember to adjust the index. First operand is asm string, second is 1170 // the HasSideEffects and AlignStack bits, then there is a flag for each. 1171 while (DefNo) { 1172 const MachineOperand &FMO = getOperand(DefIdx); 1173 assert(FMO.isImm()); 1174 // Skip over this def. 1175 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; 1176 --DefNo; 1177 } 1178 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; 1179 return true; 1180 } 1181 return false; 1182 } 1183 1184 const MCInstrDesc &MCID = getDesc(); 1185 if (UseOpIdx >= MCID.getNumOperands()) 1186 return false; 1187 const MachineOperand &MO = getOperand(UseOpIdx); 1188 if (!MO.isReg() || !MO.isUse()) 1189 return false; 1190 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO); 1191 if (DefIdx == -1) 1192 return false; 1193 if (DefOpIdx) 1194 *DefOpIdx = (unsigned)DefIdx; 1195 return true; 1196} 1197 1198/// clearKillInfo - Clears kill flags on all operands. 1199/// 1200void MachineInstr::clearKillInfo() { 1201 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1202 MachineOperand &MO = getOperand(i); 1203 if (MO.isReg() && MO.isUse()) 1204 MO.setIsKill(false); 1205 } 1206} 1207 1208/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 1209/// 1210void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 1211 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1212 const MachineOperand &MO = MI->getOperand(i); 1213 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 1214 continue; 1215 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 1216 MachineOperand &MOp = getOperand(j); 1217 if (!MOp.isIdenticalTo(MO)) 1218 continue; 1219 if (MO.isKill()) 1220 MOp.setIsKill(); 1221 else 1222 MOp.setIsDead(); 1223 break; 1224 } 1225 } 1226} 1227 1228/// copyPredicates - Copies predicate operand(s) from MI. 1229void MachineInstr::copyPredicates(const MachineInstr *MI) { 1230 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles"); 1231 1232 const MCInstrDesc &MCID = MI->getDesc(); 1233 if (!MCID.isPredicable()) 1234 return; 1235 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1236 if (MCID.OpInfo[i].isPredicate()) { 1237 // Predicated operands must be last operands. 1238 addOperand(MI->getOperand(i)); 1239 } 1240 } 1241} 1242 1243void MachineInstr::substituteRegister(unsigned FromReg, 1244 unsigned ToReg, 1245 unsigned SubIdx, 1246 const TargetRegisterInfo &RegInfo) { 1247 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) { 1248 if (SubIdx) 1249 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1250 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1251 MachineOperand &MO = getOperand(i); 1252 if (!MO.isReg() || MO.getReg() != FromReg) 1253 continue; 1254 MO.substPhysReg(ToReg, RegInfo); 1255 } 1256 } else { 1257 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1258 MachineOperand &MO = getOperand(i); 1259 if (!MO.isReg() || MO.getReg() != FromReg) 1260 continue; 1261 MO.substVirtReg(ToReg, SubIdx, RegInfo); 1262 } 1263 } 1264} 1265 1266/// isSafeToMove - Return true if it is safe to move this instruction. If 1267/// SawStore is set to true, it means that there is a store (or call) between 1268/// the instruction's location and its intended destination. 1269bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 1270 AliasAnalysis *AA, 1271 bool &SawStore) const { 1272 // Ignore stuff that we obviously can't move. 1273 if (mayStore() || isCall()) { 1274 SawStore = true; 1275 return false; 1276 } 1277 1278 if (isLabel() || isDebugValue() || 1279 isTerminator() || hasUnmodeledSideEffects()) 1280 return false; 1281 1282 // See if this instruction does a load. If so, we have to guarantee that the 1283 // loaded value doesn't change between the load and the its intended 1284 // destination. The check for isInvariantLoad gives the targe the chance to 1285 // classify the load as always returning a constant, e.g. a constant pool 1286 // load. 1287 if (mayLoad() && !isInvariantLoad(AA)) 1288 // Otherwise, this is a real load. If there is a store between the load and 1289 // end of block, or if the load is volatile, we can't move it. 1290 return !SawStore && !hasVolatileMemoryRef(); 1291 1292 return true; 1293} 1294 1295/// isSafeToReMat - Return true if it's safe to rematerialize the specified 1296/// instruction which defined the specified register instead of copying it. 1297bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 1298 AliasAnalysis *AA, 1299 unsigned DstReg) const { 1300 bool SawStore = false; 1301 if (!TII->isTriviallyReMaterializable(this, AA) || 1302 !isSafeToMove(TII, AA, SawStore)) 1303 return false; 1304 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1305 const MachineOperand &MO = getOperand(i); 1306 if (!MO.isReg()) 1307 continue; 1308 // FIXME: For now, do not remat any instruction with register operands. 1309 // Later on, we can loosen the restriction is the register operands have 1310 // not been modified between the def and use. Note, this is different from 1311 // MachineSink because the code is no longer in two-address form (at least 1312 // partially). 1313 if (MO.isUse()) 1314 return false; 1315 else if (!MO.isDead() && MO.getReg() != DstReg) 1316 return false; 1317 } 1318 return true; 1319} 1320 1321/// hasVolatileMemoryRef - Return true if this instruction may have a 1322/// volatile memory reference, or if the information describing the 1323/// memory reference is not available. Return false if it is known to 1324/// have no volatile memory references. 1325bool MachineInstr::hasVolatileMemoryRef() const { 1326 // An instruction known never to access memory won't have a volatile access. 1327 if (!mayStore() && 1328 !mayLoad() && 1329 !isCall() && 1330 !hasUnmodeledSideEffects()) 1331 return false; 1332 1333 // Otherwise, if the instruction has no memory reference information, 1334 // conservatively assume it wasn't preserved. 1335 if (memoperands_empty()) 1336 return true; 1337 1338 // Check the memory reference information for volatile references. 1339 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1340 if ((*I)->isVolatile()) 1341 return true; 1342 1343 return false; 1344} 1345 1346/// isInvariantLoad - Return true if this instruction is loading from a 1347/// location whose value is invariant across the function. For example, 1348/// loading a value from the constant pool or from the argument area 1349/// of a function if it does not change. This should only return true of 1350/// *all* loads the instruction does are invariant (if it does multiple loads). 1351bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1352 // If the instruction doesn't load at all, it isn't an invariant load. 1353 if (!mayLoad()) 1354 return false; 1355 1356 // If the instruction has lost its memoperands, conservatively assume that 1357 // it may not be an invariant load. 1358 if (memoperands_empty()) 1359 return false; 1360 1361 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1362 1363 for (mmo_iterator I = memoperands_begin(), 1364 E = memoperands_end(); I != E; ++I) { 1365 if ((*I)->isVolatile()) return false; 1366 if ((*I)->isStore()) return false; 1367 if ((*I)->isInvariant()) return true; 1368 1369 if (const Value *V = (*I)->getValue()) { 1370 // A load from a constant PseudoSourceValue is invariant. 1371 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1372 if (PSV->isConstant(MFI)) 1373 continue; 1374 // If we have an AliasAnalysis, ask it whether the memory is constant. 1375 if (AA && AA->pointsToConstantMemory( 1376 AliasAnalysis::Location(V, (*I)->getSize(), 1377 (*I)->getTBAAInfo()))) 1378 continue; 1379 } 1380 1381 // Otherwise assume conservatively. 1382 return false; 1383 } 1384 1385 // Everything checks out. 1386 return true; 1387} 1388 1389/// isConstantValuePHI - If the specified instruction is a PHI that always 1390/// merges together the same virtual register, return the register, otherwise 1391/// return 0. 1392unsigned MachineInstr::isConstantValuePHI() const { 1393 if (!isPHI()) 1394 return 0; 1395 assert(getNumOperands() >= 3 && 1396 "It's illegal to have a PHI without source operands"); 1397 1398 unsigned Reg = getOperand(1).getReg(); 1399 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1400 if (getOperand(i).getReg() != Reg) 1401 return 0; 1402 return Reg; 1403} 1404 1405bool MachineInstr::hasUnmodeledSideEffects() const { 1406 if (hasProperty(MCID::UnmodeledSideEffects)) 1407 return true; 1408 if (isInlineAsm()) { 1409 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1410 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1411 return true; 1412 } 1413 1414 return false; 1415} 1416 1417/// allDefsAreDead - Return true if all the defs of this instruction are dead. 1418/// 1419bool MachineInstr::allDefsAreDead() const { 1420 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { 1421 const MachineOperand &MO = getOperand(i); 1422 if (!MO.isReg() || MO.isUse()) 1423 continue; 1424 if (!MO.isDead()) 1425 return false; 1426 } 1427 return true; 1428} 1429 1430/// copyImplicitOps - Copy implicit register operands from specified 1431/// instruction to this instruction. 1432void MachineInstr::copyImplicitOps(const MachineInstr *MI) { 1433 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands(); 1434 i != e; ++i) { 1435 const MachineOperand &MO = MI->getOperand(i); 1436 if (MO.isReg() && MO.isImplicit()) 1437 addOperand(MO); 1438 } 1439} 1440 1441void MachineInstr::dump() const { 1442 dbgs() << " " << *this; 1443} 1444 1445static void printDebugLoc(DebugLoc DL, const MachineFunction *MF, 1446 raw_ostream &CommentOS) { 1447 const LLVMContext &Ctx = MF->getFunction()->getContext(); 1448 if (!DL.isUnknown()) { // Print source line info. 1449 DIScope Scope(DL.getScope(Ctx)); 1450 // Omit the directory, because it's likely to be long and uninteresting. 1451 if (Scope.Verify()) 1452 CommentOS << Scope.getFilename(); 1453 else 1454 CommentOS << "<unknown>"; 1455 CommentOS << ':' << DL.getLine(); 1456 if (DL.getCol() != 0) 1457 CommentOS << ':' << DL.getCol(); 1458 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx)); 1459 if (!InlinedAtDL.isUnknown()) { 1460 CommentOS << " @[ "; 1461 printDebugLoc(InlinedAtDL, MF, CommentOS); 1462 CommentOS << " ]"; 1463 } 1464 } 1465} 1466 1467void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1468 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1469 const MachineFunction *MF = 0; 1470 const MachineRegisterInfo *MRI = 0; 1471 if (const MachineBasicBlock *MBB = getParent()) { 1472 MF = MBB->getParent(); 1473 if (!TM && MF) 1474 TM = &MF->getTarget(); 1475 if (MF) 1476 MRI = &MF->getRegInfo(); 1477 } 1478 1479 // Save a list of virtual registers. 1480 SmallVector<unsigned, 8> VirtRegs; 1481 1482 // Print explicitly defined operands on the left of an assignment syntax. 1483 unsigned StartOp = 0, e = getNumOperands(); 1484 for (; StartOp < e && getOperand(StartOp).isReg() && 1485 getOperand(StartOp).isDef() && 1486 !getOperand(StartOp).isImplicit(); 1487 ++StartOp) { 1488 if (StartOp != 0) OS << ", "; 1489 getOperand(StartOp).print(OS, TM); 1490 unsigned Reg = getOperand(StartOp).getReg(); 1491 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1492 VirtRegs.push_back(Reg); 1493 } 1494 1495 if (StartOp != 0) 1496 OS << " = "; 1497 1498 // Print the opcode name. 1499 if (TM && TM->getInstrInfo()) 1500 OS << TM->getInstrInfo()->getName(getOpcode()); 1501 else 1502 OS << "UNKNOWN"; 1503 1504 // Print the rest of the operands. 1505 bool OmittedAnyCallClobbers = false; 1506 bool FirstOp = true; 1507 unsigned AsmDescOp = ~0u; 1508 unsigned AsmOpCount = 0; 1509 1510 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { 1511 // Print asm string. 1512 OS << " "; 1513 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM); 1514 1515 // Print HasSideEffects, IsAlignStack 1516 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1517 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1518 OS << " [sideeffect]"; 1519 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 1520 OS << " [alignstack]"; 1521 1522 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; 1523 FirstOp = false; 1524 } 1525 1526 1527 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1528 const MachineOperand &MO = getOperand(i); 1529 1530 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1531 VirtRegs.push_back(MO.getReg()); 1532 1533 // Omit call-clobbered registers which aren't used anywhere. This makes 1534 // call instructions much less noisy on targets where calls clobber lots 1535 // of registers. Don't rely on MO.isDead() because we may be called before 1536 // LiveVariables is run, or we may be looking at a non-allocatable reg. 1537 if (MF && isCall() && 1538 MO.isReg() && MO.isImplicit() && MO.isDef()) { 1539 unsigned Reg = MO.getReg(); 1540 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 1541 const MachineRegisterInfo &MRI = MF->getRegInfo(); 1542 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1543 bool HasAliasLive = false; 1544 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true); 1545 AI.isValid(); ++AI) { 1546 unsigned AliasReg = *AI; 1547 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1548 HasAliasLive = true; 1549 break; 1550 } 1551 } 1552 if (!HasAliasLive) { 1553 OmittedAnyCallClobbers = true; 1554 continue; 1555 } 1556 } 1557 } 1558 } 1559 1560 if (FirstOp) FirstOp = false; else OS << ","; 1561 OS << " "; 1562 if (i < getDesc().NumOperands) { 1563 const MCOperandInfo &MCOI = getDesc().OpInfo[i]; 1564 if (MCOI.isPredicate()) 1565 OS << "pred:"; 1566 if (MCOI.isOptionalDef()) 1567 OS << "opt:"; 1568 } 1569 if (isDebugValue() && MO.isMetadata()) { 1570 // Pretty print DBG_VALUE instructions. 1571 const MDNode *MD = MO.getMetadata(); 1572 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2))) 1573 OS << "!\"" << MDS->getString() << '\"'; 1574 else 1575 MO.print(OS, TM); 1576 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { 1577 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm()); 1578 } else if (i == AsmDescOp && MO.isImm()) { 1579 // Pretty print the inline asm operand descriptor. 1580 OS << '$' << AsmOpCount++; 1581 unsigned Flag = MO.getImm(); 1582 switch (InlineAsm::getKind(Flag)) { 1583 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break; 1584 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break; 1585 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; 1586 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break; 1587 case InlineAsm::Kind_Imm: OS << ":[imm"; break; 1588 case InlineAsm::Kind_Mem: OS << ":[mem"; break; 1589 default: OS << ":[??" << InlineAsm::getKind(Flag); break; 1590 } 1591 1592 unsigned RCID = 0; 1593 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { 1594 if (TM) 1595 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName(); 1596 else 1597 OS << ":RC" << RCID; 1598 } 1599 1600 unsigned TiedTo = 0; 1601 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) 1602 OS << " tiedto:$" << TiedTo; 1603 1604 OS << ']'; 1605 1606 // Compute the index of the next operand descriptor. 1607 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); 1608 } else 1609 MO.print(OS, TM); 1610 } 1611 1612 // Briefly indicate whether any call clobbers were omitted. 1613 if (OmittedAnyCallClobbers) { 1614 if (!FirstOp) OS << ","; 1615 OS << " ..."; 1616 } 1617 1618 bool HaveSemi = false; 1619 if (Flags) { 1620 if (!HaveSemi) OS << ";"; HaveSemi = true; 1621 OS << " flags: "; 1622 1623 if (Flags & FrameSetup) 1624 OS << "FrameSetup"; 1625 } 1626 1627 if (!memoperands_empty()) { 1628 if (!HaveSemi) OS << ";"; HaveSemi = true; 1629 1630 OS << " mem:"; 1631 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1632 i != e; ++i) { 1633 OS << **i; 1634 if (llvm::next(i) != e) 1635 OS << " "; 1636 } 1637 } 1638 1639 // Print the regclass of any virtual registers encountered. 1640 if (MRI && !VirtRegs.empty()) { 1641 if (!HaveSemi) OS << ";"; HaveSemi = true; 1642 for (unsigned i = 0; i != VirtRegs.size(); ++i) { 1643 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]); 1644 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]); 1645 for (unsigned j = i+1; j != VirtRegs.size();) { 1646 if (MRI->getRegClass(VirtRegs[j]) != RC) { 1647 ++j; 1648 continue; 1649 } 1650 if (VirtRegs[i] != VirtRegs[j]) 1651 OS << "," << PrintReg(VirtRegs[j]); 1652 VirtRegs.erase(VirtRegs.begin()+j); 1653 } 1654 } 1655 } 1656 1657 // Print debug location information. 1658 if (isDebugValue() && getOperand(e - 1).isMetadata()) { 1659 if (!HaveSemi) OS << ";"; HaveSemi = true; 1660 DIVariable DV(getOperand(e - 1).getMetadata()); 1661 OS << " line no:" << DV.getLineNumber(); 1662 if (MDNode *InlinedAt = DV.getInlinedAt()) { 1663 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt); 1664 if (!InlinedAtDL.isUnknown()) { 1665 OS << " inlined @[ "; 1666 printDebugLoc(InlinedAtDL, MF, OS); 1667 OS << " ]"; 1668 } 1669 } 1670 } else if (!debugLoc.isUnknown() && MF) { 1671 if (!HaveSemi) OS << ";"; HaveSemi = true; 1672 OS << " dbg:"; 1673 printDebugLoc(debugLoc, MF, OS); 1674 } 1675 1676 OS << '\n'; 1677} 1678 1679bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1680 const TargetRegisterInfo *RegInfo, 1681 bool AddIfNotFound) { 1682 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1683 bool hasAliases = isPhysReg && 1684 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1685 bool Found = false; 1686 SmallVector<unsigned,4> DeadOps; 1687 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1688 MachineOperand &MO = getOperand(i); 1689 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1690 continue; 1691 unsigned Reg = MO.getReg(); 1692 if (!Reg) 1693 continue; 1694 1695 if (Reg == IncomingReg) { 1696 if (!Found) { 1697 if (MO.isKill()) 1698 // The register is already marked kill. 1699 return true; 1700 if (isPhysReg && isRegTiedToDefOperand(i)) 1701 // Two-address uses of physregs must not be marked kill. 1702 return true; 1703 MO.setIsKill(); 1704 Found = true; 1705 } 1706 } else if (hasAliases && MO.isKill() && 1707 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1708 // A super-register kill already exists. 1709 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1710 return true; 1711 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1712 DeadOps.push_back(i); 1713 } 1714 } 1715 1716 // Trim unneeded kill operands. 1717 while (!DeadOps.empty()) { 1718 unsigned OpIdx = DeadOps.back(); 1719 if (getOperand(OpIdx).isImplicit()) 1720 RemoveOperand(OpIdx); 1721 else 1722 getOperand(OpIdx).setIsKill(false); 1723 DeadOps.pop_back(); 1724 } 1725 1726 // If not found, this means an alias of one of the operands is killed. Add a 1727 // new implicit operand if required. 1728 if (!Found && AddIfNotFound) { 1729 addOperand(MachineOperand::CreateReg(IncomingReg, 1730 false /*IsDef*/, 1731 true /*IsImp*/, 1732 true /*IsKill*/)); 1733 return true; 1734 } 1735 return Found; 1736} 1737 1738void MachineInstr::clearRegisterKills(unsigned Reg, 1739 const TargetRegisterInfo *RegInfo) { 1740 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) 1741 RegInfo = 0; 1742 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1743 MachineOperand &MO = getOperand(i); 1744 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) 1745 continue; 1746 unsigned OpReg = MO.getReg(); 1747 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg))) 1748 MO.setIsKill(false); 1749 } 1750} 1751 1752bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1753 const TargetRegisterInfo *RegInfo, 1754 bool AddIfNotFound) { 1755 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1756 bool hasAliases = isPhysReg && 1757 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1758 bool Found = false; 1759 SmallVector<unsigned,4> DeadOps; 1760 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1761 MachineOperand &MO = getOperand(i); 1762 if (!MO.isReg() || !MO.isDef()) 1763 continue; 1764 unsigned Reg = MO.getReg(); 1765 if (!Reg) 1766 continue; 1767 1768 if (Reg == IncomingReg) { 1769 MO.setIsDead(); 1770 Found = true; 1771 } else if (hasAliases && MO.isDead() && 1772 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1773 // There exists a super-register that's marked dead. 1774 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1775 return true; 1776 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1777 DeadOps.push_back(i); 1778 } 1779 } 1780 1781 // Trim unneeded dead operands. 1782 while (!DeadOps.empty()) { 1783 unsigned OpIdx = DeadOps.back(); 1784 if (getOperand(OpIdx).isImplicit()) 1785 RemoveOperand(OpIdx); 1786 else 1787 getOperand(OpIdx).setIsDead(false); 1788 DeadOps.pop_back(); 1789 } 1790 1791 // If not found, this means an alias of one of the operands is dead. Add a 1792 // new implicit operand if required. 1793 if (Found || !AddIfNotFound) 1794 return Found; 1795 1796 addOperand(MachineOperand::CreateReg(IncomingReg, 1797 true /*IsDef*/, 1798 true /*IsImp*/, 1799 false /*IsKill*/, 1800 true /*IsDead*/)); 1801 return true; 1802} 1803 1804void MachineInstr::addRegisterDefined(unsigned IncomingReg, 1805 const TargetRegisterInfo *RegInfo) { 1806 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { 1807 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1808 if (MO) 1809 return; 1810 } else { 1811 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1812 const MachineOperand &MO = getOperand(i); 1813 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() && 1814 MO.getSubReg() == 0) 1815 return; 1816 } 1817 } 1818 addOperand(MachineOperand::CreateReg(IncomingReg, 1819 true /*IsDef*/, 1820 true /*IsImp*/)); 1821} 1822 1823void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, 1824 const TargetRegisterInfo &TRI) { 1825 bool HasRegMask = false; 1826 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1827 MachineOperand &MO = getOperand(i); 1828 if (MO.isRegMask()) { 1829 HasRegMask = true; 1830 continue; 1831 } 1832 if (!MO.isReg() || !MO.isDef()) continue; 1833 unsigned Reg = MO.getReg(); 1834 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 1835 bool Dead = true; 1836 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 1837 I != E; ++I) 1838 if (TRI.regsOverlap(*I, Reg)) { 1839 Dead = false; 1840 break; 1841 } 1842 // If there are no uses, including partial uses, the def is dead. 1843 if (Dead) MO.setIsDead(); 1844 } 1845 1846 // This is a call with a register mask operand. 1847 // Mask clobbers are always dead, so add defs for the non-dead defines. 1848 if (HasRegMask) 1849 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 1850 I != E; ++I) 1851 addRegisterDefined(*I, &TRI); 1852} 1853 1854unsigned 1855MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { 1856 // Build up a buffer of hash code components. 1857 // 1858 // FIXME: This is a total hack. We should have a hash_value overload for 1859 // MachineOperand, but currently that doesn't work because there are many 1860 // different ideas of "equality" and thus different sets of information that 1861 // contribute to the hash code. This one happens to want to take a specific 1862 // subset. And it's still not clear that this routine uses the *correct* 1863 // subset of information when computing the hash code. The goal is to use the 1864 // same inputs for the hash code here that MachineInstr::isIdenticalTo uses to 1865 // test for equality when passed the 'IgnoreVRegDefs' filter flag. It would 1866 // be very useful to factor the selection of relevant inputs out of the two 1867 // functions and into a common routine, but it's not clear how that can be 1868 // done. 1869 SmallVector<size_t, 8> HashComponents; 1870 HashComponents.reserve(MI->getNumOperands() + 1); 1871 HashComponents.push_back(MI->getOpcode()); 1872 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1873 const MachineOperand &MO = MI->getOperand(i); 1874 switch (MO.getType()) { 1875 default: break; 1876 case MachineOperand::MO_Register: 1877 if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1878 continue; // Skip virtual register defs. 1879 HashComponents.push_back(hash_combine(MO.getType(), MO.getReg())); 1880 break; 1881 case MachineOperand::MO_Immediate: 1882 HashComponents.push_back(hash_combine(MO.getType(), MO.getImm())); 1883 break; 1884 case MachineOperand::MO_FrameIndex: 1885 case MachineOperand::MO_ConstantPoolIndex: 1886 case MachineOperand::MO_JumpTableIndex: 1887 HashComponents.push_back(hash_combine(MO.getType(), MO.getIndex())); 1888 break; 1889 case MachineOperand::MO_MachineBasicBlock: 1890 HashComponents.push_back(hash_combine(MO.getType(), MO.getMBB())); 1891 break; 1892 case MachineOperand::MO_GlobalAddress: 1893 HashComponents.push_back(hash_combine(MO.getType(), MO.getGlobal())); 1894 break; 1895 case MachineOperand::MO_BlockAddress: 1896 HashComponents.push_back(hash_combine(MO.getType(), 1897 MO.getBlockAddress())); 1898 break; 1899 case MachineOperand::MO_MCSymbol: 1900 HashComponents.push_back(hash_combine(MO.getType(), MO.getMCSymbol())); 1901 break; 1902 } 1903 } 1904 return hash_combine_range(HashComponents.begin(), HashComponents.end()); 1905} 1906 1907void MachineInstr::emitError(StringRef Msg) const { 1908 // Find the source location cookie. 1909 unsigned LocCookie = 0; 1910 const MDNode *LocMD = 0; 1911 for (unsigned i = getNumOperands(); i != 0; --i) { 1912 if (getOperand(i-1).isMetadata() && 1913 (LocMD = getOperand(i-1).getMetadata()) && 1914 LocMD->getNumOperands() != 0) { 1915 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) { 1916 LocCookie = CI->getZExtValue(); 1917 break; 1918 } 1919 } 1920 } 1921 1922 if (const MachineBasicBlock *MBB = getParent()) 1923 if (const MachineFunction *MF = MBB->getParent()) 1924 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); 1925 report_fatal_error(Msg); 1926} 1927