MachineInstr.cpp revision 41afb9da2c808409fb689288bc9b77bc817e235d 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/Function.h"
17#include "llvm/InlineAsm.h"
18#include "llvm/LLVMContext.h"
19#include "llvm/Metadata.h"
20#include "llvm/Module.h"
21#include "llvm/Type.h"
22#include "llvm/Value.h"
23#include "llvm/Assembly/Writer.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineMemOperand.h"
27#include "llvm/CodeGen/MachineModuleInfo.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/PseudoSourceValue.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Target/TargetMachine.h"
33#include "llvm/Target/TargetInstrInfo.h"
34#include "llvm/Target/TargetRegisterInfo.h"
35#include "llvm/Analysis/AliasAnalysis.h"
36#include "llvm/Analysis/DebugInfo.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/LeakDetector.h"
40#include "llvm/Support/MathExtras.h"
41#include "llvm/Support/raw_ostream.h"
42#include "llvm/ADT/FoldingSet.h"
43#include "llvm/ADT/Hashing.h"
44using namespace llvm;
45
46//===----------------------------------------------------------------------===//
47// MachineOperand Implementation
48//===----------------------------------------------------------------------===//
49
50/// AddRegOperandToRegInfo - Add this register operand to the specified
51/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
52/// explicitly nulled out.
53void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
54  assert(isReg() && "Can only add reg operand to use lists");
55
56  // If the reginfo pointer is null, just explicitly null out or next/prev
57  // pointers, to ensure they are not garbage.
58  if (RegInfo == 0) {
59    Contents.Reg.Prev = 0;
60    Contents.Reg.Next = 0;
61    return;
62  }
63
64  // Otherwise, add this operand to the head of the registers use/def list.
65  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
66
67  // For SSA values, we prefer to keep the definition at the start of the list.
68  // we do this by skipping over the definition if it is at the head of the
69  // list.
70  if (*Head && (*Head)->isDef())
71    Head = &(*Head)->Contents.Reg.Next;
72
73  Contents.Reg.Next = *Head;
74  if (Contents.Reg.Next) {
75    assert(getReg() == Contents.Reg.Next->getReg() &&
76           "Different regs on the same list!");
77    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
78  }
79
80  Contents.Reg.Prev = Head;
81  *Head = this;
82}
83
84/// RemoveRegOperandFromRegInfo - Remove this register operand from the
85/// MachineRegisterInfo it is linked with.
86void MachineOperand::RemoveRegOperandFromRegInfo() {
87  assert(isOnRegUseList() && "Reg operand is not on a use list");
88  // Unlink this from the doubly linked list of operands.
89  MachineOperand *NextOp = Contents.Reg.Next;
90  *Contents.Reg.Prev = NextOp;
91  if (NextOp) {
92    assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
93    NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
94  }
95  Contents.Reg.Prev = 0;
96  Contents.Reg.Next = 0;
97}
98
99void MachineOperand::setReg(unsigned Reg) {
100  if (getReg() == Reg) return; // No change.
101
102  // Otherwise, we have to change the register.  If this operand is embedded
103  // into a machine function, we need to update the old and new register's
104  // use/def lists.
105  if (MachineInstr *MI = getParent())
106    if (MachineBasicBlock *MBB = MI->getParent())
107      if (MachineFunction *MF = MBB->getParent()) {
108        RemoveRegOperandFromRegInfo();
109        SmallContents.RegNo = Reg;
110        AddRegOperandToRegInfo(&MF->getRegInfo());
111        return;
112      }
113
114  // Otherwise, just change the register, no problem.  :)
115  SmallContents.RegNo = Reg;
116}
117
118void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
119                                  const TargetRegisterInfo &TRI) {
120  assert(TargetRegisterInfo::isVirtualRegister(Reg));
121  if (SubIdx && getSubReg())
122    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
123  setReg(Reg);
124  if (SubIdx)
125    setSubReg(SubIdx);
126}
127
128void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
129  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
130  if (getSubReg()) {
131    Reg = TRI.getSubReg(Reg, getSubReg());
132    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
133    // That won't happen in legal code.
134    setSubReg(0);
135  }
136  setReg(Reg);
137}
138
139/// ChangeToImmediate - Replace this operand with a new immediate operand of
140/// the specified value.  If an operand is known to be an immediate already,
141/// the setImm method should be used.
142void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
143  // If this operand is currently a register operand, and if this is in a
144  // function, deregister the operand from the register's use/def list.
145  if (isReg() && getParent() && getParent()->getParent() &&
146      getParent()->getParent()->getParent())
147    RemoveRegOperandFromRegInfo();
148
149  OpKind = MO_Immediate;
150  Contents.ImmVal = ImmVal;
151}
152
153/// ChangeToRegister - Replace this operand with a new register operand of
154/// the specified value.  If an operand is known to be an register already,
155/// the setReg method should be used.
156void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
157                                      bool isKill, bool isDead, bool isUndef,
158                                      bool isDebug) {
159  // If this operand is already a register operand, use setReg to update the
160  // register's use/def lists.
161  if (isReg()) {
162    assert(!isEarlyClobber());
163    setReg(Reg);
164  } else {
165    // Otherwise, change this to a register and set the reg#.
166    OpKind = MO_Register;
167    SmallContents.RegNo = Reg;
168
169    // If this operand is embedded in a function, add the operand to the
170    // register's use/def list.
171    if (MachineInstr *MI = getParent())
172      if (MachineBasicBlock *MBB = MI->getParent())
173        if (MachineFunction *MF = MBB->getParent())
174          AddRegOperandToRegInfo(&MF->getRegInfo());
175  }
176
177  IsDef = isDef;
178  IsImp = isImp;
179  IsKill = isKill;
180  IsDead = isDead;
181  IsUndef = isUndef;
182  IsInternalRead = false;
183  IsEarlyClobber = false;
184  IsDebug = isDebug;
185  SubReg = 0;
186}
187
188/// isIdenticalTo - Return true if this operand is identical to the specified
189/// operand.
190bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
191  if (getType() != Other.getType() ||
192      getTargetFlags() != Other.getTargetFlags())
193    return false;
194
195  switch (getType()) {
196  case MachineOperand::MO_Register:
197    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
198           getSubReg() == Other.getSubReg();
199  case MachineOperand::MO_Immediate:
200    return getImm() == Other.getImm();
201  case MachineOperand::MO_CImmediate:
202    return getCImm() == Other.getCImm();
203  case MachineOperand::MO_FPImmediate:
204    return getFPImm() == Other.getFPImm();
205  case MachineOperand::MO_MachineBasicBlock:
206    return getMBB() == Other.getMBB();
207  case MachineOperand::MO_FrameIndex:
208    return getIndex() == Other.getIndex();
209  case MachineOperand::MO_ConstantPoolIndex:
210    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
211  case MachineOperand::MO_JumpTableIndex:
212    return getIndex() == Other.getIndex();
213  case MachineOperand::MO_GlobalAddress:
214    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
215  case MachineOperand::MO_ExternalSymbol:
216    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
217           getOffset() == Other.getOffset();
218  case MachineOperand::MO_BlockAddress:
219    return getBlockAddress() == Other.getBlockAddress();
220  case MO_RegisterMask:
221    return getRegMask() == Other.getRegMask();
222  case MachineOperand::MO_MCSymbol:
223    return getMCSymbol() == Other.getMCSymbol();
224  case MachineOperand::MO_Metadata:
225    return getMetadata() == Other.getMetadata();
226  }
227  llvm_unreachable("Invalid machine operand type");
228}
229
230/// print - Print the specified machine operand.
231///
232void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
233  // If the instruction is embedded into a basic block, we can find the
234  // target info for the instruction.
235  if (!TM)
236    if (const MachineInstr *MI = getParent())
237      if (const MachineBasicBlock *MBB = MI->getParent())
238        if (const MachineFunction *MF = MBB->getParent())
239          TM = &MF->getTarget();
240  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
241
242  switch (getType()) {
243  case MachineOperand::MO_Register:
244    OS << PrintReg(getReg(), TRI, getSubReg());
245
246    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
247        isInternalRead() || isEarlyClobber()) {
248      OS << '<';
249      bool NeedComma = false;
250      if (isDef()) {
251        if (NeedComma) OS << ',';
252        if (isEarlyClobber())
253          OS << "earlyclobber,";
254        if (isImplicit())
255          OS << "imp-";
256        OS << "def";
257        NeedComma = true;
258        // <def,read-undef> only makes sense when getSubReg() is set.
259        // Don't clutter the output otherwise.
260        if (isUndef() && getSubReg())
261          OS << ",read-undef";
262      } else if (isImplicit()) {
263          OS << "imp-use";
264          NeedComma = true;
265      }
266
267      if (isKill() || isDead() || (isUndef() && isUse()) || isInternalRead()) {
268        if (NeedComma) OS << ',';
269        NeedComma = false;
270        if (isKill()) {
271          OS << "kill";
272          NeedComma = true;
273        }
274        if (isDead()) {
275          OS << "dead";
276          NeedComma = true;
277        }
278        if (isUndef() && isUse()) {
279          if (NeedComma) OS << ',';
280          OS << "undef";
281          NeedComma = true;
282        }
283        if (isInternalRead()) {
284          if (NeedComma) OS << ',';
285          OS << "internal";
286          NeedComma = true;
287        }
288      }
289      OS << '>';
290    }
291    break;
292  case MachineOperand::MO_Immediate:
293    OS << getImm();
294    break;
295  case MachineOperand::MO_CImmediate:
296    getCImm()->getValue().print(OS, false);
297    break;
298  case MachineOperand::MO_FPImmediate:
299    if (getFPImm()->getType()->isFloatTy())
300      OS << getFPImm()->getValueAPF().convertToFloat();
301    else
302      OS << getFPImm()->getValueAPF().convertToDouble();
303    break;
304  case MachineOperand::MO_MachineBasicBlock:
305    OS << "<BB#" << getMBB()->getNumber() << ">";
306    break;
307  case MachineOperand::MO_FrameIndex:
308    OS << "<fi#" << getIndex() << '>';
309    break;
310  case MachineOperand::MO_ConstantPoolIndex:
311    OS << "<cp#" << getIndex();
312    if (getOffset()) OS << "+" << getOffset();
313    OS << '>';
314    break;
315  case MachineOperand::MO_JumpTableIndex:
316    OS << "<jt#" << getIndex() << '>';
317    break;
318  case MachineOperand::MO_GlobalAddress:
319    OS << "<ga:";
320    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
321    if (getOffset()) OS << "+" << getOffset();
322    OS << '>';
323    break;
324  case MachineOperand::MO_ExternalSymbol:
325    OS << "<es:" << getSymbolName();
326    if (getOffset()) OS << "+" << getOffset();
327    OS << '>';
328    break;
329  case MachineOperand::MO_BlockAddress:
330    OS << '<';
331    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
332    OS << '>';
333    break;
334  case MachineOperand::MO_RegisterMask:
335    OS << "<regmask>";
336    break;
337  case MachineOperand::MO_Metadata:
338    OS << '<';
339    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
340    OS << '>';
341    break;
342  case MachineOperand::MO_MCSymbol:
343    OS << "<MCSym=" << *getMCSymbol() << '>';
344    break;
345  }
346
347  if (unsigned TF = getTargetFlags())
348    OS << "[TF=" << TF << ']';
349}
350
351//===----------------------------------------------------------------------===//
352// MachineMemOperand Implementation
353//===----------------------------------------------------------------------===//
354
355/// getAddrSpace - Return the LLVM IR address space number that this pointer
356/// points into.
357unsigned MachinePointerInfo::getAddrSpace() const {
358  if (V == 0) return 0;
359  return cast<PointerType>(V->getType())->getAddressSpace();
360}
361
362/// getConstantPool - Return a MachinePointerInfo record that refers to the
363/// constant pool.
364MachinePointerInfo MachinePointerInfo::getConstantPool() {
365  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
366}
367
368/// getFixedStack - Return a MachinePointerInfo record that refers to the
369/// the specified FrameIndex.
370MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
371  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
372}
373
374MachinePointerInfo MachinePointerInfo::getJumpTable() {
375  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
376}
377
378MachinePointerInfo MachinePointerInfo::getGOT() {
379  return MachinePointerInfo(PseudoSourceValue::getGOT());
380}
381
382MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
383  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
384}
385
386MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
387                                     uint64_t s, unsigned int a,
388                                     const MDNode *TBAAInfo,
389                                     const MDNode *Ranges)
390  : PtrInfo(ptrinfo), Size(s),
391    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
392    TBAAInfo(TBAAInfo), Ranges(Ranges) {
393  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
394         "invalid pointer value");
395  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
396  assert((isLoad() || isStore()) && "Not a load/store!");
397}
398
399/// Profile - Gather unique data for the object.
400///
401void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
402  ID.AddInteger(getOffset());
403  ID.AddInteger(Size);
404  ID.AddPointer(getValue());
405  ID.AddInteger(Flags);
406}
407
408void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
409  // The Value and Offset may differ due to CSE. But the flags and size
410  // should be the same.
411  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
412  assert(MMO->getSize() == getSize() && "Size mismatch!");
413
414  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
415    // Update the alignment value.
416    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
417      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
418    // Also update the base and offset, because the new alignment may
419    // not be applicable with the old ones.
420    PtrInfo = MMO->PtrInfo;
421  }
422}
423
424/// getAlignment - Return the minimum known alignment in bytes of the
425/// actual memory reference.
426uint64_t MachineMemOperand::getAlignment() const {
427  return MinAlign(getBaseAlignment(), getOffset());
428}
429
430raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
431  assert((MMO.isLoad() || MMO.isStore()) &&
432         "SV has to be a load, store or both.");
433
434  if (MMO.isVolatile())
435    OS << "Volatile ";
436
437  if (MMO.isLoad())
438    OS << "LD";
439  if (MMO.isStore())
440    OS << "ST";
441  OS << MMO.getSize();
442
443  // Print the address information.
444  OS << "[";
445  if (!MMO.getValue())
446    OS << "<unknown>";
447  else
448    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
449
450  // If the alignment of the memory reference itself differs from the alignment
451  // of the base pointer, print the base alignment explicitly, next to the base
452  // pointer.
453  if (MMO.getBaseAlignment() != MMO.getAlignment())
454    OS << "(align=" << MMO.getBaseAlignment() << ")";
455
456  if (MMO.getOffset() != 0)
457    OS << "+" << MMO.getOffset();
458  OS << "]";
459
460  // Print the alignment of the reference.
461  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
462      MMO.getBaseAlignment() != MMO.getSize())
463    OS << "(align=" << MMO.getAlignment() << ")";
464
465  // Print TBAA info.
466  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
467    OS << "(tbaa=";
468    if (TBAAInfo->getNumOperands() > 0)
469      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
470    else
471      OS << "<unknown>";
472    OS << ")";
473  }
474
475  // Print nontemporal info.
476  if (MMO.isNonTemporal())
477    OS << "(nontemporal)";
478
479  return OS;
480}
481
482//===----------------------------------------------------------------------===//
483// MachineInstr Implementation
484//===----------------------------------------------------------------------===//
485
486/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
487/// MCID NULL and no operands.
488MachineInstr::MachineInstr()
489  : MCID(0), Flags(0), AsmPrinterFlags(0),
490    NumMemRefs(0), MemRefs(0),
491    Parent(0) {
492  // Make sure that we get added to a machine basicblock
493  LeakDetector::addGarbageObject(this);
494}
495
496void MachineInstr::addImplicitDefUseOperands() {
497  if (MCID->ImplicitDefs)
498    for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
499      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
500  if (MCID->ImplicitUses)
501    for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
502      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
503}
504
505/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
506/// implicit operands. It reserves space for the number of operands specified by
507/// the MCInstrDesc.
508MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
509  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
510    NumMemRefs(0), MemRefs(0), Parent(0) {
511  unsigned NumImplicitOps = 0;
512  if (!NoImp)
513    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
514  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
515  if (!NoImp)
516    addImplicitDefUseOperands();
517  // Make sure that we get added to a machine basicblock
518  LeakDetector::addGarbageObject(this);
519}
520
521/// MachineInstr ctor - As above, but with a DebugLoc.
522MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
523                           bool NoImp)
524  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
525    NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
526  unsigned NumImplicitOps = 0;
527  if (!NoImp)
528    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
529  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
530  if (!NoImp)
531    addImplicitDefUseOperands();
532  // Make sure that we get added to a machine basicblock
533  LeakDetector::addGarbageObject(this);
534}
535
536/// MachineInstr ctor - Work exactly the same as the ctor two above, except
537/// that the MachineInstr is created and added to the end of the specified
538/// basic block.
539MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
540  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
541    NumMemRefs(0), MemRefs(0), Parent(0) {
542  assert(MBB && "Cannot use inserting ctor with null basic block!");
543  unsigned NumImplicitOps =
544    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
545  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
546  addImplicitDefUseOperands();
547  // Make sure that we get added to a machine basicblock
548  LeakDetector::addGarbageObject(this);
549  MBB->push_back(this);  // Add instruction to end of basic block!
550}
551
552/// MachineInstr ctor - As above, but with a DebugLoc.
553///
554MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
555                           const MCInstrDesc &tid)
556  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
557    NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
558  assert(MBB && "Cannot use inserting ctor with null basic block!");
559  unsigned NumImplicitOps =
560    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
561  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
562  addImplicitDefUseOperands();
563  // Make sure that we get added to a machine basicblock
564  LeakDetector::addGarbageObject(this);
565  MBB->push_back(this);  // Add instruction to end of basic block!
566}
567
568/// MachineInstr ctor - Copies MachineInstr arg exactly
569///
570MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
571  : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
572    NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
573    Parent(0), debugLoc(MI.getDebugLoc()) {
574  Operands.reserve(MI.getNumOperands());
575
576  // Add operands
577  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
578    addOperand(MI.getOperand(i));
579
580  // Copy all the flags.
581  Flags = MI.Flags;
582
583  // Set parent to null.
584  Parent = 0;
585
586  LeakDetector::addGarbageObject(this);
587}
588
589MachineInstr::~MachineInstr() {
590  LeakDetector::removeGarbageObject(this);
591#ifndef NDEBUG
592  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
593    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
594    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
595           "Reg operand def/use list corrupted");
596  }
597#endif
598}
599
600/// getRegInfo - If this instruction is embedded into a MachineFunction,
601/// return the MachineRegisterInfo object for the current function, otherwise
602/// return null.
603MachineRegisterInfo *MachineInstr::getRegInfo() {
604  if (MachineBasicBlock *MBB = getParent())
605    return &MBB->getParent()->getRegInfo();
606  return 0;
607}
608
609/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
610/// this instruction from their respective use lists.  This requires that the
611/// operands already be on their use lists.
612void MachineInstr::RemoveRegOperandsFromUseLists() {
613  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
614    if (Operands[i].isReg())
615      Operands[i].RemoveRegOperandFromRegInfo();
616  }
617}
618
619/// AddRegOperandsToUseLists - Add all of the register operands in
620/// this instruction from their respective use lists.  This requires that the
621/// operands not be on their use lists yet.
622void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
623  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
624    if (Operands[i].isReg())
625      Operands[i].AddRegOperandToRegInfo(&RegInfo);
626  }
627}
628
629
630/// addOperand - Add the specified operand to the instruction.  If it is an
631/// implicit operand, it is added to the end of the operand list.  If it is
632/// an explicit operand it is added at the end of the explicit operand list
633/// (before the first implicit operand).
634void MachineInstr::addOperand(const MachineOperand &Op) {
635  assert(MCID && "Cannot add operands before providing an instr descriptor");
636  bool isImpReg = Op.isReg() && Op.isImplicit();
637  MachineRegisterInfo *RegInfo = getRegInfo();
638
639  // If the Operands backing store is reallocated, all register operands must
640  // be removed and re-added to RegInfo.  It is storing pointers to operands.
641  bool Reallocate = RegInfo &&
642    !Operands.empty() && Operands.size() == Operands.capacity();
643
644  // Find the insert location for the new operand.  Implicit registers go at
645  // the end, everything goes before the implicit regs.
646  unsigned OpNo = Operands.size();
647
648  // Remove all the implicit operands from RegInfo if they need to be shifted.
649  // FIXME: Allow mixed explicit and implicit operands on inline asm.
650  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
651  // implicit-defs, but they must not be moved around.  See the FIXME in
652  // InstrEmitter.cpp.
653  if (!isImpReg && !isInlineAsm()) {
654    while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
655      --OpNo;
656      if (RegInfo)
657        Operands[OpNo].RemoveRegOperandFromRegInfo();
658    }
659  }
660
661  // OpNo now points as the desired insertion point.  Unless this is a variadic
662  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
663  assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) &&
664         "Trying to add an operand to a machine instr that is already done!");
665
666  // All operands from OpNo have been removed from RegInfo.  If the Operands
667  // backing store needs to be reallocated, we also need to remove any other
668  // register operands.
669  if (Reallocate)
670    for (unsigned i = 0; i != OpNo; ++i)
671      if (Operands[i].isReg())
672        Operands[i].RemoveRegOperandFromRegInfo();
673
674  // Insert the new operand at OpNo.
675  Operands.insert(Operands.begin() + OpNo, Op);
676  Operands[OpNo].ParentMI = this;
677
678  // The Operands backing store has now been reallocated, so we can re-add the
679  // operands before OpNo.
680  if (Reallocate)
681    for (unsigned i = 0; i != OpNo; ++i)
682      if (Operands[i].isReg())
683        Operands[i].AddRegOperandToRegInfo(RegInfo);
684
685  // When adding a register operand, tell RegInfo about it.
686  if (Operands[OpNo].isReg()) {
687    // Add the new operand to RegInfo, even when RegInfo is NULL.
688    // This will initialize the linked list pointers.
689    Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
690    // If the register operand is flagged as early, mark the operand as such.
691    if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
692      Operands[OpNo].setIsEarlyClobber(true);
693  }
694
695  // Re-add all the implicit ops.
696  if (RegInfo) {
697    for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
698      assert(Operands[i].isReg() && "Should only be an implicit reg!");
699      Operands[i].AddRegOperandToRegInfo(RegInfo);
700    }
701  }
702}
703
704/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
705/// fewer operand than it started with.
706///
707void MachineInstr::RemoveOperand(unsigned OpNo) {
708  assert(OpNo < Operands.size() && "Invalid operand number");
709
710  // Special case removing the last one.
711  if (OpNo == Operands.size()-1) {
712    // If needed, remove from the reg def/use list.
713    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
714      Operands.back().RemoveRegOperandFromRegInfo();
715
716    Operands.pop_back();
717    return;
718  }
719
720  // Otherwise, we are removing an interior operand.  If we have reginfo to
721  // update, remove all operands that will be shifted down from their reg lists,
722  // move everything down, then re-add them.
723  MachineRegisterInfo *RegInfo = getRegInfo();
724  if (RegInfo) {
725    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
726      if (Operands[i].isReg())
727        Operands[i].RemoveRegOperandFromRegInfo();
728    }
729  }
730
731  Operands.erase(Operands.begin()+OpNo);
732
733  if (RegInfo) {
734    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
735      if (Operands[i].isReg())
736        Operands[i].AddRegOperandToRegInfo(RegInfo);
737    }
738  }
739}
740
741/// addMemOperand - Add a MachineMemOperand to the machine instruction.
742/// This function should be used only occasionally. The setMemRefs function
743/// is the primary method for setting up a MachineInstr's MemRefs list.
744void MachineInstr::addMemOperand(MachineFunction &MF,
745                                 MachineMemOperand *MO) {
746  mmo_iterator OldMemRefs = MemRefs;
747  uint16_t OldNumMemRefs = NumMemRefs;
748
749  uint16_t NewNum = NumMemRefs + 1;
750  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
751
752  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
753  NewMemRefs[NewNum - 1] = MO;
754
755  MemRefs = NewMemRefs;
756  NumMemRefs = NewNum;
757}
758
759bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
760  const MachineBasicBlock *MBB = getParent();
761  MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
762  while (MII != MBB->end() && MII->isInsideBundle()) {
763    if (MII->getDesc().getFlags() & Mask) {
764      if (Type == AnyInBundle)
765        return true;
766    } else {
767      if (Type == AllInBundle)
768        return false;
769    }
770    ++MII;
771  }
772
773  return Type == AllInBundle;
774}
775
776bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
777                                 MICheckType Check) const {
778  // If opcodes or number of operands are not the same then the two
779  // instructions are obviously not identical.
780  if (Other->getOpcode() != getOpcode() ||
781      Other->getNumOperands() != getNumOperands())
782    return false;
783
784  if (isBundle()) {
785    // Both instructions are bundles, compare MIs inside the bundle.
786    MachineBasicBlock::const_instr_iterator I1 = *this;
787    MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
788    MachineBasicBlock::const_instr_iterator I2 = *Other;
789    MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
790    while (++I1 != E1 && I1->isInsideBundle()) {
791      ++I2;
792      if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
793        return false;
794    }
795  }
796
797  // Check operands to make sure they match.
798  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
799    const MachineOperand &MO = getOperand(i);
800    const MachineOperand &OMO = Other->getOperand(i);
801    if (!MO.isReg()) {
802      if (!MO.isIdenticalTo(OMO))
803        return false;
804      continue;
805    }
806
807    // Clients may or may not want to ignore defs when testing for equality.
808    // For example, machine CSE pass only cares about finding common
809    // subexpressions, so it's safe to ignore virtual register defs.
810    if (MO.isDef()) {
811      if (Check == IgnoreDefs)
812        continue;
813      else if (Check == IgnoreVRegDefs) {
814        if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
815            TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
816          if (MO.getReg() != OMO.getReg())
817            return false;
818      } else {
819        if (!MO.isIdenticalTo(OMO))
820          return false;
821        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
822          return false;
823      }
824    } else {
825      if (!MO.isIdenticalTo(OMO))
826        return false;
827      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
828        return false;
829    }
830  }
831  // If DebugLoc does not match then two dbg.values are not identical.
832  if (isDebugValue())
833    if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
834        && getDebugLoc() != Other->getDebugLoc())
835      return false;
836  return true;
837}
838
839/// removeFromParent - This method unlinks 'this' from the containing basic
840/// block, and returns it, but does not delete it.
841MachineInstr *MachineInstr::removeFromParent() {
842  assert(getParent() && "Not embedded in a basic block!");
843
844  // If it's a bundle then remove the MIs inside the bundle as well.
845  if (isBundle()) {
846    MachineBasicBlock *MBB = getParent();
847    MachineBasicBlock::instr_iterator MII = *this; ++MII;
848    MachineBasicBlock::instr_iterator E = MBB->instr_end();
849    while (MII != E && MII->isInsideBundle()) {
850      MachineInstr *MI = &*MII;
851      ++MII;
852      MBB->remove(MI);
853    }
854  }
855  getParent()->remove(this);
856  return this;
857}
858
859
860/// eraseFromParent - This method unlinks 'this' from the containing basic
861/// block, and deletes it.
862void MachineInstr::eraseFromParent() {
863  assert(getParent() && "Not embedded in a basic block!");
864  // If it's a bundle then remove the MIs inside the bundle as well.
865  if (isBundle()) {
866    MachineBasicBlock *MBB = getParent();
867    MachineBasicBlock::instr_iterator MII = *this; ++MII;
868    MachineBasicBlock::instr_iterator E = MBB->instr_end();
869    while (MII != E && MII->isInsideBundle()) {
870      MachineInstr *MI = &*MII;
871      ++MII;
872      MBB->erase(MI);
873    }
874  }
875  getParent()->erase(this);
876}
877
878
879/// getNumExplicitOperands - Returns the number of non-implicit operands.
880///
881unsigned MachineInstr::getNumExplicitOperands() const {
882  unsigned NumOperands = MCID->getNumOperands();
883  if (!MCID->isVariadic())
884    return NumOperands;
885
886  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
887    const MachineOperand &MO = getOperand(i);
888    if (!MO.isReg() || !MO.isImplicit())
889      NumOperands++;
890  }
891  return NumOperands;
892}
893
894/// isBundled - Return true if this instruction part of a bundle. This is true
895/// if either itself or its following instruction is marked "InsideBundle".
896bool MachineInstr::isBundled() const {
897  if (isInsideBundle())
898    return true;
899  MachineBasicBlock::const_instr_iterator nextMI = this;
900  ++nextMI;
901  return nextMI != Parent->instr_end() && nextMI->isInsideBundle();
902}
903
904bool MachineInstr::isStackAligningInlineAsm() const {
905  if (isInlineAsm()) {
906    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
907    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
908      return true;
909  }
910  return false;
911}
912
913int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
914                                       unsigned *GroupNo) const {
915  assert(isInlineAsm() && "Expected an inline asm instruction");
916  assert(OpIdx < getNumOperands() && "OpIdx out of range");
917
918  // Ignore queries about the initial operands.
919  if (OpIdx < InlineAsm::MIOp_FirstOperand)
920    return -1;
921
922  unsigned Group = 0;
923  unsigned NumOps;
924  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
925       i += NumOps) {
926    const MachineOperand &FlagMO = getOperand(i);
927    // If we reach the implicit register operands, stop looking.
928    if (!FlagMO.isImm())
929      return -1;
930    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
931    if (i + NumOps > OpIdx) {
932      if (GroupNo)
933        *GroupNo = Group;
934      return i;
935    }
936    ++Group;
937  }
938  return -1;
939}
940
941const TargetRegisterClass*
942MachineInstr::getRegClassConstraint(unsigned OpIdx,
943                                    const TargetInstrInfo *TII,
944                                    const TargetRegisterInfo *TRI) const {
945  // Most opcodes have fixed constraints in their MCInstrDesc.
946  if (!isInlineAsm())
947    return TII->getRegClass(getDesc(), OpIdx, TRI);
948
949  if (!getOperand(OpIdx).isReg())
950    return NULL;
951
952  // For tied uses on inline asm, get the constraint from the def.
953  unsigned DefIdx;
954  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
955    OpIdx = DefIdx;
956
957  // Inline asm stores register class constraints in the flag word.
958  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
959  if (FlagIdx < 0)
960    return NULL;
961
962  unsigned Flag = getOperand(FlagIdx).getImm();
963  unsigned RCID;
964  if (InlineAsm::hasRegClassConstraint(Flag, RCID))
965    return TRI->getRegClass(RCID);
966
967  // Assume that all registers in a memory operand are pointers.
968  if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
969    return TRI->getPointerRegClass();
970
971  return NULL;
972}
973
974/// getBundleSize - Return the number of instructions inside the MI bundle.
975unsigned MachineInstr::getBundleSize() const {
976  assert(isBundle() && "Expecting a bundle");
977
978  MachineBasicBlock::const_instr_iterator I = *this;
979  unsigned Size = 0;
980  while ((++I)->isInsideBundle()) {
981    ++Size;
982  }
983  assert(Size > 1 && "Malformed bundle");
984
985  return Size;
986}
987
988/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
989/// the specific register or -1 if it is not found. It further tightens
990/// the search criteria to a use that kills the register if isKill is true.
991int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
992                                          const TargetRegisterInfo *TRI) const {
993  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
994    const MachineOperand &MO = getOperand(i);
995    if (!MO.isReg() || !MO.isUse())
996      continue;
997    unsigned MOReg = MO.getReg();
998    if (!MOReg)
999      continue;
1000    if (MOReg == Reg ||
1001        (TRI &&
1002         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1003         TargetRegisterInfo::isPhysicalRegister(Reg) &&
1004         TRI->isSubRegister(MOReg, Reg)))
1005      if (!isKill || MO.isKill())
1006        return i;
1007  }
1008  return -1;
1009}
1010
1011/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1012/// indicating if this instruction reads or writes Reg. This also considers
1013/// partial defines.
1014std::pair<bool,bool>
1015MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1016                                         SmallVectorImpl<unsigned> *Ops) const {
1017  bool PartDef = false; // Partial redefine.
1018  bool FullDef = false; // Full define.
1019  bool Use = false;
1020
1021  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1022    const MachineOperand &MO = getOperand(i);
1023    if (!MO.isReg() || MO.getReg() != Reg)
1024      continue;
1025    if (Ops)
1026      Ops->push_back(i);
1027    if (MO.isUse())
1028      Use |= !MO.isUndef();
1029    else if (MO.getSubReg() && !MO.isUndef())
1030      // A partial <def,undef> doesn't count as reading the register.
1031      PartDef = true;
1032    else
1033      FullDef = true;
1034  }
1035  // A partial redefine uses Reg unless there is also a full define.
1036  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1037}
1038
1039/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1040/// the specified register or -1 if it is not found. If isDead is true, defs
1041/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1042/// also checks if there is a def of a super-register.
1043int
1044MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1045                                        const TargetRegisterInfo *TRI) const {
1046  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1047  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1048    const MachineOperand &MO = getOperand(i);
1049    // Accept regmask operands when Overlap is set.
1050    // Ignore them when looking for a specific def operand (Overlap == false).
1051    if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1052      return i;
1053    if (!MO.isReg() || !MO.isDef())
1054      continue;
1055    unsigned MOReg = MO.getReg();
1056    bool Found = (MOReg == Reg);
1057    if (!Found && TRI && isPhys &&
1058        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1059      if (Overlap)
1060        Found = TRI->regsOverlap(MOReg, Reg);
1061      else
1062        Found = TRI->isSubRegister(MOReg, Reg);
1063    }
1064    if (Found && (!isDead || MO.isDead()))
1065      return i;
1066  }
1067  return -1;
1068}
1069
1070/// findFirstPredOperandIdx() - Find the index of the first operand in the
1071/// operand list that is used to represent the predicate. It returns -1 if
1072/// none is found.
1073int MachineInstr::findFirstPredOperandIdx() const {
1074  // Don't call MCID.findFirstPredOperandIdx() because this variant
1075  // is sometimes called on an instruction that's not yet complete, and
1076  // so the number of operands is less than the MCID indicates. In
1077  // particular, the PTX target does this.
1078  const MCInstrDesc &MCID = getDesc();
1079  if (MCID.isPredicable()) {
1080    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1081      if (MCID.OpInfo[i].isPredicate())
1082        return i;
1083  }
1084
1085  return -1;
1086}
1087
1088/// isRegTiedToUseOperand - Given the index of a register def operand,
1089/// check if the register def is tied to a source operand, due to either
1090/// two-address elimination or inline assembly constraints. Returns the
1091/// first tied use operand index by reference is UseOpIdx is not null.
1092bool MachineInstr::
1093isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
1094  if (isInlineAsm()) {
1095    assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
1096    const MachineOperand &MO = getOperand(DefOpIdx);
1097    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
1098      return false;
1099    // Determine the actual operand index that corresponds to this index.
1100    unsigned DefNo = 0;
1101    int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1102    if (FlagIdx < 0)
1103      return false;
1104
1105    // Which part of the group is DefOpIdx?
1106    unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1107
1108    for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1109         i != e; ++i) {
1110      const MachineOperand &FMO = getOperand(i);
1111      if (!FMO.isImm())
1112        continue;
1113      if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1114        continue;
1115      unsigned Idx;
1116      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1117          Idx == DefNo) {
1118        if (UseOpIdx)
1119          *UseOpIdx = (unsigned)i + 1 + DefPart;
1120        return true;
1121      }
1122    }
1123    return false;
1124  }
1125
1126  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1127  const MCInstrDesc &MCID = getDesc();
1128  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1129    const MachineOperand &MO = getOperand(i);
1130    if (MO.isReg() && MO.isUse() &&
1131        MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1132      if (UseOpIdx)
1133        *UseOpIdx = (unsigned)i;
1134      return true;
1135    }
1136  }
1137  return false;
1138}
1139
1140/// isRegTiedToDefOperand - Return true if the operand of the specified index
1141/// is a register use and it is tied to an def operand. It also returns the def
1142/// operand index by reference.
1143bool MachineInstr::
1144isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1145  if (isInlineAsm()) {
1146    const MachineOperand &MO = getOperand(UseOpIdx);
1147    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1148      return false;
1149
1150    // Find the flag operand corresponding to UseOpIdx
1151    int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1152    if (FlagIdx < 0)
1153      return false;
1154
1155    const MachineOperand &UFMO = getOperand(FlagIdx);
1156    unsigned DefNo;
1157    if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1158      if (!DefOpIdx)
1159        return true;
1160
1161      unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1162      // Remember to adjust the index. First operand is asm string, second is
1163      // the HasSideEffects and AlignStack bits, then there is a flag for each.
1164      while (DefNo) {
1165        const MachineOperand &FMO = getOperand(DefIdx);
1166        assert(FMO.isImm());
1167        // Skip over this def.
1168        DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1169        --DefNo;
1170      }
1171      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1172      return true;
1173    }
1174    return false;
1175  }
1176
1177  const MCInstrDesc &MCID = getDesc();
1178  if (UseOpIdx >= MCID.getNumOperands())
1179    return false;
1180  const MachineOperand &MO = getOperand(UseOpIdx);
1181  if (!MO.isReg() || !MO.isUse())
1182    return false;
1183  int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1184  if (DefIdx == -1)
1185    return false;
1186  if (DefOpIdx)
1187    *DefOpIdx = (unsigned)DefIdx;
1188  return true;
1189}
1190
1191/// clearKillInfo - Clears kill flags on all operands.
1192///
1193void MachineInstr::clearKillInfo() {
1194  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1195    MachineOperand &MO = getOperand(i);
1196    if (MO.isReg() && MO.isUse())
1197      MO.setIsKill(false);
1198  }
1199}
1200
1201/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1202///
1203void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1204  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1205    const MachineOperand &MO = MI->getOperand(i);
1206    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1207      continue;
1208    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1209      MachineOperand &MOp = getOperand(j);
1210      if (!MOp.isIdenticalTo(MO))
1211        continue;
1212      if (MO.isKill())
1213        MOp.setIsKill();
1214      else
1215        MOp.setIsDead();
1216      break;
1217    }
1218  }
1219}
1220
1221/// copyPredicates - Copies predicate operand(s) from MI.
1222void MachineInstr::copyPredicates(const MachineInstr *MI) {
1223  assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1224
1225  const MCInstrDesc &MCID = MI->getDesc();
1226  if (!MCID.isPredicable())
1227    return;
1228  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1229    if (MCID.OpInfo[i].isPredicate()) {
1230      // Predicated operands must be last operands.
1231      addOperand(MI->getOperand(i));
1232    }
1233  }
1234}
1235
1236void MachineInstr::substituteRegister(unsigned FromReg,
1237                                      unsigned ToReg,
1238                                      unsigned SubIdx,
1239                                      const TargetRegisterInfo &RegInfo) {
1240  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1241    if (SubIdx)
1242      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1243    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1244      MachineOperand &MO = getOperand(i);
1245      if (!MO.isReg() || MO.getReg() != FromReg)
1246        continue;
1247      MO.substPhysReg(ToReg, RegInfo);
1248    }
1249  } else {
1250    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1251      MachineOperand &MO = getOperand(i);
1252      if (!MO.isReg() || MO.getReg() != FromReg)
1253        continue;
1254      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1255    }
1256  }
1257}
1258
1259/// isSafeToMove - Return true if it is safe to move this instruction. If
1260/// SawStore is set to true, it means that there is a store (or call) between
1261/// the instruction's location and its intended destination.
1262bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1263                                AliasAnalysis *AA,
1264                                bool &SawStore) const {
1265  // Ignore stuff that we obviously can't move.
1266  if (mayStore() || isCall()) {
1267    SawStore = true;
1268    return false;
1269  }
1270
1271  if (isLabel() || isDebugValue() ||
1272      isTerminator() || hasUnmodeledSideEffects())
1273    return false;
1274
1275  // See if this instruction does a load.  If so, we have to guarantee that the
1276  // loaded value doesn't change between the load and the its intended
1277  // destination. The check for isInvariantLoad gives the targe the chance to
1278  // classify the load as always returning a constant, e.g. a constant pool
1279  // load.
1280  if (mayLoad() && !isInvariantLoad(AA))
1281    // Otherwise, this is a real load.  If there is a store between the load and
1282    // end of block, or if the load is volatile, we can't move it.
1283    return !SawStore && !hasVolatileMemoryRef();
1284
1285  return true;
1286}
1287
1288/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1289/// instruction which defined the specified register instead of copying it.
1290bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1291                                 AliasAnalysis *AA,
1292                                 unsigned DstReg) const {
1293  bool SawStore = false;
1294  if (!TII->isTriviallyReMaterializable(this, AA) ||
1295      !isSafeToMove(TII, AA, SawStore))
1296    return false;
1297  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1298    const MachineOperand &MO = getOperand(i);
1299    if (!MO.isReg())
1300      continue;
1301    // FIXME: For now, do not remat any instruction with register operands.
1302    // Later on, we can loosen the restriction is the register operands have
1303    // not been modified between the def and use. Note, this is different from
1304    // MachineSink because the code is no longer in two-address form (at least
1305    // partially).
1306    if (MO.isUse())
1307      return false;
1308    else if (!MO.isDead() && MO.getReg() != DstReg)
1309      return false;
1310  }
1311  return true;
1312}
1313
1314/// hasVolatileMemoryRef - Return true if this instruction may have a
1315/// volatile memory reference, or if the information describing the
1316/// memory reference is not available. Return false if it is known to
1317/// have no volatile memory references.
1318bool MachineInstr::hasVolatileMemoryRef() const {
1319  // An instruction known never to access memory won't have a volatile access.
1320  if (!mayStore() &&
1321      !mayLoad() &&
1322      !isCall() &&
1323      !hasUnmodeledSideEffects())
1324    return false;
1325
1326  // Otherwise, if the instruction has no memory reference information,
1327  // conservatively assume it wasn't preserved.
1328  if (memoperands_empty())
1329    return true;
1330
1331  // Check the memory reference information for volatile references.
1332  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1333    if ((*I)->isVolatile())
1334      return true;
1335
1336  return false;
1337}
1338
1339/// isInvariantLoad - Return true if this instruction is loading from a
1340/// location whose value is invariant across the function.  For example,
1341/// loading a value from the constant pool or from the argument area
1342/// of a function if it does not change.  This should only return true of
1343/// *all* loads the instruction does are invariant (if it does multiple loads).
1344bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1345  // If the instruction doesn't load at all, it isn't an invariant load.
1346  if (!mayLoad())
1347    return false;
1348
1349  // If the instruction has lost its memoperands, conservatively assume that
1350  // it may not be an invariant load.
1351  if (memoperands_empty())
1352    return false;
1353
1354  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1355
1356  for (mmo_iterator I = memoperands_begin(),
1357       E = memoperands_end(); I != E; ++I) {
1358    if ((*I)->isVolatile()) return false;
1359    if ((*I)->isStore()) return false;
1360    if ((*I)->isInvariant()) return true;
1361
1362    if (const Value *V = (*I)->getValue()) {
1363      // A load from a constant PseudoSourceValue is invariant.
1364      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1365        if (PSV->isConstant(MFI))
1366          continue;
1367      // If we have an AliasAnalysis, ask it whether the memory is constant.
1368      if (AA && AA->pointsToConstantMemory(
1369                      AliasAnalysis::Location(V, (*I)->getSize(),
1370                                              (*I)->getTBAAInfo())))
1371        continue;
1372    }
1373
1374    // Otherwise assume conservatively.
1375    return false;
1376  }
1377
1378  // Everything checks out.
1379  return true;
1380}
1381
1382/// isConstantValuePHI - If the specified instruction is a PHI that always
1383/// merges together the same virtual register, return the register, otherwise
1384/// return 0.
1385unsigned MachineInstr::isConstantValuePHI() const {
1386  if (!isPHI())
1387    return 0;
1388  assert(getNumOperands() >= 3 &&
1389         "It's illegal to have a PHI without source operands");
1390
1391  unsigned Reg = getOperand(1).getReg();
1392  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1393    if (getOperand(i).getReg() != Reg)
1394      return 0;
1395  return Reg;
1396}
1397
1398bool MachineInstr::hasUnmodeledSideEffects() const {
1399  if (hasProperty(MCID::UnmodeledSideEffects))
1400    return true;
1401  if (isInlineAsm()) {
1402    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1403    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1404      return true;
1405  }
1406
1407  return false;
1408}
1409
1410/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1411///
1412bool MachineInstr::allDefsAreDead() const {
1413  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1414    const MachineOperand &MO = getOperand(i);
1415    if (!MO.isReg() || MO.isUse())
1416      continue;
1417    if (!MO.isDead())
1418      return false;
1419  }
1420  return true;
1421}
1422
1423/// copyImplicitOps - Copy implicit register operands from specified
1424/// instruction to this instruction.
1425void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1426  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1427       i != e; ++i) {
1428    const MachineOperand &MO = MI->getOperand(i);
1429    if (MO.isReg() && MO.isImplicit())
1430      addOperand(MO);
1431  }
1432}
1433
1434void MachineInstr::dump() const {
1435  dbgs() << "  " << *this;
1436}
1437
1438static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1439                         raw_ostream &CommentOS) {
1440  const LLVMContext &Ctx = MF->getFunction()->getContext();
1441  if (!DL.isUnknown()) {          // Print source line info.
1442    DIScope Scope(DL.getScope(Ctx));
1443    // Omit the directory, because it's likely to be long and uninteresting.
1444    if (Scope.Verify())
1445      CommentOS << Scope.getFilename();
1446    else
1447      CommentOS << "<unknown>";
1448    CommentOS << ':' << DL.getLine();
1449    if (DL.getCol() != 0)
1450      CommentOS << ':' << DL.getCol();
1451    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1452    if (!InlinedAtDL.isUnknown()) {
1453      CommentOS << " @[ ";
1454      printDebugLoc(InlinedAtDL, MF, CommentOS);
1455      CommentOS << " ]";
1456    }
1457  }
1458}
1459
1460void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1461  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1462  const MachineFunction *MF = 0;
1463  const MachineRegisterInfo *MRI = 0;
1464  if (const MachineBasicBlock *MBB = getParent()) {
1465    MF = MBB->getParent();
1466    if (!TM && MF)
1467      TM = &MF->getTarget();
1468    if (MF)
1469      MRI = &MF->getRegInfo();
1470  }
1471
1472  // Save a list of virtual registers.
1473  SmallVector<unsigned, 8> VirtRegs;
1474
1475  // Print explicitly defined operands on the left of an assignment syntax.
1476  unsigned StartOp = 0, e = getNumOperands();
1477  for (; StartOp < e && getOperand(StartOp).isReg() &&
1478         getOperand(StartOp).isDef() &&
1479         !getOperand(StartOp).isImplicit();
1480       ++StartOp) {
1481    if (StartOp != 0) OS << ", ";
1482    getOperand(StartOp).print(OS, TM);
1483    unsigned Reg = getOperand(StartOp).getReg();
1484    if (TargetRegisterInfo::isVirtualRegister(Reg))
1485      VirtRegs.push_back(Reg);
1486  }
1487
1488  if (StartOp != 0)
1489    OS << " = ";
1490
1491  // Print the opcode name.
1492  if (TM && TM->getInstrInfo())
1493    OS << TM->getInstrInfo()->getName(getOpcode());
1494  else
1495    OS << "UNKNOWN";
1496
1497  // Print the rest of the operands.
1498  bool OmittedAnyCallClobbers = false;
1499  bool FirstOp = true;
1500  unsigned AsmDescOp = ~0u;
1501  unsigned AsmOpCount = 0;
1502
1503  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1504    // Print asm string.
1505    OS << " ";
1506    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1507
1508    // Print HasSideEffects, IsAlignStack
1509    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1510    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1511      OS << " [sideeffect]";
1512    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1513      OS << " [alignstack]";
1514
1515    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1516    FirstOp = false;
1517  }
1518
1519
1520  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1521    const MachineOperand &MO = getOperand(i);
1522
1523    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1524      VirtRegs.push_back(MO.getReg());
1525
1526    // Omit call-clobbered registers which aren't used anywhere. This makes
1527    // call instructions much less noisy on targets where calls clobber lots
1528    // of registers. Don't rely on MO.isDead() because we may be called before
1529    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1530    if (MF && isCall() &&
1531        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1532      unsigned Reg = MO.getReg();
1533      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1534        const MachineRegisterInfo &MRI = MF->getRegInfo();
1535        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1536          bool HasAliasLive = false;
1537          for (const uint16_t *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1538               unsigned AliasReg = *Alias; ++Alias)
1539            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1540              HasAliasLive = true;
1541              break;
1542            }
1543          if (!HasAliasLive) {
1544            OmittedAnyCallClobbers = true;
1545            continue;
1546          }
1547        }
1548      }
1549    }
1550
1551    if (FirstOp) FirstOp = false; else OS << ",";
1552    OS << " ";
1553    if (i < getDesc().NumOperands) {
1554      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1555      if (MCOI.isPredicate())
1556        OS << "pred:";
1557      if (MCOI.isOptionalDef())
1558        OS << "opt:";
1559    }
1560    if (isDebugValue() && MO.isMetadata()) {
1561      // Pretty print DBG_VALUE instructions.
1562      const MDNode *MD = MO.getMetadata();
1563      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1564        OS << "!\"" << MDS->getString() << '\"';
1565      else
1566        MO.print(OS, TM);
1567    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1568      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1569    } else if (i == AsmDescOp && MO.isImm()) {
1570      // Pretty print the inline asm operand descriptor.
1571      OS << '$' << AsmOpCount++;
1572      unsigned Flag = MO.getImm();
1573      switch (InlineAsm::getKind(Flag)) {
1574      case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
1575      case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
1576      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1577      case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
1578      case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
1579      case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
1580      default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1581      }
1582
1583      unsigned RCID = 0;
1584      if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1585        if (TM)
1586          OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1587        else
1588          OS << ":RC" << RCID;
1589      }
1590
1591      unsigned TiedTo = 0;
1592      if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1593        OS << " tiedto:$" << TiedTo;
1594
1595      OS << ']';
1596
1597      // Compute the index of the next operand descriptor.
1598      AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1599    } else
1600      MO.print(OS, TM);
1601  }
1602
1603  // Briefly indicate whether any call clobbers were omitted.
1604  if (OmittedAnyCallClobbers) {
1605    if (!FirstOp) OS << ",";
1606    OS << " ...";
1607  }
1608
1609  bool HaveSemi = false;
1610  if (Flags) {
1611    if (!HaveSemi) OS << ";"; HaveSemi = true;
1612    OS << " flags: ";
1613
1614    if (Flags & FrameSetup)
1615      OS << "FrameSetup";
1616  }
1617
1618  if (!memoperands_empty()) {
1619    if (!HaveSemi) OS << ";"; HaveSemi = true;
1620
1621    OS << " mem:";
1622    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1623         i != e; ++i) {
1624      OS << **i;
1625      if (llvm::next(i) != e)
1626        OS << " ";
1627    }
1628  }
1629
1630  // Print the regclass of any virtual registers encountered.
1631  if (MRI && !VirtRegs.empty()) {
1632    if (!HaveSemi) OS << ";"; HaveSemi = true;
1633    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1634      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1635      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1636      for (unsigned j = i+1; j != VirtRegs.size();) {
1637        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1638          ++j;
1639          continue;
1640        }
1641        if (VirtRegs[i] != VirtRegs[j])
1642          OS << "," << PrintReg(VirtRegs[j]);
1643        VirtRegs.erase(VirtRegs.begin()+j);
1644      }
1645    }
1646  }
1647
1648  // Print debug location information.
1649  if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1650    if (!HaveSemi) OS << ";"; HaveSemi = true;
1651    DIVariable DV(getOperand(e - 1).getMetadata());
1652    OS << " line no:" <<  DV.getLineNumber();
1653    if (MDNode *InlinedAt = DV.getInlinedAt()) {
1654      DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1655      if (!InlinedAtDL.isUnknown()) {
1656        OS << " inlined @[ ";
1657        printDebugLoc(InlinedAtDL, MF, OS);
1658        OS << " ]";
1659      }
1660    }
1661  } else if (!debugLoc.isUnknown() && MF) {
1662    if (!HaveSemi) OS << ";"; HaveSemi = true;
1663    OS << " dbg:";
1664    printDebugLoc(debugLoc, MF, OS);
1665  }
1666
1667  OS << '\n';
1668}
1669
1670bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1671                                     const TargetRegisterInfo *RegInfo,
1672                                     bool AddIfNotFound) {
1673  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1674  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1675  bool Found = false;
1676  SmallVector<unsigned,4> DeadOps;
1677  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1678    MachineOperand &MO = getOperand(i);
1679    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1680      continue;
1681    unsigned Reg = MO.getReg();
1682    if (!Reg)
1683      continue;
1684
1685    if (Reg == IncomingReg) {
1686      if (!Found) {
1687        if (MO.isKill())
1688          // The register is already marked kill.
1689          return true;
1690        if (isPhysReg && isRegTiedToDefOperand(i))
1691          // Two-address uses of physregs must not be marked kill.
1692          return true;
1693        MO.setIsKill();
1694        Found = true;
1695      }
1696    } else if (hasAliases && MO.isKill() &&
1697               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1698      // A super-register kill already exists.
1699      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1700        return true;
1701      if (RegInfo->isSubRegister(IncomingReg, Reg))
1702        DeadOps.push_back(i);
1703    }
1704  }
1705
1706  // Trim unneeded kill operands.
1707  while (!DeadOps.empty()) {
1708    unsigned OpIdx = DeadOps.back();
1709    if (getOperand(OpIdx).isImplicit())
1710      RemoveOperand(OpIdx);
1711    else
1712      getOperand(OpIdx).setIsKill(false);
1713    DeadOps.pop_back();
1714  }
1715
1716  // If not found, this means an alias of one of the operands is killed. Add a
1717  // new implicit operand if required.
1718  if (!Found && AddIfNotFound) {
1719    addOperand(MachineOperand::CreateReg(IncomingReg,
1720                                         false /*IsDef*/,
1721                                         true  /*IsImp*/,
1722                                         true  /*IsKill*/));
1723    return true;
1724  }
1725  return Found;
1726}
1727
1728void MachineInstr::clearRegisterKills(unsigned Reg,
1729                                      const TargetRegisterInfo *RegInfo) {
1730  if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1731    RegInfo = 0;
1732  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1733    MachineOperand &MO = getOperand(i);
1734    if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1735      continue;
1736    unsigned OpReg = MO.getReg();
1737    if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1738      MO.setIsKill(false);
1739  }
1740}
1741
1742bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1743                                   const TargetRegisterInfo *RegInfo,
1744                                   bool AddIfNotFound) {
1745  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1746  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1747  bool Found = false;
1748  SmallVector<unsigned,4> DeadOps;
1749  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1750    MachineOperand &MO = getOperand(i);
1751    if (!MO.isReg() || !MO.isDef())
1752      continue;
1753    unsigned Reg = MO.getReg();
1754    if (!Reg)
1755      continue;
1756
1757    if (Reg == IncomingReg) {
1758      MO.setIsDead();
1759      Found = true;
1760    } else if (hasAliases && MO.isDead() &&
1761               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1762      // There exists a super-register that's marked dead.
1763      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1764        return true;
1765      if (RegInfo->getSubRegisters(IncomingReg) &&
1766          RegInfo->getSuperRegisters(Reg) &&
1767          RegInfo->isSubRegister(IncomingReg, Reg))
1768        DeadOps.push_back(i);
1769    }
1770  }
1771
1772  // Trim unneeded dead operands.
1773  while (!DeadOps.empty()) {
1774    unsigned OpIdx = DeadOps.back();
1775    if (getOperand(OpIdx).isImplicit())
1776      RemoveOperand(OpIdx);
1777    else
1778      getOperand(OpIdx).setIsDead(false);
1779    DeadOps.pop_back();
1780  }
1781
1782  // If not found, this means an alias of one of the operands is dead. Add a
1783  // new implicit operand if required.
1784  if (Found || !AddIfNotFound)
1785    return Found;
1786
1787  addOperand(MachineOperand::CreateReg(IncomingReg,
1788                                       true  /*IsDef*/,
1789                                       true  /*IsImp*/,
1790                                       false /*IsKill*/,
1791                                       true  /*IsDead*/));
1792  return true;
1793}
1794
1795void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1796                                      const TargetRegisterInfo *RegInfo) {
1797  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1798    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1799    if (MO)
1800      return;
1801  } else {
1802    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1803      const MachineOperand &MO = getOperand(i);
1804      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1805          MO.getSubReg() == 0)
1806        return;
1807    }
1808  }
1809  addOperand(MachineOperand::CreateReg(IncomingReg,
1810                                       true  /*IsDef*/,
1811                                       true  /*IsImp*/));
1812}
1813
1814void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1815                                         const TargetRegisterInfo &TRI) {
1816  bool HasRegMask = false;
1817  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1818    MachineOperand &MO = getOperand(i);
1819    if (MO.isRegMask()) {
1820      HasRegMask = true;
1821      continue;
1822    }
1823    if (!MO.isReg() || !MO.isDef()) continue;
1824    unsigned Reg = MO.getReg();
1825    if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1826    bool Dead = true;
1827    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1828         I != E; ++I)
1829      if (TRI.regsOverlap(*I, Reg)) {
1830        Dead = false;
1831        break;
1832      }
1833    // If there are no uses, including partial uses, the def is dead.
1834    if (Dead) MO.setIsDead();
1835  }
1836
1837  // This is a call with a register mask operand.
1838  // Mask clobbers are always dead, so add defs for the non-dead defines.
1839  if (HasRegMask)
1840    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1841         I != E; ++I)
1842      addRegisterDefined(*I, &TRI);
1843}
1844
1845unsigned
1846MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1847  // Build up a buffer of hash code components.
1848  //
1849  // FIXME: This is a total hack. We should have a hash_value overload for
1850  // MachineOperand, but currently that doesn't work because there are many
1851  // different ideas of "equality" and thus different sets of information that
1852  // contribute to the hash code. This one happens to want to take a specific
1853  // subset. And it's still not clear that this routine uses the *correct*
1854  // subset of information when computing the hash code. The goal is to use the
1855  // same inputs for the hash code here that MachineInstr::isIdenticalTo uses to
1856  // test for equality when passed the 'IgnoreVRegDefs' filter flag. It would
1857  // be very useful to factor the selection of relevant inputs out of the two
1858  // functions and into a common routine, but it's not clear how that can be
1859  // done.
1860  SmallVector<size_t, 8> HashComponents;
1861  HashComponents.reserve(MI->getNumOperands() + 1);
1862  HashComponents.push_back(MI->getOpcode());
1863  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1864    const MachineOperand &MO = MI->getOperand(i);
1865    switch (MO.getType()) {
1866    default: break;
1867    case MachineOperand::MO_Register:
1868      if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1869        continue;  // Skip virtual register defs.
1870      HashComponents.push_back(hash_combine(MO.getType(), MO.getReg()));
1871      break;
1872    case MachineOperand::MO_Immediate:
1873      HashComponents.push_back(hash_combine(MO.getType(), MO.getImm()));
1874      break;
1875    case MachineOperand::MO_FrameIndex:
1876    case MachineOperand::MO_ConstantPoolIndex:
1877    case MachineOperand::MO_JumpTableIndex:
1878      HashComponents.push_back(hash_combine(MO.getType(), MO.getIndex()));
1879      break;
1880    case MachineOperand::MO_MachineBasicBlock:
1881      HashComponents.push_back(hash_combine(MO.getType(), MO.getMBB()));
1882      break;
1883    case MachineOperand::MO_GlobalAddress:
1884      HashComponents.push_back(hash_combine(MO.getType(), MO.getGlobal()));
1885      break;
1886    case MachineOperand::MO_BlockAddress:
1887      HashComponents.push_back(hash_combine(MO.getType(),
1888                                            MO.getBlockAddress()));
1889      break;
1890    case MachineOperand::MO_MCSymbol:
1891      HashComponents.push_back(hash_combine(MO.getType(), MO.getMCSymbol()));
1892      break;
1893    }
1894  }
1895  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1896}
1897
1898void MachineInstr::emitError(StringRef Msg) const {
1899  // Find the source location cookie.
1900  unsigned LocCookie = 0;
1901  const MDNode *LocMD = 0;
1902  for (unsigned i = getNumOperands(); i != 0; --i) {
1903    if (getOperand(i-1).isMetadata() &&
1904        (LocMD = getOperand(i-1).getMetadata()) &&
1905        LocMD->getNumOperands() != 0) {
1906      if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1907        LocCookie = CI->getZExtValue();
1908        break;
1909      }
1910    }
1911  }
1912
1913  if (const MachineBasicBlock *MBB = getParent())
1914    if (const MachineFunction *MF = MBB->getParent())
1915      return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1916  report_fatal_error(Msg);
1917}
1918