MachineInstr.cpp revision 4e526b9a5b36d9bac170c03df0a5d6fb76740ae2
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Constants.h" 15#include "llvm/CodeGen/MachineInstr.h" 16#include "llvm/Value.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineRegisterInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/CodeGen/SelectionDAGNodes.h" 21#include "llvm/Target/TargetMachine.h" 22#include "llvm/Target/TargetInstrInfo.h" 23#include "llvm/Target/TargetInstrDesc.h" 24#include "llvm/Target/TargetRegisterInfo.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/Streams.h" 27#include <ostream> 28using namespace llvm; 29 30//===----------------------------------------------------------------------===// 31// MachineOperand Implementation 32//===----------------------------------------------------------------------===// 33 34/// AddRegOperandToRegInfo - Add this register operand to the specified 35/// MachineRegisterInfo. If it is null, then the next/prev fields should be 36/// explicitly nulled out. 37void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 38 assert(isReg() && "Can only add reg operand to use lists"); 39 40 // If the reginfo pointer is null, just explicitly null out or next/prev 41 // pointers, to ensure they are not garbage. 42 if (RegInfo == 0) { 43 Contents.Reg.Prev = 0; 44 Contents.Reg.Next = 0; 45 return; 46 } 47 48 // Otherwise, add this operand to the head of the registers use/def list. 49 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 50 51 // For SSA values, we prefer to keep the definition at the start of the list. 52 // we do this by skipping over the definition if it is at the head of the 53 // list. 54 if (*Head && (*Head)->isDef()) 55 Head = &(*Head)->Contents.Reg.Next; 56 57 Contents.Reg.Next = *Head; 58 if (Contents.Reg.Next) { 59 assert(getReg() == Contents.Reg.Next->getReg() && 60 "Different regs on the same list!"); 61 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 62 } 63 64 Contents.Reg.Prev = Head; 65 *Head = this; 66} 67 68void MachineOperand::setReg(unsigned Reg) { 69 if (getReg() == Reg) return; // No change. 70 71 // Otherwise, we have to change the register. If this operand is embedded 72 // into a machine function, we need to update the old and new register's 73 // use/def lists. 74 if (MachineInstr *MI = getParent()) 75 if (MachineBasicBlock *MBB = MI->getParent()) 76 if (MachineFunction *MF = MBB->getParent()) { 77 RemoveRegOperandFromRegInfo(); 78 Contents.Reg.RegNo = Reg; 79 AddRegOperandToRegInfo(&MF->getRegInfo()); 80 return; 81 } 82 83 // Otherwise, just change the register, no problem. :) 84 Contents.Reg.RegNo = Reg; 85} 86 87/// ChangeToImmediate - Replace this operand with a new immediate operand of 88/// the specified value. If an operand is known to be an immediate already, 89/// the setImm method should be used. 90void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 91 // If this operand is currently a register operand, and if this is in a 92 // function, deregister the operand from the register's use/def list. 93 if (isReg() && getParent() && getParent()->getParent() && 94 getParent()->getParent()->getParent()) 95 RemoveRegOperandFromRegInfo(); 96 97 OpKind = MO_Immediate; 98 Contents.ImmVal = ImmVal; 99} 100 101/// ChangeToRegister - Replace this operand with a new register operand of 102/// the specified value. If an operand is known to be an register already, 103/// the setReg method should be used. 104void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 105 bool isKill, bool isDead) { 106 // If this operand is already a register operand, use setReg to update the 107 // register's use/def lists. 108 if (isReg()) { 109 setReg(Reg); 110 } else { 111 // Otherwise, change this to a register and set the reg#. 112 OpKind = MO_Register; 113 Contents.Reg.RegNo = Reg; 114 115 // If this operand is embedded in a function, add the operand to the 116 // register's use/def list. 117 if (MachineInstr *MI = getParent()) 118 if (MachineBasicBlock *MBB = MI->getParent()) 119 if (MachineFunction *MF = MBB->getParent()) 120 AddRegOperandToRegInfo(&MF->getRegInfo()); 121 } 122 123 IsDef = isDef; 124 IsImp = isImp; 125 IsKill = isKill; 126 IsDead = isDead; 127 SubReg = 0; 128} 129 130/// isIdenticalTo - Return true if this operand is identical to the specified 131/// operand. 132bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 133 if (getType() != Other.getType()) return false; 134 135 switch (getType()) { 136 default: assert(0 && "Unrecognized operand type"); 137 case MachineOperand::MO_Register: 138 return getReg() == Other.getReg() && isDef() == Other.isDef() && 139 getSubReg() == Other.getSubReg(); 140 case MachineOperand::MO_Immediate: 141 return getImm() == Other.getImm(); 142 case MachineOperand::MO_FPImmediate: 143 return getFPImm() == Other.getFPImm(); 144 case MachineOperand::MO_MachineBasicBlock: 145 return getMBB() == Other.getMBB(); 146 case MachineOperand::MO_FrameIndex: 147 return getIndex() == Other.getIndex(); 148 case MachineOperand::MO_ConstantPoolIndex: 149 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 150 case MachineOperand::MO_JumpTableIndex: 151 return getIndex() == Other.getIndex(); 152 case MachineOperand::MO_GlobalAddress: 153 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 154 case MachineOperand::MO_ExternalSymbol: 155 return !strcmp(getSymbolName(), Other.getSymbolName()) && 156 getOffset() == Other.getOffset(); 157 } 158} 159 160/// print - Print the specified machine operand. 161/// 162void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { 163 switch (getType()) { 164 case MachineOperand::MO_Register: 165 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { 166 OS << "%reg" << getReg(); 167 } else { 168 // If the instruction is embedded into a basic block, we can find the 169 // target info for the instruction. 170 if (TM == 0) 171 if (const MachineInstr *MI = getParent()) 172 if (const MachineBasicBlock *MBB = MI->getParent()) 173 if (const MachineFunction *MF = MBB->getParent()) 174 TM = &MF->getTarget(); 175 176 if (TM) 177 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name; 178 else 179 OS << "%mreg" << getReg(); 180 } 181 182 if (isDef() || isKill() || isDead() || isImplicit()) { 183 OS << "<"; 184 bool NeedComma = false; 185 if (isImplicit()) { 186 OS << (isDef() ? "imp-def" : "imp-use"); 187 NeedComma = true; 188 } else if (isDef()) { 189 OS << "def"; 190 NeedComma = true; 191 } 192 if (isKill() || isDead()) { 193 if (NeedComma) OS << ","; 194 if (isKill()) OS << "kill"; 195 if (isDead()) OS << "dead"; 196 } 197 OS << ">"; 198 } 199 break; 200 case MachineOperand::MO_Immediate: 201 OS << getImm(); 202 break; 203 case MachineOperand::MO_FPImmediate: 204 if (getFPImm()->getType() == Type::FloatTy) { 205 OS << getFPImm()->getValueAPF().convertToFloat(); 206 } else { 207 OS << getFPImm()->getValueAPF().convertToDouble(); 208 } 209 break; 210 case MachineOperand::MO_MachineBasicBlock: 211 OS << "mbb<" 212 << ((Value*)getMBB()->getBasicBlock())->getName() 213 << "," << (void*)getMBB() << ">"; 214 break; 215 case MachineOperand::MO_FrameIndex: 216 OS << "<fi#" << getIndex() << ">"; 217 break; 218 case MachineOperand::MO_ConstantPoolIndex: 219 OS << "<cp#" << getIndex(); 220 if (getOffset()) OS << "+" << getOffset(); 221 OS << ">"; 222 break; 223 case MachineOperand::MO_JumpTableIndex: 224 OS << "<jt#" << getIndex() << ">"; 225 break; 226 case MachineOperand::MO_GlobalAddress: 227 OS << "<ga:" << ((Value*)getGlobal())->getName(); 228 if (getOffset()) OS << "+" << getOffset(); 229 OS << ">"; 230 break; 231 case MachineOperand::MO_ExternalSymbol: 232 OS << "<es:" << getSymbolName(); 233 if (getOffset()) OS << "+" << getOffset(); 234 OS << ">"; 235 break; 236 default: 237 assert(0 && "Unrecognized operand type"); 238 } 239} 240 241//===----------------------------------------------------------------------===// 242// MachineMemOperand Implementation 243//===----------------------------------------------------------------------===// 244 245MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f, 246 int64_t o, uint64_t s, unsigned int a) 247 : Offset(o), Size(s), V(v), 248 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) { 249 assert(isPowerOf2_32(a) && "Alignment is not a power of 2!"); 250} 251 252//===----------------------------------------------------------------------===// 253// MachineInstr Implementation 254//===----------------------------------------------------------------------===// 255 256/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 257/// TID NULL and no operands. 258MachineInstr::MachineInstr() 259 : TID(0), NumImplicitOps(0), Parent(0) { 260} 261 262void MachineInstr::addImplicitDefUseOperands() { 263 if (TID->ImplicitDefs) 264 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) 265 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 266 if (TID->ImplicitUses) 267 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) 268 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 269} 270 271/// MachineInstr ctor - This constructor create a MachineInstr and add the 272/// implicit operands. It reserves space for number of operands specified by 273/// TargetInstrDesc or the numOperands if it is not zero. (for 274/// instructions with variable number of operands). 275MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) 276 : TID(&tid), NumImplicitOps(0), Parent(0) { 277 if (!NoImp && TID->getImplicitDefs()) 278 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 279 NumImplicitOps++; 280 if (!NoImp && TID->getImplicitUses()) 281 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 282 NumImplicitOps++; 283 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 284 if (!NoImp) 285 addImplicitDefUseOperands(); 286} 287 288/// MachineInstr ctor - Work exactly the same as the ctor above, except that the 289/// MachineInstr is created and added to the end of the specified basic block. 290/// 291MachineInstr::MachineInstr(MachineBasicBlock *MBB, 292 const TargetInstrDesc &tid) 293 : TID(&tid), NumImplicitOps(0), Parent(0) { 294 assert(MBB && "Cannot use inserting ctor with null basic block!"); 295 if (TID->ImplicitDefs) 296 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 297 NumImplicitOps++; 298 if (TID->ImplicitUses) 299 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 300 NumImplicitOps++; 301 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 302 addImplicitDefUseOperands(); 303 MBB->push_back(this); // Add instruction to end of basic block! 304} 305 306/// MachineInstr ctor - Copies MachineInstr arg exactly 307/// 308MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) { 309 TID = &MI.getDesc(); 310 NumImplicitOps = MI.NumImplicitOps; 311 Operands.reserve(MI.getNumOperands()); 312 313 // Add operands 314 for (unsigned i = 0; i != MI.getNumOperands(); ++i) { 315 Operands.push_back(MI.getOperand(i)); 316 Operands.back().ParentMI = this; 317 } 318 319 // Add memory operands. 320 for (alist<MachineMemOperand>::const_iterator i = MI.memoperands_begin(), 321 j = MI.memoperands_end(); i != j; ++i) 322 addMemOperand(MF, *i); 323 324 // Set parent to null. 325 Parent = 0; 326} 327 328MachineInstr::~MachineInstr() { 329 assert(MemOperands.empty() && 330 "MachineInstr being deleted with live memoperands!"); 331#ifndef NDEBUG 332 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 333 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 334 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 335 "Reg operand def/use list corrupted"); 336 } 337#endif 338} 339 340/// getOpcode - Returns the opcode of this MachineInstr. 341/// 342int MachineInstr::getOpcode() const { 343 return TID->Opcode; 344} 345 346/// getRegInfo - If this instruction is embedded into a MachineFunction, 347/// return the MachineRegisterInfo object for the current function, otherwise 348/// return null. 349MachineRegisterInfo *MachineInstr::getRegInfo() { 350 if (MachineBasicBlock *MBB = getParent()) 351 return &MBB->getParent()->getRegInfo(); 352 return 0; 353} 354 355/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 356/// this instruction from their respective use lists. This requires that the 357/// operands already be on their use lists. 358void MachineInstr::RemoveRegOperandsFromUseLists() { 359 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 360 if (Operands[i].isReg()) 361 Operands[i].RemoveRegOperandFromRegInfo(); 362 } 363} 364 365/// AddRegOperandsToUseLists - Add all of the register operands in 366/// this instruction from their respective use lists. This requires that the 367/// operands not be on their use lists yet. 368void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 369 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 370 if (Operands[i].isReg()) 371 Operands[i].AddRegOperandToRegInfo(&RegInfo); 372 } 373} 374 375 376/// addOperand - Add the specified operand to the instruction. If it is an 377/// implicit operand, it is added to the end of the operand list. If it is 378/// an explicit operand it is added at the end of the explicit operand list 379/// (before the first implicit operand). 380void MachineInstr::addOperand(const MachineOperand &Op) { 381 bool isImpReg = Op.isReg() && Op.isImplicit(); 382 assert((isImpReg || !OperandsComplete()) && 383 "Trying to add an operand to a machine instr that is already done!"); 384 385 // If we are adding the operand to the end of the list, our job is simpler. 386 // This is true most of the time, so this is a reasonable optimization. 387 if (isImpReg || NumImplicitOps == 0) { 388 // We can only do this optimization if we know that the operand list won't 389 // reallocate. 390 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { 391 Operands.push_back(Op); 392 393 // Set the parent of the operand. 394 Operands.back().ParentMI = this; 395 396 // If the operand is a register, update the operand's use list. 397 if (Op.isReg()) 398 Operands.back().AddRegOperandToRegInfo(getRegInfo()); 399 return; 400 } 401 } 402 403 // Otherwise, we have to insert a real operand before any implicit ones. 404 unsigned OpNo = Operands.size()-NumImplicitOps; 405 406 MachineRegisterInfo *RegInfo = getRegInfo(); 407 408 // If this instruction isn't embedded into a function, then we don't need to 409 // update any operand lists. 410 if (RegInfo == 0) { 411 // Simple insertion, no reginfo update needed for other register operands. 412 Operands.insert(Operands.begin()+OpNo, Op); 413 Operands[OpNo].ParentMI = this; 414 415 // Do explicitly set the reginfo for this operand though, to ensure the 416 // next/prev fields are properly nulled out. 417 if (Operands[OpNo].isReg()) 418 Operands[OpNo].AddRegOperandToRegInfo(0); 419 420 } else if (Operands.size()+1 <= Operands.capacity()) { 421 // Otherwise, we have to remove register operands from their register use 422 // list, add the operand, then add the register operands back to their use 423 // list. This also must handle the case when the operand list reallocates 424 // to somewhere else. 425 426 // If insertion of this operand won't cause reallocation of the operand 427 // list, just remove the implicit operands, add the operand, then re-add all 428 // the rest of the operands. 429 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 430 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 431 Operands[i].RemoveRegOperandFromRegInfo(); 432 } 433 434 // Add the operand. If it is a register, add it to the reg list. 435 Operands.insert(Operands.begin()+OpNo, Op); 436 Operands[OpNo].ParentMI = this; 437 438 if (Operands[OpNo].isReg()) 439 Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 440 441 // Re-add all the implicit ops. 442 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { 443 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 444 Operands[i].AddRegOperandToRegInfo(RegInfo); 445 } 446 } else { 447 // Otherwise, we will be reallocating the operand list. Remove all reg 448 // operands from their list, then readd them after the operand list is 449 // reallocated. 450 RemoveRegOperandsFromUseLists(); 451 452 Operands.insert(Operands.begin()+OpNo, Op); 453 Operands[OpNo].ParentMI = this; 454 455 // Re-add all the operands. 456 AddRegOperandsToUseLists(*RegInfo); 457 } 458} 459 460/// RemoveOperand - Erase an operand from an instruction, leaving it with one 461/// fewer operand than it started with. 462/// 463void MachineInstr::RemoveOperand(unsigned OpNo) { 464 assert(OpNo < Operands.size() && "Invalid operand number"); 465 466 // Special case removing the last one. 467 if (OpNo == Operands.size()-1) { 468 // If needed, remove from the reg def/use list. 469 if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 470 Operands.back().RemoveRegOperandFromRegInfo(); 471 472 Operands.pop_back(); 473 return; 474 } 475 476 // Otherwise, we are removing an interior operand. If we have reginfo to 477 // update, remove all operands that will be shifted down from their reg lists, 478 // move everything down, then re-add them. 479 MachineRegisterInfo *RegInfo = getRegInfo(); 480 if (RegInfo) { 481 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 482 if (Operands[i].isReg()) 483 Operands[i].RemoveRegOperandFromRegInfo(); 484 } 485 } 486 487 Operands.erase(Operands.begin()+OpNo); 488 489 if (RegInfo) { 490 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 491 if (Operands[i].isReg()) 492 Operands[i].AddRegOperandToRegInfo(RegInfo); 493 } 494 } 495} 496 497/// addMemOperand - Add a MachineMemOperand to the machine instruction, 498/// referencing arbitrary storage. 499void MachineInstr::addMemOperand(MachineFunction &MF, 500 const MachineMemOperand &MO) { 501 MemOperands.push_back(MF.CreateMachineMemOperand(MO)); 502} 503 504/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands. 505void MachineInstr::clearMemOperands(MachineFunction &MF) { 506 while (!MemOperands.empty()) 507 MF.DeleteMachineMemOperand(MemOperands.remove(MemOperands.begin())); 508} 509 510 511/// removeFromParent - This method unlinks 'this' from the containing basic 512/// block, and returns it, but does not delete it. 513MachineInstr *MachineInstr::removeFromParent() { 514 assert(getParent() && "Not embedded in a basic block!"); 515 getParent()->remove(this); 516 return this; 517} 518 519 520/// eraseFromParent - This method unlinks 'this' from the containing basic 521/// block, and deletes it. 522void MachineInstr::eraseFromParent() { 523 assert(getParent() && "Not embedded in a basic block!"); 524 getParent()->erase(this); 525} 526 527 528/// OperandComplete - Return true if it's illegal to add a new operand 529/// 530bool MachineInstr::OperandsComplete() const { 531 unsigned short NumOperands = TID->getNumOperands(); 532 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) 533 return true; // Broken: we have all the operands of this instruction! 534 return false; 535} 536 537/// getNumExplicitOperands - Returns the number of non-implicit operands. 538/// 539unsigned MachineInstr::getNumExplicitOperands() const { 540 unsigned NumOperands = TID->getNumOperands(); 541 if (!TID->isVariadic()) 542 return NumOperands; 543 544 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) { 545 const MachineOperand &MO = getOperand(NumOperands); 546 if (!MO.isRegister() || !MO.isImplicit()) 547 NumOperands++; 548 } 549 return NumOperands; 550} 551 552 553/// isLabel - Returns true if the MachineInstr represents a label. 554/// 555bool MachineInstr::isLabel() const { 556 return getOpcode() == TargetInstrInfo::DBG_LABEL || 557 getOpcode() == TargetInstrInfo::EH_LABEL || 558 getOpcode() == TargetInstrInfo::GC_LABEL; 559} 560 561/// isDebugLabel - Returns true if the MachineInstr represents a debug label. 562/// 563bool MachineInstr::isDebugLabel() const { 564 return getOpcode() == TargetInstrInfo::DBG_LABEL; 565} 566 567/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 568/// the specific register or -1 if it is not found. It further tightening 569/// the search criteria to a use that kills the register if isKill is true. 570int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 571 const TargetRegisterInfo *TRI) const { 572 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 573 const MachineOperand &MO = getOperand(i); 574 if (!MO.isRegister() || !MO.isUse()) 575 continue; 576 unsigned MOReg = MO.getReg(); 577 if (!MOReg) 578 continue; 579 if (MOReg == Reg || 580 (TRI && 581 TargetRegisterInfo::isPhysicalRegister(MOReg) && 582 TargetRegisterInfo::isPhysicalRegister(Reg) && 583 TRI->isSubRegister(MOReg, Reg))) 584 if (!isKill || MO.isKill()) 585 return i; 586 } 587 return -1; 588} 589 590/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 591/// the specified register or -1 if it is not found. If isDead is true, defs 592/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 593/// also checks if there is a def of a super-register. 594int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, 595 const TargetRegisterInfo *TRI) const { 596 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 597 const MachineOperand &MO = getOperand(i); 598 if (!MO.isRegister() || !MO.isDef()) 599 continue; 600 unsigned MOReg = MO.getReg(); 601 if (MOReg == Reg || 602 (TRI && 603 TargetRegisterInfo::isPhysicalRegister(MOReg) && 604 TargetRegisterInfo::isPhysicalRegister(Reg) && 605 TRI->isSubRegister(MOReg, Reg))) 606 if (!isDead || MO.isDead()) 607 return i; 608 } 609 return -1; 610} 611 612/// findFirstPredOperandIdx() - Find the index of the first operand in the 613/// operand list that is used to represent the predicate. It returns -1 if 614/// none is found. 615int MachineInstr::findFirstPredOperandIdx() const { 616 const TargetInstrDesc &TID = getDesc(); 617 if (TID.isPredicable()) { 618 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 619 if (TID.OpInfo[i].isPredicate()) 620 return i; 621 } 622 623 return -1; 624} 625 626/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due 627/// to two addr elimination. 628bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const { 629 const TargetInstrDesc &TID = getDesc(); 630 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 631 const MachineOperand &MO1 = getOperand(i); 632 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) { 633 for (unsigned j = i+1; j < e; ++j) { 634 const MachineOperand &MO2 = getOperand(j); 635 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg && 636 TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i) 637 return true; 638 } 639 } 640 } 641 return false; 642} 643 644/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 645/// 646void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 647 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 648 const MachineOperand &MO = MI->getOperand(i); 649 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead())) 650 continue; 651 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 652 MachineOperand &MOp = getOperand(j); 653 if (!MOp.isIdenticalTo(MO)) 654 continue; 655 if (MO.isKill()) 656 MOp.setIsKill(); 657 else 658 MOp.setIsDead(); 659 break; 660 } 661 } 662} 663 664/// copyPredicates - Copies predicate operand(s) from MI. 665void MachineInstr::copyPredicates(const MachineInstr *MI) { 666 const TargetInstrDesc &TID = MI->getDesc(); 667 if (!TID.isPredicable()) 668 return; 669 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 670 if (TID.OpInfo[i].isPredicate()) { 671 // Predicated operands must be last operands. 672 addOperand(MI->getOperand(i)); 673 } 674 } 675} 676 677/// isSafeToMove - Return true if it is safe to move this instruction. If 678/// SawStore is set to true, it means that there is a store (or call) between 679/// the instruction's location and its intended destination. 680bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) { 681 // Ignore stuff that we obviously can't move. 682 if (TID->mayStore() || TID->isCall()) { 683 SawStore = true; 684 return false; 685 } 686 if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects()) 687 return false; 688 689 // See if this instruction does a load. If so, we have to guarantee that the 690 // loaded value doesn't change between the load and the its intended 691 // destination. The check for isInvariantLoad gives the targe the chance to 692 // classify the load as always returning a constant, e.g. a constant pool 693 // load. 694 if (TID->mayLoad() && !TII->isInvariantLoad(this)) { 695 // Otherwise, this is a real load. If there is a store between the load and 696 // end of block, we can't sink the load. 697 // 698 // FIXME: we can't do this transformation until we know that the load is 699 // not volatile, and machineinstrs don't keep this info. :( 700 // 701 //if (SawStore) 702 return false; 703 } 704 return true; 705} 706 707void MachineInstr::dump() const { 708 cerr << " " << *this; 709} 710 711void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { 712 // Specialize printing if op#0 is definition 713 unsigned StartOp = 0; 714 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) { 715 getOperand(0).print(OS, TM); 716 OS << " = "; 717 ++StartOp; // Don't print this operand again! 718 } 719 720 OS << getDesc().getName(); 721 722 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 723 if (i != StartOp) 724 OS << ","; 725 OS << " "; 726 getOperand(i).print(OS, TM); 727 } 728 729 if (!memoperands_empty()) { 730 OS << ", Mem:"; 731 for (alist<MachineMemOperand>::const_iterator i = memoperands_begin(), 732 e = memoperands_end(); i != e; ++i) { 733 const MachineMemOperand &MRO = *i; 734 const Value *V = MRO.getValue(); 735 736 assert((MRO.isLoad() || MRO.isStore()) && 737 "SV has to be a load, store or both."); 738 739 if (MRO.isVolatile()) 740 OS << "Volatile "; 741 742 if (MRO.isLoad()) 743 OS << "LD"; 744 if (MRO.isStore()) 745 OS << "ST"; 746 747 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") ["; 748 749 if (!V) 750 OS << "<unknown>"; 751 else if (!V->getName().empty()) 752 OS << V->getName(); 753 else if (isa<PseudoSourceValue>(V)) 754 OS << *V; 755 else 756 OS << V; 757 758 OS << " + " << MRO.getOffset() << "]"; 759 } 760 } 761 762 OS << "\n"; 763} 764 765bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 766 const TargetRegisterInfo *RegInfo, 767 bool AddIfNotFound) { 768 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 769 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 770 SmallVector<unsigned,4> DeadOps; 771 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 772 MachineOperand &MO = getOperand(i); 773 if (!MO.isRegister() || !MO.isUse()) 774 continue; 775 unsigned Reg = MO.getReg(); 776 if (!Reg) 777 continue; 778 779 if (Reg == IncomingReg) { 780 MO.setIsKill(); 781 return true; 782 } 783 if (hasAliases && MO.isKill() && 784 TargetRegisterInfo::isPhysicalRegister(Reg)) { 785 // A super-register kill already exists. 786 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 787 return true; 788 if (RegInfo->isSubRegister(IncomingReg, Reg)) 789 DeadOps.push_back(i); 790 } 791 } 792 793 // Trim unneeded kill operands. 794 while (!DeadOps.empty()) { 795 unsigned OpIdx = DeadOps.back(); 796 if (getOperand(OpIdx).isImplicit()) 797 RemoveOperand(OpIdx); 798 else 799 getOperand(OpIdx).setIsKill(false); 800 DeadOps.pop_back(); 801 } 802 803 // If not found, this means an alias of one of the operands is killed. Add a 804 // new implicit operand if required. 805 if (AddIfNotFound) { 806 addOperand(MachineOperand::CreateReg(IncomingReg, 807 false /*IsDef*/, 808 true /*IsImp*/, 809 true /*IsKill*/)); 810 return true; 811 } 812 return false; 813} 814 815bool MachineInstr::addRegisterDead(unsigned IncomingReg, 816 const TargetRegisterInfo *RegInfo, 817 bool AddIfNotFound) { 818 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 819 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 820 SmallVector<unsigned,4> DeadOps; 821 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 822 MachineOperand &MO = getOperand(i); 823 if (!MO.isRegister() || !MO.isDef()) 824 continue; 825 unsigned Reg = MO.getReg(); 826 if (Reg == IncomingReg) { 827 MO.setIsDead(); 828 return true; 829 } 830 if (hasAliases && MO.isDead() && 831 TargetRegisterInfo::isPhysicalRegister(Reg)) { 832 // There exists a super-register that's marked dead. 833 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 834 return true; 835 if (RegInfo->isSubRegister(IncomingReg, Reg)) 836 DeadOps.push_back(i); 837 } 838 } 839 840 // Trim unneeded dead operands. 841 while (!DeadOps.empty()) { 842 unsigned OpIdx = DeadOps.back(); 843 if (getOperand(OpIdx).isImplicit()) 844 RemoveOperand(OpIdx); 845 else 846 getOperand(OpIdx).setIsDead(false); 847 DeadOps.pop_back(); 848 } 849 850 // If not found, this means an alias of one of the operand is dead. Add a 851 // new implicit operand. 852 if (AddIfNotFound) { 853 addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/, 854 true/*IsImp*/,false/*IsKill*/, 855 true/*IsDead*/)); 856 return true; 857 } 858 return false; 859} 860