MachineInstr.cpp revision 7739cad69d2590f556afc9fc3048f967b5a3f4f6 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/Function.h"
17#include "llvm/InlineAsm.h"
18#include "llvm/LLVMContext.h"
19#include "llvm/Metadata.h"
20#include "llvm/Module.h"
21#include "llvm/Type.h"
22#include "llvm/Value.h"
23#include "llvm/Assembly/Writer.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineMemOperand.h"
27#include "llvm/CodeGen/MachineModuleInfo.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/PseudoSourceValue.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Target/TargetMachine.h"
33#include "llvm/Target/TargetInstrInfo.h"
34#include "llvm/Target/TargetRegisterInfo.h"
35#include "llvm/Analysis/AliasAnalysis.h"
36#include "llvm/Analysis/DebugInfo.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/LeakDetector.h"
40#include "llvm/Support/MathExtras.h"
41#include "llvm/Support/raw_ostream.h"
42#include "llvm/ADT/FoldingSet.h"
43using namespace llvm;
44
45//===----------------------------------------------------------------------===//
46// MachineOperand Implementation
47//===----------------------------------------------------------------------===//
48
49/// AddRegOperandToRegInfo - Add this register operand to the specified
50/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
51/// explicitly nulled out.
52void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
53  assert(isReg() && "Can only add reg operand to use lists");
54
55  // If the reginfo pointer is null, just explicitly null out or next/prev
56  // pointers, to ensure they are not garbage.
57  if (RegInfo == 0) {
58    Contents.Reg.Prev = 0;
59    Contents.Reg.Next = 0;
60    return;
61  }
62
63  // Otherwise, add this operand to the head of the registers use/def list.
64  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
65
66  // For SSA values, we prefer to keep the definition at the start of the list.
67  // we do this by skipping over the definition if it is at the head of the
68  // list.
69  if (*Head && (*Head)->isDef())
70    Head = &(*Head)->Contents.Reg.Next;
71
72  Contents.Reg.Next = *Head;
73  if (Contents.Reg.Next) {
74    assert(getReg() == Contents.Reg.Next->getReg() &&
75           "Different regs on the same list!");
76    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
77  }
78
79  Contents.Reg.Prev = Head;
80  *Head = this;
81}
82
83/// RemoveRegOperandFromRegInfo - Remove this register operand from the
84/// MachineRegisterInfo it is linked with.
85void MachineOperand::RemoveRegOperandFromRegInfo() {
86  assert(isOnRegUseList() && "Reg operand is not on a use list");
87  // Unlink this from the doubly linked list of operands.
88  MachineOperand *NextOp = Contents.Reg.Next;
89  *Contents.Reg.Prev = NextOp;
90  if (NextOp) {
91    assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
92    NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
93  }
94  Contents.Reg.Prev = 0;
95  Contents.Reg.Next = 0;
96}
97
98void MachineOperand::setReg(unsigned Reg) {
99  if (getReg() == Reg) return; // No change.
100
101  // Otherwise, we have to change the register.  If this operand is embedded
102  // into a machine function, we need to update the old and new register's
103  // use/def lists.
104  if (MachineInstr *MI = getParent())
105    if (MachineBasicBlock *MBB = MI->getParent())
106      if (MachineFunction *MF = MBB->getParent()) {
107        RemoveRegOperandFromRegInfo();
108        SmallContents.RegNo = Reg;
109        AddRegOperandToRegInfo(&MF->getRegInfo());
110        return;
111      }
112
113  // Otherwise, just change the register, no problem.  :)
114  SmallContents.RegNo = Reg;
115}
116
117void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
118                                  const TargetRegisterInfo &TRI) {
119  assert(TargetRegisterInfo::isVirtualRegister(Reg));
120  if (SubIdx && getSubReg())
121    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
122  setReg(Reg);
123  if (SubIdx)
124    setSubReg(SubIdx);
125}
126
127void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
128  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
129  if (getSubReg()) {
130    Reg = TRI.getSubReg(Reg, getSubReg());
131    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
132    // That won't happen in legal code.
133    setSubReg(0);
134  }
135  setReg(Reg);
136}
137
138/// ChangeToImmediate - Replace this operand with a new immediate operand of
139/// the specified value.  If an operand is known to be an immediate already,
140/// the setImm method should be used.
141void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
142  // If this operand is currently a register operand, and if this is in a
143  // function, deregister the operand from the register's use/def list.
144  if (isReg() && getParent() && getParent()->getParent() &&
145      getParent()->getParent()->getParent())
146    RemoveRegOperandFromRegInfo();
147
148  OpKind = MO_Immediate;
149  Contents.ImmVal = ImmVal;
150}
151
152/// ChangeToRegister - Replace this operand with a new register operand of
153/// the specified value.  If an operand is known to be an register already,
154/// the setReg method should be used.
155void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
156                                      bool isKill, bool isDead, bool isUndef,
157                                      bool isDebug) {
158  // If this operand is already a register operand, use setReg to update the
159  // register's use/def lists.
160  if (isReg()) {
161    assert(!isEarlyClobber());
162    setReg(Reg);
163  } else {
164    // Otherwise, change this to a register and set the reg#.
165    OpKind = MO_Register;
166    SmallContents.RegNo = Reg;
167
168    // If this operand is embedded in a function, add the operand to the
169    // register's use/def list.
170    if (MachineInstr *MI = getParent())
171      if (MachineBasicBlock *MBB = MI->getParent())
172        if (MachineFunction *MF = MBB->getParent())
173          AddRegOperandToRegInfo(&MF->getRegInfo());
174  }
175
176  IsDef = isDef;
177  IsImp = isImp;
178  IsKill = isKill;
179  IsDead = isDead;
180  IsUndef = isUndef;
181  IsInternalRead = false;
182  IsEarlyClobber = false;
183  IsDebug = isDebug;
184  SubReg = 0;
185}
186
187/// isIdenticalTo - Return true if this operand is identical to the specified
188/// operand.
189bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
190  if (getType() != Other.getType() ||
191      getTargetFlags() != Other.getTargetFlags())
192    return false;
193
194  switch (getType()) {
195  case MachineOperand::MO_Register:
196    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
197           getSubReg() == Other.getSubReg();
198  case MachineOperand::MO_Immediate:
199    return getImm() == Other.getImm();
200  case MachineOperand::MO_CImmediate:
201    return getCImm() == Other.getCImm();
202  case MachineOperand::MO_FPImmediate:
203    return getFPImm() == Other.getFPImm();
204  case MachineOperand::MO_MachineBasicBlock:
205    return getMBB() == Other.getMBB();
206  case MachineOperand::MO_FrameIndex:
207    return getIndex() == Other.getIndex();
208  case MachineOperand::MO_ConstantPoolIndex:
209    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
210  case MachineOperand::MO_JumpTableIndex:
211    return getIndex() == Other.getIndex();
212  case MachineOperand::MO_GlobalAddress:
213    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
214  case MachineOperand::MO_ExternalSymbol:
215    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
216           getOffset() == Other.getOffset();
217  case MachineOperand::MO_BlockAddress:
218    return getBlockAddress() == Other.getBlockAddress();
219  case MO_RegisterMask:
220    return getRegMask() == Other.getRegMask();
221  case MachineOperand::MO_MCSymbol:
222    return getMCSymbol() == Other.getMCSymbol();
223  case MachineOperand::MO_Metadata:
224    return getMetadata() == Other.getMetadata();
225  }
226  llvm_unreachable("Invalid machine operand type");
227}
228
229/// print - Print the specified machine operand.
230///
231void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
232  // If the instruction is embedded into a basic block, we can find the
233  // target info for the instruction.
234  if (!TM)
235    if (const MachineInstr *MI = getParent())
236      if (const MachineBasicBlock *MBB = MI->getParent())
237        if (const MachineFunction *MF = MBB->getParent())
238          TM = &MF->getTarget();
239  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
240
241  switch (getType()) {
242  case MachineOperand::MO_Register:
243    OS << PrintReg(getReg(), TRI, getSubReg());
244
245    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
246        isInternalRead() || isEarlyClobber()) {
247      OS << '<';
248      bool NeedComma = false;
249      if (isDef()) {
250        if (NeedComma) OS << ',';
251        if (isEarlyClobber())
252          OS << "earlyclobber,";
253        if (isImplicit())
254          OS << "imp-";
255        OS << "def";
256        NeedComma = true;
257      } else if (isImplicit()) {
258          OS << "imp-use";
259          NeedComma = true;
260      }
261
262      if (isKill() || isDead() || isUndef() || isInternalRead()) {
263        if (NeedComma) OS << ',';
264        NeedComma = false;
265        if (isKill()) {
266          OS << "kill";
267          NeedComma = true;
268        }
269        if (isDead()) {
270          OS << "dead";
271          NeedComma = true;
272        }
273        if (isUndef()) {
274          if (NeedComma) OS << ',';
275          OS << "undef";
276          NeedComma = true;
277        }
278        if (isInternalRead()) {
279          if (NeedComma) OS << ',';
280          OS << "internal";
281          NeedComma = true;
282        }
283      }
284      OS << '>';
285    }
286    break;
287  case MachineOperand::MO_Immediate:
288    OS << getImm();
289    break;
290  case MachineOperand::MO_CImmediate:
291    getCImm()->getValue().print(OS, false);
292    break;
293  case MachineOperand::MO_FPImmediate:
294    if (getFPImm()->getType()->isFloatTy())
295      OS << getFPImm()->getValueAPF().convertToFloat();
296    else
297      OS << getFPImm()->getValueAPF().convertToDouble();
298    break;
299  case MachineOperand::MO_MachineBasicBlock:
300    OS << "<BB#" << getMBB()->getNumber() << ">";
301    break;
302  case MachineOperand::MO_FrameIndex:
303    OS << "<fi#" << getIndex() << '>';
304    break;
305  case MachineOperand::MO_ConstantPoolIndex:
306    OS << "<cp#" << getIndex();
307    if (getOffset()) OS << "+" << getOffset();
308    OS << '>';
309    break;
310  case MachineOperand::MO_JumpTableIndex:
311    OS << "<jt#" << getIndex() << '>';
312    break;
313  case MachineOperand::MO_GlobalAddress:
314    OS << "<ga:";
315    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
316    if (getOffset()) OS << "+" << getOffset();
317    OS << '>';
318    break;
319  case MachineOperand::MO_ExternalSymbol:
320    OS << "<es:" << getSymbolName();
321    if (getOffset()) OS << "+" << getOffset();
322    OS << '>';
323    break;
324  case MachineOperand::MO_BlockAddress:
325    OS << '<';
326    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
327    OS << '>';
328    break;
329  case MachineOperand::MO_RegisterMask:
330    OS << (getRegMask() ? "<regmask>" : "<regmask:null>");
331    break;
332  case MachineOperand::MO_Metadata:
333    OS << '<';
334    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
335    OS << '>';
336    break;
337  case MachineOperand::MO_MCSymbol:
338    OS << "<MCSym=" << *getMCSymbol() << '>';
339    break;
340  }
341
342  if (unsigned TF = getTargetFlags())
343    OS << "[TF=" << TF << ']';
344}
345
346//===----------------------------------------------------------------------===//
347// MachineMemOperand Implementation
348//===----------------------------------------------------------------------===//
349
350/// getAddrSpace - Return the LLVM IR address space number that this pointer
351/// points into.
352unsigned MachinePointerInfo::getAddrSpace() const {
353  if (V == 0) return 0;
354  return cast<PointerType>(V->getType())->getAddressSpace();
355}
356
357/// getConstantPool - Return a MachinePointerInfo record that refers to the
358/// constant pool.
359MachinePointerInfo MachinePointerInfo::getConstantPool() {
360  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
361}
362
363/// getFixedStack - Return a MachinePointerInfo record that refers to the
364/// the specified FrameIndex.
365MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
366  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
367}
368
369MachinePointerInfo MachinePointerInfo::getJumpTable() {
370  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
371}
372
373MachinePointerInfo MachinePointerInfo::getGOT() {
374  return MachinePointerInfo(PseudoSourceValue::getGOT());
375}
376
377MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
378  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
379}
380
381MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
382                                     uint64_t s, unsigned int a,
383                                     const MDNode *TBAAInfo)
384  : PtrInfo(ptrinfo), Size(s),
385    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
386    TBAAInfo(TBAAInfo) {
387  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
388         "invalid pointer value");
389  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
390  assert((isLoad() || isStore()) && "Not a load/store!");
391}
392
393/// Profile - Gather unique data for the object.
394///
395void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
396  ID.AddInteger(getOffset());
397  ID.AddInteger(Size);
398  ID.AddPointer(getValue());
399  ID.AddInteger(Flags);
400}
401
402void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
403  // The Value and Offset may differ due to CSE. But the flags and size
404  // should be the same.
405  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
406  assert(MMO->getSize() == getSize() && "Size mismatch!");
407
408  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
409    // Update the alignment value.
410    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
411      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
412    // Also update the base and offset, because the new alignment may
413    // not be applicable with the old ones.
414    PtrInfo = MMO->PtrInfo;
415  }
416}
417
418/// getAlignment - Return the minimum known alignment in bytes of the
419/// actual memory reference.
420uint64_t MachineMemOperand::getAlignment() const {
421  return MinAlign(getBaseAlignment(), getOffset());
422}
423
424raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
425  assert((MMO.isLoad() || MMO.isStore()) &&
426         "SV has to be a load, store or both.");
427
428  if (MMO.isVolatile())
429    OS << "Volatile ";
430
431  if (MMO.isLoad())
432    OS << "LD";
433  if (MMO.isStore())
434    OS << "ST";
435  OS << MMO.getSize();
436
437  // Print the address information.
438  OS << "[";
439  if (!MMO.getValue())
440    OS << "<unknown>";
441  else
442    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
443
444  // If the alignment of the memory reference itself differs from the alignment
445  // of the base pointer, print the base alignment explicitly, next to the base
446  // pointer.
447  if (MMO.getBaseAlignment() != MMO.getAlignment())
448    OS << "(align=" << MMO.getBaseAlignment() << ")";
449
450  if (MMO.getOffset() != 0)
451    OS << "+" << MMO.getOffset();
452  OS << "]";
453
454  // Print the alignment of the reference.
455  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
456      MMO.getBaseAlignment() != MMO.getSize())
457    OS << "(align=" << MMO.getAlignment() << ")";
458
459  // Print TBAA info.
460  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
461    OS << "(tbaa=";
462    if (TBAAInfo->getNumOperands() > 0)
463      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
464    else
465      OS << "<unknown>";
466    OS << ")";
467  }
468
469  // Print nontemporal info.
470  if (MMO.isNonTemporal())
471    OS << "(nontemporal)";
472
473  return OS;
474}
475
476//===----------------------------------------------------------------------===//
477// MachineInstr Implementation
478//===----------------------------------------------------------------------===//
479
480/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
481/// MCID NULL and no operands.
482MachineInstr::MachineInstr()
483  : MCID(0), Flags(0), AsmPrinterFlags(0),
484    MemRefs(0), MemRefsEnd(0),
485    Parent(0) {
486  // Make sure that we get added to a machine basicblock
487  LeakDetector::addGarbageObject(this);
488}
489
490void MachineInstr::addImplicitDefUseOperands() {
491  if (MCID->ImplicitDefs)
492    for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs)
493      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
494  if (MCID->ImplicitUses)
495    for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses)
496      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
497}
498
499/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
500/// implicit operands. It reserves space for the number of operands specified by
501/// the MCInstrDesc.
502MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
503  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
504    MemRefs(0), MemRefsEnd(0), Parent(0) {
505  unsigned NumImplicitOps = 0;
506  if (!NoImp)
507    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
508  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
509  if (!NoImp)
510    addImplicitDefUseOperands();
511  // Make sure that we get added to a machine basicblock
512  LeakDetector::addGarbageObject(this);
513}
514
515/// MachineInstr ctor - As above, but with a DebugLoc.
516MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
517                           bool NoImp)
518  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
519    MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
520  unsigned NumImplicitOps = 0;
521  if (!NoImp)
522    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
523  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
524  if (!NoImp)
525    addImplicitDefUseOperands();
526  // Make sure that we get added to a machine basicblock
527  LeakDetector::addGarbageObject(this);
528}
529
530/// MachineInstr ctor - Work exactly the same as the ctor two above, except
531/// that the MachineInstr is created and added to the end of the specified
532/// basic block.
533MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
534  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
535    MemRefs(0), MemRefsEnd(0), Parent(0) {
536  assert(MBB && "Cannot use inserting ctor with null basic block!");
537  unsigned NumImplicitOps =
538    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
539  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
540  addImplicitDefUseOperands();
541  // Make sure that we get added to a machine basicblock
542  LeakDetector::addGarbageObject(this);
543  MBB->push_back(this);  // Add instruction to end of basic block!
544}
545
546/// MachineInstr ctor - As above, but with a DebugLoc.
547///
548MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
549                           const MCInstrDesc &tid)
550  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
551    MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
552  assert(MBB && "Cannot use inserting ctor with null basic block!");
553  unsigned NumImplicitOps =
554    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
555  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
556  addImplicitDefUseOperands();
557  // Make sure that we get added to a machine basicblock
558  LeakDetector::addGarbageObject(this);
559  MBB->push_back(this);  // Add instruction to end of basic block!
560}
561
562/// MachineInstr ctor - Copies MachineInstr arg exactly
563///
564MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
565  : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
566    MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
567    Parent(0), debugLoc(MI.getDebugLoc()) {
568  Operands.reserve(MI.getNumOperands());
569
570  // Add operands
571  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
572    addOperand(MI.getOperand(i));
573
574  // Copy all the flags.
575  Flags = MI.Flags;
576
577  // Set parent to null.
578  Parent = 0;
579
580  LeakDetector::addGarbageObject(this);
581}
582
583MachineInstr::~MachineInstr() {
584  LeakDetector::removeGarbageObject(this);
585#ifndef NDEBUG
586  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
587    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
588    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
589           "Reg operand def/use list corrupted");
590  }
591#endif
592}
593
594/// getRegInfo - If this instruction is embedded into a MachineFunction,
595/// return the MachineRegisterInfo object for the current function, otherwise
596/// return null.
597MachineRegisterInfo *MachineInstr::getRegInfo() {
598  if (MachineBasicBlock *MBB = getParent())
599    return &MBB->getParent()->getRegInfo();
600  return 0;
601}
602
603/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
604/// this instruction from their respective use lists.  This requires that the
605/// operands already be on their use lists.
606void MachineInstr::RemoveRegOperandsFromUseLists() {
607  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
608    if (Operands[i].isReg())
609      Operands[i].RemoveRegOperandFromRegInfo();
610  }
611}
612
613/// AddRegOperandsToUseLists - Add all of the register operands in
614/// this instruction from their respective use lists.  This requires that the
615/// operands not be on their use lists yet.
616void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
617  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
618    if (Operands[i].isReg())
619      Operands[i].AddRegOperandToRegInfo(&RegInfo);
620  }
621}
622
623
624/// addOperand - Add the specified operand to the instruction.  If it is an
625/// implicit operand, it is added to the end of the operand list.  If it is
626/// an explicit operand it is added at the end of the explicit operand list
627/// (before the first implicit operand).
628void MachineInstr::addOperand(const MachineOperand &Op) {
629  assert(MCID && "Cannot add operands before providing an instr descriptor");
630  bool isImpReg = Op.isReg() && Op.isImplicit();
631  MachineRegisterInfo *RegInfo = getRegInfo();
632
633  // If the Operands backing store is reallocated, all register operands must
634  // be removed and re-added to RegInfo.  It is storing pointers to operands.
635  bool Reallocate = RegInfo &&
636    !Operands.empty() && Operands.size() == Operands.capacity();
637
638  // Find the insert location for the new operand.  Implicit registers go at
639  // the end, everything goes before the implicit regs.
640  unsigned OpNo = Operands.size();
641
642  // Remove all the implicit operands from RegInfo if they need to be shifted.
643  // FIXME: Allow mixed explicit and implicit operands on inline asm.
644  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
645  // implicit-defs, but they must not be moved around.  See the FIXME in
646  // InstrEmitter.cpp.
647  if (!isImpReg && !isInlineAsm()) {
648    while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
649      --OpNo;
650      if (RegInfo)
651        Operands[OpNo].RemoveRegOperandFromRegInfo();
652    }
653  }
654
655  // OpNo now points as the desired insertion point.  Unless this is a variadic
656  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
657  assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) &&
658         "Trying to add an operand to a machine instr that is already done!");
659
660  // All operands from OpNo have been removed from RegInfo.  If the Operands
661  // backing store needs to be reallocated, we also need to remove any other
662  // register operands.
663  if (Reallocate)
664    for (unsigned i = 0; i != OpNo; ++i)
665      if (Operands[i].isReg())
666        Operands[i].RemoveRegOperandFromRegInfo();
667
668  // Insert the new operand at OpNo.
669  Operands.insert(Operands.begin() + OpNo, Op);
670  Operands[OpNo].ParentMI = this;
671
672  // The Operands backing store has now been reallocated, so we can re-add the
673  // operands before OpNo.
674  if (Reallocate)
675    for (unsigned i = 0; i != OpNo; ++i)
676      if (Operands[i].isReg())
677        Operands[i].AddRegOperandToRegInfo(RegInfo);
678
679  // When adding a register operand, tell RegInfo about it.
680  if (Operands[OpNo].isReg()) {
681    // Add the new operand to RegInfo, even when RegInfo is NULL.
682    // This will initialize the linked list pointers.
683    Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
684    // If the register operand is flagged as early, mark the operand as such.
685    if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
686      Operands[OpNo].setIsEarlyClobber(true);
687  }
688
689  // Re-add all the implicit ops.
690  if (RegInfo) {
691    for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
692      assert(Operands[i].isReg() && "Should only be an implicit reg!");
693      Operands[i].AddRegOperandToRegInfo(RegInfo);
694    }
695  }
696}
697
698/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
699/// fewer operand than it started with.
700///
701void MachineInstr::RemoveOperand(unsigned OpNo) {
702  assert(OpNo < Operands.size() && "Invalid operand number");
703
704  // Special case removing the last one.
705  if (OpNo == Operands.size()-1) {
706    // If needed, remove from the reg def/use list.
707    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
708      Operands.back().RemoveRegOperandFromRegInfo();
709
710    Operands.pop_back();
711    return;
712  }
713
714  // Otherwise, we are removing an interior operand.  If we have reginfo to
715  // update, remove all operands that will be shifted down from their reg lists,
716  // move everything down, then re-add them.
717  MachineRegisterInfo *RegInfo = getRegInfo();
718  if (RegInfo) {
719    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
720      if (Operands[i].isReg())
721        Operands[i].RemoveRegOperandFromRegInfo();
722    }
723  }
724
725  Operands.erase(Operands.begin()+OpNo);
726
727  if (RegInfo) {
728    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
729      if (Operands[i].isReg())
730        Operands[i].AddRegOperandToRegInfo(RegInfo);
731    }
732  }
733}
734
735/// addMemOperand - Add a MachineMemOperand to the machine instruction.
736/// This function should be used only occasionally. The setMemRefs function
737/// is the primary method for setting up a MachineInstr's MemRefs list.
738void MachineInstr::addMemOperand(MachineFunction &MF,
739                                 MachineMemOperand *MO) {
740  mmo_iterator OldMemRefs = MemRefs;
741  mmo_iterator OldMemRefsEnd = MemRefsEnd;
742
743  size_t NewNum = (MemRefsEnd - MemRefs) + 1;
744  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
745  mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
746
747  std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
748  NewMemRefs[NewNum - 1] = MO;
749
750  MemRefs = NewMemRefs;
751  MemRefsEnd = NewMemRefsEnd;
752}
753
754bool
755MachineInstr::hasProperty(unsigned MCFlag, QueryType Type) const {
756  if (Type == IgnoreBundle || !isBundle())
757    return getDesc().getFlags() & (1 << MCFlag);
758
759  const MachineBasicBlock *MBB = getParent();
760  MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
761  while (MII != MBB->end() && MII->isInsideBundle()) {
762    if (MII->getDesc().getFlags() & (1 << MCFlag)) {
763      if (Type == AnyInBundle)
764        return true;
765    } else {
766      if (Type == AllInBundle)
767        return false;
768    }
769    ++MII;
770  }
771
772  return Type == AllInBundle;
773}
774
775bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
776                                 MICheckType Check) const {
777  // If opcodes or number of operands are not the same then the two
778  // instructions are obviously not identical.
779  if (Other->getOpcode() != getOpcode() ||
780      Other->getNumOperands() != getNumOperands())
781    return false;
782
783  if (isBundle()) {
784    // Both instructions are bundles, compare MIs inside the bundle.
785    MachineBasicBlock::const_instr_iterator I1 = *this;
786    MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
787    MachineBasicBlock::const_instr_iterator I2 = *Other;
788    MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
789    while (++I1 != E1 && I1->isInsideBundle()) {
790      ++I2;
791      if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
792        return false;
793    }
794  }
795
796  // Check operands to make sure they match.
797  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
798    const MachineOperand &MO = getOperand(i);
799    const MachineOperand &OMO = Other->getOperand(i);
800    if (!MO.isReg()) {
801      if (!MO.isIdenticalTo(OMO))
802        return false;
803      continue;
804    }
805
806    // Clients may or may not want to ignore defs when testing for equality.
807    // For example, machine CSE pass only cares about finding common
808    // subexpressions, so it's safe to ignore virtual register defs.
809    if (MO.isDef()) {
810      if (Check == IgnoreDefs)
811        continue;
812      else if (Check == IgnoreVRegDefs) {
813        if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
814            TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
815          if (MO.getReg() != OMO.getReg())
816            return false;
817      } else {
818        if (!MO.isIdenticalTo(OMO))
819          return false;
820        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
821          return false;
822      }
823    } else {
824      if (!MO.isIdenticalTo(OMO))
825        return false;
826      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
827        return false;
828    }
829  }
830  // If DebugLoc does not match then two dbg.values are not identical.
831  if (isDebugValue())
832    if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
833        && getDebugLoc() != Other->getDebugLoc())
834      return false;
835  return true;
836}
837
838/// removeFromParent - This method unlinks 'this' from the containing basic
839/// block, and returns it, but does not delete it.
840MachineInstr *MachineInstr::removeFromParent() {
841  assert(getParent() && "Not embedded in a basic block!");
842
843  // If it's a bundle then remove the MIs inside the bundle as well.
844  if (isBundle()) {
845    MachineBasicBlock *MBB = getParent();
846    MachineBasicBlock::instr_iterator MII = *this; ++MII;
847    MachineBasicBlock::instr_iterator E = MBB->instr_end();
848    while (MII != E && MII->isInsideBundle()) {
849      MachineInstr *MI = &*MII;
850      ++MII;
851      MBB->remove(MI);
852    }
853  }
854  getParent()->remove(this);
855  return this;
856}
857
858
859/// eraseFromParent - This method unlinks 'this' from the containing basic
860/// block, and deletes it.
861void MachineInstr::eraseFromParent() {
862  assert(getParent() && "Not embedded in a basic block!");
863  // If it's a bundle then remove the MIs inside the bundle as well.
864  if (isBundle()) {
865    MachineBasicBlock *MBB = getParent();
866    MachineBasicBlock::instr_iterator MII = *this; ++MII;
867    MachineBasicBlock::instr_iterator E = MBB->instr_end();
868    while (MII != E && MII->isInsideBundle()) {
869      MachineInstr *MI = &*MII;
870      ++MII;
871      MBB->erase(MI);
872    }
873  }
874  getParent()->erase(this);
875}
876
877
878/// getNumExplicitOperands - Returns the number of non-implicit operands.
879///
880unsigned MachineInstr::getNumExplicitOperands() const {
881  unsigned NumOperands = MCID->getNumOperands();
882  if (!MCID->isVariadic())
883    return NumOperands;
884
885  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
886    const MachineOperand &MO = getOperand(i);
887    if (!MO.isReg() || !MO.isImplicit())
888      NumOperands++;
889  }
890  return NumOperands;
891}
892
893bool MachineInstr::isStackAligningInlineAsm() const {
894  if (isInlineAsm()) {
895    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
896    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
897      return true;
898  }
899  return false;
900}
901
902int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
903                                       unsigned *GroupNo) const {
904  assert(isInlineAsm() && "Expected an inline asm instruction");
905  assert(OpIdx < getNumOperands() && "OpIdx out of range");
906
907  // Ignore queries about the initial operands.
908  if (OpIdx < InlineAsm::MIOp_FirstOperand)
909    return -1;
910
911  unsigned Group = 0;
912  unsigned NumOps;
913  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
914       i += NumOps) {
915    const MachineOperand &FlagMO = getOperand(i);
916    // If we reach the implicit register operands, stop looking.
917    if (!FlagMO.isImm())
918      return -1;
919    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
920    if (i + NumOps > OpIdx) {
921      if (GroupNo)
922        *GroupNo = Group;
923      return i;
924    }
925    ++Group;
926  }
927  return -1;
928}
929
930const TargetRegisterClass*
931MachineInstr::getRegClassConstraint(unsigned OpIdx,
932                                    const TargetInstrInfo *TII,
933                                    const TargetRegisterInfo *TRI) const {
934  // Most opcodes have fixed constraints in their MCInstrDesc.
935  if (!isInlineAsm())
936    return TII->getRegClass(getDesc(), OpIdx, TRI);
937
938  if (!getOperand(OpIdx).isReg())
939    return NULL;
940
941  // For tied uses on inline asm, get the constraint from the def.
942  unsigned DefIdx;
943  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
944    OpIdx = DefIdx;
945
946  // Inline asm stores register class constraints in the flag word.
947  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
948  if (FlagIdx < 0)
949    return NULL;
950
951  unsigned Flag = getOperand(FlagIdx).getImm();
952  unsigned RCID;
953  if (InlineAsm::hasRegClassConstraint(Flag, RCID))
954    return TRI->getRegClass(RCID);
955
956  // Assume that all registers in a memory operand are pointers.
957  if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
958    return TRI->getPointerRegClass();
959
960  return NULL;
961}
962
963/// getBundleSize - Return the number of instructions inside the MI bundle.
964unsigned MachineInstr::getBundleSize() const {
965  assert(isBundle() && "Expecting a bundle");
966
967  MachineBasicBlock::const_instr_iterator I = *this;
968  unsigned Size = 0;
969  while ((++I)->isInsideBundle()) {
970    ++Size;
971  }
972  assert(Size > 1 && "Malformed bundle");
973
974  return Size;
975}
976
977/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
978/// the specific register or -1 if it is not found. It further tightens
979/// the search criteria to a use that kills the register if isKill is true.
980int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
981                                          const TargetRegisterInfo *TRI) const {
982  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
983    const MachineOperand &MO = getOperand(i);
984    if (!MO.isReg() || !MO.isUse())
985      continue;
986    unsigned MOReg = MO.getReg();
987    if (!MOReg)
988      continue;
989    if (MOReg == Reg ||
990        (TRI &&
991         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
992         TargetRegisterInfo::isPhysicalRegister(Reg) &&
993         TRI->isSubRegister(MOReg, Reg)))
994      if (!isKill || MO.isKill())
995        return i;
996  }
997  return -1;
998}
999
1000/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1001/// indicating if this instruction reads or writes Reg. This also considers
1002/// partial defines.
1003std::pair<bool,bool>
1004MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1005                                         SmallVectorImpl<unsigned> *Ops) const {
1006  bool PartDef = false; // Partial redefine.
1007  bool FullDef = false; // Full define.
1008  bool Use = false;
1009
1010  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1011    const MachineOperand &MO = getOperand(i);
1012    if (!MO.isReg() || MO.getReg() != Reg)
1013      continue;
1014    if (Ops)
1015      Ops->push_back(i);
1016    if (MO.isUse())
1017      Use |= !MO.isUndef();
1018    else if (MO.getSubReg() && !MO.isUndef())
1019      // A partial <def,undef> doesn't count as reading the register.
1020      PartDef = true;
1021    else
1022      FullDef = true;
1023  }
1024  // A partial redefine uses Reg unless there is also a full define.
1025  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1026}
1027
1028/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1029/// the specified register or -1 if it is not found. If isDead is true, defs
1030/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1031/// also checks if there is a def of a super-register.
1032int
1033MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1034                                        const TargetRegisterInfo *TRI) const {
1035  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1036  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1037    const MachineOperand &MO = getOperand(i);
1038    if (!MO.isReg() || !MO.isDef())
1039      continue;
1040    unsigned MOReg = MO.getReg();
1041    bool Found = (MOReg == Reg);
1042    if (!Found && TRI && isPhys &&
1043        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1044      if (Overlap)
1045        Found = TRI->regsOverlap(MOReg, Reg);
1046      else
1047        Found = TRI->isSubRegister(MOReg, Reg);
1048    }
1049    if (Found && (!isDead || MO.isDead()))
1050      return i;
1051  }
1052  return -1;
1053}
1054
1055/// findFirstPredOperandIdx() - Find the index of the first operand in the
1056/// operand list that is used to represent the predicate. It returns -1 if
1057/// none is found.
1058int MachineInstr::findFirstPredOperandIdx() const {
1059  // Don't call MCID.findFirstPredOperandIdx() because this variant
1060  // is sometimes called on an instruction that's not yet complete, and
1061  // so the number of operands is less than the MCID indicates. In
1062  // particular, the PTX target does this.
1063  const MCInstrDesc &MCID = getDesc();
1064  if (MCID.isPredicable()) {
1065    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1066      if (MCID.OpInfo[i].isPredicate())
1067        return i;
1068  }
1069
1070  return -1;
1071}
1072
1073/// isRegTiedToUseOperand - Given the index of a register def operand,
1074/// check if the register def is tied to a source operand, due to either
1075/// two-address elimination or inline assembly constraints. Returns the
1076/// first tied use operand index by reference is UseOpIdx is not null.
1077bool MachineInstr::
1078isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
1079  if (isInlineAsm()) {
1080    assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
1081    const MachineOperand &MO = getOperand(DefOpIdx);
1082    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
1083      return false;
1084    // Determine the actual operand index that corresponds to this index.
1085    unsigned DefNo = 0;
1086    int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1087    if (FlagIdx < 0)
1088      return false;
1089
1090    // Which part of the group is DefOpIdx?
1091    unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1092
1093    for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1094         i != e; ++i) {
1095      const MachineOperand &FMO = getOperand(i);
1096      if (!FMO.isImm())
1097        continue;
1098      if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1099        continue;
1100      unsigned Idx;
1101      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1102          Idx == DefNo) {
1103        if (UseOpIdx)
1104          *UseOpIdx = (unsigned)i + 1 + DefPart;
1105        return true;
1106      }
1107    }
1108    return false;
1109  }
1110
1111  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1112  const MCInstrDesc &MCID = getDesc();
1113  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1114    const MachineOperand &MO = getOperand(i);
1115    if (MO.isReg() && MO.isUse() &&
1116        MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1117      if (UseOpIdx)
1118        *UseOpIdx = (unsigned)i;
1119      return true;
1120    }
1121  }
1122  return false;
1123}
1124
1125/// isRegTiedToDefOperand - Return true if the operand of the specified index
1126/// is a register use and it is tied to an def operand. It also returns the def
1127/// operand index by reference.
1128bool MachineInstr::
1129isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1130  if (isInlineAsm()) {
1131    const MachineOperand &MO = getOperand(UseOpIdx);
1132    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1133      return false;
1134
1135    // Find the flag operand corresponding to UseOpIdx
1136    int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1137    if (FlagIdx < 0)
1138      return false;
1139
1140    const MachineOperand &UFMO = getOperand(FlagIdx);
1141    unsigned DefNo;
1142    if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1143      if (!DefOpIdx)
1144        return true;
1145
1146      unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1147      // Remember to adjust the index. First operand is asm string, second is
1148      // the HasSideEffects and AlignStack bits, then there is a flag for each.
1149      while (DefNo) {
1150        const MachineOperand &FMO = getOperand(DefIdx);
1151        assert(FMO.isImm());
1152        // Skip over this def.
1153        DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1154        --DefNo;
1155      }
1156      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1157      return true;
1158    }
1159    return false;
1160  }
1161
1162  const MCInstrDesc &MCID = getDesc();
1163  if (UseOpIdx >= MCID.getNumOperands())
1164    return false;
1165  const MachineOperand &MO = getOperand(UseOpIdx);
1166  if (!MO.isReg() || !MO.isUse())
1167    return false;
1168  int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1169  if (DefIdx == -1)
1170    return false;
1171  if (DefOpIdx)
1172    *DefOpIdx = (unsigned)DefIdx;
1173  return true;
1174}
1175
1176/// clearKillInfo - Clears kill flags on all operands.
1177///
1178void MachineInstr::clearKillInfo() {
1179  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1180    MachineOperand &MO = getOperand(i);
1181    if (MO.isReg() && MO.isUse())
1182      MO.setIsKill(false);
1183  }
1184}
1185
1186/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1187///
1188void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1189  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1190    const MachineOperand &MO = MI->getOperand(i);
1191    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1192      continue;
1193    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1194      MachineOperand &MOp = getOperand(j);
1195      if (!MOp.isIdenticalTo(MO))
1196        continue;
1197      if (MO.isKill())
1198        MOp.setIsKill();
1199      else
1200        MOp.setIsDead();
1201      break;
1202    }
1203  }
1204}
1205
1206/// copyPredicates - Copies predicate operand(s) from MI.
1207void MachineInstr::copyPredicates(const MachineInstr *MI) {
1208  assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1209
1210  const MCInstrDesc &MCID = MI->getDesc();
1211  if (!MCID.isPredicable())
1212    return;
1213  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1214    if (MCID.OpInfo[i].isPredicate()) {
1215      // Predicated operands must be last operands.
1216      addOperand(MI->getOperand(i));
1217    }
1218  }
1219}
1220
1221void MachineInstr::substituteRegister(unsigned FromReg,
1222                                      unsigned ToReg,
1223                                      unsigned SubIdx,
1224                                      const TargetRegisterInfo &RegInfo) {
1225  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1226    if (SubIdx)
1227      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1228    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1229      MachineOperand &MO = getOperand(i);
1230      if (!MO.isReg() || MO.getReg() != FromReg)
1231        continue;
1232      MO.substPhysReg(ToReg, RegInfo);
1233    }
1234  } else {
1235    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1236      MachineOperand &MO = getOperand(i);
1237      if (!MO.isReg() || MO.getReg() != FromReg)
1238        continue;
1239      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1240    }
1241  }
1242}
1243
1244/// isSafeToMove - Return true if it is safe to move this instruction. If
1245/// SawStore is set to true, it means that there is a store (or call) between
1246/// the instruction's location and its intended destination.
1247bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1248                                AliasAnalysis *AA,
1249                                bool &SawStore) const {
1250  // Ignore stuff that we obviously can't move.
1251  if (mayStore() || isCall()) {
1252    SawStore = true;
1253    return false;
1254  }
1255
1256  if (isLabel() || isDebugValue() ||
1257      isTerminator() || hasUnmodeledSideEffects())
1258    return false;
1259
1260  // See if this instruction does a load.  If so, we have to guarantee that the
1261  // loaded value doesn't change between the load and the its intended
1262  // destination. The check for isInvariantLoad gives the targe the chance to
1263  // classify the load as always returning a constant, e.g. a constant pool
1264  // load.
1265  if (mayLoad() && !isInvariantLoad(AA))
1266    // Otherwise, this is a real load.  If there is a store between the load and
1267    // end of block, or if the load is volatile, we can't move it.
1268    return !SawStore && !hasVolatileMemoryRef();
1269
1270  return true;
1271}
1272
1273/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1274/// instruction which defined the specified register instead of copying it.
1275bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1276                                 AliasAnalysis *AA,
1277                                 unsigned DstReg) const {
1278  bool SawStore = false;
1279  if (!TII->isTriviallyReMaterializable(this, AA) ||
1280      !isSafeToMove(TII, AA, SawStore))
1281    return false;
1282  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1283    const MachineOperand &MO = getOperand(i);
1284    if (!MO.isReg())
1285      continue;
1286    // FIXME: For now, do not remat any instruction with register operands.
1287    // Later on, we can loosen the restriction is the register operands have
1288    // not been modified between the def and use. Note, this is different from
1289    // MachineSink because the code is no longer in two-address form (at least
1290    // partially).
1291    if (MO.isUse())
1292      return false;
1293    else if (!MO.isDead() && MO.getReg() != DstReg)
1294      return false;
1295  }
1296  return true;
1297}
1298
1299/// hasVolatileMemoryRef - Return true if this instruction may have a
1300/// volatile memory reference, or if the information describing the
1301/// memory reference is not available. Return false if it is known to
1302/// have no volatile memory references.
1303bool MachineInstr::hasVolatileMemoryRef() const {
1304  // An instruction known never to access memory won't have a volatile access.
1305  if (!mayStore() &&
1306      !mayLoad() &&
1307      !isCall() &&
1308      !hasUnmodeledSideEffects())
1309    return false;
1310
1311  // Otherwise, if the instruction has no memory reference information,
1312  // conservatively assume it wasn't preserved.
1313  if (memoperands_empty())
1314    return true;
1315
1316  // Check the memory reference information for volatile references.
1317  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1318    if ((*I)->isVolatile())
1319      return true;
1320
1321  return false;
1322}
1323
1324/// isInvariantLoad - Return true if this instruction is loading from a
1325/// location whose value is invariant across the function.  For example,
1326/// loading a value from the constant pool or from the argument area
1327/// of a function if it does not change.  This should only return true of
1328/// *all* loads the instruction does are invariant (if it does multiple loads).
1329bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1330  // If the instruction doesn't load at all, it isn't an invariant load.
1331  if (!mayLoad())
1332    return false;
1333
1334  // If the instruction has lost its memoperands, conservatively assume that
1335  // it may not be an invariant load.
1336  if (memoperands_empty())
1337    return false;
1338
1339  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1340
1341  for (mmo_iterator I = memoperands_begin(),
1342       E = memoperands_end(); I != E; ++I) {
1343    if ((*I)->isVolatile()) return false;
1344    if ((*I)->isStore()) return false;
1345    if ((*I)->isInvariant()) return true;
1346
1347    if (const Value *V = (*I)->getValue()) {
1348      // A load from a constant PseudoSourceValue is invariant.
1349      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1350        if (PSV->isConstant(MFI))
1351          continue;
1352      // If we have an AliasAnalysis, ask it whether the memory is constant.
1353      if (AA && AA->pointsToConstantMemory(
1354                      AliasAnalysis::Location(V, (*I)->getSize(),
1355                                              (*I)->getTBAAInfo())))
1356        continue;
1357    }
1358
1359    // Otherwise assume conservatively.
1360    return false;
1361  }
1362
1363  // Everything checks out.
1364  return true;
1365}
1366
1367/// isConstantValuePHI - If the specified instruction is a PHI that always
1368/// merges together the same virtual register, return the register, otherwise
1369/// return 0.
1370unsigned MachineInstr::isConstantValuePHI() const {
1371  if (!isPHI())
1372    return 0;
1373  assert(getNumOperands() >= 3 &&
1374         "It's illegal to have a PHI without source operands");
1375
1376  unsigned Reg = getOperand(1).getReg();
1377  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1378    if (getOperand(i).getReg() != Reg)
1379      return 0;
1380  return Reg;
1381}
1382
1383bool MachineInstr::hasUnmodeledSideEffects() const {
1384  if (hasProperty(MCID::UnmodeledSideEffects))
1385    return true;
1386  if (isInlineAsm()) {
1387    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1388    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1389      return true;
1390  }
1391
1392  return false;
1393}
1394
1395/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1396///
1397bool MachineInstr::allDefsAreDead() const {
1398  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1399    const MachineOperand &MO = getOperand(i);
1400    if (!MO.isReg() || MO.isUse())
1401      continue;
1402    if (!MO.isDead())
1403      return false;
1404  }
1405  return true;
1406}
1407
1408/// copyImplicitOps - Copy implicit register operands from specified
1409/// instruction to this instruction.
1410void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1411  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1412       i != e; ++i) {
1413    const MachineOperand &MO = MI->getOperand(i);
1414    if (MO.isReg() && MO.isImplicit())
1415      addOperand(MO);
1416  }
1417}
1418
1419void MachineInstr::dump() const {
1420  dbgs() << "  " << *this;
1421}
1422
1423static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1424                         raw_ostream &CommentOS) {
1425  const LLVMContext &Ctx = MF->getFunction()->getContext();
1426  if (!DL.isUnknown()) {          // Print source line info.
1427    DIScope Scope(DL.getScope(Ctx));
1428    // Omit the directory, because it's likely to be long and uninteresting.
1429    if (Scope.Verify())
1430      CommentOS << Scope.getFilename();
1431    else
1432      CommentOS << "<unknown>";
1433    CommentOS << ':' << DL.getLine();
1434    if (DL.getCol() != 0)
1435      CommentOS << ':' << DL.getCol();
1436    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1437    if (!InlinedAtDL.isUnknown()) {
1438      CommentOS << " @[ ";
1439      printDebugLoc(InlinedAtDL, MF, CommentOS);
1440      CommentOS << " ]";
1441    }
1442  }
1443}
1444
1445void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1446  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1447  const MachineFunction *MF = 0;
1448  const MachineRegisterInfo *MRI = 0;
1449  if (const MachineBasicBlock *MBB = getParent()) {
1450    MF = MBB->getParent();
1451    if (!TM && MF)
1452      TM = &MF->getTarget();
1453    if (MF)
1454      MRI = &MF->getRegInfo();
1455  }
1456
1457  // Save a list of virtual registers.
1458  SmallVector<unsigned, 8> VirtRegs;
1459
1460  // Print explicitly defined operands on the left of an assignment syntax.
1461  unsigned StartOp = 0, e = getNumOperands();
1462  for (; StartOp < e && getOperand(StartOp).isReg() &&
1463         getOperand(StartOp).isDef() &&
1464         !getOperand(StartOp).isImplicit();
1465       ++StartOp) {
1466    if (StartOp != 0) OS << ", ";
1467    getOperand(StartOp).print(OS, TM);
1468    unsigned Reg = getOperand(StartOp).getReg();
1469    if (TargetRegisterInfo::isVirtualRegister(Reg))
1470      VirtRegs.push_back(Reg);
1471  }
1472
1473  if (StartOp != 0)
1474    OS << " = ";
1475
1476  // Print the opcode name.
1477  OS << getDesc().getName();
1478
1479  // Print the rest of the operands.
1480  bool OmittedAnyCallClobbers = false;
1481  bool FirstOp = true;
1482  unsigned AsmDescOp = ~0u;
1483  unsigned AsmOpCount = 0;
1484
1485  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1486    // Print asm string.
1487    OS << " ";
1488    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1489
1490    // Print HasSideEffects, IsAlignStack
1491    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1492    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1493      OS << " [sideeffect]";
1494    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1495      OS << " [alignstack]";
1496
1497    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1498    FirstOp = false;
1499  }
1500
1501
1502  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1503    const MachineOperand &MO = getOperand(i);
1504
1505    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1506      VirtRegs.push_back(MO.getReg());
1507
1508    // Omit call-clobbered registers which aren't used anywhere. This makes
1509    // call instructions much less noisy on targets where calls clobber lots
1510    // of registers. Don't rely on MO.isDead() because we may be called before
1511    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1512    if (MF && isCall() &&
1513        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1514      unsigned Reg = MO.getReg();
1515      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1516        const MachineRegisterInfo &MRI = MF->getRegInfo();
1517        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1518          bool HasAliasLive = false;
1519          for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1520               unsigned AliasReg = *Alias; ++Alias)
1521            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1522              HasAliasLive = true;
1523              break;
1524            }
1525          if (!HasAliasLive) {
1526            OmittedAnyCallClobbers = true;
1527            continue;
1528          }
1529        }
1530      }
1531    }
1532
1533    if (FirstOp) FirstOp = false; else OS << ",";
1534    OS << " ";
1535    if (i < getDesc().NumOperands) {
1536      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1537      if (MCOI.isPredicate())
1538        OS << "pred:";
1539      if (MCOI.isOptionalDef())
1540        OS << "opt:";
1541    }
1542    if (isDebugValue() && MO.isMetadata()) {
1543      // Pretty print DBG_VALUE instructions.
1544      const MDNode *MD = MO.getMetadata();
1545      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1546        OS << "!\"" << MDS->getString() << '\"';
1547      else
1548        MO.print(OS, TM);
1549    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1550      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1551    } else if (i == AsmDescOp && MO.isImm()) {
1552      // Pretty print the inline asm operand descriptor.
1553      OS << '$' << AsmOpCount++;
1554      unsigned Flag = MO.getImm();
1555      switch (InlineAsm::getKind(Flag)) {
1556      case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
1557      case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
1558      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1559      case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
1560      case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
1561      case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
1562      default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1563      }
1564
1565      unsigned RCID = 0;
1566      if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1567        if (TM)
1568          OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1569        else
1570          OS << ":RC" << RCID;
1571      }
1572
1573      unsigned TiedTo = 0;
1574      if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1575        OS << " tiedto:$" << TiedTo;
1576
1577      OS << ']';
1578
1579      // Compute the index of the next operand descriptor.
1580      AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1581    } else
1582      MO.print(OS, TM);
1583  }
1584
1585  // Briefly indicate whether any call clobbers were omitted.
1586  if (OmittedAnyCallClobbers) {
1587    if (!FirstOp) OS << ",";
1588    OS << " ...";
1589  }
1590
1591  bool HaveSemi = false;
1592  if (Flags) {
1593    if (!HaveSemi) OS << ";"; HaveSemi = true;
1594    OS << " flags: ";
1595
1596    if (Flags & FrameSetup)
1597      OS << "FrameSetup";
1598  }
1599
1600  if (!memoperands_empty()) {
1601    if (!HaveSemi) OS << ";"; HaveSemi = true;
1602
1603    OS << " mem:";
1604    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1605         i != e; ++i) {
1606      OS << **i;
1607      if (llvm::next(i) != e)
1608        OS << " ";
1609    }
1610  }
1611
1612  // Print the regclass of any virtual registers encountered.
1613  if (MRI && !VirtRegs.empty()) {
1614    if (!HaveSemi) OS << ";"; HaveSemi = true;
1615    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1616      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1617      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1618      for (unsigned j = i+1; j != VirtRegs.size();) {
1619        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1620          ++j;
1621          continue;
1622        }
1623        if (VirtRegs[i] != VirtRegs[j])
1624          OS << "," << PrintReg(VirtRegs[j]);
1625        VirtRegs.erase(VirtRegs.begin()+j);
1626      }
1627    }
1628  }
1629
1630  // Print debug location information.
1631  if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1632    if (!HaveSemi) OS << ";"; HaveSemi = true;
1633    DIVariable DV(getOperand(e - 1).getMetadata());
1634    OS << " line no:" <<  DV.getLineNumber();
1635    if (MDNode *InlinedAt = DV.getInlinedAt()) {
1636      DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1637      if (!InlinedAtDL.isUnknown()) {
1638        OS << " inlined @[ ";
1639        printDebugLoc(InlinedAtDL, MF, OS);
1640        OS << " ]";
1641      }
1642    }
1643  } else if (!debugLoc.isUnknown() && MF) {
1644    if (!HaveSemi) OS << ";"; HaveSemi = true;
1645    OS << " dbg:";
1646    printDebugLoc(debugLoc, MF, OS);
1647  }
1648
1649  OS << '\n';
1650}
1651
1652bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1653                                     const TargetRegisterInfo *RegInfo,
1654                                     bool AddIfNotFound) {
1655  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1656  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1657  bool Found = false;
1658  SmallVector<unsigned,4> DeadOps;
1659  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1660    MachineOperand &MO = getOperand(i);
1661    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1662      continue;
1663    unsigned Reg = MO.getReg();
1664    if (!Reg)
1665      continue;
1666
1667    if (Reg == IncomingReg) {
1668      if (!Found) {
1669        if (MO.isKill())
1670          // The register is already marked kill.
1671          return true;
1672        if (isPhysReg && isRegTiedToDefOperand(i))
1673          // Two-address uses of physregs must not be marked kill.
1674          return true;
1675        MO.setIsKill();
1676        Found = true;
1677      }
1678    } else if (hasAliases && MO.isKill() &&
1679               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1680      // A super-register kill already exists.
1681      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1682        return true;
1683      if (RegInfo->isSubRegister(IncomingReg, Reg))
1684        DeadOps.push_back(i);
1685    }
1686  }
1687
1688  // Trim unneeded kill operands.
1689  while (!DeadOps.empty()) {
1690    unsigned OpIdx = DeadOps.back();
1691    if (getOperand(OpIdx).isImplicit())
1692      RemoveOperand(OpIdx);
1693    else
1694      getOperand(OpIdx).setIsKill(false);
1695    DeadOps.pop_back();
1696  }
1697
1698  // If not found, this means an alias of one of the operands is killed. Add a
1699  // new implicit operand if required.
1700  if (!Found && AddIfNotFound) {
1701    addOperand(MachineOperand::CreateReg(IncomingReg,
1702                                         false /*IsDef*/,
1703                                         true  /*IsImp*/,
1704                                         true  /*IsKill*/));
1705    return true;
1706  }
1707  return Found;
1708}
1709
1710bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1711                                   const TargetRegisterInfo *RegInfo,
1712                                   bool AddIfNotFound) {
1713  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1714  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1715  bool Found = false;
1716  SmallVector<unsigned,4> DeadOps;
1717  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1718    MachineOperand &MO = getOperand(i);
1719    if (!MO.isReg() || !MO.isDef())
1720      continue;
1721    unsigned Reg = MO.getReg();
1722    if (!Reg)
1723      continue;
1724
1725    if (Reg == IncomingReg) {
1726      MO.setIsDead();
1727      Found = true;
1728    } else if (hasAliases && MO.isDead() &&
1729               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1730      // There exists a super-register that's marked dead.
1731      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1732        return true;
1733      if (RegInfo->getSubRegisters(IncomingReg) &&
1734          RegInfo->getSuperRegisters(Reg) &&
1735          RegInfo->isSubRegister(IncomingReg, Reg))
1736        DeadOps.push_back(i);
1737    }
1738  }
1739
1740  // Trim unneeded dead operands.
1741  while (!DeadOps.empty()) {
1742    unsigned OpIdx = DeadOps.back();
1743    if (getOperand(OpIdx).isImplicit())
1744      RemoveOperand(OpIdx);
1745    else
1746      getOperand(OpIdx).setIsDead(false);
1747    DeadOps.pop_back();
1748  }
1749
1750  // If not found, this means an alias of one of the operands is dead. Add a
1751  // new implicit operand if required.
1752  if (Found || !AddIfNotFound)
1753    return Found;
1754
1755  addOperand(MachineOperand::CreateReg(IncomingReg,
1756                                       true  /*IsDef*/,
1757                                       true  /*IsImp*/,
1758                                       false /*IsKill*/,
1759                                       true  /*IsDead*/));
1760  return true;
1761}
1762
1763void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1764                                      const TargetRegisterInfo *RegInfo) {
1765  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1766    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1767    if (MO)
1768      return;
1769  } else {
1770    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1771      const MachineOperand &MO = getOperand(i);
1772      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1773          MO.getSubReg() == 0)
1774        return;
1775    }
1776  }
1777  addOperand(MachineOperand::CreateReg(IncomingReg,
1778                                       true  /*IsDef*/,
1779                                       true  /*IsImp*/));
1780}
1781
1782void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1783                                         const TargetRegisterInfo &TRI) {
1784  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1785    MachineOperand &MO = getOperand(i);
1786    if (!MO.isReg() || !MO.isDef()) continue;
1787    unsigned Reg = MO.getReg();
1788    if (Reg == 0) continue;
1789    bool Dead = true;
1790    for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1791         E = UsedRegs.end(); I != E; ++I)
1792      if (TRI.regsOverlap(*I, Reg)) {
1793        Dead = false;
1794        break;
1795      }
1796    // If there are no uses, including partial uses, the def is dead.
1797    if (Dead) MO.setIsDead();
1798  }
1799}
1800
1801unsigned
1802MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1803  unsigned Hash = MI->getOpcode() * 37;
1804  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1805    const MachineOperand &MO = MI->getOperand(i);
1806    uint64_t Key = (uint64_t)MO.getType() << 32;
1807    switch (MO.getType()) {
1808    default: break;
1809    case MachineOperand::MO_Register:
1810      if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1811        continue;  // Skip virtual register defs.
1812      Key |= MO.getReg();
1813      break;
1814    case MachineOperand::MO_Immediate:
1815      Key |= MO.getImm();
1816      break;
1817    case MachineOperand::MO_FrameIndex:
1818    case MachineOperand::MO_ConstantPoolIndex:
1819    case MachineOperand::MO_JumpTableIndex:
1820      Key |= MO.getIndex();
1821      break;
1822    case MachineOperand::MO_MachineBasicBlock:
1823      Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1824      break;
1825    case MachineOperand::MO_GlobalAddress:
1826      Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1827      break;
1828    case MachineOperand::MO_BlockAddress:
1829      Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1830      break;
1831    case MachineOperand::MO_MCSymbol:
1832      Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1833      break;
1834    }
1835    Key += ~(Key << 32);
1836    Key ^= (Key >> 22);
1837    Key += ~(Key << 13);
1838    Key ^= (Key >> 8);
1839    Key += (Key << 3);
1840    Key ^= (Key >> 15);
1841    Key += ~(Key << 27);
1842    Key ^= (Key >> 31);
1843    Hash = (unsigned)Key + Hash * 37;
1844  }
1845  return Hash;
1846}
1847
1848void MachineInstr::emitError(StringRef Msg) const {
1849  // Find the source location cookie.
1850  unsigned LocCookie = 0;
1851  const MDNode *LocMD = 0;
1852  for (unsigned i = getNumOperands(); i != 0; --i) {
1853    if (getOperand(i-1).isMetadata() &&
1854        (LocMD = getOperand(i-1).getMetadata()) &&
1855        LocMD->getNumOperands() != 0) {
1856      if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1857        LocCookie = CI->getZExtValue();
1858        break;
1859      }
1860    }
1861  }
1862
1863  if (const MachineBasicBlock *MBB = getParent())
1864    if (const MachineFunction *MF = MBB->getParent())
1865      return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1866  report_fatal_error(Msg);
1867}
1868