MachineInstr.cpp revision 9c130672761e006c47ea23b34a7bd414f2cd8368
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineInstr.h" 15#include "llvm/Constants.h" 16#include "llvm/DebugInfo.h" 17#include "llvm/Function.h" 18#include "llvm/InlineAsm.h" 19#include "llvm/LLVMContext.h" 20#include "llvm/Metadata.h" 21#include "llvm/Module.h" 22#include "llvm/Type.h" 23#include "llvm/Value.h" 24#include "llvm/Assembly/Writer.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineMemOperand.h" 28#include "llvm/CodeGen/MachineModuleInfo.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/CodeGen/PseudoSourceValue.h" 31#include "llvm/MC/MCInstrDesc.h" 32#include "llvm/MC/MCSymbol.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/Target/TargetInstrInfo.h" 35#include "llvm/Target/TargetRegisterInfo.h" 36#include "llvm/Analysis/AliasAnalysis.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Support/LeakDetector.h" 40#include "llvm/Support/MathExtras.h" 41#include "llvm/Support/raw_ostream.h" 42#include "llvm/ADT/FoldingSet.h" 43#include "llvm/ADT/Hashing.h" 44using namespace llvm; 45 46//===----------------------------------------------------------------------===// 47// MachineOperand Implementation 48//===----------------------------------------------------------------------===// 49 50void MachineOperand::setReg(unsigned Reg) { 51 if (getReg() == Reg) return; // No change. 52 53 // Otherwise, we have to change the register. If this operand is embedded 54 // into a machine function, we need to update the old and new register's 55 // use/def lists. 56 if (MachineInstr *MI = getParent()) 57 if (MachineBasicBlock *MBB = MI->getParent()) 58 if (MachineFunction *MF = MBB->getParent()) { 59 MachineRegisterInfo &MRI = MF->getRegInfo(); 60 MRI.removeRegOperandFromUseList(this); 61 SmallContents.RegNo = Reg; 62 MRI.addRegOperandToUseList(this); 63 return; 64 } 65 66 // Otherwise, just change the register, no problem. :) 67 SmallContents.RegNo = Reg; 68} 69 70void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, 71 const TargetRegisterInfo &TRI) { 72 assert(TargetRegisterInfo::isVirtualRegister(Reg)); 73 if (SubIdx && getSubReg()) 74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 75 setReg(Reg); 76 if (SubIdx) 77 setSubReg(SubIdx); 78} 79 80void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { 81 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 82 if (getSubReg()) { 83 Reg = TRI.getSubReg(Reg, getSubReg()); 84 // Note that getSubReg() may return 0 if the sub-register doesn't exist. 85 // That won't happen in legal code. 86 setSubReg(0); 87 } 88 setReg(Reg); 89} 90 91/// Change a def to a use, or a use to a def. 92void MachineOperand::setIsDef(bool Val) { 93 assert(isReg() && "Wrong MachineOperand accessor"); 94 assert((!Val || !isDebug()) && "Marking a debug operation as def"); 95 if (IsDef == Val) 96 return; 97 // MRI may keep uses and defs in different list positions. 98 if (MachineInstr *MI = getParent()) 99 if (MachineBasicBlock *MBB = MI->getParent()) 100 if (MachineFunction *MF = MBB->getParent()) { 101 MachineRegisterInfo &MRI = MF->getRegInfo(); 102 MRI.removeRegOperandFromUseList(this); 103 IsDef = Val; 104 MRI.addRegOperandToUseList(this); 105 return; 106 } 107 IsDef = Val; 108} 109 110/// ChangeToImmediate - Replace this operand with a new immediate operand of 111/// the specified value. If an operand is known to be an immediate already, 112/// the setImm method should be used. 113void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 114 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); 115 // If this operand is currently a register operand, and if this is in a 116 // function, deregister the operand from the register's use/def list. 117 if (isReg() && isOnRegUseList()) 118 if (MachineInstr *MI = getParent()) 119 if (MachineBasicBlock *MBB = MI->getParent()) 120 if (MachineFunction *MF = MBB->getParent()) 121 MF->getRegInfo().removeRegOperandFromUseList(this); 122 123 OpKind = MO_Immediate; 124 Contents.ImmVal = ImmVal; 125} 126 127/// ChangeToRegister - Replace this operand with a new register operand of 128/// the specified value. If an operand is known to be an register already, 129/// the setReg method should be used. 130void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 131 bool isKill, bool isDead, bool isUndef, 132 bool isDebug) { 133 MachineRegisterInfo *RegInfo = 0; 134 if (MachineInstr *MI = getParent()) 135 if (MachineBasicBlock *MBB = MI->getParent()) 136 if (MachineFunction *MF = MBB->getParent()) 137 RegInfo = &MF->getRegInfo(); 138 // If this operand is already a register operand, remove it from the 139 // register's use/def lists. 140 bool WasReg = isReg(); 141 if (RegInfo && WasReg) 142 RegInfo->removeRegOperandFromUseList(this); 143 144 // Change this to a register and set the reg#. 145 OpKind = MO_Register; 146 SmallContents.RegNo = Reg; 147 SubReg = 0; 148 IsDef = isDef; 149 IsImp = isImp; 150 IsKill = isKill; 151 IsDead = isDead; 152 IsUndef = isUndef; 153 IsInternalRead = false; 154 IsEarlyClobber = false; 155 IsDebug = isDebug; 156 // Ensure isOnRegUseList() returns false. 157 Contents.Reg.Prev = 0; 158 // Preserve the tie when the operand was already a register. 159 if (!WasReg) 160 TiedTo = 0; 161 162 // If this operand is embedded in a function, add the operand to the 163 // register's use/def list. 164 if (RegInfo) 165 RegInfo->addRegOperandToUseList(this); 166} 167 168/// isIdenticalTo - Return true if this operand is identical to the specified 169/// operand. Note that this should stay in sync with the hash_value overload 170/// below. 171bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 172 if (getType() != Other.getType() || 173 getTargetFlags() != Other.getTargetFlags()) 174 return false; 175 176 switch (getType()) { 177 case MachineOperand::MO_Register: 178 return getReg() == Other.getReg() && isDef() == Other.isDef() && 179 getSubReg() == Other.getSubReg(); 180 case MachineOperand::MO_Immediate: 181 return getImm() == Other.getImm(); 182 case MachineOperand::MO_CImmediate: 183 return getCImm() == Other.getCImm(); 184 case MachineOperand::MO_FPImmediate: 185 return getFPImm() == Other.getFPImm(); 186 case MachineOperand::MO_MachineBasicBlock: 187 return getMBB() == Other.getMBB(); 188 case MachineOperand::MO_FrameIndex: 189 return getIndex() == Other.getIndex(); 190 case MachineOperand::MO_ConstantPoolIndex: 191 case MachineOperand::MO_TargetIndex: 192 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 193 case MachineOperand::MO_JumpTableIndex: 194 return getIndex() == Other.getIndex(); 195 case MachineOperand::MO_GlobalAddress: 196 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 197 case MachineOperand::MO_ExternalSymbol: 198 return !strcmp(getSymbolName(), Other.getSymbolName()) && 199 getOffset() == Other.getOffset(); 200 case MachineOperand::MO_BlockAddress: 201 return getBlockAddress() == Other.getBlockAddress(); 202 case MO_RegisterMask: 203 return getRegMask() == Other.getRegMask(); 204 case MachineOperand::MO_MCSymbol: 205 return getMCSymbol() == Other.getMCSymbol(); 206 case MachineOperand::MO_Metadata: 207 return getMetadata() == Other.getMetadata(); 208 } 209 llvm_unreachable("Invalid machine operand type"); 210} 211 212// Note: this must stay exactly in sync with isIdenticalTo above. 213hash_code llvm::hash_value(const MachineOperand &MO) { 214 switch (MO.getType()) { 215 case MachineOperand::MO_Register: 216 // Register operands don't have target flags. 217 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); 218 case MachineOperand::MO_Immediate: 219 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm()); 220 case MachineOperand::MO_CImmediate: 221 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm()); 222 case MachineOperand::MO_FPImmediate: 223 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm()); 224 case MachineOperand::MO_MachineBasicBlock: 225 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB()); 226 case MachineOperand::MO_FrameIndex: 227 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 228 case MachineOperand::MO_ConstantPoolIndex: 229 case MachineOperand::MO_TargetIndex: 230 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(), 231 MO.getOffset()); 232 case MachineOperand::MO_JumpTableIndex: 233 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 234 case MachineOperand::MO_ExternalSymbol: 235 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(), 236 MO.getSymbolName()); 237 case MachineOperand::MO_GlobalAddress: 238 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(), 239 MO.getOffset()); 240 case MachineOperand::MO_BlockAddress: 241 return hash_combine(MO.getType(), MO.getTargetFlags(), 242 MO.getBlockAddress()); 243 case MachineOperand::MO_RegisterMask: 244 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask()); 245 case MachineOperand::MO_Metadata: 246 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata()); 247 case MachineOperand::MO_MCSymbol: 248 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol()); 249 } 250 llvm_unreachable("Invalid machine operand type"); 251} 252 253/// print - Print the specified machine operand. 254/// 255void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 256 // If the instruction is embedded into a basic block, we can find the 257 // target info for the instruction. 258 if (!TM) 259 if (const MachineInstr *MI = getParent()) 260 if (const MachineBasicBlock *MBB = MI->getParent()) 261 if (const MachineFunction *MF = MBB->getParent()) 262 TM = &MF->getTarget(); 263 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; 264 265 switch (getType()) { 266 case MachineOperand::MO_Register: 267 OS << PrintReg(getReg(), TRI, getSubReg()); 268 269 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 270 isInternalRead() || isEarlyClobber() || isTied()) { 271 OS << '<'; 272 bool NeedComma = false; 273 if (isDef()) { 274 if (NeedComma) OS << ','; 275 if (isEarlyClobber()) 276 OS << "earlyclobber,"; 277 if (isImplicit()) 278 OS << "imp-"; 279 OS << "def"; 280 NeedComma = true; 281 // <def,read-undef> only makes sense when getSubReg() is set. 282 // Don't clutter the output otherwise. 283 if (isUndef() && getSubReg()) 284 OS << ",read-undef"; 285 } else if (isImplicit()) { 286 OS << "imp-use"; 287 NeedComma = true; 288 } 289 290 if (isKill()) { 291 if (NeedComma) OS << ','; 292 OS << "kill"; 293 NeedComma = true; 294 } 295 if (isDead()) { 296 if (NeedComma) OS << ','; 297 OS << "dead"; 298 NeedComma = true; 299 } 300 if (isUndef() && isUse()) { 301 if (NeedComma) OS << ','; 302 OS << "undef"; 303 NeedComma = true; 304 } 305 if (isInternalRead()) { 306 if (NeedComma) OS << ','; 307 OS << "internal"; 308 NeedComma = true; 309 } 310 if (isTied()) { 311 if (NeedComma) OS << ','; 312 OS << "tied"; 313 if (TiedTo != 15) 314 OS << unsigned(TiedTo - 1); 315 NeedComma = true; 316 } 317 OS << '>'; 318 } 319 break; 320 case MachineOperand::MO_Immediate: 321 OS << getImm(); 322 break; 323 case MachineOperand::MO_CImmediate: 324 getCImm()->getValue().print(OS, false); 325 break; 326 case MachineOperand::MO_FPImmediate: 327 if (getFPImm()->getType()->isFloatTy()) 328 OS << getFPImm()->getValueAPF().convertToFloat(); 329 else 330 OS << getFPImm()->getValueAPF().convertToDouble(); 331 break; 332 case MachineOperand::MO_MachineBasicBlock: 333 OS << "<BB#" << getMBB()->getNumber() << ">"; 334 break; 335 case MachineOperand::MO_FrameIndex: 336 OS << "<fi#" << getIndex() << '>'; 337 break; 338 case MachineOperand::MO_ConstantPoolIndex: 339 OS << "<cp#" << getIndex(); 340 if (getOffset()) OS << "+" << getOffset(); 341 OS << '>'; 342 break; 343 case MachineOperand::MO_TargetIndex: 344 OS << "<ti#" << getIndex(); 345 if (getOffset()) OS << "+" << getOffset(); 346 OS << '>'; 347 break; 348 case MachineOperand::MO_JumpTableIndex: 349 OS << "<jt#" << getIndex() << '>'; 350 break; 351 case MachineOperand::MO_GlobalAddress: 352 OS << "<ga:"; 353 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 354 if (getOffset()) OS << "+" << getOffset(); 355 OS << '>'; 356 break; 357 case MachineOperand::MO_ExternalSymbol: 358 OS << "<es:" << getSymbolName(); 359 if (getOffset()) OS << "+" << getOffset(); 360 OS << '>'; 361 break; 362 case MachineOperand::MO_BlockAddress: 363 OS << '<'; 364 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 365 OS << '>'; 366 break; 367 case MachineOperand::MO_RegisterMask: 368 OS << "<regmask>"; 369 break; 370 case MachineOperand::MO_Metadata: 371 OS << '<'; 372 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 373 OS << '>'; 374 break; 375 case MachineOperand::MO_MCSymbol: 376 OS << "<MCSym=" << *getMCSymbol() << '>'; 377 break; 378 } 379 380 if (unsigned TF = getTargetFlags()) 381 OS << "[TF=" << TF << ']'; 382} 383 384//===----------------------------------------------------------------------===// 385// MachineMemOperand Implementation 386//===----------------------------------------------------------------------===// 387 388/// getAddrSpace - Return the LLVM IR address space number that this pointer 389/// points into. 390unsigned MachinePointerInfo::getAddrSpace() const { 391 if (V == 0) return 0; 392 return cast<PointerType>(V->getType())->getAddressSpace(); 393} 394 395/// getConstantPool - Return a MachinePointerInfo record that refers to the 396/// constant pool. 397MachinePointerInfo MachinePointerInfo::getConstantPool() { 398 return MachinePointerInfo(PseudoSourceValue::getConstantPool()); 399} 400 401/// getFixedStack - Return a MachinePointerInfo record that refers to the 402/// the specified FrameIndex. 403MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) { 404 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset); 405} 406 407MachinePointerInfo MachinePointerInfo::getJumpTable() { 408 return MachinePointerInfo(PseudoSourceValue::getJumpTable()); 409} 410 411MachinePointerInfo MachinePointerInfo::getGOT() { 412 return MachinePointerInfo(PseudoSourceValue::getGOT()); 413} 414 415MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) { 416 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset); 417} 418 419MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f, 420 uint64_t s, unsigned int a, 421 const MDNode *TBAAInfo, 422 const MDNode *Ranges) 423 : PtrInfo(ptrinfo), Size(s), 424 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)), 425 TBAAInfo(TBAAInfo), Ranges(Ranges) { 426 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) && 427 "invalid pointer value"); 428 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 429 assert((isLoad() || isStore()) && "Not a load/store!"); 430} 431 432/// Profile - Gather unique data for the object. 433/// 434void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 435 ID.AddInteger(getOffset()); 436 ID.AddInteger(Size); 437 ID.AddPointer(getValue()); 438 ID.AddInteger(Flags); 439} 440 441void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 442 // The Value and Offset may differ due to CSE. But the flags and size 443 // should be the same. 444 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 445 assert(MMO->getSize() == getSize() && "Size mismatch!"); 446 447 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 448 // Update the alignment value. 449 Flags = (Flags & ((1 << MOMaxBits) - 1)) | 450 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); 451 // Also update the base and offset, because the new alignment may 452 // not be applicable with the old ones. 453 PtrInfo = MMO->PtrInfo; 454 } 455} 456 457/// getAlignment - Return the minimum known alignment in bytes of the 458/// actual memory reference. 459uint64_t MachineMemOperand::getAlignment() const { 460 return MinAlign(getBaseAlignment(), getOffset()); 461} 462 463raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 464 assert((MMO.isLoad() || MMO.isStore()) && 465 "SV has to be a load, store or both."); 466 467 if (MMO.isVolatile()) 468 OS << "Volatile "; 469 470 if (MMO.isLoad()) 471 OS << "LD"; 472 if (MMO.isStore()) 473 OS << "ST"; 474 OS << MMO.getSize(); 475 476 // Print the address information. 477 OS << "["; 478 if (!MMO.getValue()) 479 OS << "<unknown>"; 480 else 481 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 482 483 // If the alignment of the memory reference itself differs from the alignment 484 // of the base pointer, print the base alignment explicitly, next to the base 485 // pointer. 486 if (MMO.getBaseAlignment() != MMO.getAlignment()) 487 OS << "(align=" << MMO.getBaseAlignment() << ")"; 488 489 if (MMO.getOffset() != 0) 490 OS << "+" << MMO.getOffset(); 491 OS << "]"; 492 493 // Print the alignment of the reference. 494 if (MMO.getBaseAlignment() != MMO.getAlignment() || 495 MMO.getBaseAlignment() != MMO.getSize()) 496 OS << "(align=" << MMO.getAlignment() << ")"; 497 498 // Print TBAA info. 499 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) { 500 OS << "(tbaa="; 501 if (TBAAInfo->getNumOperands() > 0) 502 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false); 503 else 504 OS << "<unknown>"; 505 OS << ")"; 506 } 507 508 // Print nontemporal info. 509 if (MMO.isNonTemporal()) 510 OS << "(nontemporal)"; 511 512 return OS; 513} 514 515//===----------------------------------------------------------------------===// 516// MachineInstr Implementation 517//===----------------------------------------------------------------------===// 518 519/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 520/// MCID NULL and no operands. 521MachineInstr::MachineInstr() 522 : MCID(0), Flags(0), AsmPrinterFlags(0), 523 NumMemRefs(0), MemRefs(0), 524 Parent(0) { 525 // Make sure that we get added to a machine basicblock 526 LeakDetector::addGarbageObject(this); 527} 528 529void MachineInstr::addImplicitDefUseOperands() { 530 if (MCID->ImplicitDefs) 531 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 532 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 533 if (MCID->ImplicitUses) 534 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) 535 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 536} 537 538/// MachineInstr ctor - This constructor creates a MachineInstr and adds the 539/// implicit operands. It reserves space for the number of operands specified by 540/// the MCInstrDesc. 541MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp) 542 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 543 NumMemRefs(0), MemRefs(0), Parent(0) { 544 unsigned NumImplicitOps = 0; 545 if (!NoImp) 546 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 547 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 548 if (!NoImp) 549 addImplicitDefUseOperands(); 550 // Make sure that we get added to a machine basicblock 551 LeakDetector::addGarbageObject(this); 552} 553 554/// MachineInstr ctor - As above, but with a DebugLoc. 555MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl, 556 bool NoImp) 557 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 558 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) { 559 unsigned NumImplicitOps = 0; 560 if (!NoImp) 561 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 562 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 563 if (!NoImp) 564 addImplicitDefUseOperands(); 565 // Make sure that we get added to a machine basicblock 566 LeakDetector::addGarbageObject(this); 567} 568 569/// MachineInstr ctor - Work exactly the same as the ctor two above, except 570/// that the MachineInstr is created and added to the end of the specified 571/// basic block. 572MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid) 573 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 574 NumMemRefs(0), MemRefs(0), Parent(0) { 575 assert(MBB && "Cannot use inserting ctor with null basic block!"); 576 unsigned NumImplicitOps = 577 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 578 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 579 addImplicitDefUseOperands(); 580 // Make sure that we get added to a machine basicblock 581 LeakDetector::addGarbageObject(this); 582 MBB->push_back(this); // Add instruction to end of basic block! 583} 584 585/// MachineInstr ctor - As above, but with a DebugLoc. 586/// 587MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 588 const MCInstrDesc &tid) 589 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 590 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) { 591 assert(MBB && "Cannot use inserting ctor with null basic block!"); 592 unsigned NumImplicitOps = 593 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 594 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 595 addImplicitDefUseOperands(); 596 // Make sure that we get added to a machine basicblock 597 LeakDetector::addGarbageObject(this); 598 MBB->push_back(this); // Add instruction to end of basic block! 599} 600 601/// MachineInstr ctor - Copies MachineInstr arg exactly 602/// 603MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 604 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0), 605 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs), 606 Parent(0), debugLoc(MI.getDebugLoc()) { 607 Operands.reserve(MI.getNumOperands()); 608 609 // Add operands 610 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 611 addOperand(MI.getOperand(i)); 612 613 // Copy all the flags. 614 Flags = MI.Flags; 615 616 // Set parent to null. 617 Parent = 0; 618 619 LeakDetector::addGarbageObject(this); 620} 621 622MachineInstr::~MachineInstr() { 623 LeakDetector::removeGarbageObject(this); 624#ifndef NDEBUG 625 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 626 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 627 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 628 "Reg operand def/use list corrupted"); 629 } 630#endif 631} 632 633/// getRegInfo - If this instruction is embedded into a MachineFunction, 634/// return the MachineRegisterInfo object for the current function, otherwise 635/// return null. 636MachineRegisterInfo *MachineInstr::getRegInfo() { 637 if (MachineBasicBlock *MBB = getParent()) 638 return &MBB->getParent()->getRegInfo(); 639 return 0; 640} 641 642/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 643/// this instruction from their respective use lists. This requires that the 644/// operands already be on their use lists. 645void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { 646 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 647 if (Operands[i].isReg()) 648 MRI.removeRegOperandFromUseList(&Operands[i]); 649} 650 651/// AddRegOperandsToUseLists - Add all of the register operands in 652/// this instruction from their respective use lists. This requires that the 653/// operands not be on their use lists yet. 654void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { 655 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 656 if (Operands[i].isReg()) 657 MRI.addRegOperandToUseList(&Operands[i]); 658} 659 660/// addOperand - Add the specified operand to the instruction. If it is an 661/// implicit operand, it is added to the end of the operand list. If it is 662/// an explicit operand it is added at the end of the explicit operand list 663/// (before the first implicit operand). 664void MachineInstr::addOperand(const MachineOperand &Op) { 665 assert(MCID && "Cannot add operands before providing an instr descriptor"); 666 bool isImpReg = Op.isReg() && Op.isImplicit(); 667 MachineRegisterInfo *RegInfo = getRegInfo(); 668 669 // If the Operands backing store is reallocated, all register operands must 670 // be removed and re-added to RegInfo. It is storing pointers to operands. 671 bool Reallocate = RegInfo && 672 !Operands.empty() && Operands.size() == Operands.capacity(); 673 674 // Find the insert location for the new operand. Implicit registers go at 675 // the end, everything goes before the implicit regs. 676 unsigned OpNo = Operands.size(); 677 678 // Remove all the implicit operands from RegInfo if they need to be shifted. 679 // FIXME: Allow mixed explicit and implicit operands on inline asm. 680 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as 681 // implicit-defs, but they must not be moved around. See the FIXME in 682 // InstrEmitter.cpp. 683 if (!isImpReg && !isInlineAsm()) { 684 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { 685 --OpNo; 686 assert(!Operands[OpNo].isTied() && "Cannot move tied operands"); 687 if (RegInfo) 688 RegInfo->removeRegOperandFromUseList(&Operands[OpNo]); 689 } 690 } 691 692 // OpNo now points as the desired insertion point. Unless this is a variadic 693 // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). 694 // RegMask operands go between the explicit and implicit operands. 695 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || 696 OpNo < MCID->getNumOperands()) && 697 "Trying to add an operand to a machine instr that is already done!"); 698 699 // All operands from OpNo have been removed from RegInfo. If the Operands 700 // backing store needs to be reallocated, we also need to remove any other 701 // register operands. 702 if (Reallocate) 703 for (unsigned i = 0; i != OpNo; ++i) 704 if (Operands[i].isReg()) 705 RegInfo->removeRegOperandFromUseList(&Operands[i]); 706 707 // Insert the new operand at OpNo. 708 Operands.insert(Operands.begin() + OpNo, Op); 709 Operands[OpNo].ParentMI = this; 710 711 // The Operands backing store has now been reallocated, so we can re-add the 712 // operands before OpNo. 713 if (Reallocate) 714 for (unsigned i = 0; i != OpNo; ++i) 715 if (Operands[i].isReg()) 716 RegInfo->addRegOperandToUseList(&Operands[i]); 717 718 // When adding a register operand, tell RegInfo about it. 719 if (Operands[OpNo].isReg()) { 720 // Ensure isOnRegUseList() returns false, regardless of Op's status. 721 Operands[OpNo].Contents.Reg.Prev = 0; 722 // Ignore existing ties. This is not a property that can be copied. 723 Operands[OpNo].TiedTo = 0; 724 // Add the new operand to RegInfo. 725 if (RegInfo) 726 RegInfo->addRegOperandToUseList(&Operands[OpNo]); 727 // The MCID operand information isn't accurate until we start adding 728 // explicit operands. The implicit operands are added first, then the 729 // explicits are inserted before them. 730 if (!isImpReg) { 731 // Tie uses to defs as indicated in MCInstrDesc. 732 if (Operands[OpNo].isUse()) { 733 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); 734 if (DefIdx != -1) 735 tieOperands(DefIdx, OpNo); 736 } 737 // If the register operand is flagged as early, mark the operand as such. 738 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 739 Operands[OpNo].setIsEarlyClobber(true); 740 } 741 } 742 743 // Re-add all the implicit ops. 744 if (RegInfo) { 745 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) { 746 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 747 RegInfo->addRegOperandToUseList(&Operands[i]); 748 } 749 } 750} 751 752/// RemoveOperand - Erase an operand from an instruction, leaving it with one 753/// fewer operand than it started with. 754/// 755void MachineInstr::RemoveOperand(unsigned OpNo) { 756 assert(OpNo < Operands.size() && "Invalid operand number"); 757 untieRegOperand(OpNo); 758 MachineRegisterInfo *RegInfo = getRegInfo(); 759 760 // Special case removing the last one. 761 if (OpNo == Operands.size()-1) { 762 // If needed, remove from the reg def/use list. 763 if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList()) 764 RegInfo->removeRegOperandFromUseList(&Operands.back()); 765 766 Operands.pop_back(); 767 return; 768 } 769 770 // Otherwise, we are removing an interior operand. If we have reginfo to 771 // update, remove all operands that will be shifted down from their reg lists, 772 // move everything down, then re-add them. 773 if (RegInfo) { 774 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 775 if (Operands[i].isReg()) 776 RegInfo->removeRegOperandFromUseList(&Operands[i]); 777 } 778 } 779 780#ifndef NDEBUG 781 // Moving tied operands would break the ties. 782 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) 783 if (Operands[i].isReg()) 784 assert(!Operands[i].isTied() && "Cannot move tied operands"); 785#endif 786 787 Operands.erase(Operands.begin()+OpNo); 788 789 if (RegInfo) { 790 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 791 if (Operands[i].isReg()) 792 RegInfo->addRegOperandToUseList(&Operands[i]); 793 } 794 } 795} 796 797/// addMemOperand - Add a MachineMemOperand to the machine instruction. 798/// This function should be used only occasionally. The setMemRefs function 799/// is the primary method for setting up a MachineInstr's MemRefs list. 800void MachineInstr::addMemOperand(MachineFunction &MF, 801 MachineMemOperand *MO) { 802 mmo_iterator OldMemRefs = MemRefs; 803 uint16_t OldNumMemRefs = NumMemRefs; 804 805 uint16_t NewNum = NumMemRefs + 1; 806 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 807 808 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs); 809 NewMemRefs[NewNum - 1] = MO; 810 811 MemRefs = NewMemRefs; 812 NumMemRefs = NewNum; 813} 814 815bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const { 816 const MachineBasicBlock *MBB = getParent(); 817 MachineBasicBlock::const_instr_iterator MII = *this; ++MII; 818 while (MII != MBB->end() && MII->isInsideBundle()) { 819 if (MII->getDesc().getFlags() & Mask) { 820 if (Type == AnyInBundle) 821 return true; 822 } else { 823 if (Type == AllInBundle) 824 return false; 825 } 826 ++MII; 827 } 828 829 return Type == AllInBundle; 830} 831 832bool MachineInstr::isIdenticalTo(const MachineInstr *Other, 833 MICheckType Check) const { 834 // If opcodes or number of operands are not the same then the two 835 // instructions are obviously not identical. 836 if (Other->getOpcode() != getOpcode() || 837 Other->getNumOperands() != getNumOperands()) 838 return false; 839 840 if (isBundle()) { 841 // Both instructions are bundles, compare MIs inside the bundle. 842 MachineBasicBlock::const_instr_iterator I1 = *this; 843 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end(); 844 MachineBasicBlock::const_instr_iterator I2 = *Other; 845 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end(); 846 while (++I1 != E1 && I1->isInsideBundle()) { 847 ++I2; 848 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check)) 849 return false; 850 } 851 } 852 853 // Check operands to make sure they match. 854 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 855 const MachineOperand &MO = getOperand(i); 856 const MachineOperand &OMO = Other->getOperand(i); 857 if (!MO.isReg()) { 858 if (!MO.isIdenticalTo(OMO)) 859 return false; 860 continue; 861 } 862 863 // Clients may or may not want to ignore defs when testing for equality. 864 // For example, machine CSE pass only cares about finding common 865 // subexpressions, so it's safe to ignore virtual register defs. 866 if (MO.isDef()) { 867 if (Check == IgnoreDefs) 868 continue; 869 else if (Check == IgnoreVRegDefs) { 870 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 871 TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) 872 if (MO.getReg() != OMO.getReg()) 873 return false; 874 } else { 875 if (!MO.isIdenticalTo(OMO)) 876 return false; 877 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) 878 return false; 879 } 880 } else { 881 if (!MO.isIdenticalTo(OMO)) 882 return false; 883 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) 884 return false; 885 } 886 } 887 // If DebugLoc does not match then two dbg.values are not identical. 888 if (isDebugValue()) 889 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown() 890 && getDebugLoc() != Other->getDebugLoc()) 891 return false; 892 return true; 893} 894 895/// removeFromParent - This method unlinks 'this' from the containing basic 896/// block, and returns it, but does not delete it. 897MachineInstr *MachineInstr::removeFromParent() { 898 assert(getParent() && "Not embedded in a basic block!"); 899 900 // If it's a bundle then remove the MIs inside the bundle as well. 901 if (isBundle()) { 902 MachineBasicBlock *MBB = getParent(); 903 MachineBasicBlock::instr_iterator MII = *this; ++MII; 904 MachineBasicBlock::instr_iterator E = MBB->instr_end(); 905 while (MII != E && MII->isInsideBundle()) { 906 MachineInstr *MI = &*MII; 907 ++MII; 908 MBB->remove(MI); 909 } 910 } 911 getParent()->remove(this); 912 return this; 913} 914 915 916/// eraseFromParent - This method unlinks 'this' from the containing basic 917/// block, and deletes it. 918void MachineInstr::eraseFromParent() { 919 assert(getParent() && "Not embedded in a basic block!"); 920 // If it's a bundle then remove the MIs inside the bundle as well. 921 if (isBundle()) { 922 MachineBasicBlock *MBB = getParent(); 923 MachineBasicBlock::instr_iterator MII = *this; ++MII; 924 MachineBasicBlock::instr_iterator E = MBB->instr_end(); 925 while (MII != E && MII->isInsideBundle()) { 926 MachineInstr *MI = &*MII; 927 ++MII; 928 MBB->erase(MI); 929 } 930 } 931 // Erase the individual instruction, which may itself be inside a bundle. 932 getParent()->erase_instr(this); 933} 934 935 936/// getNumExplicitOperands - Returns the number of non-implicit operands. 937/// 938unsigned MachineInstr::getNumExplicitOperands() const { 939 unsigned NumOperands = MCID->getNumOperands(); 940 if (!MCID->isVariadic()) 941 return NumOperands; 942 943 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 944 const MachineOperand &MO = getOperand(i); 945 if (!MO.isReg() || !MO.isImplicit()) 946 NumOperands++; 947 } 948 return NumOperands; 949} 950 951/// isBundled - Return true if this instruction part of a bundle. This is true 952/// if either itself or its following instruction is marked "InsideBundle". 953bool MachineInstr::isBundled() const { 954 if (isInsideBundle()) 955 return true; 956 MachineBasicBlock::const_instr_iterator nextMI = this; 957 ++nextMI; 958 return nextMI != Parent->instr_end() && nextMI->isInsideBundle(); 959} 960 961bool MachineInstr::isStackAligningInlineAsm() const { 962 if (isInlineAsm()) { 963 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 964 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 965 return true; 966 } 967 return false; 968} 969 970int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, 971 unsigned *GroupNo) const { 972 assert(isInlineAsm() && "Expected an inline asm instruction"); 973 assert(OpIdx < getNumOperands() && "OpIdx out of range"); 974 975 // Ignore queries about the initial operands. 976 if (OpIdx < InlineAsm::MIOp_FirstOperand) 977 return -1; 978 979 unsigned Group = 0; 980 unsigned NumOps; 981 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 982 i += NumOps) { 983 const MachineOperand &FlagMO = getOperand(i); 984 // If we reach the implicit register operands, stop looking. 985 if (!FlagMO.isImm()) 986 return -1; 987 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 988 if (i + NumOps > OpIdx) { 989 if (GroupNo) 990 *GroupNo = Group; 991 return i; 992 } 993 ++Group; 994 } 995 return -1; 996} 997 998const TargetRegisterClass* 999MachineInstr::getRegClassConstraint(unsigned OpIdx, 1000 const TargetInstrInfo *TII, 1001 const TargetRegisterInfo *TRI) const { 1002 assert(getParent() && "Can't have an MBB reference here!"); 1003 assert(getParent()->getParent() && "Can't have an MF reference here!"); 1004 const MachineFunction &MF = *getParent()->getParent(); 1005 1006 // Most opcodes have fixed constraints in their MCInstrDesc. 1007 if (!isInlineAsm()) 1008 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); 1009 1010 if (!getOperand(OpIdx).isReg()) 1011 return NULL; 1012 1013 // For tied uses on inline asm, get the constraint from the def. 1014 unsigned DefIdx; 1015 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 1016 OpIdx = DefIdx; 1017 1018 // Inline asm stores register class constraints in the flag word. 1019 int FlagIdx = findInlineAsmFlagIdx(OpIdx); 1020 if (FlagIdx < 0) 1021 return NULL; 1022 1023 unsigned Flag = getOperand(FlagIdx).getImm(); 1024 unsigned RCID; 1025 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) 1026 return TRI->getRegClass(RCID); 1027 1028 // Assume that all registers in a memory operand are pointers. 1029 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem) 1030 return TRI->getPointerRegClass(MF); 1031 1032 return NULL; 1033} 1034 1035/// getBundleSize - Return the number of instructions inside the MI bundle. 1036unsigned MachineInstr::getBundleSize() const { 1037 assert(isBundle() && "Expecting a bundle"); 1038 1039 MachineBasicBlock::const_instr_iterator I = *this; 1040 unsigned Size = 0; 1041 while ((++I)->isInsideBundle()) { 1042 ++Size; 1043 } 1044 assert(Size > 1 && "Malformed bundle"); 1045 1046 return Size; 1047} 1048 1049/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 1050/// the specific register or -1 if it is not found. It further tightens 1051/// the search criteria to a use that kills the register if isKill is true. 1052int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 1053 const TargetRegisterInfo *TRI) const { 1054 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1055 const MachineOperand &MO = getOperand(i); 1056 if (!MO.isReg() || !MO.isUse()) 1057 continue; 1058 unsigned MOReg = MO.getReg(); 1059 if (!MOReg) 1060 continue; 1061 if (MOReg == Reg || 1062 (TRI && 1063 TargetRegisterInfo::isPhysicalRegister(MOReg) && 1064 TargetRegisterInfo::isPhysicalRegister(Reg) && 1065 TRI->isSubRegister(MOReg, Reg))) 1066 if (!isKill || MO.isKill()) 1067 return i; 1068 } 1069 return -1; 1070} 1071 1072/// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 1073/// indicating if this instruction reads or writes Reg. This also considers 1074/// partial defines. 1075std::pair<bool,bool> 1076MachineInstr::readsWritesVirtualRegister(unsigned Reg, 1077 SmallVectorImpl<unsigned> *Ops) const { 1078 bool PartDef = false; // Partial redefine. 1079 bool FullDef = false; // Full define. 1080 bool Use = false; 1081 1082 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1083 const MachineOperand &MO = getOperand(i); 1084 if (!MO.isReg() || MO.getReg() != Reg) 1085 continue; 1086 if (Ops) 1087 Ops->push_back(i); 1088 if (MO.isUse()) 1089 Use |= !MO.isUndef(); 1090 else if (MO.getSubReg() && !MO.isUndef()) 1091 // A partial <def,undef> doesn't count as reading the register. 1092 PartDef = true; 1093 else 1094 FullDef = true; 1095 } 1096 // A partial redefine uses Reg unless there is also a full define. 1097 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); 1098} 1099 1100/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 1101/// the specified register or -1 if it is not found. If isDead is true, defs 1102/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 1103/// also checks if there is a def of a super-register. 1104int 1105MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, 1106 const TargetRegisterInfo *TRI) const { 1107 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg); 1108 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1109 const MachineOperand &MO = getOperand(i); 1110 // Accept regmask operands when Overlap is set. 1111 // Ignore them when looking for a specific def operand (Overlap == false). 1112 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) 1113 return i; 1114 if (!MO.isReg() || !MO.isDef()) 1115 continue; 1116 unsigned MOReg = MO.getReg(); 1117 bool Found = (MOReg == Reg); 1118 if (!Found && TRI && isPhys && 1119 TargetRegisterInfo::isPhysicalRegister(MOReg)) { 1120 if (Overlap) 1121 Found = TRI->regsOverlap(MOReg, Reg); 1122 else 1123 Found = TRI->isSubRegister(MOReg, Reg); 1124 } 1125 if (Found && (!isDead || MO.isDead())) 1126 return i; 1127 } 1128 return -1; 1129} 1130 1131/// findFirstPredOperandIdx() - Find the index of the first operand in the 1132/// operand list that is used to represent the predicate. It returns -1 if 1133/// none is found. 1134int MachineInstr::findFirstPredOperandIdx() const { 1135 // Don't call MCID.findFirstPredOperandIdx() because this variant 1136 // is sometimes called on an instruction that's not yet complete, and 1137 // so the number of operands is less than the MCID indicates. In 1138 // particular, the PTX target does this. 1139 const MCInstrDesc &MCID = getDesc(); 1140 if (MCID.isPredicable()) { 1141 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 1142 if (MCID.OpInfo[i].isPredicate()) 1143 return i; 1144 } 1145 1146 return -1; 1147} 1148 1149// MachineOperand::TiedTo is 4 bits wide. 1150const unsigned TiedMax = 15; 1151 1152/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. 1153/// 1154/// Use and def operands can be tied together, indicated by a non-zero TiedTo 1155/// field. TiedTo can have these values: 1156/// 1157/// 0: Operand is not tied to anything. 1158/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1). 1159/// TiedMax: Tied to an operand >= TiedMax-1. 1160/// 1161/// The tied def must be one of the first TiedMax operands on a normal 1162/// instruction. INLINEASM instructions allow more tied defs. 1163/// 1164void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { 1165 MachineOperand &DefMO = getOperand(DefIdx); 1166 MachineOperand &UseMO = getOperand(UseIdx); 1167 assert(DefMO.isDef() && "DefIdx must be a def operand"); 1168 assert(UseMO.isUse() && "UseIdx must be a use operand"); 1169 assert(!DefMO.isTied() && "Def is already tied to another use"); 1170 assert(!UseMO.isTied() && "Use is already tied to another def"); 1171 1172 if (DefIdx < TiedMax) 1173 UseMO.TiedTo = DefIdx + 1; 1174 else { 1175 // Inline asm can use the group descriptors to find tied operands, but on 1176 // normal instruction, the tied def must be within the first TiedMax 1177 // operands. 1178 assert(isInlineAsm() && "DefIdx out of range"); 1179 UseMO.TiedTo = TiedMax; 1180 } 1181 1182 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx(). 1183 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); 1184} 1185 1186/// Given the index of a tied register operand, find the operand it is tied to. 1187/// Defs are tied to uses and vice versa. Returns the index of the tied operand 1188/// which must exist. 1189unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const { 1190 const MachineOperand &MO = getOperand(OpIdx); 1191 assert(MO.isTied() && "Operand isn't tied"); 1192 1193 // Normally TiedTo is in range. 1194 if (MO.TiedTo < TiedMax) 1195 return MO.TiedTo - 1; 1196 1197 // Uses on normal instructions can be out of range. 1198 if (!isInlineAsm()) { 1199 // Normal tied defs must be in the 0..TiedMax-1 range. 1200 if (MO.isUse()) 1201 return TiedMax - 1; 1202 // MO is a def. Search for the tied use. 1203 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) { 1204 const MachineOperand &UseMO = getOperand(i); 1205 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) 1206 return i; 1207 } 1208 llvm_unreachable("Can't find tied use"); 1209 } 1210 1211 // Now deal with inline asm by parsing the operand group descriptor flags. 1212 // Find the beginning of each operand group. 1213 SmallVector<unsigned, 8> GroupIdx; 1214 unsigned OpIdxGroup = ~0u; 1215 unsigned NumOps; 1216 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 1217 i += NumOps) { 1218 const MachineOperand &FlagMO = getOperand(i); 1219 assert(FlagMO.isImm() && "Invalid tied operand on inline asm"); 1220 unsigned CurGroup = GroupIdx.size(); 1221 GroupIdx.push_back(i); 1222 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 1223 // OpIdx belongs to this operand group. 1224 if (OpIdx > i && OpIdx < i + NumOps) 1225 OpIdxGroup = CurGroup; 1226 unsigned TiedGroup; 1227 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup)) 1228 continue; 1229 // Operands in this group are tied to operands in TiedGroup which must be 1230 // earlier. Find the number of operands between the two groups. 1231 unsigned Delta = i - GroupIdx[TiedGroup]; 1232 1233 // OpIdx is a use tied to TiedGroup. 1234 if (OpIdxGroup == CurGroup) 1235 return OpIdx - Delta; 1236 1237 // OpIdx is a def tied to this use group. 1238 if (OpIdxGroup == TiedGroup) 1239 return OpIdx + Delta; 1240 } 1241 llvm_unreachable("Invalid tied operand on inline asm"); 1242} 1243 1244/// isRegTiedToUseOperand - Given the index of a register def operand, 1245/// check if the register def is tied to a source operand, due to either 1246/// two-address elimination or inline assembly constraints. Returns the 1247/// first tied use operand index by reference is UseOpIdx is not null. 1248bool MachineInstr:: 1249isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const { 1250 if (isInlineAsm()) { 1251 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand); 1252 const MachineOperand &MO = getOperand(DefOpIdx); 1253 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0) 1254 return false; 1255 // Determine the actual operand index that corresponds to this index. 1256 unsigned DefNo = 0; 1257 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo); 1258 if (FlagIdx < 0) 1259 return false; 1260 1261 // Which part of the group is DefOpIdx? 1262 unsigned DefPart = DefOpIdx - (FlagIdx + 1); 1263 1264 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); 1265 i != e; ++i) { 1266 const MachineOperand &FMO = getOperand(i); 1267 if (!FMO.isImm()) 1268 continue; 1269 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse()) 1270 continue; 1271 unsigned Idx; 1272 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 1273 Idx == DefNo) { 1274 if (UseOpIdx) 1275 *UseOpIdx = (unsigned)i + 1 + DefPart; 1276 return true; 1277 } 1278 } 1279 return false; 1280 } 1281 1282 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); 1283 const MCInstrDesc &MCID = getDesc(); 1284 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { 1285 const MachineOperand &MO = getOperand(i); 1286 if (MO.isReg() && MO.isUse() && 1287 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) { 1288 if (UseOpIdx) 1289 *UseOpIdx = (unsigned)i; 1290 return true; 1291 } 1292 } 1293 return false; 1294} 1295 1296/// isRegTiedToDefOperand - Return true if the operand of the specified index 1297/// is a register use and it is tied to an def operand. It also returns the def 1298/// operand index by reference. 1299bool MachineInstr:: 1300isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const { 1301 if (isInlineAsm()) { 1302 const MachineOperand &MO = getOperand(UseOpIdx); 1303 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0) 1304 return false; 1305 1306 // Find the flag operand corresponding to UseOpIdx 1307 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx); 1308 if (FlagIdx < 0) 1309 return false; 1310 1311 const MachineOperand &UFMO = getOperand(FlagIdx); 1312 unsigned DefNo; 1313 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) { 1314 if (!DefOpIdx) 1315 return true; 1316 1317 unsigned DefIdx = InlineAsm::MIOp_FirstOperand; 1318 // Remember to adjust the index. First operand is asm string, second is 1319 // the HasSideEffects and AlignStack bits, then there is a flag for each. 1320 while (DefNo) { 1321 const MachineOperand &FMO = getOperand(DefIdx); 1322 assert(FMO.isImm()); 1323 // Skip over this def. 1324 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1; 1325 --DefNo; 1326 } 1327 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx; 1328 return true; 1329 } 1330 return false; 1331 } 1332 1333 const MCInstrDesc &MCID = getDesc(); 1334 if (UseOpIdx >= MCID.getNumOperands()) 1335 return false; 1336 const MachineOperand &MO = getOperand(UseOpIdx); 1337 if (!MO.isReg() || !MO.isUse()) 1338 return false; 1339 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO); 1340 if (DefIdx == -1) 1341 return false; 1342 if (DefOpIdx) 1343 *DefOpIdx = (unsigned)DefIdx; 1344 return true; 1345} 1346 1347/// clearKillInfo - Clears kill flags on all operands. 1348/// 1349void MachineInstr::clearKillInfo() { 1350 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1351 MachineOperand &MO = getOperand(i); 1352 if (MO.isReg() && MO.isUse()) 1353 MO.setIsKill(false); 1354 } 1355} 1356 1357/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 1358/// 1359void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 1360 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1361 const MachineOperand &MO = MI->getOperand(i); 1362 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 1363 continue; 1364 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 1365 MachineOperand &MOp = getOperand(j); 1366 if (!MOp.isIdenticalTo(MO)) 1367 continue; 1368 if (MO.isKill()) 1369 MOp.setIsKill(); 1370 else 1371 MOp.setIsDead(); 1372 break; 1373 } 1374 } 1375} 1376 1377/// copyPredicates - Copies predicate operand(s) from MI. 1378void MachineInstr::copyPredicates(const MachineInstr *MI) { 1379 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles"); 1380 1381 const MCInstrDesc &MCID = MI->getDesc(); 1382 if (!MCID.isPredicable()) 1383 return; 1384 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1385 if (MCID.OpInfo[i].isPredicate()) { 1386 // Predicated operands must be last operands. 1387 addOperand(MI->getOperand(i)); 1388 } 1389 } 1390} 1391 1392void MachineInstr::substituteRegister(unsigned FromReg, 1393 unsigned ToReg, 1394 unsigned SubIdx, 1395 const TargetRegisterInfo &RegInfo) { 1396 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) { 1397 if (SubIdx) 1398 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1399 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1400 MachineOperand &MO = getOperand(i); 1401 if (!MO.isReg() || MO.getReg() != FromReg) 1402 continue; 1403 MO.substPhysReg(ToReg, RegInfo); 1404 } 1405 } else { 1406 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1407 MachineOperand &MO = getOperand(i); 1408 if (!MO.isReg() || MO.getReg() != FromReg) 1409 continue; 1410 MO.substVirtReg(ToReg, SubIdx, RegInfo); 1411 } 1412 } 1413} 1414 1415/// isSafeToMove - Return true if it is safe to move this instruction. If 1416/// SawStore is set to true, it means that there is a store (or call) between 1417/// the instruction's location and its intended destination. 1418bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 1419 AliasAnalysis *AA, 1420 bool &SawStore) const { 1421 // Ignore stuff that we obviously can't move. 1422 // 1423 // Treat volatile loads as stores. This is not strictly necessary for 1424 // volatiles, but it is required for atomic loads. It is now allowed to move 1425 // a load across an atomic load with Ordering > Monotonic. 1426 if (mayStore() || isCall() || 1427 (mayLoad() && hasOrderedMemoryRef())) { 1428 SawStore = true; 1429 return false; 1430 } 1431 1432 if (isLabel() || isDebugValue() || 1433 isTerminator() || hasUnmodeledSideEffects()) 1434 return false; 1435 1436 // See if this instruction does a load. If so, we have to guarantee that the 1437 // loaded value doesn't change between the load and the its intended 1438 // destination. The check for isInvariantLoad gives the targe the chance to 1439 // classify the load as always returning a constant, e.g. a constant pool 1440 // load. 1441 if (mayLoad() && !isInvariantLoad(AA)) 1442 // Otherwise, this is a real load. If there is a store between the load and 1443 // end of block, we can't move it. 1444 return !SawStore; 1445 1446 return true; 1447} 1448 1449/// isSafeToReMat - Return true if it's safe to rematerialize the specified 1450/// instruction which defined the specified register instead of copying it. 1451bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 1452 AliasAnalysis *AA, 1453 unsigned DstReg) const { 1454 bool SawStore = false; 1455 if (!TII->isTriviallyReMaterializable(this, AA) || 1456 !isSafeToMove(TII, AA, SawStore)) 1457 return false; 1458 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1459 const MachineOperand &MO = getOperand(i); 1460 if (!MO.isReg()) 1461 continue; 1462 // FIXME: For now, do not remat any instruction with register operands. 1463 // Later on, we can loosen the restriction is the register operands have 1464 // not been modified between the def and use. Note, this is different from 1465 // MachineSink because the code is no longer in two-address form (at least 1466 // partially). 1467 if (MO.isUse()) 1468 return false; 1469 else if (!MO.isDead() && MO.getReg() != DstReg) 1470 return false; 1471 } 1472 return true; 1473} 1474 1475/// hasOrderedMemoryRef - Return true if this instruction may have an ordered 1476/// or volatile memory reference, or if the information describing the memory 1477/// reference is not available. Return false if it is known to have no ordered 1478/// memory references. 1479bool MachineInstr::hasOrderedMemoryRef() const { 1480 // An instruction known never to access memory won't have a volatile access. 1481 if (!mayStore() && 1482 !mayLoad() && 1483 !isCall() && 1484 !hasUnmodeledSideEffects()) 1485 return false; 1486 1487 // Otherwise, if the instruction has no memory reference information, 1488 // conservatively assume it wasn't preserved. 1489 if (memoperands_empty()) 1490 return true; 1491 1492 // Check the memory reference information for ordered references. 1493 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1494 if (!(*I)->isUnordered()) 1495 return true; 1496 1497 return false; 1498} 1499 1500/// isInvariantLoad - Return true if this instruction is loading from a 1501/// location whose value is invariant across the function. For example, 1502/// loading a value from the constant pool or from the argument area 1503/// of a function if it does not change. This should only return true of 1504/// *all* loads the instruction does are invariant (if it does multiple loads). 1505bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1506 // If the instruction doesn't load at all, it isn't an invariant load. 1507 if (!mayLoad()) 1508 return false; 1509 1510 // If the instruction has lost its memoperands, conservatively assume that 1511 // it may not be an invariant load. 1512 if (memoperands_empty()) 1513 return false; 1514 1515 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1516 1517 for (mmo_iterator I = memoperands_begin(), 1518 E = memoperands_end(); I != E; ++I) { 1519 if ((*I)->isVolatile()) return false; 1520 if ((*I)->isStore()) return false; 1521 if ((*I)->isInvariant()) return true; 1522 1523 if (const Value *V = (*I)->getValue()) { 1524 // A load from a constant PseudoSourceValue is invariant. 1525 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1526 if (PSV->isConstant(MFI)) 1527 continue; 1528 // If we have an AliasAnalysis, ask it whether the memory is constant. 1529 if (AA && AA->pointsToConstantMemory( 1530 AliasAnalysis::Location(V, (*I)->getSize(), 1531 (*I)->getTBAAInfo()))) 1532 continue; 1533 } 1534 1535 // Otherwise assume conservatively. 1536 return false; 1537 } 1538 1539 // Everything checks out. 1540 return true; 1541} 1542 1543/// isConstantValuePHI - If the specified instruction is a PHI that always 1544/// merges together the same virtual register, return the register, otherwise 1545/// return 0. 1546unsigned MachineInstr::isConstantValuePHI() const { 1547 if (!isPHI()) 1548 return 0; 1549 assert(getNumOperands() >= 3 && 1550 "It's illegal to have a PHI without source operands"); 1551 1552 unsigned Reg = getOperand(1).getReg(); 1553 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1554 if (getOperand(i).getReg() != Reg) 1555 return 0; 1556 return Reg; 1557} 1558 1559bool MachineInstr::hasUnmodeledSideEffects() const { 1560 if (hasProperty(MCID::UnmodeledSideEffects)) 1561 return true; 1562 if (isInlineAsm()) { 1563 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1564 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1565 return true; 1566 } 1567 1568 return false; 1569} 1570 1571/// allDefsAreDead - Return true if all the defs of this instruction are dead. 1572/// 1573bool MachineInstr::allDefsAreDead() const { 1574 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { 1575 const MachineOperand &MO = getOperand(i); 1576 if (!MO.isReg() || MO.isUse()) 1577 continue; 1578 if (!MO.isDead()) 1579 return false; 1580 } 1581 return true; 1582} 1583 1584/// copyImplicitOps - Copy implicit register operands from specified 1585/// instruction to this instruction. 1586void MachineInstr::copyImplicitOps(const MachineInstr *MI) { 1587 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands(); 1588 i != e; ++i) { 1589 const MachineOperand &MO = MI->getOperand(i); 1590 if (MO.isReg() && MO.isImplicit()) 1591 addOperand(MO); 1592 } 1593} 1594 1595void MachineInstr::dump() const { 1596 dbgs() << " " << *this; 1597} 1598 1599static void printDebugLoc(DebugLoc DL, const MachineFunction *MF, 1600 raw_ostream &CommentOS) { 1601 const LLVMContext &Ctx = MF->getFunction()->getContext(); 1602 if (!DL.isUnknown()) { // Print source line info. 1603 DIScope Scope(DL.getScope(Ctx)); 1604 // Omit the directory, because it's likely to be long and uninteresting. 1605 if (Scope.Verify()) 1606 CommentOS << Scope.getFilename(); 1607 else 1608 CommentOS << "<unknown>"; 1609 CommentOS << ':' << DL.getLine(); 1610 if (DL.getCol() != 0) 1611 CommentOS << ':' << DL.getCol(); 1612 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx)); 1613 if (!InlinedAtDL.isUnknown()) { 1614 CommentOS << " @[ "; 1615 printDebugLoc(InlinedAtDL, MF, CommentOS); 1616 CommentOS << " ]"; 1617 } 1618 } 1619} 1620 1621void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1622 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1623 const MachineFunction *MF = 0; 1624 const MachineRegisterInfo *MRI = 0; 1625 if (const MachineBasicBlock *MBB = getParent()) { 1626 MF = MBB->getParent(); 1627 if (!TM && MF) 1628 TM = &MF->getTarget(); 1629 if (MF) 1630 MRI = &MF->getRegInfo(); 1631 } 1632 1633 // Save a list of virtual registers. 1634 SmallVector<unsigned, 8> VirtRegs; 1635 1636 // Print explicitly defined operands on the left of an assignment syntax. 1637 unsigned StartOp = 0, e = getNumOperands(); 1638 for (; StartOp < e && getOperand(StartOp).isReg() && 1639 getOperand(StartOp).isDef() && 1640 !getOperand(StartOp).isImplicit(); 1641 ++StartOp) { 1642 if (StartOp != 0) OS << ", "; 1643 getOperand(StartOp).print(OS, TM); 1644 unsigned Reg = getOperand(StartOp).getReg(); 1645 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1646 VirtRegs.push_back(Reg); 1647 } 1648 1649 if (StartOp != 0) 1650 OS << " = "; 1651 1652 // Print the opcode name. 1653 if (TM && TM->getInstrInfo()) 1654 OS << TM->getInstrInfo()->getName(getOpcode()); 1655 else 1656 OS << "UNKNOWN"; 1657 1658 // Print the rest of the operands. 1659 bool OmittedAnyCallClobbers = false; 1660 bool FirstOp = true; 1661 unsigned AsmDescOp = ~0u; 1662 unsigned AsmOpCount = 0; 1663 1664 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { 1665 // Print asm string. 1666 OS << " "; 1667 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM); 1668 1669 // Print HasSideEffects, IsAlignStack 1670 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1671 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1672 OS << " [sideeffect]"; 1673 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 1674 OS << " [alignstack]"; 1675 1676 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; 1677 FirstOp = false; 1678 } 1679 1680 1681 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1682 const MachineOperand &MO = getOperand(i); 1683 1684 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1685 VirtRegs.push_back(MO.getReg()); 1686 1687 // Omit call-clobbered registers which aren't used anywhere. This makes 1688 // call instructions much less noisy on targets where calls clobber lots 1689 // of registers. Don't rely on MO.isDead() because we may be called before 1690 // LiveVariables is run, or we may be looking at a non-allocatable reg. 1691 if (MF && isCall() && 1692 MO.isReg() && MO.isImplicit() && MO.isDef()) { 1693 unsigned Reg = MO.getReg(); 1694 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 1695 const MachineRegisterInfo &MRI = MF->getRegInfo(); 1696 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1697 bool HasAliasLive = false; 1698 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true); 1699 AI.isValid(); ++AI) { 1700 unsigned AliasReg = *AI; 1701 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1702 HasAliasLive = true; 1703 break; 1704 } 1705 } 1706 if (!HasAliasLive) { 1707 OmittedAnyCallClobbers = true; 1708 continue; 1709 } 1710 } 1711 } 1712 } 1713 1714 if (FirstOp) FirstOp = false; else OS << ","; 1715 OS << " "; 1716 if (i < getDesc().NumOperands) { 1717 const MCOperandInfo &MCOI = getDesc().OpInfo[i]; 1718 if (MCOI.isPredicate()) 1719 OS << "pred:"; 1720 if (MCOI.isOptionalDef()) 1721 OS << "opt:"; 1722 } 1723 if (isDebugValue() && MO.isMetadata()) { 1724 // Pretty print DBG_VALUE instructions. 1725 const MDNode *MD = MO.getMetadata(); 1726 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2))) 1727 OS << "!\"" << MDS->getString() << '\"'; 1728 else 1729 MO.print(OS, TM); 1730 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { 1731 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm()); 1732 } else if (i == AsmDescOp && MO.isImm()) { 1733 // Pretty print the inline asm operand descriptor. 1734 OS << '$' << AsmOpCount++; 1735 unsigned Flag = MO.getImm(); 1736 switch (InlineAsm::getKind(Flag)) { 1737 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break; 1738 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break; 1739 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; 1740 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break; 1741 case InlineAsm::Kind_Imm: OS << ":[imm"; break; 1742 case InlineAsm::Kind_Mem: OS << ":[mem"; break; 1743 default: OS << ":[??" << InlineAsm::getKind(Flag); break; 1744 } 1745 1746 unsigned RCID = 0; 1747 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { 1748 if (TM) 1749 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName(); 1750 else 1751 OS << ":RC" << RCID; 1752 } 1753 1754 unsigned TiedTo = 0; 1755 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) 1756 OS << " tiedto:$" << TiedTo; 1757 1758 OS << ']'; 1759 1760 // Compute the index of the next operand descriptor. 1761 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); 1762 } else 1763 MO.print(OS, TM); 1764 } 1765 1766 // Briefly indicate whether any call clobbers were omitted. 1767 if (OmittedAnyCallClobbers) { 1768 if (!FirstOp) OS << ","; 1769 OS << " ..."; 1770 } 1771 1772 bool HaveSemi = false; 1773 if (Flags) { 1774 if (!HaveSemi) OS << ";"; HaveSemi = true; 1775 OS << " flags: "; 1776 1777 if (Flags & FrameSetup) 1778 OS << "FrameSetup"; 1779 } 1780 1781 if (!memoperands_empty()) { 1782 if (!HaveSemi) OS << ";"; HaveSemi = true; 1783 1784 OS << " mem:"; 1785 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1786 i != e; ++i) { 1787 OS << **i; 1788 if (llvm::next(i) != e) 1789 OS << " "; 1790 } 1791 } 1792 1793 // Print the regclass of any virtual registers encountered. 1794 if (MRI && !VirtRegs.empty()) { 1795 if (!HaveSemi) OS << ";"; HaveSemi = true; 1796 for (unsigned i = 0; i != VirtRegs.size(); ++i) { 1797 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]); 1798 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]); 1799 for (unsigned j = i+1; j != VirtRegs.size();) { 1800 if (MRI->getRegClass(VirtRegs[j]) != RC) { 1801 ++j; 1802 continue; 1803 } 1804 if (VirtRegs[i] != VirtRegs[j]) 1805 OS << "," << PrintReg(VirtRegs[j]); 1806 VirtRegs.erase(VirtRegs.begin()+j); 1807 } 1808 } 1809 } 1810 1811 // Print debug location information. 1812 if (isDebugValue() && getOperand(e - 1).isMetadata()) { 1813 if (!HaveSemi) OS << ";"; HaveSemi = true; 1814 DIVariable DV(getOperand(e - 1).getMetadata()); 1815 OS << " line no:" << DV.getLineNumber(); 1816 if (MDNode *InlinedAt = DV.getInlinedAt()) { 1817 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt); 1818 if (!InlinedAtDL.isUnknown()) { 1819 OS << " inlined @[ "; 1820 printDebugLoc(InlinedAtDL, MF, OS); 1821 OS << " ]"; 1822 } 1823 } 1824 } else if (!debugLoc.isUnknown() && MF) { 1825 if (!HaveSemi) OS << ";"; HaveSemi = true; 1826 OS << " dbg:"; 1827 printDebugLoc(debugLoc, MF, OS); 1828 } 1829 1830 OS << '\n'; 1831} 1832 1833bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1834 const TargetRegisterInfo *RegInfo, 1835 bool AddIfNotFound) { 1836 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1837 bool hasAliases = isPhysReg && 1838 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1839 bool Found = false; 1840 SmallVector<unsigned,4> DeadOps; 1841 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1842 MachineOperand &MO = getOperand(i); 1843 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1844 continue; 1845 unsigned Reg = MO.getReg(); 1846 if (!Reg) 1847 continue; 1848 1849 if (Reg == IncomingReg) { 1850 if (!Found) { 1851 if (MO.isKill()) 1852 // The register is already marked kill. 1853 return true; 1854 if (isPhysReg && isRegTiedToDefOperand(i)) 1855 // Two-address uses of physregs must not be marked kill. 1856 return true; 1857 MO.setIsKill(); 1858 Found = true; 1859 } 1860 } else if (hasAliases && MO.isKill() && 1861 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1862 // A super-register kill already exists. 1863 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1864 return true; 1865 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1866 DeadOps.push_back(i); 1867 } 1868 } 1869 1870 // Trim unneeded kill operands. 1871 while (!DeadOps.empty()) { 1872 unsigned OpIdx = DeadOps.back(); 1873 if (getOperand(OpIdx).isImplicit()) 1874 RemoveOperand(OpIdx); 1875 else 1876 getOperand(OpIdx).setIsKill(false); 1877 DeadOps.pop_back(); 1878 } 1879 1880 // If not found, this means an alias of one of the operands is killed. Add a 1881 // new implicit operand if required. 1882 if (!Found && AddIfNotFound) { 1883 addOperand(MachineOperand::CreateReg(IncomingReg, 1884 false /*IsDef*/, 1885 true /*IsImp*/, 1886 true /*IsKill*/)); 1887 return true; 1888 } 1889 return Found; 1890} 1891 1892void MachineInstr::clearRegisterKills(unsigned Reg, 1893 const TargetRegisterInfo *RegInfo) { 1894 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) 1895 RegInfo = 0; 1896 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1897 MachineOperand &MO = getOperand(i); 1898 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) 1899 continue; 1900 unsigned OpReg = MO.getReg(); 1901 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg))) 1902 MO.setIsKill(false); 1903 } 1904} 1905 1906bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1907 const TargetRegisterInfo *RegInfo, 1908 bool AddIfNotFound) { 1909 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1910 bool hasAliases = isPhysReg && 1911 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1912 bool Found = false; 1913 SmallVector<unsigned,4> DeadOps; 1914 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1915 MachineOperand &MO = getOperand(i); 1916 if (!MO.isReg() || !MO.isDef()) 1917 continue; 1918 unsigned Reg = MO.getReg(); 1919 if (!Reg) 1920 continue; 1921 1922 if (Reg == IncomingReg) { 1923 MO.setIsDead(); 1924 Found = true; 1925 } else if (hasAliases && MO.isDead() && 1926 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1927 // There exists a super-register that's marked dead. 1928 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1929 return true; 1930 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1931 DeadOps.push_back(i); 1932 } 1933 } 1934 1935 // Trim unneeded dead operands. 1936 while (!DeadOps.empty()) { 1937 unsigned OpIdx = DeadOps.back(); 1938 if (getOperand(OpIdx).isImplicit()) 1939 RemoveOperand(OpIdx); 1940 else 1941 getOperand(OpIdx).setIsDead(false); 1942 DeadOps.pop_back(); 1943 } 1944 1945 // If not found, this means an alias of one of the operands is dead. Add a 1946 // new implicit operand if required. 1947 if (Found || !AddIfNotFound) 1948 return Found; 1949 1950 addOperand(MachineOperand::CreateReg(IncomingReg, 1951 true /*IsDef*/, 1952 true /*IsImp*/, 1953 false /*IsKill*/, 1954 true /*IsDead*/)); 1955 return true; 1956} 1957 1958void MachineInstr::addRegisterDefined(unsigned IncomingReg, 1959 const TargetRegisterInfo *RegInfo) { 1960 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { 1961 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1962 if (MO) 1963 return; 1964 } else { 1965 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1966 const MachineOperand &MO = getOperand(i); 1967 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() && 1968 MO.getSubReg() == 0) 1969 return; 1970 } 1971 } 1972 addOperand(MachineOperand::CreateReg(IncomingReg, 1973 true /*IsDef*/, 1974 true /*IsImp*/)); 1975} 1976 1977void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, 1978 const TargetRegisterInfo &TRI) { 1979 bool HasRegMask = false; 1980 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1981 MachineOperand &MO = getOperand(i); 1982 if (MO.isRegMask()) { 1983 HasRegMask = true; 1984 continue; 1985 } 1986 if (!MO.isReg() || !MO.isDef()) continue; 1987 unsigned Reg = MO.getReg(); 1988 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 1989 bool Dead = true; 1990 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 1991 I != E; ++I) 1992 if (TRI.regsOverlap(*I, Reg)) { 1993 Dead = false; 1994 break; 1995 } 1996 // If there are no uses, including partial uses, the def is dead. 1997 if (Dead) MO.setIsDead(); 1998 } 1999 2000 // This is a call with a register mask operand. 2001 // Mask clobbers are always dead, so add defs for the non-dead defines. 2002 if (HasRegMask) 2003 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 2004 I != E; ++I) 2005 addRegisterDefined(*I, &TRI); 2006} 2007 2008unsigned 2009MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { 2010 // Build up a buffer of hash code components. 2011 SmallVector<size_t, 8> HashComponents; 2012 HashComponents.reserve(MI->getNumOperands() + 1); 2013 HashComponents.push_back(MI->getOpcode()); 2014 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2015 const MachineOperand &MO = MI->getOperand(i); 2016 if (MO.isReg() && MO.isDef() && 2017 TargetRegisterInfo::isVirtualRegister(MO.getReg())) 2018 continue; // Skip virtual register defs. 2019 2020 HashComponents.push_back(hash_value(MO)); 2021 } 2022 return hash_combine_range(HashComponents.begin(), HashComponents.end()); 2023} 2024 2025void MachineInstr::emitError(StringRef Msg) const { 2026 // Find the source location cookie. 2027 unsigned LocCookie = 0; 2028 const MDNode *LocMD = 0; 2029 for (unsigned i = getNumOperands(); i != 0; --i) { 2030 if (getOperand(i-1).isMetadata() && 2031 (LocMD = getOperand(i-1).getMetadata()) && 2032 LocMD->getNumOperands() != 0) { 2033 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) { 2034 LocCookie = CI->getZExtValue(); 2035 break; 2036 } 2037 } 2038 } 2039 2040 if (const MachineBasicBlock *MBB = getParent()) 2041 if (const MachineFunction *MF = MBB->getParent()) 2042 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); 2043 report_fatal_error(Msg); 2044} 2045