MachineInstr.cpp revision bcf28c08b3f0a3c4aa1be8f1485f6452d9a2b690
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Constants.h" 15#include "llvm/CodeGen/MachineInstr.h" 16#include "llvm/Value.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineRegisterInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetMachine.h" 21#include "llvm/Target/TargetInstrInfo.h" 22#include "llvm/Target/TargetInstrDesc.h" 23#include "llvm/Target/TargetRegisterInfo.h" 24#include "llvm/Support/LeakDetector.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/Streams.h" 27#include "llvm/Support/raw_ostream.h" 28#include "llvm/ADT/FoldingSet.h" 29#include <ostream> 30using namespace llvm; 31 32//===----------------------------------------------------------------------===// 33// MachineOperand Implementation 34//===----------------------------------------------------------------------===// 35 36/// AddRegOperandToRegInfo - Add this register operand to the specified 37/// MachineRegisterInfo. If it is null, then the next/prev fields should be 38/// explicitly nulled out. 39void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 40 assert(isReg() && "Can only add reg operand to use lists"); 41 42 // If the reginfo pointer is null, just explicitly null out or next/prev 43 // pointers, to ensure they are not garbage. 44 if (RegInfo == 0) { 45 Contents.Reg.Prev = 0; 46 Contents.Reg.Next = 0; 47 return; 48 } 49 50 // Otherwise, add this operand to the head of the registers use/def list. 51 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 52 53 // For SSA values, we prefer to keep the definition at the start of the list. 54 // we do this by skipping over the definition if it is at the head of the 55 // list. 56 if (*Head && (*Head)->isDef()) 57 Head = &(*Head)->Contents.Reg.Next; 58 59 Contents.Reg.Next = *Head; 60 if (Contents.Reg.Next) { 61 assert(getReg() == Contents.Reg.Next->getReg() && 62 "Different regs on the same list!"); 63 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 64 } 65 66 Contents.Reg.Prev = Head; 67 *Head = this; 68} 69 70void MachineOperand::setReg(unsigned Reg) { 71 if (getReg() == Reg) return; // No change. 72 73 // Otherwise, we have to change the register. If this operand is embedded 74 // into a machine function, we need to update the old and new register's 75 // use/def lists. 76 if (MachineInstr *MI = getParent()) 77 if (MachineBasicBlock *MBB = MI->getParent()) 78 if (MachineFunction *MF = MBB->getParent()) { 79 RemoveRegOperandFromRegInfo(); 80 Contents.Reg.RegNo = Reg; 81 AddRegOperandToRegInfo(&MF->getRegInfo()); 82 return; 83 } 84 85 // Otherwise, just change the register, no problem. :) 86 Contents.Reg.RegNo = Reg; 87} 88 89/// ChangeToImmediate - Replace this operand with a new immediate operand of 90/// the specified value. If an operand is known to be an immediate already, 91/// the setImm method should be used. 92void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 93 // If this operand is currently a register operand, and if this is in a 94 // function, deregister the operand from the register's use/def list. 95 if (isReg() && getParent() && getParent()->getParent() && 96 getParent()->getParent()->getParent()) 97 RemoveRegOperandFromRegInfo(); 98 99 OpKind = MO_Immediate; 100 Contents.ImmVal = ImmVal; 101} 102 103/// ChangeToRegister - Replace this operand with a new register operand of 104/// the specified value. If an operand is known to be an register already, 105/// the setReg method should be used. 106void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 107 bool isKill, bool isDead) { 108 // If this operand is already a register operand, use setReg to update the 109 // register's use/def lists. 110 if (isReg()) { 111 assert(!isEarlyClobber()); 112 setReg(Reg); 113 } else { 114 // Otherwise, change this to a register and set the reg#. 115 OpKind = MO_Register; 116 Contents.Reg.RegNo = Reg; 117 118 // If this operand is embedded in a function, add the operand to the 119 // register's use/def list. 120 if (MachineInstr *MI = getParent()) 121 if (MachineBasicBlock *MBB = MI->getParent()) 122 if (MachineFunction *MF = MBB->getParent()) 123 AddRegOperandToRegInfo(&MF->getRegInfo()); 124 } 125 126 IsDef = isDef; 127 IsImp = isImp; 128 IsKill = isKill; 129 IsDead = isDead; 130 IsEarlyClobber = false; 131 SubReg = 0; 132} 133 134/// isIdenticalTo - Return true if this operand is identical to the specified 135/// operand. 136bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 137 if (getType() != Other.getType()) return false; 138 139 switch (getType()) { 140 default: assert(0 && "Unrecognized operand type"); 141 case MachineOperand::MO_Register: 142 return getReg() == Other.getReg() && isDef() == Other.isDef() && 143 getSubReg() == Other.getSubReg(); 144 case MachineOperand::MO_Immediate: 145 return getImm() == Other.getImm(); 146 case MachineOperand::MO_FPImmediate: 147 return getFPImm() == Other.getFPImm(); 148 case MachineOperand::MO_MachineBasicBlock: 149 return getMBB() == Other.getMBB(); 150 case MachineOperand::MO_FrameIndex: 151 return getIndex() == Other.getIndex(); 152 case MachineOperand::MO_ConstantPoolIndex: 153 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 154 case MachineOperand::MO_JumpTableIndex: 155 return getIndex() == Other.getIndex(); 156 case MachineOperand::MO_GlobalAddress: 157 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 158 case MachineOperand::MO_ExternalSymbol: 159 return !strcmp(getSymbolName(), Other.getSymbolName()) && 160 getOffset() == Other.getOffset(); 161 } 162} 163 164/// print - Print the specified machine operand. 165/// 166void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { 167 raw_os_ostream RawOS(OS); 168 print(RawOS, TM); 169} 170 171void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 172 switch (getType()) { 173 case MachineOperand::MO_Register: 174 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { 175 OS << "%reg" << getReg(); 176 } else { 177 // If the instruction is embedded into a basic block, we can find the 178 // target info for the instruction. 179 if (TM == 0) 180 if (const MachineInstr *MI = getParent()) 181 if (const MachineBasicBlock *MBB = MI->getParent()) 182 if (const MachineFunction *MF = MBB->getParent()) 183 TM = &MF->getTarget(); 184 185 if (TM) 186 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name; 187 else 188 OS << "%mreg" << getReg(); 189 } 190 191 if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) { 192 OS << "<"; 193 bool NeedComma = false; 194 if (isImplicit()) { 195 if (NeedComma) OS << ","; 196 OS << (isDef() ? "imp-def" : "imp-use"); 197 NeedComma = true; 198 } else if (isDef()) { 199 if (NeedComma) OS << ","; 200 if (isEarlyClobber()) 201 OS << "earlyclobber,"; 202 OS << "def"; 203 NeedComma = true; 204 } 205 if (isKill() || isDead()) { 206 if (NeedComma) OS << ","; 207 if (isKill()) OS << "kill"; 208 if (isDead()) OS << "dead"; 209 } 210 OS << ">"; 211 } 212 break; 213 case MachineOperand::MO_Immediate: 214 OS << getImm(); 215 break; 216 case MachineOperand::MO_FPImmediate: 217 if (getFPImm()->getType() == Type::FloatTy) { 218 OS << getFPImm()->getValueAPF().convertToFloat(); 219 } else { 220 OS << getFPImm()->getValueAPF().convertToDouble(); 221 } 222 break; 223 case MachineOperand::MO_MachineBasicBlock: 224 OS << "mbb<" 225 << ((Value*)getMBB()->getBasicBlock())->getName() 226 << "," << (void*)getMBB() << ">"; 227 break; 228 case MachineOperand::MO_FrameIndex: 229 OS << "<fi#" << getIndex() << ">"; 230 break; 231 case MachineOperand::MO_ConstantPoolIndex: 232 OS << "<cp#" << getIndex(); 233 if (getOffset()) OS << "+" << getOffset(); 234 OS << ">"; 235 break; 236 case MachineOperand::MO_JumpTableIndex: 237 OS << "<jt#" << getIndex() << ">"; 238 break; 239 case MachineOperand::MO_GlobalAddress: 240 OS << "<ga:" << ((Value*)getGlobal())->getName(); 241 if (getOffset()) OS << "+" << getOffset(); 242 OS << ">"; 243 break; 244 case MachineOperand::MO_ExternalSymbol: 245 OS << "<es:" << getSymbolName(); 246 if (getOffset()) OS << "+" << getOffset(); 247 OS << ">"; 248 break; 249 default: 250 assert(0 && "Unrecognized operand type"); 251 } 252} 253 254//===----------------------------------------------------------------------===// 255// MachineMemOperand Implementation 256//===----------------------------------------------------------------------===// 257 258MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f, 259 int64_t o, uint64_t s, unsigned int a) 260 : Offset(o), Size(s), V(v), 261 Flags((f & 7) | ((Log2_32(a) + 1) << 3)) { 262 assert(isPowerOf2_32(a) && "Alignment is not a power of 2!"); 263 assert((isLoad() || isStore()) && "Not a load/store!"); 264} 265 266/// Profile - Gather unique data for the object. 267/// 268void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 269 ID.AddInteger(Offset); 270 ID.AddInteger(Size); 271 ID.AddPointer(V); 272 ID.AddInteger(Flags); 273} 274 275//===----------------------------------------------------------------------===// 276// MachineInstr Implementation 277//===----------------------------------------------------------------------===// 278 279/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 280/// TID NULL and no operands. 281MachineInstr::MachineInstr() 282 : TID(0), NumImplicitOps(0), Parent(0) { 283 // Make sure that we get added to a machine basicblock 284 LeakDetector::addGarbageObject(this); 285} 286 287void MachineInstr::addImplicitDefUseOperands() { 288 if (TID->ImplicitDefs) 289 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) 290 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 291 if (TID->ImplicitUses) 292 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) 293 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 294} 295 296/// MachineInstr ctor - This constructor create a MachineInstr and add the 297/// implicit operands. It reserves space for number of operands specified by 298/// TargetInstrDesc or the numOperands if it is not zero. (for 299/// instructions with variable number of operands). 300MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) 301 : TID(&tid), NumImplicitOps(0), Parent(0) { 302 if (!NoImp && TID->getImplicitDefs()) 303 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 304 NumImplicitOps++; 305 if (!NoImp && TID->getImplicitUses()) 306 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 307 NumImplicitOps++; 308 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 309 if (!NoImp) 310 addImplicitDefUseOperands(); 311 // Make sure that we get added to a machine basicblock 312 LeakDetector::addGarbageObject(this); 313} 314 315/// MachineInstr ctor - Work exactly the same as the ctor above, except that the 316/// MachineInstr is created and added to the end of the specified basic block. 317/// 318MachineInstr::MachineInstr(MachineBasicBlock *MBB, 319 const TargetInstrDesc &tid) 320 : TID(&tid), NumImplicitOps(0), Parent(0) { 321 assert(MBB && "Cannot use inserting ctor with null basic block!"); 322 if (TID->ImplicitDefs) 323 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 324 NumImplicitOps++; 325 if (TID->ImplicitUses) 326 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 327 NumImplicitOps++; 328 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 329 addImplicitDefUseOperands(); 330 // Make sure that we get added to a machine basicblock 331 LeakDetector::addGarbageObject(this); 332 MBB->push_back(this); // Add instruction to end of basic block! 333} 334 335/// MachineInstr ctor - Copies MachineInstr arg exactly 336/// 337MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 338 : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0) { 339 Operands.reserve(MI.getNumOperands()); 340 341 // Add operands 342 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 343 addOperand(MI.getOperand(i)); 344 NumImplicitOps = MI.NumImplicitOps; 345 346 // Add memory operands. 347 for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(), 348 j = MI.memoperands_end(); i != j; ++i) 349 addMemOperand(MF, *i); 350 351 // Set parent to null. 352 Parent = 0; 353 354 LeakDetector::addGarbageObject(this); 355} 356 357MachineInstr::~MachineInstr() { 358 LeakDetector::removeGarbageObject(this); 359 assert(MemOperands.empty() && 360 "MachineInstr being deleted with live memoperands!"); 361#ifndef NDEBUG 362 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 363 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 364 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 365 "Reg operand def/use list corrupted"); 366 } 367#endif 368} 369 370/// getRegInfo - If this instruction is embedded into a MachineFunction, 371/// return the MachineRegisterInfo object for the current function, otherwise 372/// return null. 373MachineRegisterInfo *MachineInstr::getRegInfo() { 374 if (MachineBasicBlock *MBB = getParent()) 375 return &MBB->getParent()->getRegInfo(); 376 return 0; 377} 378 379/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 380/// this instruction from their respective use lists. This requires that the 381/// operands already be on their use lists. 382void MachineInstr::RemoveRegOperandsFromUseLists() { 383 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 384 if (Operands[i].isReg()) 385 Operands[i].RemoveRegOperandFromRegInfo(); 386 } 387} 388 389/// AddRegOperandsToUseLists - Add all of the register operands in 390/// this instruction from their respective use lists. This requires that the 391/// operands not be on their use lists yet. 392void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 393 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 394 if (Operands[i].isReg()) 395 Operands[i].AddRegOperandToRegInfo(&RegInfo); 396 } 397} 398 399 400/// addOperand - Add the specified operand to the instruction. If it is an 401/// implicit operand, it is added to the end of the operand list. If it is 402/// an explicit operand it is added at the end of the explicit operand list 403/// (before the first implicit operand). 404void MachineInstr::addOperand(const MachineOperand &Op) { 405 bool isImpReg = Op.isReg() && Op.isImplicit(); 406 assert((isImpReg || !OperandsComplete()) && 407 "Trying to add an operand to a machine instr that is already done!"); 408 409 MachineRegisterInfo *RegInfo = getRegInfo(); 410 411 // If we are adding the operand to the end of the list, our job is simpler. 412 // This is true most of the time, so this is a reasonable optimization. 413 if (isImpReg || NumImplicitOps == 0) { 414 // We can only do this optimization if we know that the operand list won't 415 // reallocate. 416 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { 417 Operands.push_back(Op); 418 419 // Set the parent of the operand. 420 Operands.back().ParentMI = this; 421 422 // If the operand is a register, update the operand's use list. 423 if (Op.isReg()) 424 Operands.back().AddRegOperandToRegInfo(RegInfo); 425 return; 426 } 427 } 428 429 // Otherwise, we have to insert a real operand before any implicit ones. 430 unsigned OpNo = Operands.size()-NumImplicitOps; 431 432 // If this instruction isn't embedded into a function, then we don't need to 433 // update any operand lists. 434 if (RegInfo == 0) { 435 // Simple insertion, no reginfo update needed for other register operands. 436 Operands.insert(Operands.begin()+OpNo, Op); 437 Operands[OpNo].ParentMI = this; 438 439 // Do explicitly set the reginfo for this operand though, to ensure the 440 // next/prev fields are properly nulled out. 441 if (Operands[OpNo].isReg()) 442 Operands[OpNo].AddRegOperandToRegInfo(0); 443 444 } else if (Operands.size()+1 <= Operands.capacity()) { 445 // Otherwise, we have to remove register operands from their register use 446 // list, add the operand, then add the register operands back to their use 447 // list. This also must handle the case when the operand list reallocates 448 // to somewhere else. 449 450 // If insertion of this operand won't cause reallocation of the operand 451 // list, just remove the implicit operands, add the operand, then re-add all 452 // the rest of the operands. 453 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 454 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 455 Operands[i].RemoveRegOperandFromRegInfo(); 456 } 457 458 // Add the operand. If it is a register, add it to the reg list. 459 Operands.insert(Operands.begin()+OpNo, Op); 460 Operands[OpNo].ParentMI = this; 461 462 if (Operands[OpNo].isReg()) 463 Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 464 465 // Re-add all the implicit ops. 466 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { 467 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 468 Operands[i].AddRegOperandToRegInfo(RegInfo); 469 } 470 } else { 471 // Otherwise, we will be reallocating the operand list. Remove all reg 472 // operands from their list, then readd them after the operand list is 473 // reallocated. 474 RemoveRegOperandsFromUseLists(); 475 476 Operands.insert(Operands.begin()+OpNo, Op); 477 Operands[OpNo].ParentMI = this; 478 479 // Re-add all the operands. 480 AddRegOperandsToUseLists(*RegInfo); 481 } 482} 483 484/// RemoveOperand - Erase an operand from an instruction, leaving it with one 485/// fewer operand than it started with. 486/// 487void MachineInstr::RemoveOperand(unsigned OpNo) { 488 assert(OpNo < Operands.size() && "Invalid operand number"); 489 490 // Special case removing the last one. 491 if (OpNo == Operands.size()-1) { 492 // If needed, remove from the reg def/use list. 493 if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 494 Operands.back().RemoveRegOperandFromRegInfo(); 495 496 Operands.pop_back(); 497 return; 498 } 499 500 // Otherwise, we are removing an interior operand. If we have reginfo to 501 // update, remove all operands that will be shifted down from their reg lists, 502 // move everything down, then re-add them. 503 MachineRegisterInfo *RegInfo = getRegInfo(); 504 if (RegInfo) { 505 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 506 if (Operands[i].isReg()) 507 Operands[i].RemoveRegOperandFromRegInfo(); 508 } 509 } 510 511 Operands.erase(Operands.begin()+OpNo); 512 513 if (RegInfo) { 514 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 515 if (Operands[i].isReg()) 516 Operands[i].AddRegOperandToRegInfo(RegInfo); 517 } 518 } 519} 520 521/// addMemOperand - Add a MachineMemOperand to the machine instruction, 522/// referencing arbitrary storage. 523void MachineInstr::addMemOperand(MachineFunction &MF, 524 const MachineMemOperand &MO) { 525 MemOperands.push_back(MO); 526} 527 528/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands. 529void MachineInstr::clearMemOperands(MachineFunction &MF) { 530 MemOperands.clear(); 531} 532 533 534/// removeFromParent - This method unlinks 'this' from the containing basic 535/// block, and returns it, but does not delete it. 536MachineInstr *MachineInstr::removeFromParent() { 537 assert(getParent() && "Not embedded in a basic block!"); 538 getParent()->remove(this); 539 return this; 540} 541 542 543/// eraseFromParent - This method unlinks 'this' from the containing basic 544/// block, and deletes it. 545void MachineInstr::eraseFromParent() { 546 assert(getParent() && "Not embedded in a basic block!"); 547 getParent()->erase(this); 548} 549 550 551/// OperandComplete - Return true if it's illegal to add a new operand 552/// 553bool MachineInstr::OperandsComplete() const { 554 unsigned short NumOperands = TID->getNumOperands(); 555 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) 556 return true; // Broken: we have all the operands of this instruction! 557 return false; 558} 559 560/// getNumExplicitOperands - Returns the number of non-implicit operands. 561/// 562unsigned MachineInstr::getNumExplicitOperands() const { 563 unsigned NumOperands = TID->getNumOperands(); 564 if (!TID->isVariadic()) 565 return NumOperands; 566 567 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) { 568 const MachineOperand &MO = getOperand(NumOperands); 569 if (!MO.isReg() || !MO.isImplicit()) 570 NumOperands++; 571 } 572 return NumOperands; 573} 574 575 576/// isLabel - Returns true if the MachineInstr represents a label. 577/// 578bool MachineInstr::isLabel() const { 579 return getOpcode() == TargetInstrInfo::DBG_LABEL || 580 getOpcode() == TargetInstrInfo::EH_LABEL || 581 getOpcode() == TargetInstrInfo::GC_LABEL; 582} 583 584/// isDebugLabel - Returns true if the MachineInstr represents a debug label. 585/// 586bool MachineInstr::isDebugLabel() const { 587 return getOpcode() == TargetInstrInfo::DBG_LABEL; 588} 589 590/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 591/// the specific register or -1 if it is not found. It further tightening 592/// the search criteria to a use that kills the register if isKill is true. 593int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 594 const TargetRegisterInfo *TRI) const { 595 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 596 const MachineOperand &MO = getOperand(i); 597 if (!MO.isReg() || !MO.isUse()) 598 continue; 599 unsigned MOReg = MO.getReg(); 600 if (!MOReg) 601 continue; 602 if (MOReg == Reg || 603 (TRI && 604 TargetRegisterInfo::isPhysicalRegister(MOReg) && 605 TargetRegisterInfo::isPhysicalRegister(Reg) && 606 TRI->isSubRegister(MOReg, Reg))) 607 if (!isKill || MO.isKill()) 608 return i; 609 } 610 return -1; 611} 612 613/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 614/// the specified register or -1 if it is not found. If isDead is true, defs 615/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 616/// also checks if there is a def of a super-register. 617int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, 618 const TargetRegisterInfo *TRI) const { 619 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 620 const MachineOperand &MO = getOperand(i); 621 if (!MO.isReg() || !MO.isDef()) 622 continue; 623 unsigned MOReg = MO.getReg(); 624 if (MOReg == Reg || 625 (TRI && 626 TargetRegisterInfo::isPhysicalRegister(MOReg) && 627 TargetRegisterInfo::isPhysicalRegister(Reg) && 628 TRI->isSubRegister(MOReg, Reg))) 629 if (!isDead || MO.isDead()) 630 return i; 631 } 632 return -1; 633} 634 635/// findFirstPredOperandIdx() - Find the index of the first operand in the 636/// operand list that is used to represent the predicate. It returns -1 if 637/// none is found. 638int MachineInstr::findFirstPredOperandIdx() const { 639 const TargetInstrDesc &TID = getDesc(); 640 if (TID.isPredicable()) { 641 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 642 if (TID.OpInfo[i].isPredicate()) 643 return i; 644 } 645 646 return -1; 647} 648 649/// isRegReDefinedByTwoAddr - Given the index of a register def operand, 650/// check if the register def is a re-definition due to two addr elimination. 651bool MachineInstr::isRegReDefinedByTwoAddr(unsigned DefIdx) const{ 652 assert(getOperand(DefIdx).isDef() && "DefIdx is not a def!"); 653 const TargetInstrDesc &TID = getDesc(); 654 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 655 const MachineOperand &MO = getOperand(i); 656 if (MO.isReg() && MO.isUse() && 657 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx) 658 return true; 659 } 660 return false; 661} 662 663/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 664/// 665void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 666 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 667 const MachineOperand &MO = MI->getOperand(i); 668 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 669 continue; 670 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 671 MachineOperand &MOp = getOperand(j); 672 if (!MOp.isIdenticalTo(MO)) 673 continue; 674 if (MO.isKill()) 675 MOp.setIsKill(); 676 else 677 MOp.setIsDead(); 678 break; 679 } 680 } 681} 682 683/// copyPredicates - Copies predicate operand(s) from MI. 684void MachineInstr::copyPredicates(const MachineInstr *MI) { 685 const TargetInstrDesc &TID = MI->getDesc(); 686 if (!TID.isPredicable()) 687 return; 688 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 689 if (TID.OpInfo[i].isPredicate()) { 690 // Predicated operands must be last operands. 691 addOperand(MI->getOperand(i)); 692 } 693 } 694} 695 696/// isSafeToMove - Return true if it is safe to move this instruction. If 697/// SawStore is set to true, it means that there is a store (or call) between 698/// the instruction's location and its intended destination. 699bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 700 bool &SawStore) const { 701 // Ignore stuff that we obviously can't move. 702 if (TID->mayStore() || TID->isCall()) { 703 SawStore = true; 704 return false; 705 } 706 if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects()) 707 return false; 708 709 // See if this instruction does a load. If so, we have to guarantee that the 710 // loaded value doesn't change between the load and the its intended 711 // destination. The check for isInvariantLoad gives the targe the chance to 712 // classify the load as always returning a constant, e.g. a constant pool 713 // load. 714 if (TID->mayLoad() && !TII->isInvariantLoad(this)) 715 // Otherwise, this is a real load. If there is a store between the load and 716 // end of block, or if the laod is volatile, we can't move it. 717 return !SawStore && !hasVolatileMemoryRef(); 718 719 return true; 720} 721 722/// isSafeToReMat - Return true if it's safe to rematerialize the specified 723/// instruction which defined the specified register instead of copying it. 724bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 725 unsigned DstReg) const { 726 bool SawStore = false; 727 if (!getDesc().isRematerializable() || 728 !TII->isTriviallyReMaterializable(this) || 729 !isSafeToMove(TII, SawStore)) 730 return false; 731 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 732 const MachineOperand &MO = getOperand(i); 733 if (!MO.isReg()) 734 continue; 735 // FIXME: For now, do not remat any instruction with register operands. 736 // Later on, we can loosen the restriction is the register operands have 737 // not been modified between the def and use. Note, this is different from 738 // MachineSink because the code is no longer in two-address form (at least 739 // partially). 740 if (MO.isUse()) 741 return false; 742 else if (!MO.isDead() && MO.getReg() != DstReg) 743 return false; 744 } 745 return true; 746} 747 748/// hasVolatileMemoryRef - Return true if this instruction may have a 749/// volatile memory reference, or if the information describing the 750/// memory reference is not available. Return false if it is known to 751/// have no volatile memory references. 752bool MachineInstr::hasVolatileMemoryRef() const { 753 // An instruction known never to access memory won't have a volatile access. 754 if (!TID->mayStore() && 755 !TID->mayLoad() && 756 !TID->isCall() && 757 !TID->hasUnmodeledSideEffects()) 758 return false; 759 760 // Otherwise, if the instruction has no memory reference information, 761 // conservatively assume it wasn't preserved. 762 if (memoperands_empty()) 763 return true; 764 765 // Check the memory reference information for volatile references. 766 for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(), 767 E = memoperands_end(); I != E; ++I) 768 if (I->isVolatile()) 769 return true; 770 771 return false; 772} 773 774void MachineInstr::dump() const { 775 cerr << " " << *this; 776} 777 778void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { 779 raw_os_ostream RawOS(OS); 780 print(RawOS, TM); 781} 782 783void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 784 // Specialize printing if op#0 is definition 785 unsigned StartOp = 0; 786 if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) { 787 getOperand(0).print(OS, TM); 788 OS << " = "; 789 ++StartOp; // Don't print this operand again! 790 } 791 792 OS << getDesc().getName(); 793 794 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 795 if (i != StartOp) 796 OS << ","; 797 OS << " "; 798 getOperand(i).print(OS, TM); 799 } 800 801 if (!memoperands_empty()) { 802 OS << ", Mem:"; 803 for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(), 804 e = memoperands_end(); i != e; ++i) { 805 const MachineMemOperand &MRO = *i; 806 const Value *V = MRO.getValue(); 807 808 assert((MRO.isLoad() || MRO.isStore()) && 809 "SV has to be a load, store or both."); 810 811 if (MRO.isVolatile()) 812 OS << "Volatile "; 813 814 if (MRO.isLoad()) 815 OS << "LD"; 816 if (MRO.isStore()) 817 OS << "ST"; 818 819 OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") ["; 820 821 if (!V) 822 OS << "<unknown>"; 823 else if (!V->getName().empty()) 824 OS << V->getName(); 825 else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) { 826 PSV->print(OS); 827 } else 828 OS << V; 829 830 OS << " + " << MRO.getOffset() << "]"; 831 } 832 } 833 834 OS << "\n"; 835} 836 837bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 838 const TargetRegisterInfo *RegInfo, 839 bool AddIfNotFound) { 840 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 841 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 842 bool Found = false; 843 SmallVector<unsigned,4> DeadOps; 844 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 845 MachineOperand &MO = getOperand(i); 846 if (!MO.isReg() || !MO.isUse()) 847 continue; 848 unsigned Reg = MO.getReg(); 849 if (!Reg) 850 continue; 851 852 if (Reg == IncomingReg) { 853 if (!Found) { 854 if (MO.isKill()) 855 // The register is already marked kill. 856 return true; 857 MO.setIsKill(); 858 Found = true; 859 } 860 } else if (hasAliases && MO.isKill() && 861 TargetRegisterInfo::isPhysicalRegister(Reg)) { 862 // A super-register kill already exists. 863 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 864 return true; 865 if (RegInfo->isSubRegister(IncomingReg, Reg)) 866 DeadOps.push_back(i); 867 } 868 } 869 870 // Trim unneeded kill operands. 871 while (!DeadOps.empty()) { 872 unsigned OpIdx = DeadOps.back(); 873 if (getOperand(OpIdx).isImplicit()) 874 RemoveOperand(OpIdx); 875 else 876 getOperand(OpIdx).setIsKill(false); 877 DeadOps.pop_back(); 878 } 879 880 // If not found, this means an alias of one of the operands is killed. Add a 881 // new implicit operand if required. 882 if (!Found && AddIfNotFound) { 883 addOperand(MachineOperand::CreateReg(IncomingReg, 884 false /*IsDef*/, 885 true /*IsImp*/, 886 true /*IsKill*/)); 887 return true; 888 } 889 return Found; 890} 891 892bool MachineInstr::addRegisterDead(unsigned IncomingReg, 893 const TargetRegisterInfo *RegInfo, 894 bool AddIfNotFound) { 895 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 896 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg); 897 bool Found = false; 898 SmallVector<unsigned,4> DeadOps; 899 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 900 MachineOperand &MO = getOperand(i); 901 if (!MO.isReg() || !MO.isDef()) 902 continue; 903 unsigned Reg = MO.getReg(); 904 if (!Reg) 905 continue; 906 907 if (Reg == IncomingReg) { 908 if (!Found) { 909 if (MO.isDead()) 910 // The register is already marked dead. 911 return true; 912 MO.setIsDead(); 913 Found = true; 914 } 915 } else if (hasAliases && MO.isDead() && 916 TargetRegisterInfo::isPhysicalRegister(Reg)) { 917 // There exists a super-register that's marked dead. 918 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 919 return true; 920 if (RegInfo->getSubRegisters(IncomingReg) && 921 RegInfo->getSuperRegisters(Reg) && 922 RegInfo->isSubRegister(IncomingReg, Reg)) 923 DeadOps.push_back(i); 924 } 925 } 926 927 // Trim unneeded dead operands. 928 while (!DeadOps.empty()) { 929 unsigned OpIdx = DeadOps.back(); 930 if (getOperand(OpIdx).isImplicit()) 931 RemoveOperand(OpIdx); 932 else 933 getOperand(OpIdx).setIsDead(false); 934 DeadOps.pop_back(); 935 } 936 937 // If not found, this means an alias of one of the operands is dead. Add a 938 // new implicit operand if required. 939 if (!Found && AddIfNotFound) { 940 addOperand(MachineOperand::CreateReg(IncomingReg, 941 true /*IsDef*/, 942 true /*IsImp*/, 943 false /*IsKill*/, 944 true /*IsDead*/)); 945 return true; 946 } 947 return Found; 948} 949