MachineInstr.cpp revision f73823000e2d5d6e1cf65bdf5a107297e18d35fb 
1//===-- MachineInstr.cpp --------------------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/CodeGen/MachineFunction.h"
16#include "llvm/Target/TargetMachine.h"
17#include "llvm/Target/TargetInstrInfo.h"
18#include "llvm/Target/MRegisterInfo.h"
19#include "llvm/Support/LeakDetector.h"
20#include "llvm/Support/Streams.h"
21#include <ostream>
22using namespace llvm;
23
24//===----------------------------------------------------------------------===//
25// MachineOperand Implementation
26//===----------------------------------------------------------------------===//
27
28/// isIdenticalTo - Return true if this operand is identical to the specified
29/// operand.
30bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
31  if (getType() != Other.getType()) return false;
32
33  switch (getType()) {
34  default: assert(0 && "Unrecognized operand type");
35  case MachineOperand::MO_Register:
36    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
37           getSubReg() == Other.getSubReg();
38  case MachineOperand::MO_Immediate:
39    return getImm() == Other.getImm();
40  case MachineOperand::MO_MachineBasicBlock:
41    return getMBB() == Other.getMBB();
42  case MachineOperand::MO_FrameIndex:
43    return getFrameIndex() == Other.getFrameIndex();
44  case MachineOperand::MO_ConstantPoolIndex:
45    return getConstantPoolIndex() == Other.getConstantPoolIndex() &&
46           getOffset() == Other.getOffset();
47  case MachineOperand::MO_JumpTableIndex:
48    return getJumpTableIndex() == Other.getJumpTableIndex();
49  case MachineOperand::MO_GlobalAddress:
50    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
51  case MachineOperand::MO_ExternalSymbol:
52    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
53           getOffset() == Other.getOffset();
54  }
55}
56
57/// print - Print the specified machine operand.
58///
59void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
60  switch (getType()) {
61  case MachineOperand::MO_Register:
62    if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
63      OS << "%reg" << getReg();
64    } else {
65      // If the instruction is embedded into a basic block, we can find the
66      // target
67      // info for the instruction.
68      if (TM == 0)
69        if (const MachineInstr *MI = getParent())
70          if (const MachineBasicBlock *MBB = MI->getParent())
71            if (const MachineFunction *MF = MBB->getParent())
72              TM = &MF->getTarget();
73
74      if (TM)
75        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
76      else
77        OS << "%mreg" << getReg();
78    }
79
80    if (isDef() || isKill() || isDead() || isImplicit()) {
81      OS << "<";
82      bool NeedComma = false;
83      if (isImplicit()) {
84        OS << (isDef() ? "imp-def" : "imp-use");
85        NeedComma = true;
86      } else if (isDef()) {
87        OS << "def";
88        NeedComma = true;
89      }
90      if (isKill() || isDead()) {
91        if (NeedComma)    OS << ",";
92        if (isKill()) OS << "kill";
93        if (isDead()) OS << "dead";
94      }
95      OS << ">";
96    }
97    break;
98  case MachineOperand::MO_Immediate:
99    OS << getImm();
100    break;
101  case MachineOperand::MO_MachineBasicBlock:
102    OS << "mbb<"
103       << ((Value*)getMachineBasicBlock()->getBasicBlock())->getName()
104       << "," << (void*)getMachineBasicBlock() << ">";
105    break;
106  case MachineOperand::MO_FrameIndex:
107    OS << "<fi#" << getFrameIndex() << ">";
108    break;
109  case MachineOperand::MO_ConstantPoolIndex:
110    OS << "<cp#" << getConstantPoolIndex();
111    if (getOffset()) OS << "+" << getOffset();
112    OS << ">";
113    break;
114  case MachineOperand::MO_JumpTableIndex:
115    OS << "<jt#" << getJumpTableIndex() << ">";
116    break;
117  case MachineOperand::MO_GlobalAddress:
118    OS << "<ga:" << ((Value*)getGlobal())->getName();
119    if (getOffset()) OS << "+" << getOffset();
120    OS << ">";
121    break;
122  case MachineOperand::MO_ExternalSymbol:
123    OS << "<es:" << getSymbolName();
124    if (getOffset()) OS << "+" << getOffset();
125    OS << ">";
126    break;
127  default:
128    assert(0 && "Unrecognized operand type");
129  }
130}
131
132//===----------------------------------------------------------------------===//
133// MachineInstr Implementation
134//===----------------------------------------------------------------------===//
135
136/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
137/// TID NULL and no operands.
138MachineInstr::MachineInstr()
139  : TID(0), NumImplicitOps(0), parent(0) {
140  // Make sure that we get added to a machine basicblock
141  LeakDetector::addGarbageObject(this);
142}
143
144void MachineInstr::addImplicitDefUseOperands() {
145  if (TID->ImplicitDefs)
146    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
147      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
148  if (TID->ImplicitUses)
149    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
150      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
151}
152
153/// MachineInstr ctor - This constructor create a MachineInstr and add the
154/// implicit operands. It reserves space for number of operands specified by
155/// TargetInstrDescriptor or the numOperands if it is not zero. (for
156/// instructions with variable number of operands).
157MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
158  : TID(&tid), NumImplicitOps(0), parent(0) {
159  if (!NoImp && TID->ImplicitDefs)
160    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
161      NumImplicitOps++;
162  if (!NoImp && TID->ImplicitUses)
163    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
164      NumImplicitOps++;
165  Operands.reserve(NumImplicitOps + TID->numOperands);
166  if (!NoImp)
167    addImplicitDefUseOperands();
168  // Make sure that we get added to a machine basicblock
169  LeakDetector::addGarbageObject(this);
170}
171
172/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
173/// MachineInstr is created and added to the end of the specified basic block.
174///
175MachineInstr::MachineInstr(MachineBasicBlock *MBB,
176                           const TargetInstrDescriptor &tid)
177  : TID(&tid), NumImplicitOps(0), parent(0) {
178  assert(MBB && "Cannot use inserting ctor with null basic block!");
179  if (TID->ImplicitDefs)
180    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
181      NumImplicitOps++;
182  if (TID->ImplicitUses)
183    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
184      NumImplicitOps++;
185  Operands.reserve(NumImplicitOps + TID->numOperands);
186  addImplicitDefUseOperands();
187  // Make sure that we get added to a machine basicblock
188  LeakDetector::addGarbageObject(this);
189  MBB->push_back(this);  // Add instruction to end of basic block!
190}
191
192/// MachineInstr ctor - Copies MachineInstr arg exactly
193///
194MachineInstr::MachineInstr(const MachineInstr &MI) {
195  TID = MI.getInstrDescriptor();
196  NumImplicitOps = MI.NumImplicitOps;
197  Operands.reserve(MI.getNumOperands());
198
199  // Add operands
200  for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
201    Operands.push_back(MI.getOperand(i));
202    Operands.back().ParentMI = this;
203  }
204
205  // Set parent, next, and prev to null
206  parent = 0;
207  prev = 0;
208  next = 0;
209}
210
211
212MachineInstr::~MachineInstr() {
213  LeakDetector::removeGarbageObject(this);
214#ifndef NDEBUG
215  for (unsigned i = 0, e = Operands.size(); i != e; ++i)
216    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
217#endif
218}
219
220/// getOpcode - Returns the opcode of this MachineInstr.
221///
222int MachineInstr::getOpcode() const {
223  return TID->Opcode;
224}
225
226/// removeFromParent - This method unlinks 'this' from the containing basic
227/// block, and returns it, but does not delete it.
228MachineInstr *MachineInstr::removeFromParent() {
229  assert(getParent() && "Not embedded in a basic block!");
230  getParent()->remove(this);
231  return this;
232}
233
234
235/// OperandComplete - Return true if it's illegal to add a new operand
236///
237bool MachineInstr::OperandsComplete() const {
238  unsigned short NumOperands = TID->numOperands;
239  if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
240      getNumOperands()-NumImplicitOps >= NumOperands)
241    return true;  // Broken: we have all the operands of this instruction!
242  return false;
243}
244
245/// getNumExplicitOperands - Returns the number of non-implicit operands.
246///
247unsigned MachineInstr::getNumExplicitOperands() const {
248  unsigned NumOperands = TID->numOperands;
249  if ((TID->Flags & M_VARIABLE_OPS) == 0)
250    return NumOperands;
251
252  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
253    const MachineOperand &MO = getOperand(NumOperands);
254    if (!MO.isRegister() || !MO.isImplicit())
255      NumOperands++;
256  }
257  return NumOperands;
258}
259
260
261/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
262/// the specific register or -1 if it is not found. It further tightening
263/// the search criteria to a use that kills the register if isKill is true.
264int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
265  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
266    const MachineOperand &MO = getOperand(i);
267    if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
268      if (!isKill || MO.isKill())
269        return i;
270  }
271  return -1;
272}
273
274/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
275/// the specific register or NULL if it is not found.
276MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
277  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
278    MachineOperand &MO = getOperand(i);
279    if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
280      return &MO;
281  }
282  return NULL;
283}
284
285/// findFirstPredOperandIdx() - Find the index of the first operand in the
286/// operand list that is used to represent the predicate. It returns -1 if
287/// none is found.
288int MachineInstr::findFirstPredOperandIdx() const {
289  const TargetInstrDescriptor *TID = getInstrDescriptor();
290  if (TID->Flags & M_PREDICABLE) {
291    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
292      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
293        return i;
294  }
295
296  return -1;
297}
298
299/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
300/// to two addr elimination.
301bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
302  const TargetInstrDescriptor *TID = getInstrDescriptor();
303  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
304    const MachineOperand &MO1 = getOperand(i);
305    if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
306      for (unsigned j = i+1; j < e; ++j) {
307        const MachineOperand &MO2 = getOperand(j);
308        if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
309            TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
310          return true;
311      }
312    }
313  }
314  return false;
315}
316
317/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
318///
319void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
320  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
321    const MachineOperand &MO = MI->getOperand(i);
322    if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
323      continue;
324    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
325      MachineOperand &MOp = getOperand(j);
326      if (!MOp.isIdenticalTo(MO))
327        continue;
328      if (MO.isKill())
329        MOp.setIsKill();
330      else
331        MOp.setIsDead();
332      break;
333    }
334  }
335}
336
337/// copyPredicates - Copies predicate operand(s) from MI.
338void MachineInstr::copyPredicates(const MachineInstr *MI) {
339  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
340  if (TID->Flags & M_PREDICABLE) {
341    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
342      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
343        // Predicated operands must be last operands.
344        addOperand(MI->getOperand(i));
345      }
346    }
347  }
348}
349
350void MachineInstr::dump() const {
351  cerr << "  " << *this;
352}
353
354void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
355  // Specialize printing if op#0 is definition
356  unsigned StartOp = 0;
357  if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
358    getOperand(0).print(OS, TM);
359    OS << " = ";
360    ++StartOp;   // Don't print this operand again!
361  }
362
363  OS << getInstrDescriptor()->Name;
364
365  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
366    if (i != StartOp)
367      OS << ",";
368    OS << " ";
369    getOperand(i).print(OS, TM);
370  }
371
372  OS << "\n";
373}
374
375