MachineInstr.cpp revision fa9457276a2174aaf302240dd32d89900ad021ae 
1//===-- MachineInstr.cpp --------------------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/CodeGen/MachineFunction.h"
16#include "llvm/Target/TargetMachine.h"
17#include "llvm/Target/TargetInstrInfo.h"
18#include "llvm/Target/MRegisterInfo.h"
19#include "llvm/Support/LeakDetector.h"
20#include "llvm/Support/Streams.h"
21#include <ostream>
22using namespace llvm;
23
24/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
25/// TID NULL and no operands.
26MachineInstr::MachineInstr()
27  : TID(0), NumImplicitOps(0), parent(0) {
28  // Make sure that we get added to a machine basicblock
29  LeakDetector::addGarbageObject(this);
30}
31
32void MachineInstr::addImplicitDefUseOperands() {
33  if (TID->ImplicitDefs)
34    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) {
35      MachineOperand Op;
36      Op.opType = MachineOperand::MO_Register;
37      Op.IsDef = true;
38      Op.IsImp = true;
39      Op.IsKill = false;
40      Op.IsDead = false;
41      Op.contents.RegNo = *ImpDefs;
42      Operands.push_back(Op);
43    }
44  if (TID->ImplicitUses)
45    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) {
46      MachineOperand Op;
47      Op.opType = MachineOperand::MO_Register;
48      Op.IsDef = false;
49      Op.IsImp = true;
50      Op.IsKill = false;
51      Op.IsDead = false;
52      Op.contents.RegNo = *ImpUses;
53      Operands.push_back(Op);
54    }
55}
56
57/// MachineInstr ctor - This constructor create a MachineInstr and add the
58/// implicit operands. It reserves space for number of operands specified by
59/// TargetInstrDescriptor or the numOperands if it is not zero. (for
60/// instructions with variable number of operands).
61MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
62  : TID(&tid), NumImplicitOps(0), parent(0) {
63  if (!NoImp && TID->ImplicitDefs)
64    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
65      NumImplicitOps++;
66  if (!NoImp && TID->ImplicitUses)
67    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
68      NumImplicitOps++;
69  Operands.reserve(NumImplicitOps + TID->numOperands);
70  if (!NoImp)
71    addImplicitDefUseOperands();
72  // Make sure that we get added to a machine basicblock
73  LeakDetector::addGarbageObject(this);
74}
75
76/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
77/// MachineInstr is created and added to the end of the specified basic block.
78///
79MachineInstr::MachineInstr(MachineBasicBlock *MBB,
80                           const TargetInstrDescriptor &tid)
81  : TID(&tid), NumImplicitOps(0), parent(0) {
82  assert(MBB && "Cannot use inserting ctor with null basic block!");
83  if (TID->ImplicitDefs)
84    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
85      NumImplicitOps++;
86  if (TID->ImplicitUses)
87    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
88      NumImplicitOps++;
89  Operands.reserve(NumImplicitOps + TID->numOperands);
90  addImplicitDefUseOperands();
91  // Make sure that we get added to a machine basicblock
92  LeakDetector::addGarbageObject(this);
93  MBB->push_back(this);  // Add instruction to end of basic block!
94}
95
96/// MachineInstr ctor - Copies MachineInstr arg exactly
97///
98MachineInstr::MachineInstr(const MachineInstr &MI) {
99  TID = MI.getInstrDescriptor();
100  NumImplicitOps = MI.NumImplicitOps;
101  Operands.reserve(MI.getNumOperands());
102
103  // Add operands
104  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
105    Operands.push_back(MI.getOperand(i));
106
107  // Set parent, next, and prev to null
108  parent = 0;
109  prev = 0;
110  next = 0;
111}
112
113
114MachineInstr::~MachineInstr() {
115  LeakDetector::removeGarbageObject(this);
116}
117
118/// getOpcode - Returns the opcode of this MachineInstr.
119///
120int MachineInstr::getOpcode() const {
121  return TID->Opcode;
122}
123
124/// removeFromParent - This method unlinks 'this' from the containing basic
125/// block, and returns it, but does not delete it.
126MachineInstr *MachineInstr::removeFromParent() {
127  assert(getParent() && "Not embedded in a basic block!");
128  getParent()->remove(this);
129  return this;
130}
131
132
133/// OperandComplete - Return true if it's illegal to add a new operand
134///
135bool MachineInstr::OperandsComplete() const {
136  unsigned short NumOperands = TID->numOperands;
137  if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
138      getNumOperands()-NumImplicitOps >= NumOperands)
139    return true;  // Broken: we have all the operands of this instruction!
140  return false;
141}
142
143/// getNumExplicitOperands - Returns the number of non-implicit operands.
144///
145unsigned MachineInstr::getNumExplicitOperands() const {
146  unsigned NumOperands = TID->numOperands;
147  if ((TID->Flags & M_VARIABLE_OPS) == 0)
148    return NumOperands;
149
150  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
151    const MachineOperand &MO = getOperand(NumOperands);
152    if (!MO.isRegister() || !MO.isImplicit())
153      NumOperands++;
154  }
155  return NumOperands;
156}
157
158/// isIdenticalTo - Return true if this operand is identical to the specified
159/// operand.
160bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
161  if (getType() != Other.getType()) return false;
162
163  switch (getType()) {
164  default: assert(0 && "Unrecognized operand type");
165  case MachineOperand::MO_Register:
166    return getReg() == Other.getReg() && isDef() == Other.isDef();
167  case MachineOperand::MO_Immediate:
168    return getImm() == Other.getImm();
169  case MachineOperand::MO_MachineBasicBlock:
170    return getMBB() == Other.getMBB();
171  case MachineOperand::MO_FrameIndex:
172    return getFrameIndex() == Other.getFrameIndex();
173  case MachineOperand::MO_ConstantPoolIndex:
174    return getConstantPoolIndex() == Other.getConstantPoolIndex() &&
175           getOffset() == Other.getOffset();
176  case MachineOperand::MO_JumpTableIndex:
177    return getJumpTableIndex() == Other.getJumpTableIndex();
178  case MachineOperand::MO_GlobalAddress:
179    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
180  case MachineOperand::MO_ExternalSymbol:
181    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
182           getOffset() == Other.getOffset();
183  }
184}
185
186/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
187/// the specific register or -1 if it is not found. It further tightening
188/// the search criteria to a use that kills the register if isKill is true.
189int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
190  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
191    const MachineOperand &MO = getOperand(i);
192    if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
193      if (!isKill || MO.isKill())
194        return i;
195  }
196  return -1;
197}
198
199/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
200/// the specific register or NULL if it is not found.
201MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
202  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
203    MachineOperand &MO = getOperand(i);
204    if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
205      return &MO;
206  }
207  return NULL;
208}
209
210/// findFirstPredOperandIdx() - Find the index of the first operand in the
211/// operand list that is used to represent the predicate. It returns -1 if
212/// none is found.
213int MachineInstr::findFirstPredOperandIdx() const {
214  const TargetInstrDescriptor *TID = getInstrDescriptor();
215  if (TID->Flags & M_PREDICABLE) {
216    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
217      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
218        return i;
219  }
220
221  return -1;
222}
223
224/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
225/// to two addr elimination.
226bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
227  const TargetInstrDescriptor *TID = getInstrDescriptor();
228  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
229    const MachineOperand &MO1 = getOperand(i);
230    if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
231      for (unsigned j = i+1; j < e; ++j) {
232        const MachineOperand &MO2 = getOperand(j);
233        if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
234            TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
235          return true;
236      }
237    }
238  }
239  return false;
240}
241
242/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
243///
244void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
245  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
246    const MachineOperand &MO = MI->getOperand(i);
247    if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
248      continue;
249    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
250      MachineOperand &MOp = getOperand(j);
251      if (!MOp.isIdenticalTo(MO))
252        continue;
253      if (MO.isKill())
254        MOp.setIsKill();
255      else
256        MOp.setIsDead();
257      break;
258    }
259  }
260}
261
262/// copyPredicates - Copies predicate operand(s) from MI.
263void MachineInstr::copyPredicates(const MachineInstr *MI) {
264  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
265  if (TID->Flags & M_PREDICABLE) {
266    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
267      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
268        const MachineOperand &MO = MI->getOperand(i);
269        // Predicated operands must be last operands.
270        if (MO.isRegister())
271          addRegOperand(MO.getReg(), false);
272        else {
273          addImmOperand(MO.getImm());
274        }
275      }
276    }
277  }
278}
279
280void MachineInstr::dump() const {
281  cerr << "  " << *this;
282}
283
284static inline void OutputReg(std::ostream &os, unsigned RegNo,
285                             const MRegisterInfo *MRI = 0) {
286  if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
287    if (MRI)
288      os << "%" << MRI->get(RegNo).Name;
289    else
290      os << "%mreg(" << RegNo << ")";
291  } else
292    os << "%reg" << RegNo;
293}
294
295static void print(const MachineOperand &MO, std::ostream &OS,
296                  const TargetMachine *TM) {
297  const MRegisterInfo *MRI = 0;
298
299  if (TM) MRI = TM->getRegisterInfo();
300
301  switch (MO.getType()) {
302  case MachineOperand::MO_Register:
303    OutputReg(OS, MO.getReg(), MRI);
304    break;
305  case MachineOperand::MO_Immediate:
306    OS << MO.getImmedValue();
307    break;
308  case MachineOperand::MO_MachineBasicBlock:
309    OS << "mbb<"
310       << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
311       << "," << (void*)MO.getMachineBasicBlock() << ">";
312    break;
313  case MachineOperand::MO_FrameIndex:
314    OS << "<fi#" << MO.getFrameIndex() << ">";
315    break;
316  case MachineOperand::MO_ConstantPoolIndex:
317    OS << "<cp#" << MO.getConstantPoolIndex() << ">";
318    break;
319  case MachineOperand::MO_JumpTableIndex:
320    OS << "<jt#" << MO.getJumpTableIndex() << ">";
321    break;
322  case MachineOperand::MO_GlobalAddress:
323    OS << "<ga:" << ((Value*)MO.getGlobal())->getName();
324    if (MO.getOffset()) OS << "+" << MO.getOffset();
325    OS << ">";
326    break;
327  case MachineOperand::MO_ExternalSymbol:
328    OS << "<es:" << MO.getSymbolName();
329    if (MO.getOffset()) OS << "+" << MO.getOffset();
330    OS << ">";
331    break;
332  default:
333    assert(0 && "Unrecognized operand type");
334  }
335}
336
337void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
338  unsigned StartOp = 0;
339
340   // Specialize printing if op#0 is definition
341  if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
342    ::print(getOperand(0), OS, TM);
343    if (getOperand(0).isDead())
344      OS << "<dead>";
345    OS << " = ";
346    ++StartOp;   // Don't print this operand again!
347  }
348
349  if (TID)
350    OS << TID->Name;
351
352  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
353    const MachineOperand& mop = getOperand(i);
354    if (i != StartOp)
355      OS << ",";
356    OS << " ";
357    ::print(mop, OS, TM);
358
359    if (mop.isRegister()) {
360      if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
361        OS << "<";
362        bool NeedComma = false;
363        if (mop.isImplicit()) {
364          OS << (mop.isDef() ? "imp-def" : "imp-use");
365          NeedComma = true;
366        } else if (mop.isDef()) {
367          OS << "def";
368          NeedComma = true;
369        }
370        if (mop.isKill() || mop.isDead()) {
371          if (NeedComma)
372            OS << ",";
373          if (mop.isKill())
374            OS << "kill";
375          if (mop.isDead())
376            OS << "dead";
377        }
378        OS << ">";
379      }
380    }
381  }
382
383  OS << "\n";
384}
385
386void MachineInstr::print(std::ostream &os) const {
387  // If the instruction is embedded into a basic block, we can find the target
388  // info for the instruction.
389  if (const MachineBasicBlock *MBB = getParent()) {
390    const MachineFunction *MF = MBB->getParent();
391    if (MF)
392      print(os, &MF->getTarget());
393    else
394      print(os, 0);
395  }
396
397  // Otherwise, print it out in the "raw" format without symbolic register names
398  // and such.
399  os << getInstrDescriptor()->Name;
400
401  for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
402    os << "\t" << getOperand(i);
403    if (getOperand(i).isRegister() && getOperand(i).isDef())
404      os << "<d>";
405  }
406
407  os << "\n";
408}
409
410void MachineOperand::print(std::ostream &OS) const {
411  switch (getType()) {
412  case MO_Register:
413    OutputReg(OS, getReg());
414    break;
415  case MO_Immediate:
416    OS << (long)getImmedValue();
417    break;
418  case MO_MachineBasicBlock:
419    OS << "<mbb:"
420       << ((Value*)getMachineBasicBlock()->getBasicBlock())->getName()
421       << "@" << (void*)getMachineBasicBlock() << ">";
422    break;
423  case MO_FrameIndex:
424    OS << "<fi#" << getFrameIndex() << ">";
425    break;
426  case MO_ConstantPoolIndex:
427    OS << "<cp#" << getConstantPoolIndex() << ">";
428    break;
429  case MO_JumpTableIndex:
430    OS << "<jt#" << getJumpTableIndex() << ">";
431    break;
432  case MO_GlobalAddress:
433    OS << "<ga:" << ((Value*)getGlobal())->getName() << ">";
434    break;
435  case MO_ExternalSymbol:
436    OS << "<es:" << getSymbolName() << ">";
437    break;
438  default:
439    assert(0 && "Unrecognized operand type");
440    break;
441  }
442}
443
444