MipsInstrInfo.h revision c4f24eb584f6b4dba3caba2ed766c7c4bf1bf8af 
1//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSINSTRUCTIONINFO_H
15#define MIPSINSTRUCTIONINFO_H
16
17#include "Mips.h"
18#include "llvm/Support/ErrorHandling.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "MipsRegisterInfo.h"
21
22namespace llvm {
23
24namespace Mips {
25
26  // Mips Branch Codes
27  enum FPBranchCode {
28    BRANCH_F,
29    BRANCH_T,
30    BRANCH_FL,
31    BRANCH_TL,
32    BRANCH_INVALID
33  };
34
35  // Mips Condition Codes
36  enum CondCode {
37    // To be used with float branch True
38    FCOND_F,
39    FCOND_UN,
40    FCOND_OEQ,
41    FCOND_UEQ,
42    FCOND_OLT,
43    FCOND_ULT,
44    FCOND_OLE,
45    FCOND_ULE,
46    FCOND_SF,
47    FCOND_NGLE,
48    FCOND_SEQ,
49    FCOND_NGL,
50    FCOND_LT,
51    FCOND_NGE,
52    FCOND_LE,
53    FCOND_NGT,
54
55    // To be used with float branch False
56    // This conditions have the same mnemonic as the
57    // above ones, but are used with a branch False;
58    FCOND_T,
59    FCOND_OR,
60    FCOND_UNE,
61    FCOND_ONE,
62    FCOND_UGE,
63    FCOND_OGE,
64    FCOND_UGT,
65    FCOND_OGT,
66    FCOND_ST,
67    FCOND_GLE,
68    FCOND_SNE,
69    FCOND_GL,
70    FCOND_NLT,
71    FCOND_GE,
72    FCOND_NLE,
73    FCOND_GT
74  };
75
76  /// GetOppositeBranchOpc - Return the inverse of the specified
77  /// opcode, e.g. turning BEQ to BNE.
78  unsigned GetOppositeBranchOpc(unsigned Opc);
79
80  /// MipsCCToString - Map each FP condition code to its string
81  inline static const char *MipsFCCToString(Mips::CondCode CC)
82  {
83    switch (CC) {
84      default: llvm_unreachable("Unknown condition code");
85      case FCOND_F:
86      case FCOND_T:   return "f";
87      case FCOND_UN:
88      case FCOND_OR:  return "un";
89      case FCOND_OEQ:
90      case FCOND_UNE: return "eq";
91      case FCOND_UEQ:
92      case FCOND_ONE: return "ueq";
93      case FCOND_OLT:
94      case FCOND_UGE: return "olt";
95      case FCOND_ULT:
96      case FCOND_OGE: return "ult";
97      case FCOND_OLE:
98      case FCOND_UGT: return "ole";
99      case FCOND_ULE:
100      case FCOND_OGT: return "ule";
101      case FCOND_SF:
102      case FCOND_ST:  return "sf";
103      case FCOND_NGLE:
104      case FCOND_GLE: return "ngle";
105      case FCOND_SEQ:
106      case FCOND_SNE: return "seq";
107      case FCOND_NGL:
108      case FCOND_GL:  return "ngl";
109      case FCOND_LT:
110      case FCOND_NLT: return "lt";
111      case FCOND_NGE:
112      case FCOND_GE:  return "nge";
113      case FCOND_LE:
114      case FCOND_NLE: return "le";
115      case FCOND_NGT:
116      case FCOND_GT:  return "ngt";
117    }
118  }
119}
120
121/// MipsII - This namespace holds all of the target specific flags that
122/// instruction info tracks.
123///
124namespace MipsII {
125  /// Target Operand Flag enum.
126  enum TOF {
127    //===------------------------------------------------------------------===//
128    // Mips Specific MachineOperand flags.
129
130    MO_NO_FLAG,
131
132    /// MO_GOT - Represents the offset into the global offset table at which
133    /// the address the relocation entry symbol resides during execution.
134    MO_GOT,
135
136    /// MO_GOT_CALL - Represents the offset into the global offset table at
137    /// which the address of a call site relocation entry symbol resides
138    /// during execution. This is different from the above since this flag
139    /// can only be present in call instructions.
140    MO_GOT_CALL,
141
142    /// MO_GPREL - Represents the offset from the current gp value to be used
143    /// for the relocatable object file being produced.
144    MO_GPREL,
145
146    /// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
147    /// address.
148    MO_ABS_HI,
149    MO_ABS_LO,
150
151    /// MO_TLSGD - Represents the offset into the global offset table at which
152    // the module ID and TSL block offset reside during execution (General
153    // Dynamic TLS).
154    MO_TLSGD,
155
156    /// MO_GOTTPREL - Represents the offset from the thread pointer (Initial
157    // Exec TLS).
158    MO_GOTTPREL,
159
160    /// MO_TPREL_HI/LO - Represents the hi and low part of the offset from
161    // the thread pointer (Local Exec TLS).
162    MO_TPREL_HI,
163    MO_TPREL_LO
164  };
165}
166
167class MipsInstrInfo : public TargetInstrInfoImpl {
168  MipsTargetMachine &TM;
169  const MipsRegisterInfo RI;
170public:
171  explicit MipsInstrInfo(MipsTargetMachine &TM);
172
173  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
174  /// such, whenever a client has an instance of instruction info, it should
175  /// always be able to get register info as well (through this method).
176  ///
177  virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
178
179  /// isLoadFromStackSlot - If the specified machine instruction is a direct
180  /// load from a stack slot, return the virtual or physical register number of
181  /// the destination along with the FrameIndex of the loaded stack slot.  If
182  /// not, return 0.  This predicate must return 0 if the instruction has
183  /// any side effects other than loading from the stack slot.
184  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
185                                       int &FrameIndex) const;
186
187  /// isStoreToStackSlot - If the specified machine instruction is a direct
188  /// store to a stack slot, return the virtual or physical register number of
189  /// the source reg along with the FrameIndex of the loaded stack slot.  If
190  /// not, return 0.  This predicate must return 0 if the instruction has
191  /// any side effects other than storing to the stack slot.
192  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
193                                      int &FrameIndex) const;
194
195  /// Branch Analysis
196  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
197                             MachineBasicBlock *&FBB,
198                             SmallVectorImpl<MachineOperand> &Cond,
199                             bool AllowModify) const;
200  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
201
202private:
203  void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
204                   const SmallVectorImpl<MachineOperand>& Cond) const;
205
206public:
207  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
208                                MachineBasicBlock *FBB,
209                                const SmallVectorImpl<MachineOperand> &Cond,
210                                DebugLoc DL) const;
211  virtual void copyPhysReg(MachineBasicBlock &MBB,
212                           MachineBasicBlock::iterator MI, DebugLoc DL,
213                           unsigned DestReg, unsigned SrcReg,
214                           bool KillSrc) const;
215  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
216                                   MachineBasicBlock::iterator MBBI,
217                                   unsigned SrcReg, bool isKill, int FrameIndex,
218                                   const TargetRegisterClass *RC,
219                                   const TargetRegisterInfo *TRI) const;
220
221  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
222                                    MachineBasicBlock::iterator MBBI,
223                                    unsigned DestReg, int FrameIndex,
224                                    const TargetRegisterClass *RC,
225                                    const TargetRegisterInfo *TRI) const;
226
227  virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
228                                                 int FrameIx, uint64_t Offset,
229                                                 const MDNode *MDPtr,
230                                                 DebugLoc DL) const;
231
232  virtual
233  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
234
235  /// Insert nop instruction when hazard condition is found
236  virtual void insertNoop(MachineBasicBlock &MBB,
237                          MachineBasicBlock::iterator MI) const;
238
239  /// getGlobalBaseReg - Return a virtual register initialized with the
240  /// the global base register value. Output instructions required to
241  /// initialize the register in the function entry block, if necessary.
242  ///
243  unsigned getGlobalBaseReg(MachineFunction *MF) const;
244};
245
246}
247
248#endif
249