PPCFrameLowering.cpp revision 100a94bc93dcf9af99eba169599ce950faf0df7e
1//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PPC implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCFrameLowering.h" 15#include "PPCInstrBuilder.h" 16#include "PPCInstrInfo.h" 17#include "PPCMachineFunctionInfo.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/MachineModuleInfo.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/RegisterScavenging.h" 24#include "llvm/IR/Function.h" 25#include "llvm/Target/TargetOptions.h" 26 27using namespace llvm; 28 29// FIXME This disables some code that aligns the stack to a boundary bigger than 30// the default (16 bytes on Darwin) when there is a stack local of greater 31// alignment. This does not currently work, because the delta between old and 32// new stack pointers is added to offsets that reference incoming parameters 33// after the prolog is generated, and the code that does that doesn't handle a 34// variable delta. You don't want to do that anyway; a better approach is to 35// reserve another register that retains to the incoming stack pointer, and 36// reference parameters relative to that. 37#define ALIGN_STACK 0 38 39 40/// VRRegNo - Map from a numbered VR register to its enum value. 41/// 42static const uint16_t VRRegNo[] = { 43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 47}; 48 49/// RemoveVRSaveCode - We have found that this function does not need any code 50/// to manipulate the VRSAVE register, even though it uses vector registers. 51/// This can happen when the only registers used are known to be live in or out 52/// of the function. Remove all of the VRSAVE related code from the function. 53/// FIXME: The removal of the code results in a compile failure at -O0 when the 54/// function contains a function call, as the GPR containing original VRSAVE 55/// contents is spilled and reloaded around the call. Without the prolog code, 56/// the spill instruction refers to an undefined register. This code needs 57/// to account for all uses of that GPR. 58static void RemoveVRSaveCode(MachineInstr *MI) { 59 MachineBasicBlock *Entry = MI->getParent(); 60 MachineFunction *MF = Entry->getParent(); 61 62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 63 MachineBasicBlock::iterator MBBI = MI; 64 ++MBBI; 65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 66 MBBI->eraseFromParent(); 67 68 bool RemovedAllMTVRSAVEs = true; 69 // See if we can find and remove the MTVRSAVE instruction from all of the 70 // epilog blocks. 71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 72 // If last instruction is a return instruction, add an epilogue 73 if (!I->empty() && I->back().isReturn()) { 74 bool FoundIt = false; 75 for (MBBI = I->end(); MBBI != I->begin(); ) { 76 --MBBI; 77 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 78 MBBI->eraseFromParent(); // remove it. 79 FoundIt = true; 80 break; 81 } 82 } 83 RemovedAllMTVRSAVEs &= FoundIt; 84 } 85 } 86 87 // If we found and removed all MTVRSAVE instructions, remove the read of 88 // VRSAVE as well. 89 if (RemovedAllMTVRSAVEs) { 90 MBBI = MI; 91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 92 --MBBI; 93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 94 MBBI->eraseFromParent(); 95 } 96 97 // Finally, nuke the UPDATE_VRSAVE. 98 MI->eraseFromParent(); 99} 100 101// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 102// instruction selector. Based on the vector registers that have been used, 103// transform this into the appropriate ORI instruction. 104static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 105 MachineFunction *MF = MI->getParent()->getParent(); 106 DebugLoc dl = MI->getDebugLoc(); 107 108 unsigned UsedRegMask = 0; 109 for (unsigned i = 0; i != 32; ++i) 110 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 111 UsedRegMask |= 1 << (31-i); 112 113 // Live in and live out values already must be in the mask, so don't bother 114 // marking them. 115 for (MachineRegisterInfo::livein_iterator 116 I = MF->getRegInfo().livein_begin(), 117 E = MF->getRegInfo().livein_end(); I != E; ++I) { 118 unsigned RegNo = getPPCRegisterNumbering(I->first); 119 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 120 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 121 } 122 123 // Live out registers appear as use operands on return instructions. 124 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 125 UsedRegMask != 0 && BI != BE; ++BI) { 126 const MachineBasicBlock &MBB = *BI; 127 if (MBB.empty() || !MBB.back().isReturn()) 128 continue; 129 const MachineInstr &Ret = MBB.back(); 130 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 131 const MachineOperand &MO = Ret.getOperand(I); 132 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 133 continue; 134 unsigned RegNo = getPPCRegisterNumbering(MO.getReg()); 135 UsedRegMask &= ~(1 << (31-RegNo)); 136 } 137 } 138 139 // If no registers are used, turn this into a copy. 140 if (UsedRegMask == 0) { 141 // Remove all VRSAVE code. 142 RemoveVRSaveCode(MI); 143 return; 144 } 145 146 unsigned SrcReg = MI->getOperand(1).getReg(); 147 unsigned DstReg = MI->getOperand(0).getReg(); 148 149 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 150 if (DstReg != SrcReg) 151 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 152 .addReg(SrcReg) 153 .addImm(UsedRegMask); 154 else 155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 156 .addReg(SrcReg, RegState::Kill) 157 .addImm(UsedRegMask); 158 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 159 if (DstReg != SrcReg) 160 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 161 .addReg(SrcReg) 162 .addImm(UsedRegMask >> 16); 163 else 164 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 165 .addReg(SrcReg, RegState::Kill) 166 .addImm(UsedRegMask >> 16); 167 } else { 168 if (DstReg != SrcReg) 169 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 170 .addReg(SrcReg) 171 .addImm(UsedRegMask >> 16); 172 else 173 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 174 .addReg(SrcReg, RegState::Kill) 175 .addImm(UsedRegMask >> 16); 176 177 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 178 .addReg(DstReg, RegState::Kill) 179 .addImm(UsedRegMask & 0xFFFF); 180 } 181 182 // Remove the old UPDATE_VRSAVE instruction. 183 MI->eraseFromParent(); 184} 185 186static bool spillsCR(const MachineFunction &MF) { 187 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 188 return FuncInfo->isCRSpilled(); 189} 190 191/// determineFrameLayout - Determine the size of the frame and maximum call 192/// frame size. 193void PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const { 194 MachineFrameInfo *MFI = MF.getFrameInfo(); 195 196 // Get the number of bytes to allocate from the FrameInfo 197 unsigned FrameSize = MFI->getStackSize(); 198 199 // Get the alignments provided by the target, and the maximum alignment 200 // (if any) of the fixed frame objects. 201 unsigned MaxAlign = MFI->getMaxAlignment(); 202 unsigned TargetAlign = getStackAlignment(); 203 unsigned AlignMask = TargetAlign - 1; // 204 205 // If we are a leaf function, and use up to 224 bytes of stack space, 206 // don't have a frame pointer, calls, or dynamic alloca then we do not need 207 // to adjust the stack pointer (we fit in the Red Zone). For 64-bit 208 // SVR4, we also require a stack frame if we need to spill the CR, 209 // since this spill area is addressed relative to the stack pointer. 210 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 211 // stackless code if all local vars are reg-allocated. 212 bool DisableRedZone = MF.getFunction()->getAttributes(). 213 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone); 214 if (!DisableRedZone && 215 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 216 !Subtarget.isSVR4ABI() || // allocated locals. 217 FrameSize == 0) && 218 FrameSize <= 224 && // Fits in red zone. 219 !MFI->hasVarSizedObjects() && // No dynamic alloca. 220 !MFI->adjustsStack() && // No calls. 221 !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave. 222 Subtarget.isSVR4ABI() 223 && spillsCR(MF)) && 224 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 225 // No need for frame 226 MFI->setStackSize(0); 227 return; 228 } 229 230 // Get the maximum call frame size of all the calls. 231 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 232 233 // Maximum call frame needs to be at least big enough for linkage and 8 args. 234 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 235 Subtarget.isDarwinABI()); 236 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 237 238 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 239 // that allocations will be aligned. 240 if (MFI->hasVarSizedObjects()) 241 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 242 243 // Update maximum call frame size. 244 MFI->setMaxCallFrameSize(maxCallFrameSize); 245 246 // Include call frame size in total. 247 FrameSize += maxCallFrameSize; 248 249 // Make sure the frame is aligned. 250 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 251 252 // Update frame info. 253 MFI->setStackSize(FrameSize); 254} 255 256// hasFP - Return true if the specified function actually has a dedicated frame 257// pointer register. 258bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 259 const MachineFrameInfo *MFI = MF.getFrameInfo(); 260 // FIXME: This is pretty much broken by design: hasFP() might be called really 261 // early, before the stack layout was calculated and thus hasFP() might return 262 // true or false here depending on the time of call. 263 return (MFI->getStackSize()) && needsFP(MF); 264} 265 266// needsFP - Return true if the specified function should have a dedicated frame 267// pointer register. This is true if the function has variable sized allocas or 268// if frame pointer elimination is disabled. 269bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 270 const MachineFrameInfo *MFI = MF.getFrameInfo(); 271 272 // Naked functions have no stack frame pushed, so we don't have a frame 273 // pointer. 274 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 275 Attribute::Naked)) 276 return false; 277 278 return MF.getTarget().Options.DisableFramePointerElim(MF) || 279 MFI->hasVarSizedObjects() || 280 (MF.getTarget().Options.GuaranteedTailCallOpt && 281 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 282} 283 284 285void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 286 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 287 MachineBasicBlock::iterator MBBI = MBB.begin(); 288 MachineFrameInfo *MFI = MF.getFrameInfo(); 289 const PPCInstrInfo &TII = 290 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 291 292 MachineModuleInfo &MMI = MF.getMMI(); 293 DebugLoc dl; 294 bool needsFrameMoves = MMI.hasDebugInfo() || 295 MF.getFunction()->needsUnwindTableEntry(); 296 297 // Prepare for frame info. 298 MCSymbol *FrameLabel = 0; 299 300 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 301 // process it. 302 if (!Subtarget.isSVR4ABI()) 303 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 304 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 305 HandleVRSaveUpdate(MBBI, TII); 306 break; 307 } 308 } 309 310 // Move MBBI back to the beginning of the function. 311 MBBI = MBB.begin(); 312 313 // Work out frame sizes. 314 // FIXME: determineFrameLayout() may change the frame size. This should be 315 // moved upper, to some hook. 316 determineFrameLayout(MF); 317 unsigned FrameSize = MFI->getStackSize(); 318 319 int NegFrameSize = -FrameSize; 320 321 // Get processor type. 322 bool isPPC64 = Subtarget.isPPC64(); 323 // Get operating system 324 bool isDarwinABI = Subtarget.isDarwinABI(); 325 // Check if the link register (LR) must be saved. 326 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 327 bool MustSaveLR = FI->mustSaveLR(); 328 // Do we have a frame pointer for this function? 329 bool HasFP = hasFP(MF); 330 331 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 332 333 int FPOffset = 0; 334 if (HasFP) { 335 if (Subtarget.isSVR4ABI()) { 336 MachineFrameInfo *FFI = MF.getFrameInfo(); 337 int FPIndex = FI->getFramePointerSaveIndex(); 338 assert(FPIndex && "No Frame Pointer Save Slot!"); 339 FPOffset = FFI->getObjectOffset(FPIndex); 340 } else { 341 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 342 } 343 } 344 345 if (isPPC64) { 346 if (MustSaveLR) 347 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 348 349 if (HasFP) 350 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 351 .addReg(PPC::X31) 352 .addImm(FPOffset/4) 353 .addReg(PPC::X1); 354 355 if (MustSaveLR) 356 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 357 .addReg(PPC::X0) 358 .addImm(LROffset / 4) 359 .addReg(PPC::X1); 360 } else { 361 if (MustSaveLR) 362 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 363 364 if (HasFP) 365 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative 366 // offsets of R1 is not allowed. 367 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 368 .addReg(PPC::R31) 369 .addImm(FPOffset) 370 .addReg(PPC::R1); 371 372 if (MustSaveLR) 373 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 374 .addReg(PPC::R0) 375 .addImm(LROffset) 376 .addReg(PPC::R1); 377 } 378 379 // Skip if a leaf routine. 380 if (!FrameSize) return; 381 382 // Get stack alignments. 383 unsigned TargetAlign = getStackAlignment(); 384 unsigned MaxAlign = MFI->getMaxAlignment(); 385 386 // Adjust stack pointer: r1 += NegFrameSize. 387 // If there is a preferred stack alignment, align R1 now 388 if (!isPPC64) { 389 // PPC32. 390 if (ALIGN_STACK && MaxAlign > TargetAlign) { 391 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 392 "Invalid alignment!"); 393 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 394 395 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 396 .addReg(PPC::R1) 397 .addImm(0) 398 .addImm(32 - Log2_32(MaxAlign)) 399 .addImm(31); 400 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 401 .addReg(PPC::R0, RegState::Kill) 402 .addImm(NegFrameSize); 403 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 404 .addReg(PPC::R1, RegState::Kill) 405 .addReg(PPC::R1) 406 .addReg(PPC::R0); 407 } else if (isInt<16>(NegFrameSize)) { 408 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 409 .addReg(PPC::R1) 410 .addImm(NegFrameSize) 411 .addReg(PPC::R1); 412 } else { 413 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 414 .addImm(NegFrameSize >> 16); 415 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 416 .addReg(PPC::R0, RegState::Kill) 417 .addImm(NegFrameSize & 0xFFFF); 418 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 419 .addReg(PPC::R1, RegState::Kill) 420 .addReg(PPC::R1) 421 .addReg(PPC::R0); 422 } 423 } else { // PPC64. 424 if (ALIGN_STACK && MaxAlign > TargetAlign) { 425 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 426 "Invalid alignment!"); 427 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 428 429 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 430 .addReg(PPC::X1) 431 .addImm(0) 432 .addImm(64 - Log2_32(MaxAlign)); 433 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 434 .addReg(PPC::X0) 435 .addImm(NegFrameSize); 436 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 437 .addReg(PPC::X1, RegState::Kill) 438 .addReg(PPC::X1) 439 .addReg(PPC::X0); 440 } else if (isInt<16>(NegFrameSize)) { 441 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 442 .addReg(PPC::X1) 443 .addImm(NegFrameSize / 4) 444 .addReg(PPC::X1); 445 } else { 446 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 447 .addImm(NegFrameSize >> 16); 448 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 449 .addReg(PPC::X0, RegState::Kill) 450 .addImm(NegFrameSize & 0xFFFF); 451 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 452 .addReg(PPC::X1, RegState::Kill) 453 .addReg(PPC::X1) 454 .addReg(PPC::X0); 455 } 456 } 457 458 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 459 460 // Add the "machine moves" for the instructions we generated above, but in 461 // reverse order. 462 if (needsFrameMoves) { 463 // Mark effective beginning of when frame pointer becomes valid. 464 FrameLabel = MMI.getContext().CreateTempSymbol(); 465 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 466 467 // Show update of SP. 468 if (NegFrameSize) { 469 MachineLocation SPDst(MachineLocation::VirtualFP); 470 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 471 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 472 } else { 473 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 474 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 475 } 476 477 if (HasFP) { 478 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 479 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 480 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 481 } 482 483 if (MustSaveLR) { 484 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 485 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 486 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 487 } 488 } 489 490 MCSymbol *ReadyLabel = 0; 491 492 // If there is a frame pointer, copy R1 into R31 493 if (HasFP) { 494 if (!isPPC64) { 495 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 496 .addReg(PPC::R1) 497 .addReg(PPC::R1); 498 } else { 499 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 500 .addReg(PPC::X1) 501 .addReg(PPC::X1); 502 } 503 504 if (needsFrameMoves) { 505 ReadyLabel = MMI.getContext().CreateTempSymbol(); 506 507 // Mark effective beginning of when frame pointer is ready. 508 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 509 510 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 511 (isPPC64 ? PPC::X1 : PPC::R1)); 512 MachineLocation FPSrc(MachineLocation::VirtualFP); 513 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 514 } 515 } 516 517 if (needsFrameMoves) { 518 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 519 520 // Add callee saved registers to move list. 521 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 522 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 523 unsigned Reg = CSI[I].getReg(); 524 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 525 526 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 527 // subregisters of CR2. We just need to emit a move of CR2. 528 if (PPC::CRBITRCRegClass.contains(Reg)) 529 continue; 530 531 // For SVR4, don't emit a move for the CR spill slot if we haven't 532 // spilled CRs. 533 if (Subtarget.isSVR4ABI() 534 && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 535 && !spillsCR(MF)) 536 continue; 537 538 // For 64-bit SVR4 when we have spilled CRs, the spill location 539 // is SP+8, not a frame-relative slot. 540 if (Subtarget.isSVR4ABI() 541 && Subtarget.isPPC64() 542 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 543 MachineLocation CSDst(PPC::X1, 8); 544 MachineLocation CSSrc(PPC::CR2); 545 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 546 continue; 547 } 548 549 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 550 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 551 MachineLocation CSSrc(Reg); 552 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 553 } 554 } 555} 556 557void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 558 MachineBasicBlock &MBB) const { 559 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 560 assert(MBBI != MBB.end() && "Returning block has no terminator"); 561 const PPCInstrInfo &TII = 562 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 563 564 unsigned RetOpcode = MBBI->getOpcode(); 565 DebugLoc dl; 566 567 assert((RetOpcode == PPC::BLR || 568 RetOpcode == PPC::TCRETURNri || 569 RetOpcode == PPC::TCRETURNdi || 570 RetOpcode == PPC::TCRETURNai || 571 RetOpcode == PPC::TCRETURNri8 || 572 RetOpcode == PPC::TCRETURNdi8 || 573 RetOpcode == PPC::TCRETURNai8) && 574 "Can only insert epilog into returning blocks"); 575 576 // Get alignment info so we know how to restore r1 577 const MachineFrameInfo *MFI = MF.getFrameInfo(); 578 unsigned TargetAlign = getStackAlignment(); 579 unsigned MaxAlign = MFI->getMaxAlignment(); 580 581 // Get the number of bytes allocated from the FrameInfo. 582 int FrameSize = MFI->getStackSize(); 583 584 // Get processor type. 585 bool isPPC64 = Subtarget.isPPC64(); 586 // Get operating system 587 bool isDarwinABI = Subtarget.isDarwinABI(); 588 // Check if the link register (LR) has been saved. 589 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 590 bool MustSaveLR = FI->mustSaveLR(); 591 // Do we have a frame pointer for this function? 592 bool HasFP = hasFP(MF); 593 594 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 595 596 int FPOffset = 0; 597 if (HasFP) { 598 if (Subtarget.isSVR4ABI()) { 599 MachineFrameInfo *FFI = MF.getFrameInfo(); 600 int FPIndex = FI->getFramePointerSaveIndex(); 601 assert(FPIndex && "No Frame Pointer Save Slot!"); 602 FPOffset = FFI->getObjectOffset(FPIndex); 603 } else { 604 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 605 } 606 } 607 608 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 609 RetOpcode == PPC::TCRETURNdi || 610 RetOpcode == PPC::TCRETURNai || 611 RetOpcode == PPC::TCRETURNri8 || 612 RetOpcode == PPC::TCRETURNdi8 || 613 RetOpcode == PPC::TCRETURNai8; 614 615 if (UsesTCRet) { 616 int MaxTCRetDelta = FI->getTailCallSPDelta(); 617 MachineOperand &StackAdjust = MBBI->getOperand(1); 618 assert(StackAdjust.isImm() && "Expecting immediate value."); 619 // Adjust stack pointer. 620 int StackAdj = StackAdjust.getImm(); 621 int Delta = StackAdj - MaxTCRetDelta; 622 assert((Delta >= 0) && "Delta must be positive"); 623 if (MaxTCRetDelta>0) 624 FrameSize += (StackAdj +Delta); 625 else 626 FrameSize += StackAdj; 627 } 628 629 if (FrameSize) { 630 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 631 // on entry to the function. Add this offset back now. 632 if (!isPPC64) { 633 // If this function contained a fastcc call and GuaranteedTailCallOpt is 634 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 635 // call which invalidates the stack pointer value in SP(0). So we use the 636 // value of R31 in this case. 637 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 638 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 639 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 640 .addReg(PPC::R31).addImm(FrameSize); 641 } else if(FI->hasFastCall()) { 642 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 643 .addImm(FrameSize >> 16); 644 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 645 .addReg(PPC::R0, RegState::Kill) 646 .addImm(FrameSize & 0xFFFF); 647 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 648 .addReg(PPC::R1) 649 .addReg(PPC::R31) 650 .addReg(PPC::R0); 651 } else if (isInt<16>(FrameSize) && 652 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 653 !MFI->hasVarSizedObjects()) { 654 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 655 .addReg(PPC::R1).addImm(FrameSize); 656 } else { 657 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 658 .addImm(0).addReg(PPC::R1); 659 } 660 } else { 661 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 662 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 663 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 664 .addReg(PPC::X31).addImm(FrameSize); 665 } else if(FI->hasFastCall()) { 666 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 667 .addImm(FrameSize >> 16); 668 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 669 .addReg(PPC::X0, RegState::Kill) 670 .addImm(FrameSize & 0xFFFF); 671 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 672 .addReg(PPC::X1) 673 .addReg(PPC::X31) 674 .addReg(PPC::X0); 675 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 676 !MFI->hasVarSizedObjects()) { 677 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 678 .addReg(PPC::X1).addImm(FrameSize); 679 } else { 680 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 681 .addImm(0).addReg(PPC::X1); 682 } 683 } 684 } 685 686 if (isPPC64) { 687 if (MustSaveLR) 688 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 689 .addImm(LROffset/4).addReg(PPC::X1); 690 691 if (HasFP) 692 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 693 .addImm(FPOffset/4).addReg(PPC::X1); 694 695 if (MustSaveLR) 696 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 697 } else { 698 if (MustSaveLR) 699 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 700 .addImm(LROffset).addReg(PPC::R1); 701 702 if (HasFP) 703 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 704 .addImm(FPOffset).addReg(PPC::R1); 705 706 if (MustSaveLR) 707 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 708 } 709 710 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 711 // call optimization 712 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 713 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 714 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 715 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 716 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 717 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 718 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 719 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 720 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 721 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 722 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 723 724 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 725 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 726 .addReg(StackReg).addImm(CallerAllocatedAmt); 727 } else { 728 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 729 .addImm(CallerAllocatedAmt >> 16); 730 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 731 .addReg(TmpReg, RegState::Kill) 732 .addImm(CallerAllocatedAmt & 0xFFFF); 733 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 734 .addReg(StackReg) 735 .addReg(FPReg) 736 .addReg(TmpReg); 737 } 738 } else if (RetOpcode == PPC::TCRETURNdi) { 739 MBBI = MBB.getLastNonDebugInstr(); 740 MachineOperand &JumpTarget = MBBI->getOperand(0); 741 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 742 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 743 } else if (RetOpcode == PPC::TCRETURNri) { 744 MBBI = MBB.getLastNonDebugInstr(); 745 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 746 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 747 } else if (RetOpcode == PPC::TCRETURNai) { 748 MBBI = MBB.getLastNonDebugInstr(); 749 MachineOperand &JumpTarget = MBBI->getOperand(0); 750 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 751 } else if (RetOpcode == PPC::TCRETURNdi8) { 752 MBBI = MBB.getLastNonDebugInstr(); 753 MachineOperand &JumpTarget = MBBI->getOperand(0); 754 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 755 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 756 } else if (RetOpcode == PPC::TCRETURNri8) { 757 MBBI = MBB.getLastNonDebugInstr(); 758 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 759 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 760 } else if (RetOpcode == PPC::TCRETURNai8) { 761 MBBI = MBB.getLastNonDebugInstr(); 762 MachineOperand &JumpTarget = MBBI->getOperand(0); 763 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 764 } 765} 766 767/// MustSaveLR - Return true if this function requires that we save the LR 768/// register onto the stack in the prolog and restore it in the epilog of the 769/// function. 770static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 771 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 772 773 // We need a save/restore of LR if there is any def of LR (which is 774 // defined by calls, including the PIC setup sequence), or if there is 775 // some use of the LR stack slot (e.g. for builtin_return_address). 776 // (LR comes in 32 and 64 bit versions.) 777 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 778 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 779} 780 781void 782PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 783 RegScavenger *RS) const { 784 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 785 786 // Save and clear the LR state. 787 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 788 unsigned LR = RegInfo->getRARegister(); 789 FI->setMustSaveLR(MustSaveLR(MF, LR)); 790 MachineRegisterInfo &MRI = MF.getRegInfo(); 791 MRI.setPhysRegUnused(LR); 792 793 // Save R31 if necessary 794 int FPSI = FI->getFramePointerSaveIndex(); 795 bool isPPC64 = Subtarget.isPPC64(); 796 bool isDarwinABI = Subtarget.isDarwinABI(); 797 MachineFrameInfo *MFI = MF.getFrameInfo(); 798 799 // If the frame pointer save index hasn't been defined yet. 800 if (!FPSI && needsFP(MF)) { 801 // Find out what the fix offset of the frame pointer save area. 802 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 803 // Allocate the frame index for frame pointer save area. 804 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 805 // Save the result. 806 FI->setFramePointerSaveIndex(FPSI); 807 } 808 809 // Reserve stack space to move the linkage area to in case of a tail call. 810 int TCSPDelta = 0; 811 if (MF.getTarget().Options.GuaranteedTailCallOpt && 812 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 813 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 814 } 815 816 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 817 // function uses CR 2, 3, or 4. 818 if (!isPPC64 && !isDarwinABI && 819 (MRI.isPhysRegUsed(PPC::CR2) || 820 MRI.isPhysRegUsed(PPC::CR3) || 821 MRI.isPhysRegUsed(PPC::CR4))) { 822 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 823 FI->setCRSpillFrameIndex(FrameIdx); 824 } 825 826 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 827 // a large stack, which will require scavenging a register to materialize a 828 // large offset. 829 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 830 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 831 // r0 for now. 832 833 if (RegInfo->requiresRegisterScavenging(MF)) 834 if (MFI->hasVarSizedObjects() || spillsCR(MF)) { 835 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 836 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 837 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 838 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 839 RC->getAlignment(), 840 false)); 841 } 842} 843 844void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF) 845 const { 846 // Early exit if not using the SVR4 ABI. 847 if (!Subtarget.isSVR4ABI()) 848 return; 849 850 // Get callee saved register information. 851 MachineFrameInfo *FFI = MF.getFrameInfo(); 852 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 853 854 // Early exit if no callee saved registers are modified! 855 if (CSI.empty() && !needsFP(MF)) { 856 return; 857 } 858 859 unsigned MinGPR = PPC::R31; 860 unsigned MinG8R = PPC::X31; 861 unsigned MinFPR = PPC::F31; 862 unsigned MinVR = PPC::V31; 863 864 bool HasGPSaveArea = false; 865 bool HasG8SaveArea = false; 866 bool HasFPSaveArea = false; 867 bool HasVRSAVESaveArea = false; 868 bool HasVRSaveArea = false; 869 870 SmallVector<CalleeSavedInfo, 18> GPRegs; 871 SmallVector<CalleeSavedInfo, 18> G8Regs; 872 SmallVector<CalleeSavedInfo, 18> FPRegs; 873 SmallVector<CalleeSavedInfo, 18> VRegs; 874 875 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 876 unsigned Reg = CSI[i].getReg(); 877 if (PPC::GPRCRegClass.contains(Reg)) { 878 HasGPSaveArea = true; 879 880 GPRegs.push_back(CSI[i]); 881 882 if (Reg < MinGPR) { 883 MinGPR = Reg; 884 } 885 } else if (PPC::G8RCRegClass.contains(Reg)) { 886 HasG8SaveArea = true; 887 888 G8Regs.push_back(CSI[i]); 889 890 if (Reg < MinG8R) { 891 MinG8R = Reg; 892 } 893 } else if (PPC::F8RCRegClass.contains(Reg)) { 894 HasFPSaveArea = true; 895 896 FPRegs.push_back(CSI[i]); 897 898 if (Reg < MinFPR) { 899 MinFPR = Reg; 900 } 901 } else if (PPC::CRBITRCRegClass.contains(Reg) || 902 PPC::CRRCRegClass.contains(Reg)) { 903 ; // do nothing, as we already know whether CRs are spilled 904 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 905 HasVRSAVESaveArea = true; 906 } else if (PPC::VRRCRegClass.contains(Reg)) { 907 HasVRSaveArea = true; 908 909 VRegs.push_back(CSI[i]); 910 911 if (Reg < MinVR) { 912 MinVR = Reg; 913 } 914 } else { 915 llvm_unreachable("Unknown RegisterClass!"); 916 } 917 } 918 919 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 920 921 int64_t LowerBound = 0; 922 923 // Take into account stack space reserved for tail calls. 924 int TCSPDelta = 0; 925 if (MF.getTarget().Options.GuaranteedTailCallOpt && 926 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 927 LowerBound = TCSPDelta; 928 } 929 930 // The Floating-point register save area is right below the back chain word 931 // of the previous stack frame. 932 if (HasFPSaveArea) { 933 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 934 int FI = FPRegs[i].getFrameIdx(); 935 936 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 937 } 938 939 LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8; 940 } 941 942 // Check whether the frame pointer register is allocated. If so, make sure it 943 // is spilled to the correct offset. 944 if (needsFP(MF)) { 945 HasGPSaveArea = true; 946 947 int FI = PFI->getFramePointerSaveIndex(); 948 assert(FI && "No Frame Pointer Save Slot!"); 949 950 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 951 } 952 953 // General register save area starts right below the Floating-point 954 // register save area. 955 if (HasGPSaveArea || HasG8SaveArea) { 956 // Move general register save area spill slots down, taking into account 957 // the size of the Floating-point register save area. 958 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 959 int FI = GPRegs[i].getFrameIdx(); 960 961 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 962 } 963 964 // Move general register save area spill slots down, taking into account 965 // the size of the Floating-point register save area. 966 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 967 int FI = G8Regs[i].getFrameIdx(); 968 969 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 970 } 971 972 unsigned MinReg = 973 std::min<unsigned>(getPPCRegisterNumbering(MinGPR), 974 getPPCRegisterNumbering(MinG8R)); 975 976 if (Subtarget.isPPC64()) { 977 LowerBound -= (31 - MinReg + 1) * 8; 978 } else { 979 LowerBound -= (31 - MinReg + 1) * 4; 980 } 981 } 982 983 // For 32-bit only, the CR save area is below the general register 984 // save area. For 64-bit SVR4, the CR save area is addressed relative 985 // to the stack pointer and hence does not need an adjustment here. 986 // Only CR2 (the first nonvolatile spilled) has an associated frame 987 // index so that we have a single uniform save area. 988 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 989 // Adjust the frame index of the CR spill slot. 990 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 991 unsigned Reg = CSI[i].getReg(); 992 993 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 994 // Leave Darwin logic as-is. 995 || (!Subtarget.isSVR4ABI() && 996 (PPC::CRBITRCRegClass.contains(Reg) || 997 PPC::CRRCRegClass.contains(Reg)))) { 998 int FI = CSI[i].getFrameIdx(); 999 1000 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1001 } 1002 } 1003 1004 LowerBound -= 4; // The CR save area is always 4 bytes long. 1005 } 1006 1007 if (HasVRSAVESaveArea) { 1008 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1009 // which have the VRSAVE register class? 1010 // Adjust the frame index of the VRSAVE spill slot. 1011 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1012 unsigned Reg = CSI[i].getReg(); 1013 1014 if (PPC::VRSAVERCRegClass.contains(Reg)) { 1015 int FI = CSI[i].getFrameIdx(); 1016 1017 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1018 } 1019 } 1020 1021 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1022 } 1023 1024 if (HasVRSaveArea) { 1025 // Insert alignment padding, we need 16-byte alignment. 1026 LowerBound = (LowerBound - 15) & ~(15); 1027 1028 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1029 int FI = VRegs[i].getFrameIdx(); 1030 1031 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1032 } 1033 } 1034} 1035 1036bool 1037PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1038 MachineBasicBlock::iterator MI, 1039 const std::vector<CalleeSavedInfo> &CSI, 1040 const TargetRegisterInfo *TRI) const { 1041 1042 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1043 // Return false otherwise to maintain pre-existing behavior. 1044 if (!Subtarget.isSVR4ABI()) 1045 return false; 1046 1047 MachineFunction *MF = MBB.getParent(); 1048 const PPCInstrInfo &TII = 1049 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1050 DebugLoc DL; 1051 bool CRSpilled = false; 1052 1053 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1054 unsigned Reg = CSI[i].getReg(); 1055 // CR2 through CR4 are the nonvolatile CR fields. 1056 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1057 1058 if (CRSpilled && IsCRField) 1059 continue; 1060 1061 // Add the callee-saved register as live-in; it's killed at the spill. 1062 MBB.addLiveIn(Reg); 1063 1064 // Insert the spill to the stack frame. 1065 if (IsCRField) { 1066 CRSpilled = true; 1067 // The first time we see a CR field, store the whole CR into the 1068 // save slot via GPR12 (available in the prolog for 32- and 64-bit). 1069 if (Subtarget.isPPC64()) { 1070 // 64-bit: SP+8 1071 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::X12)); 1072 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW)) 1073 .addReg(PPC::X12, 1074 getKillRegState(true)) 1075 .addImm(8) 1076 .addReg(PPC::X1)); 1077 } else { 1078 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1079 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1080 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)); 1081 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1082 .addReg(PPC::R12, 1083 getKillRegState(true)), 1084 CSI[i].getFrameIdx())); 1085 } 1086 1087 // Record that we spill the CR in this function. 1088 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1089 FuncInfo->setSpillsCR(); 1090 } else { 1091 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1092 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1093 CSI[i].getFrameIdx(), RC, TRI); 1094 } 1095 } 1096 return true; 1097} 1098 1099static void 1100restoreCRs(bool isPPC64, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1101 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1102 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1103 1104 MachineFunction *MF = MBB.getParent(); 1105 const PPCInstrInfo &TII = 1106 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1107 DebugLoc DL; 1108 unsigned RestoreOp, MoveReg; 1109 1110 if (isPPC64) { 1111 // 64-bit: SP+8 1112 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::LWZ), PPC::X12) 1113 .addImm(8) 1114 .addReg(PPC::X1)); 1115 RestoreOp = PPC::MTCRF8; 1116 MoveReg = PPC::X12; 1117 } else { 1118 // 32-bit: FP-relative 1119 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1120 PPC::R12), 1121 CSI[CSIIndex].getFrameIdx())); 1122 RestoreOp = PPC::MTCRF; 1123 MoveReg = PPC::R12; 1124 } 1125 1126 if (CR2Spilled) 1127 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1128 .addReg(MoveReg)); 1129 1130 if (CR3Spilled) 1131 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1132 .addReg(MoveReg)); 1133 1134 if (CR4Spilled) 1135 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1136 .addReg(MoveReg)); 1137} 1138 1139void PPCFrameLowering:: 1140eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1141 MachineBasicBlock::iterator I) const { 1142 const PPCInstrInfo &TII = 1143 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 1144 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1145 I->getOpcode() == PPC::ADJCALLSTACKUP) { 1146 // Add (actually subtract) back the amount the callee popped on return. 1147 if (int CalleeAmt = I->getOperand(1).getImm()) { 1148 bool is64Bit = Subtarget.isPPC64(); 1149 CalleeAmt *= -1; 1150 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1151 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1152 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1153 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1154 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1155 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1156 MachineInstr *MI = I; 1157 DebugLoc dl = MI->getDebugLoc(); 1158 1159 if (isInt<16>(CalleeAmt)) { 1160 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1161 .addReg(StackReg, RegState::Kill) 1162 .addImm(CalleeAmt); 1163 } else { 1164 MachineBasicBlock::iterator MBBI = I; 1165 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1166 .addImm(CalleeAmt >> 16); 1167 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1168 .addReg(TmpReg, RegState::Kill) 1169 .addImm(CalleeAmt & 0xFFFF); 1170 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1171 .addReg(StackReg, RegState::Kill) 1172 .addReg(TmpReg); 1173 } 1174 } 1175 } 1176 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1177 MBB.erase(I); 1178} 1179 1180bool 1181PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1182 MachineBasicBlock::iterator MI, 1183 const std::vector<CalleeSavedInfo> &CSI, 1184 const TargetRegisterInfo *TRI) const { 1185 1186 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1187 // Return false otherwise to maintain pre-existing behavior. 1188 if (!Subtarget.isSVR4ABI()) 1189 return false; 1190 1191 MachineFunction *MF = MBB.getParent(); 1192 const PPCInstrInfo &TII = 1193 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1194 bool CR2Spilled = false; 1195 bool CR3Spilled = false; 1196 bool CR4Spilled = false; 1197 unsigned CSIIndex = 0; 1198 1199 // Initialize insertion-point logic; we will be restoring in reverse 1200 // order of spill. 1201 MachineBasicBlock::iterator I = MI, BeforeI = I; 1202 bool AtStart = I == MBB.begin(); 1203 1204 if (!AtStart) 1205 --BeforeI; 1206 1207 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1208 unsigned Reg = CSI[i].getReg(); 1209 1210 if (Reg == PPC::CR2) { 1211 CR2Spilled = true; 1212 // The spill slot is associated only with CR2, which is the 1213 // first nonvolatile spilled. Save it here. 1214 CSIIndex = i; 1215 continue; 1216 } else if (Reg == PPC::CR3) { 1217 CR3Spilled = true; 1218 continue; 1219 } else if (Reg == PPC::CR4) { 1220 CR4Spilled = true; 1221 continue; 1222 } else { 1223 // When we first encounter a non-CR register after seeing at 1224 // least one CR register, restore all spilled CRs together. 1225 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1226 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1227 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled, 1228 MBB, I, CSI, CSIIndex); 1229 CR2Spilled = CR3Spilled = CR4Spilled = false; 1230 } 1231 1232 // Default behavior for non-CR saves. 1233 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1234 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1235 RC, TRI); 1236 assert(I != MBB.begin() && 1237 "loadRegFromStackSlot didn't insert any code!"); 1238 } 1239 1240 // Insert in reverse order. 1241 if (AtStart) 1242 I = MBB.begin(); 1243 else { 1244 I = BeforeI; 1245 ++I; 1246 } 1247 } 1248 1249 // If we haven't yet spilled the CRs, do so now. 1250 if (CR2Spilled || CR3Spilled || CR4Spilled) 1251 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled, 1252 MBB, I, CSI, CSIIndex); 1253 1254 return true; 1255} 1256 1257