PPCFrameLowering.cpp revision 4f28c1c71450c711e96aa283de53739d8b4504cd
1//=====- PPCFrameLowering.cpp - PPC Frame Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PPC implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCFrameLowering.h" 15#include "PPCInstrInfo.h" 16#include "PPCMachineFunctionInfo.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/MachineModuleInfo.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/RegisterScavenging.h" 24#include "llvm/Target/TargetOptions.h" 25 26using namespace llvm; 27 28// FIXME This disables some code that aligns the stack to a boundary bigger than 29// the default (16 bytes on Darwin) when there is a stack local of greater 30// alignment. This does not currently work, because the delta between old and 31// new stack pointers is added to offsets that reference incoming parameters 32// after the prolog is generated, and the code that does that doesn't handle a 33// variable delta. You don't want to do that anyway; a better approach is to 34// reserve another register that retains to the incoming stack pointer, and 35// reference parameters relative to that. 36#define ALIGN_STACK 0 37 38 39/// VRRegNo - Map from a numbered VR register to its enum value. 40/// 41static const unsigned short VRRegNo[] = { 42 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 43 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 44 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 45 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 46}; 47 48/// RemoveVRSaveCode - We have found that this function does not need any code 49/// to manipulate the VRSAVE register, even though it uses vector registers. 50/// This can happen when the only registers used are known to be live in or out 51/// of the function. Remove all of the VRSAVE related code from the function. 52static void RemoveVRSaveCode(MachineInstr *MI) { 53 MachineBasicBlock *Entry = MI->getParent(); 54 MachineFunction *MF = Entry->getParent(); 55 56 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 57 MachineBasicBlock::iterator MBBI = MI; 58 ++MBBI; 59 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 60 MBBI->eraseFromParent(); 61 62 bool RemovedAllMTVRSAVEs = true; 63 // See if we can find and remove the MTVRSAVE instruction from all of the 64 // epilog blocks. 65 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 66 // If last instruction is a return instruction, add an epilogue 67 if (!I->empty() && I->back().getDesc().isReturn()) { 68 bool FoundIt = false; 69 for (MBBI = I->end(); MBBI != I->begin(); ) { 70 --MBBI; 71 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 72 MBBI->eraseFromParent(); // remove it. 73 FoundIt = true; 74 break; 75 } 76 } 77 RemovedAllMTVRSAVEs &= FoundIt; 78 } 79 } 80 81 // If we found and removed all MTVRSAVE instructions, remove the read of 82 // VRSAVE as well. 83 if (RemovedAllMTVRSAVEs) { 84 MBBI = MI; 85 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 86 --MBBI; 87 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 88 MBBI->eraseFromParent(); 89 } 90 91 // Finally, nuke the UPDATE_VRSAVE. 92 MI->eraseFromParent(); 93} 94 95// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 96// instruction selector. Based on the vector registers that have been used, 97// transform this into the appropriate ORI instruction. 98static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 99 MachineFunction *MF = MI->getParent()->getParent(); 100 DebugLoc dl = MI->getDebugLoc(); 101 102 unsigned UsedRegMask = 0; 103 for (unsigned i = 0; i != 32; ++i) 104 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 105 UsedRegMask |= 1 << (31-i); 106 107 // Live in and live out values already must be in the mask, so don't bother 108 // marking them. 109 for (MachineRegisterInfo::livein_iterator 110 I = MF->getRegInfo().livein_begin(), 111 E = MF->getRegInfo().livein_end(); I != E; ++I) { 112 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); 113 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 114 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 115 } 116 for (MachineRegisterInfo::liveout_iterator 117 I = MF->getRegInfo().liveout_begin(), 118 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 119 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); 120 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 121 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 122 } 123 124 // If no registers are used, turn this into a copy. 125 if (UsedRegMask == 0) { 126 // Remove all VRSAVE code. 127 RemoveVRSaveCode(MI); 128 return; 129 } 130 131 unsigned SrcReg = MI->getOperand(1).getReg(); 132 unsigned DstReg = MI->getOperand(0).getReg(); 133 134 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 135 if (DstReg != SrcReg) 136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 137 .addReg(SrcReg) 138 .addImm(UsedRegMask); 139 else 140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 141 .addReg(SrcReg, RegState::Kill) 142 .addImm(UsedRegMask); 143 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 144 if (DstReg != SrcReg) 145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 146 .addReg(SrcReg) 147 .addImm(UsedRegMask >> 16); 148 else 149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 150 .addReg(SrcReg, RegState::Kill) 151 .addImm(UsedRegMask >> 16); 152 } else { 153 if (DstReg != SrcReg) 154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 155 .addReg(SrcReg) 156 .addImm(UsedRegMask >> 16); 157 else 158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 159 .addReg(SrcReg, RegState::Kill) 160 .addImm(UsedRegMask >> 16); 161 162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 163 .addReg(DstReg, RegState::Kill) 164 .addImm(UsedRegMask & 0xFFFF); 165 } 166 167 // Remove the old UPDATE_VRSAVE instruction. 168 MI->eraseFromParent(); 169} 170 171/// determineFrameLayout - Determine the size of the frame and maximum call 172/// frame size. 173void PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const { 174 MachineFrameInfo *MFI = MF.getFrameInfo(); 175 176 // Get the number of bytes to allocate from the FrameInfo 177 unsigned FrameSize = MFI->getStackSize(); 178 179 // Get the alignments provided by the target, and the maximum alignment 180 // (if any) of the fixed frame objects. 181 unsigned MaxAlign = MFI->getMaxAlignment(); 182 unsigned TargetAlign = getStackAlignment(); 183 unsigned AlignMask = TargetAlign - 1; // 184 185 // If we are a leaf function, and use up to 224 bytes of stack space, 186 // don't have a frame pointer, calls, or dynamic alloca then we do not need 187 // to adjust the stack pointer (we fit in the Red Zone). 188 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone); 189 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. 190 if (!DisableRedZone && 191 FrameSize <= 224 && // Fits in red zone. 192 !MFI->hasVarSizedObjects() && // No dynamic alloca. 193 !MFI->adjustsStack() && // No calls. 194 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 195 // No need for frame 196 MFI->setStackSize(0); 197 return; 198 } 199 200 // Get the maximum call frame size of all the calls. 201 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 202 203 // Maximum call frame needs to be at least big enough for linkage and 8 args. 204 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 205 Subtarget.isDarwinABI()); 206 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 207 208 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 209 // that allocations will be aligned. 210 if (MFI->hasVarSizedObjects()) 211 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 212 213 // Update maximum call frame size. 214 MFI->setMaxCallFrameSize(maxCallFrameSize); 215 216 // Include call frame size in total. 217 FrameSize += maxCallFrameSize; 218 219 // Make sure the frame is aligned. 220 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 221 222 // Update frame info. 223 MFI->setStackSize(FrameSize); 224} 225 226// hasFP - Return true if the specified function actually has a dedicated frame 227// pointer register. 228bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 229 const MachineFrameInfo *MFI = MF.getFrameInfo(); 230 // FIXME: This is pretty much broken by design: hasFP() might be called really 231 // early, before the stack layout was calculated and thus hasFP() might return 232 // true or false here depending on the time of call. 233 return (MFI->getStackSize()) && needsFP(MF); 234} 235 236// needsFP - Return true if the specified function should have a dedicated frame 237// pointer register. This is true if the function has variable sized allocas or 238// if frame pointer elimination is disabled. 239bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 240 const MachineFrameInfo *MFI = MF.getFrameInfo(); 241 242 // Naked functions have no stack frame pushed, so we don't have a frame 243 // pointer. 244 if (MF.getFunction()->hasFnAttr(Attribute::Naked)) 245 return false; 246 247 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() || 248 (GuaranteedTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 249} 250 251 252void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 253 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 254 MachineBasicBlock::iterator MBBI = MBB.begin(); 255 MachineFrameInfo *MFI = MF.getFrameInfo(); 256 const PPCInstrInfo &TII = 257 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 258 259 MachineModuleInfo &MMI = MF.getMMI(); 260 DebugLoc dl; 261 bool needsFrameMoves = MMI.hasDebugInfo() || 262 !MF.getFunction()->doesNotThrow() || 263 UnwindTablesMandatory; 264 265 // Prepare for frame info. 266 MCSymbol *FrameLabel = 0; 267 268 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 269 // process it. 270 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 271 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 272 HandleVRSaveUpdate(MBBI, TII); 273 break; 274 } 275 } 276 277 // Move MBBI back to the beginning of the function. 278 MBBI = MBB.begin(); 279 280 // Work out frame sizes. 281 // FIXME: determineFrameLayout() may change the frame size. This should be 282 // moved upper, to some hook. 283 determineFrameLayout(MF); 284 unsigned FrameSize = MFI->getStackSize(); 285 286 int NegFrameSize = -FrameSize; 287 288 // Get processor type. 289 bool isPPC64 = Subtarget.isPPC64(); 290 // Get operating system 291 bool isDarwinABI = Subtarget.isDarwinABI(); 292 // Check if the link register (LR) must be saved. 293 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 294 bool MustSaveLR = FI->mustSaveLR(); 295 // Do we have a frame pointer for this function? 296 bool HasFP = hasFP(MF); 297 298 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 299 300 int FPOffset = 0; 301 if (HasFP) { 302 if (Subtarget.isSVR4ABI()) { 303 MachineFrameInfo *FFI = MF.getFrameInfo(); 304 int FPIndex = FI->getFramePointerSaveIndex(); 305 assert(FPIndex && "No Frame Pointer Save Slot!"); 306 FPOffset = FFI->getObjectOffset(FPIndex); 307 } else { 308 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 309 } 310 } 311 312 if (isPPC64) { 313 if (MustSaveLR) 314 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 315 316 if (HasFP) 317 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 318 .addReg(PPC::X31) 319 .addImm(FPOffset/4) 320 .addReg(PPC::X1); 321 322 if (MustSaveLR) 323 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 324 .addReg(PPC::X0) 325 .addImm(LROffset / 4) 326 .addReg(PPC::X1); 327 } else { 328 if (MustSaveLR) 329 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 330 331 if (HasFP) 332 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 333 .addReg(PPC::R31) 334 .addImm(FPOffset) 335 .addReg(PPC::R1); 336 337 if (MustSaveLR) 338 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 339 .addReg(PPC::R0) 340 .addImm(LROffset) 341 .addReg(PPC::R1); 342 } 343 344 // Skip if a leaf routine. 345 if (!FrameSize) return; 346 347 // Get stack alignments. 348 unsigned TargetAlign = getStackAlignment(); 349 unsigned MaxAlign = MFI->getMaxAlignment(); 350 351 // Adjust stack pointer: r1 += NegFrameSize. 352 // If there is a preferred stack alignment, align R1 now 353 if (!isPPC64) { 354 // PPC32. 355 if (ALIGN_STACK && MaxAlign > TargetAlign) { 356 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 357 "Invalid alignment!"); 358 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 359 360 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 361 .addReg(PPC::R1) 362 .addImm(0) 363 .addImm(32 - Log2_32(MaxAlign)) 364 .addImm(31); 365 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 366 .addReg(PPC::R0, RegState::Kill) 367 .addImm(NegFrameSize); 368 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 369 .addReg(PPC::R1) 370 .addReg(PPC::R1) 371 .addReg(PPC::R0); 372 } else if (isInt<16>(NegFrameSize)) { 373 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 374 .addReg(PPC::R1) 375 .addImm(NegFrameSize) 376 .addReg(PPC::R1); 377 } else { 378 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 379 .addImm(NegFrameSize >> 16); 380 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 381 .addReg(PPC::R0, RegState::Kill) 382 .addImm(NegFrameSize & 0xFFFF); 383 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) 384 .addReg(PPC::R1) 385 .addReg(PPC::R1) 386 .addReg(PPC::R0); 387 } 388 } else { // PPC64. 389 if (ALIGN_STACK && MaxAlign > TargetAlign) { 390 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 391 "Invalid alignment!"); 392 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 393 394 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 395 .addReg(PPC::X1) 396 .addImm(0) 397 .addImm(64 - Log2_32(MaxAlign)); 398 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 399 .addReg(PPC::X0) 400 .addImm(NegFrameSize); 401 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 402 .addReg(PPC::X1) 403 .addReg(PPC::X1) 404 .addReg(PPC::X0); 405 } else if (isInt<16>(NegFrameSize)) { 406 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 407 .addReg(PPC::X1) 408 .addImm(NegFrameSize / 4) 409 .addReg(PPC::X1); 410 } else { 411 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 412 .addImm(NegFrameSize >> 16); 413 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 414 .addReg(PPC::X0, RegState::Kill) 415 .addImm(NegFrameSize & 0xFFFF); 416 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) 417 .addReg(PPC::X1) 418 .addReg(PPC::X1) 419 .addReg(PPC::X0); 420 } 421 } 422 423 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 424 425 // Add the "machine moves" for the instructions we generated above, but in 426 // reverse order. 427 if (needsFrameMoves) { 428 // Mark effective beginning of when frame pointer becomes valid. 429 FrameLabel = MMI.getContext().CreateTempSymbol(); 430 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 431 432 // Show update of SP. 433 if (NegFrameSize) { 434 MachineLocation SPDst(MachineLocation::VirtualFP); 435 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 436 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 437 } else { 438 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 439 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 440 } 441 442 if (HasFP) { 443 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 444 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 445 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 446 } 447 448 if (MustSaveLR) { 449 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 450 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 451 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 452 } 453 } 454 455 MCSymbol *ReadyLabel = 0; 456 457 // If there is a frame pointer, copy R1 into R31 458 if (HasFP) { 459 if (!isPPC64) { 460 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 461 .addReg(PPC::R1) 462 .addReg(PPC::R1); 463 } else { 464 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 465 .addReg(PPC::X1) 466 .addReg(PPC::X1); 467 } 468 469 if (needsFrameMoves) { 470 ReadyLabel = MMI.getContext().CreateTempSymbol(); 471 472 // Mark effective beginning of when frame pointer is ready. 473 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 474 475 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 476 (isPPC64 ? PPC::X1 : PPC::R1)); 477 MachineLocation FPSrc(MachineLocation::VirtualFP); 478 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 479 } 480 } 481 482 if (needsFrameMoves) { 483 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 484 485 // Add callee saved registers to move list. 486 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 487 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 488 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 489 unsigned Reg = CSI[I].getReg(); 490 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 491 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 492 MachineLocation CSSrc(Reg); 493 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 494 } 495 } 496} 497 498void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 499 MachineBasicBlock &MBB) const { 500 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 501 assert(MBBI != MBB.end() && "Returning block has no terminator"); 502 const PPCInstrInfo &TII = 503 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 504 505 unsigned RetOpcode = MBBI->getOpcode(); 506 DebugLoc dl; 507 508 assert((RetOpcode == PPC::BLR || 509 RetOpcode == PPC::TCRETURNri || 510 RetOpcode == PPC::TCRETURNdi || 511 RetOpcode == PPC::TCRETURNai || 512 RetOpcode == PPC::TCRETURNri8 || 513 RetOpcode == PPC::TCRETURNdi8 || 514 RetOpcode == PPC::TCRETURNai8) && 515 "Can only insert epilog into returning blocks"); 516 517 // Get alignment info so we know how to restore r1 518 const MachineFrameInfo *MFI = MF.getFrameInfo(); 519 unsigned TargetAlign = getStackAlignment(); 520 unsigned MaxAlign = MFI->getMaxAlignment(); 521 522 // Get the number of bytes allocated from the FrameInfo. 523 int FrameSize = MFI->getStackSize(); 524 525 // Get processor type. 526 bool isPPC64 = Subtarget.isPPC64(); 527 // Get operating system 528 bool isDarwinABI = Subtarget.isDarwinABI(); 529 // Check if the link register (LR) has been saved. 530 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 531 bool MustSaveLR = FI->mustSaveLR(); 532 // Do we have a frame pointer for this function? 533 bool HasFP = hasFP(MF); 534 535 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 536 537 int FPOffset = 0; 538 if (HasFP) { 539 if (Subtarget.isSVR4ABI()) { 540 MachineFrameInfo *FFI = MF.getFrameInfo(); 541 int FPIndex = FI->getFramePointerSaveIndex(); 542 assert(FPIndex && "No Frame Pointer Save Slot!"); 543 FPOffset = FFI->getObjectOffset(FPIndex); 544 } else { 545 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 546 } 547 } 548 549 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 550 RetOpcode == PPC::TCRETURNdi || 551 RetOpcode == PPC::TCRETURNai || 552 RetOpcode == PPC::TCRETURNri8 || 553 RetOpcode == PPC::TCRETURNdi8 || 554 RetOpcode == PPC::TCRETURNai8; 555 556 if (UsesTCRet) { 557 int MaxTCRetDelta = FI->getTailCallSPDelta(); 558 MachineOperand &StackAdjust = MBBI->getOperand(1); 559 assert(StackAdjust.isImm() && "Expecting immediate value."); 560 // Adjust stack pointer. 561 int StackAdj = StackAdjust.getImm(); 562 int Delta = StackAdj - MaxTCRetDelta; 563 assert((Delta >= 0) && "Delta must be positive"); 564 if (MaxTCRetDelta>0) 565 FrameSize += (StackAdj +Delta); 566 else 567 FrameSize += StackAdj; 568 } 569 570 if (FrameSize) { 571 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 572 // on entry to the function. Add this offset back now. 573 if (!isPPC64) { 574 // If this function contained a fastcc call and GuaranteedTailCallOpt is 575 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 576 // call which invalidates the stack pointer value in SP(0). So we use the 577 // value of R31 in this case. 578 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 579 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 580 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 581 .addReg(PPC::R31).addImm(FrameSize); 582 } else if(FI->hasFastCall()) { 583 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 584 .addImm(FrameSize >> 16); 585 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 586 .addReg(PPC::R0, RegState::Kill) 587 .addImm(FrameSize & 0xFFFF); 588 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 589 .addReg(PPC::R1) 590 .addReg(PPC::R31) 591 .addReg(PPC::R0); 592 } else if (isInt<16>(FrameSize) && 593 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 594 !MFI->hasVarSizedObjects()) { 595 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 596 .addReg(PPC::R1).addImm(FrameSize); 597 } else { 598 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 599 .addImm(0).addReg(PPC::R1); 600 } 601 } else { 602 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 603 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 604 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 605 .addReg(PPC::X31).addImm(FrameSize); 606 } else if(FI->hasFastCall()) { 607 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 608 .addImm(FrameSize >> 16); 609 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 610 .addReg(PPC::X0, RegState::Kill) 611 .addImm(FrameSize & 0xFFFF); 612 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 613 .addReg(PPC::X1) 614 .addReg(PPC::X31) 615 .addReg(PPC::X0); 616 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 617 !MFI->hasVarSizedObjects()) { 618 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 619 .addReg(PPC::X1).addImm(FrameSize); 620 } else { 621 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 622 .addImm(0).addReg(PPC::X1); 623 } 624 } 625 } 626 627 if (isPPC64) { 628 if (MustSaveLR) 629 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 630 .addImm(LROffset/4).addReg(PPC::X1); 631 632 if (HasFP) 633 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 634 .addImm(FPOffset/4).addReg(PPC::X1); 635 636 if (MustSaveLR) 637 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 638 } else { 639 if (MustSaveLR) 640 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 641 .addImm(LROffset).addReg(PPC::R1); 642 643 if (HasFP) 644 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 645 .addImm(FPOffset).addReg(PPC::R1); 646 647 if (MustSaveLR) 648 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 649 } 650 651 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 652 // call optimization 653 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 654 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 655 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 656 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 657 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 658 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 659 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 660 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 661 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 662 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 663 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 664 665 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 666 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 667 .addReg(StackReg).addImm(CallerAllocatedAmt); 668 } else { 669 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 670 .addImm(CallerAllocatedAmt >> 16); 671 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 672 .addReg(TmpReg, RegState::Kill) 673 .addImm(CallerAllocatedAmt & 0xFFFF); 674 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 675 .addReg(StackReg) 676 .addReg(FPReg) 677 .addReg(TmpReg); 678 } 679 } else if (RetOpcode == PPC::TCRETURNdi) { 680 MBBI = MBB.getLastNonDebugInstr(); 681 MachineOperand &JumpTarget = MBBI->getOperand(0); 682 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 683 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 684 } else if (RetOpcode == PPC::TCRETURNri) { 685 MBBI = MBB.getLastNonDebugInstr(); 686 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 687 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 688 } else if (RetOpcode == PPC::TCRETURNai) { 689 MBBI = MBB.getLastNonDebugInstr(); 690 MachineOperand &JumpTarget = MBBI->getOperand(0); 691 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 692 } else if (RetOpcode == PPC::TCRETURNdi8) { 693 MBBI = MBB.getLastNonDebugInstr(); 694 MachineOperand &JumpTarget = MBBI->getOperand(0); 695 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 696 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 697 } else if (RetOpcode == PPC::TCRETURNri8) { 698 MBBI = MBB.getLastNonDebugInstr(); 699 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 700 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 701 } else if (RetOpcode == PPC::TCRETURNai8) { 702 MBBI = MBB.getLastNonDebugInstr(); 703 MachineOperand &JumpTarget = MBBI->getOperand(0); 704 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 705 } 706} 707 708void PPCFrameLowering::getInitialFrameState(std::vector<MachineMove> &Moves) const { 709 // Initial state of the frame pointer is R1. 710 MachineLocation Dst(MachineLocation::VirtualFP); 711 MachineLocation Src(PPC::R1, 0); 712 Moves.push_back(MachineMove(0, Dst, Src)); 713} 714 715static bool spillsCR(const MachineFunction &MF) { 716 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 717 return FuncInfo->isCRSpilled(); 718} 719 720/// MustSaveLR - Return true if this function requires that we save the LR 721/// register onto the stack in the prolog and restore it in the epilog of the 722/// function. 723static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 724 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 725 726 // We need a save/restore of LR if there is any def of LR (which is 727 // defined by calls, including the PIC setup sequence), or if there is 728 // some use of the LR stack slot (e.g. for builtin_return_address). 729 // (LR comes in 32 and 64 bit versions.) 730 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 731 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 732} 733 734void 735PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 736 RegScavenger *RS) const { 737 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 738 739 // Save and clear the LR state. 740 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 741 unsigned LR = RegInfo->getRARegister(); 742 FI->setMustSaveLR(MustSaveLR(MF, LR)); 743 MF.getRegInfo().setPhysRegUnused(LR); 744 745 // Save R31 if necessary 746 int FPSI = FI->getFramePointerSaveIndex(); 747 bool isPPC64 = Subtarget.isPPC64(); 748 bool isDarwinABI = Subtarget.isDarwinABI(); 749 MachineFrameInfo *MFI = MF.getFrameInfo(); 750 751 // If the frame pointer save index hasn't been defined yet. 752 if (!FPSI && needsFP(MF)) { 753 // Find out what the fix offset of the frame pointer save area. 754 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 755 // Allocate the frame index for frame pointer save area. 756 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 757 // Save the result. 758 FI->setFramePointerSaveIndex(FPSI); 759 } 760 761 // Reserve stack space to move the linkage area to in case of a tail call. 762 int TCSPDelta = 0; 763 if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 764 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 765 } 766 767 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 768 // a large stack, which will require scavenging a register to materialize a 769 // large offset. 770 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 771 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 772 // r0 for now. 773 774 if (RegInfo->requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable. 775 if (needsFP(MF) || spillsCR(MF)) { 776 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 777 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 778 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 779 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 780 RC->getAlignment(), 781 false)); 782 } 783} 784 785void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF) 786 const { 787 // Early exit if not using the SVR4 ABI. 788 if (!Subtarget.isSVR4ABI()) 789 return; 790 791 // Get callee saved register information. 792 MachineFrameInfo *FFI = MF.getFrameInfo(); 793 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 794 795 // Early exit if no callee saved registers are modified! 796 if (CSI.empty() && !needsFP(MF)) { 797 return; 798 } 799 800 unsigned MinGPR = PPC::R31; 801 unsigned MinG8R = PPC::X31; 802 unsigned MinFPR = PPC::F31; 803 unsigned MinVR = PPC::V31; 804 805 bool HasGPSaveArea = false; 806 bool HasG8SaveArea = false; 807 bool HasFPSaveArea = false; 808 bool HasCRSaveArea = false; 809 bool HasVRSAVESaveArea = false; 810 bool HasVRSaveArea = false; 811 812 SmallVector<CalleeSavedInfo, 18> GPRegs; 813 SmallVector<CalleeSavedInfo, 18> G8Regs; 814 SmallVector<CalleeSavedInfo, 18> FPRegs; 815 SmallVector<CalleeSavedInfo, 18> VRegs; 816 817 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 818 unsigned Reg = CSI[i].getReg(); 819 if (PPC::GPRCRegisterClass->contains(Reg)) { 820 HasGPSaveArea = true; 821 822 GPRegs.push_back(CSI[i]); 823 824 if (Reg < MinGPR) { 825 MinGPR = Reg; 826 } 827 } else if (PPC::G8RCRegisterClass->contains(Reg)) { 828 HasG8SaveArea = true; 829 830 G8Regs.push_back(CSI[i]); 831 832 if (Reg < MinG8R) { 833 MinG8R = Reg; 834 } 835 } else if (PPC::F8RCRegisterClass->contains(Reg)) { 836 HasFPSaveArea = true; 837 838 FPRegs.push_back(CSI[i]); 839 840 if (Reg < MinFPR) { 841 MinFPR = Reg; 842 } 843// FIXME SVR4: Disable CR save area for now. 844 } else if (PPC::CRBITRCRegisterClass->contains(Reg) 845 || PPC::CRRCRegisterClass->contains(Reg)) { 846// HasCRSaveArea = true; 847 } else if (PPC::VRSAVERCRegisterClass->contains(Reg)) { 848 HasVRSAVESaveArea = true; 849 } else if (PPC::VRRCRegisterClass->contains(Reg)) { 850 HasVRSaveArea = true; 851 852 VRegs.push_back(CSI[i]); 853 854 if (Reg < MinVR) { 855 MinVR = Reg; 856 } 857 } else { 858 llvm_unreachable("Unknown RegisterClass!"); 859 } 860 } 861 862 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 863 864 int64_t LowerBound = 0; 865 866 // Take into account stack space reserved for tail calls. 867 int TCSPDelta = 0; 868 if (GuaranteedTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 869 LowerBound = TCSPDelta; 870 } 871 872 // The Floating-point register save area is right below the back chain word 873 // of the previous stack frame. 874 if (HasFPSaveArea) { 875 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 876 int FI = FPRegs[i].getFrameIdx(); 877 878 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 879 } 880 881 LowerBound -= (31 - PPCRegisterInfo::getRegisterNumbering(MinFPR) + 1) * 8; 882 } 883 884 // Check whether the frame pointer register is allocated. If so, make sure it 885 // is spilled to the correct offset. 886 if (needsFP(MF)) { 887 HasGPSaveArea = true; 888 889 int FI = PFI->getFramePointerSaveIndex(); 890 assert(FI && "No Frame Pointer Save Slot!"); 891 892 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 893 } 894 895 // General register save area starts right below the Floating-point 896 // register save area. 897 if (HasGPSaveArea || HasG8SaveArea) { 898 // Move general register save area spill slots down, taking into account 899 // the size of the Floating-point register save area. 900 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 901 int FI = GPRegs[i].getFrameIdx(); 902 903 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 904 } 905 906 // Move general register save area spill slots down, taking into account 907 // the size of the Floating-point register save area. 908 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 909 int FI = G8Regs[i].getFrameIdx(); 910 911 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 912 } 913 914 unsigned MinReg = 915 std::min<unsigned>(PPCRegisterInfo::getRegisterNumbering(MinGPR), 916 PPCRegisterInfo::getRegisterNumbering(MinG8R)); 917 918 if (Subtarget.isPPC64()) { 919 LowerBound -= (31 - MinReg + 1) * 8; 920 } else { 921 LowerBound -= (31 - MinReg + 1) * 4; 922 } 923 } 924 925 // The CR save area is below the general register save area. 926 if (HasCRSaveArea) { 927 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 928 // which have the CR/CRBIT register class? 929 // Adjust the frame index of the CR spill slot. 930 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 931 unsigned Reg = CSI[i].getReg(); 932 933 if (PPC::CRBITRCRegisterClass->contains(Reg) || 934 PPC::CRRCRegisterClass->contains(Reg)) { 935 int FI = CSI[i].getFrameIdx(); 936 937 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 938 } 939 } 940 941 LowerBound -= 4; // The CR save area is always 4 bytes long. 942 } 943 944 if (HasVRSAVESaveArea) { 945 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 946 // which have the VRSAVE register class? 947 // Adjust the frame index of the VRSAVE spill slot. 948 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 949 unsigned Reg = CSI[i].getReg(); 950 951 if (PPC::VRSAVERCRegisterClass->contains(Reg)) { 952 int FI = CSI[i].getFrameIdx(); 953 954 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 955 } 956 } 957 958 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 959 } 960 961 if (HasVRSaveArea) { 962 // Insert alignment padding, we need 16-byte alignment. 963 LowerBound = (LowerBound - 15) & ~(15); 964 965 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 966 int FI = VRegs[i].getFrameIdx(); 967 968 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 969 } 970 } 971} 972