PPCFrameLowering.cpp revision 6765834754cbb3cb0f15b4b15e98c5e73fa50066
1//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PPC implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCFrameLowering.h" 15#include "PPCInstrInfo.h" 16#include "PPCInstrBuilder.h" 17#include "PPCMachineFunctionInfo.h" 18#include "llvm/Function.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineModuleInfo.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/RegisterScavenging.h" 25#include "llvm/Target/TargetOptions.h" 26 27using namespace llvm; 28 29// FIXME This disables some code that aligns the stack to a boundary bigger than 30// the default (16 bytes on Darwin) when there is a stack local of greater 31// alignment. This does not currently work, because the delta between old and 32// new stack pointers is added to offsets that reference incoming parameters 33// after the prolog is generated, and the code that does that doesn't handle a 34// variable delta. You don't want to do that anyway; a better approach is to 35// reserve another register that retains to the incoming stack pointer, and 36// reference parameters relative to that. 37#define ALIGN_STACK 0 38 39 40/// VRRegNo - Map from a numbered VR register to its enum value. 41/// 42static const uint16_t VRRegNo[] = { 43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 47}; 48 49/// RemoveVRSaveCode - We have found that this function does not need any code 50/// to manipulate the VRSAVE register, even though it uses vector registers. 51/// This can happen when the only registers used are known to be live in or out 52/// of the function. Remove all of the VRSAVE related code from the function. 53static void RemoveVRSaveCode(MachineInstr *MI) { 54 MachineBasicBlock *Entry = MI->getParent(); 55 MachineFunction *MF = Entry->getParent(); 56 57 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 58 MachineBasicBlock::iterator MBBI = MI; 59 ++MBBI; 60 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 61 MBBI->eraseFromParent(); 62 63 bool RemovedAllMTVRSAVEs = true; 64 // See if we can find and remove the MTVRSAVE instruction from all of the 65 // epilog blocks. 66 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 67 // If last instruction is a return instruction, add an epilogue 68 if (!I->empty() && I->back().isReturn()) { 69 bool FoundIt = false; 70 for (MBBI = I->end(); MBBI != I->begin(); ) { 71 --MBBI; 72 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 73 MBBI->eraseFromParent(); // remove it. 74 FoundIt = true; 75 break; 76 } 77 } 78 RemovedAllMTVRSAVEs &= FoundIt; 79 } 80 } 81 82 // If we found and removed all MTVRSAVE instructions, remove the read of 83 // VRSAVE as well. 84 if (RemovedAllMTVRSAVEs) { 85 MBBI = MI; 86 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 87 --MBBI; 88 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 89 MBBI->eraseFromParent(); 90 } 91 92 // Finally, nuke the UPDATE_VRSAVE. 93 MI->eraseFromParent(); 94} 95 96// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 97// instruction selector. Based on the vector registers that have been used, 98// transform this into the appropriate ORI instruction. 99static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 100 MachineFunction *MF = MI->getParent()->getParent(); 101 DebugLoc dl = MI->getDebugLoc(); 102 103 unsigned UsedRegMask = 0; 104 for (unsigned i = 0; i != 32; ++i) 105 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 106 UsedRegMask |= 1 << (31-i); 107 108 // Live in and live out values already must be in the mask, so don't bother 109 // marking them. 110 for (MachineRegisterInfo::livein_iterator 111 I = MF->getRegInfo().livein_begin(), 112 E = MF->getRegInfo().livein_end(); I != E; ++I) { 113 unsigned RegNo = getPPCRegisterNumbering(I->first); 114 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 115 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 116 } 117 for (MachineRegisterInfo::liveout_iterator 118 I = MF->getRegInfo().liveout_begin(), 119 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 120 unsigned RegNo = getPPCRegisterNumbering(*I); 121 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 122 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 123 } 124 125 // If no registers are used, turn this into a copy. 126 if (UsedRegMask == 0) { 127 // Remove all VRSAVE code. 128 RemoveVRSaveCode(MI); 129 return; 130 } 131 132 unsigned SrcReg = MI->getOperand(1).getReg(); 133 unsigned DstReg = MI->getOperand(0).getReg(); 134 135 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 136 if (DstReg != SrcReg) 137 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 138 .addReg(SrcReg) 139 .addImm(UsedRegMask); 140 else 141 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 142 .addReg(SrcReg, RegState::Kill) 143 .addImm(UsedRegMask); 144 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 145 if (DstReg != SrcReg) 146 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 147 .addReg(SrcReg) 148 .addImm(UsedRegMask >> 16); 149 else 150 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 151 .addReg(SrcReg, RegState::Kill) 152 .addImm(UsedRegMask >> 16); 153 } else { 154 if (DstReg != SrcReg) 155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 156 .addReg(SrcReg) 157 .addImm(UsedRegMask >> 16); 158 else 159 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 160 .addReg(SrcReg, RegState::Kill) 161 .addImm(UsedRegMask >> 16); 162 163 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 164 .addReg(DstReg, RegState::Kill) 165 .addImm(UsedRegMask & 0xFFFF); 166 } 167 168 // Remove the old UPDATE_VRSAVE instruction. 169 MI->eraseFromParent(); 170} 171 172static bool spillsCR(const MachineFunction &MF) { 173 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 174 return FuncInfo->isCRSpilled(); 175} 176 177/// determineFrameLayout - Determine the size of the frame and maximum call 178/// frame size. 179void PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const { 180 MachineFrameInfo *MFI = MF.getFrameInfo(); 181 182 // Get the number of bytes to allocate from the FrameInfo 183 unsigned FrameSize = MFI->getStackSize(); 184 185 // Get the alignments provided by the target, and the maximum alignment 186 // (if any) of the fixed frame objects. 187 unsigned MaxAlign = MFI->getMaxAlignment(); 188 unsigned TargetAlign = getStackAlignment(); 189 unsigned AlignMask = TargetAlign - 1; // 190 191 // If we are a leaf function, and use up to 224 bytes of stack space, 192 // don't have a frame pointer, calls, or dynamic alloca then we do not need 193 // to adjust the stack pointer (we fit in the Red Zone). For 64-bit 194 // SVR4, we also require a stack frame if we need to spill the CR, 195 // since this spill area is addressed relative to the stack pointer. 196 bool DisableRedZone = MF.getFunction()->getFnAttributes(). 197 hasAttribute(Attributes::NoRedZone); 198 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. However, it can 199 // still generate stackless code if all local vars are reg-allocated. 200 // Try: (FrameSize <= 224 201 // || (FrameSize == 0 && Subtarget.isPPC32 && Subtarget.isSVR4ABI())) 202 if (!DisableRedZone && 203 FrameSize <= 224 && // Fits in red zone. 204 !MFI->hasVarSizedObjects() && // No dynamic alloca. 205 !MFI->adjustsStack() && // No calls. 206 !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave. 207 Subtarget.isSVR4ABI() 208 && spillsCR(MF)) && 209 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 210 // No need for frame 211 MFI->setStackSize(0); 212 return; 213 } 214 215 // Get the maximum call frame size of all the calls. 216 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 217 218 // Maximum call frame needs to be at least big enough for linkage and 8 args. 219 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 220 Subtarget.isDarwinABI()); 221 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 222 223 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 224 // that allocations will be aligned. 225 if (MFI->hasVarSizedObjects()) 226 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 227 228 // Update maximum call frame size. 229 MFI->setMaxCallFrameSize(maxCallFrameSize); 230 231 // Include call frame size in total. 232 FrameSize += maxCallFrameSize; 233 234 // Make sure the frame is aligned. 235 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 236 237 // Update frame info. 238 MFI->setStackSize(FrameSize); 239} 240 241// hasFP - Return true if the specified function actually has a dedicated frame 242// pointer register. 243bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 244 const MachineFrameInfo *MFI = MF.getFrameInfo(); 245 // FIXME: This is pretty much broken by design: hasFP() might be called really 246 // early, before the stack layout was calculated and thus hasFP() might return 247 // true or false here depending on the time of call. 248 return (MFI->getStackSize()) && needsFP(MF); 249} 250 251// needsFP - Return true if the specified function should have a dedicated frame 252// pointer register. This is true if the function has variable sized allocas or 253// if frame pointer elimination is disabled. 254bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 255 const MachineFrameInfo *MFI = MF.getFrameInfo(); 256 257 // Naked functions have no stack frame pushed, so we don't have a frame 258 // pointer. 259 if (MF.getFunction()->getFnAttributes().hasAttribute(Attributes::Naked)) 260 return false; 261 262 return MF.getTarget().Options.DisableFramePointerElim(MF) || 263 MFI->hasVarSizedObjects() || 264 (MF.getTarget().Options.GuaranteedTailCallOpt && 265 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 266} 267 268 269void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 270 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 271 MachineBasicBlock::iterator MBBI = MBB.begin(); 272 MachineFrameInfo *MFI = MF.getFrameInfo(); 273 const PPCInstrInfo &TII = 274 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 275 276 MachineModuleInfo &MMI = MF.getMMI(); 277 DebugLoc dl; 278 bool needsFrameMoves = MMI.hasDebugInfo() || 279 MF.getFunction()->needsUnwindTableEntry(); 280 281 // Prepare for frame info. 282 MCSymbol *FrameLabel = 0; 283 284 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 285 // process it. 286 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 287 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 288 HandleVRSaveUpdate(MBBI, TII); 289 break; 290 } 291 } 292 293 // Move MBBI back to the beginning of the function. 294 MBBI = MBB.begin(); 295 296 // Work out frame sizes. 297 // FIXME: determineFrameLayout() may change the frame size. This should be 298 // moved upper, to some hook. 299 determineFrameLayout(MF); 300 unsigned FrameSize = MFI->getStackSize(); 301 302 int NegFrameSize = -FrameSize; 303 304 // Get processor type. 305 bool isPPC64 = Subtarget.isPPC64(); 306 // Get operating system 307 bool isDarwinABI = Subtarget.isDarwinABI(); 308 // Check if the link register (LR) must be saved. 309 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 310 bool MustSaveLR = FI->mustSaveLR(); 311 // Do we have a frame pointer for this function? 312 bool HasFP = hasFP(MF); 313 314 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 315 316 int FPOffset = 0; 317 if (HasFP) { 318 if (Subtarget.isSVR4ABI()) { 319 MachineFrameInfo *FFI = MF.getFrameInfo(); 320 int FPIndex = FI->getFramePointerSaveIndex(); 321 assert(FPIndex && "No Frame Pointer Save Slot!"); 322 FPOffset = FFI->getObjectOffset(FPIndex); 323 } else { 324 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 325 } 326 } 327 328 if (isPPC64) { 329 if (MustSaveLR) 330 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 331 332 if (HasFP) 333 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 334 .addReg(PPC::X31) 335 .addImm(FPOffset/4) 336 .addReg(PPC::X1); 337 338 if (MustSaveLR) 339 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 340 .addReg(PPC::X0) 341 .addImm(LROffset / 4) 342 .addReg(PPC::X1); 343 } else { 344 if (MustSaveLR) 345 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 346 347 if (HasFP) 348 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative 349 // offsets of R1 is not allowed. 350 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 351 .addReg(PPC::R31) 352 .addImm(FPOffset) 353 .addReg(PPC::R1); 354 355 if (MustSaveLR) 356 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 357 .addReg(PPC::R0) 358 .addImm(LROffset) 359 .addReg(PPC::R1); 360 } 361 362 // Skip if a leaf routine. 363 if (!FrameSize) return; 364 365 // Get stack alignments. 366 unsigned TargetAlign = getStackAlignment(); 367 unsigned MaxAlign = MFI->getMaxAlignment(); 368 369 // Adjust stack pointer: r1 += NegFrameSize. 370 // If there is a preferred stack alignment, align R1 now 371 if (!isPPC64) { 372 // PPC32. 373 if (ALIGN_STACK && MaxAlign > TargetAlign) { 374 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 375 "Invalid alignment!"); 376 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 377 378 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 379 .addReg(PPC::R1) 380 .addImm(0) 381 .addImm(32 - Log2_32(MaxAlign)) 382 .addImm(31); 383 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 384 .addReg(PPC::R0, RegState::Kill) 385 .addImm(NegFrameSize); 386 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 387 .addReg(PPC::R1, RegState::Kill) 388 .addReg(PPC::R1) 389 .addReg(PPC::R0); 390 } else if (isInt<16>(NegFrameSize)) { 391 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 392 .addReg(PPC::R1) 393 .addImm(NegFrameSize) 394 .addReg(PPC::R1); 395 } else { 396 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 397 .addImm(NegFrameSize >> 16); 398 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 399 .addReg(PPC::R0, RegState::Kill) 400 .addImm(NegFrameSize & 0xFFFF); 401 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 402 .addReg(PPC::R1, RegState::Kill) 403 .addReg(PPC::R1) 404 .addReg(PPC::R0); 405 } 406 } else { // PPC64. 407 if (ALIGN_STACK && MaxAlign > TargetAlign) { 408 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 409 "Invalid alignment!"); 410 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 411 412 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 413 .addReg(PPC::X1) 414 .addImm(0) 415 .addImm(64 - Log2_32(MaxAlign)); 416 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 417 .addReg(PPC::X0) 418 .addImm(NegFrameSize); 419 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 420 .addReg(PPC::X1, RegState::Kill) 421 .addReg(PPC::X1) 422 .addReg(PPC::X0); 423 } else if (isInt<16>(NegFrameSize)) { 424 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 425 .addReg(PPC::X1) 426 .addImm(NegFrameSize / 4) 427 .addReg(PPC::X1); 428 } else { 429 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 430 .addImm(NegFrameSize >> 16); 431 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 432 .addReg(PPC::X0, RegState::Kill) 433 .addImm(NegFrameSize & 0xFFFF); 434 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 435 .addReg(PPC::X1, RegState::Kill) 436 .addReg(PPC::X1) 437 .addReg(PPC::X0); 438 } 439 } 440 441 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 442 443 // Add the "machine moves" for the instructions we generated above, but in 444 // reverse order. 445 if (needsFrameMoves) { 446 // Mark effective beginning of when frame pointer becomes valid. 447 FrameLabel = MMI.getContext().CreateTempSymbol(); 448 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 449 450 // Show update of SP. 451 if (NegFrameSize) { 452 MachineLocation SPDst(MachineLocation::VirtualFP); 453 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 454 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 455 } else { 456 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 457 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 458 } 459 460 if (HasFP) { 461 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 462 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 463 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 464 } 465 466 if (MustSaveLR) { 467 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 468 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 469 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 470 } 471 } 472 473 MCSymbol *ReadyLabel = 0; 474 475 // If there is a frame pointer, copy R1 into R31 476 if (HasFP) { 477 if (!isPPC64) { 478 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 479 .addReg(PPC::R1) 480 .addReg(PPC::R1); 481 } else { 482 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 483 .addReg(PPC::X1) 484 .addReg(PPC::X1); 485 } 486 487 if (needsFrameMoves) { 488 ReadyLabel = MMI.getContext().CreateTempSymbol(); 489 490 // Mark effective beginning of when frame pointer is ready. 491 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 492 493 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 494 (isPPC64 ? PPC::X1 : PPC::R1)); 495 MachineLocation FPSrc(MachineLocation::VirtualFP); 496 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 497 } 498 } 499 500 if (needsFrameMoves) { 501 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 502 503 // Add callee saved registers to move list. 504 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 505 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 506 unsigned Reg = CSI[I].getReg(); 507 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 508 509 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 510 // subregisters of CR2. We just need to emit a move of CR2. 511 if (PPC::CRBITRCRegClass.contains(Reg)) 512 continue; 513 514 // For SVR4, don't emit a move for the CR spill slot if we haven't 515 // spilled CRs. 516 if (Subtarget.isSVR4ABI() 517 && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 518 && !spillsCR(MF)) 519 continue; 520 521 // For 64-bit SVR4 when we have spilled CRs, the spill location 522 // is SP+8, not a frame-relative slot. 523 if (Subtarget.isSVR4ABI() 524 && Subtarget.isPPC64() 525 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 526 MachineLocation CSDst(PPC::X1, 8); 527 MachineLocation CSSrc(PPC::CR2); 528 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 529 continue; 530 } 531 532 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 533 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 534 MachineLocation CSSrc(Reg); 535 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 536 } 537 } 538} 539 540void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 541 MachineBasicBlock &MBB) const { 542 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 543 assert(MBBI != MBB.end() && "Returning block has no terminator"); 544 const PPCInstrInfo &TII = 545 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 546 547 unsigned RetOpcode = MBBI->getOpcode(); 548 DebugLoc dl; 549 550 assert((RetOpcode == PPC::BLR || 551 RetOpcode == PPC::TCRETURNri || 552 RetOpcode == PPC::TCRETURNdi || 553 RetOpcode == PPC::TCRETURNai || 554 RetOpcode == PPC::TCRETURNri8 || 555 RetOpcode == PPC::TCRETURNdi8 || 556 RetOpcode == PPC::TCRETURNai8) && 557 "Can only insert epilog into returning blocks"); 558 559 // Get alignment info so we know how to restore r1 560 const MachineFrameInfo *MFI = MF.getFrameInfo(); 561 unsigned TargetAlign = getStackAlignment(); 562 unsigned MaxAlign = MFI->getMaxAlignment(); 563 564 // Get the number of bytes allocated from the FrameInfo. 565 int FrameSize = MFI->getStackSize(); 566 567 // Get processor type. 568 bool isPPC64 = Subtarget.isPPC64(); 569 // Get operating system 570 bool isDarwinABI = Subtarget.isDarwinABI(); 571 // Check if the link register (LR) has been saved. 572 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 573 bool MustSaveLR = FI->mustSaveLR(); 574 // Do we have a frame pointer for this function? 575 bool HasFP = hasFP(MF); 576 577 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 578 579 int FPOffset = 0; 580 if (HasFP) { 581 if (Subtarget.isSVR4ABI()) { 582 MachineFrameInfo *FFI = MF.getFrameInfo(); 583 int FPIndex = FI->getFramePointerSaveIndex(); 584 assert(FPIndex && "No Frame Pointer Save Slot!"); 585 FPOffset = FFI->getObjectOffset(FPIndex); 586 } else { 587 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 588 } 589 } 590 591 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 592 RetOpcode == PPC::TCRETURNdi || 593 RetOpcode == PPC::TCRETURNai || 594 RetOpcode == PPC::TCRETURNri8 || 595 RetOpcode == PPC::TCRETURNdi8 || 596 RetOpcode == PPC::TCRETURNai8; 597 598 if (UsesTCRet) { 599 int MaxTCRetDelta = FI->getTailCallSPDelta(); 600 MachineOperand &StackAdjust = MBBI->getOperand(1); 601 assert(StackAdjust.isImm() && "Expecting immediate value."); 602 // Adjust stack pointer. 603 int StackAdj = StackAdjust.getImm(); 604 int Delta = StackAdj - MaxTCRetDelta; 605 assert((Delta >= 0) && "Delta must be positive"); 606 if (MaxTCRetDelta>0) 607 FrameSize += (StackAdj +Delta); 608 else 609 FrameSize += StackAdj; 610 } 611 612 if (FrameSize) { 613 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 614 // on entry to the function. Add this offset back now. 615 if (!isPPC64) { 616 // If this function contained a fastcc call and GuaranteedTailCallOpt is 617 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 618 // call which invalidates the stack pointer value in SP(0). So we use the 619 // value of R31 in this case. 620 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 621 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 622 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 623 .addReg(PPC::R31).addImm(FrameSize); 624 } else if(FI->hasFastCall()) { 625 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 626 .addImm(FrameSize >> 16); 627 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 628 .addReg(PPC::R0, RegState::Kill) 629 .addImm(FrameSize & 0xFFFF); 630 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 631 .addReg(PPC::R1) 632 .addReg(PPC::R31) 633 .addReg(PPC::R0); 634 } else if (isInt<16>(FrameSize) && 635 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 636 !MFI->hasVarSizedObjects()) { 637 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 638 .addReg(PPC::R1).addImm(FrameSize); 639 } else { 640 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 641 .addImm(0).addReg(PPC::R1); 642 } 643 } else { 644 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 645 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 646 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 647 .addReg(PPC::X31).addImm(FrameSize); 648 } else if(FI->hasFastCall()) { 649 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 650 .addImm(FrameSize >> 16); 651 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 652 .addReg(PPC::X0, RegState::Kill) 653 .addImm(FrameSize & 0xFFFF); 654 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 655 .addReg(PPC::X1) 656 .addReg(PPC::X31) 657 .addReg(PPC::X0); 658 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 659 !MFI->hasVarSizedObjects()) { 660 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 661 .addReg(PPC::X1).addImm(FrameSize); 662 } else { 663 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 664 .addImm(0).addReg(PPC::X1); 665 } 666 } 667 } 668 669 if (isPPC64) { 670 if (MustSaveLR) 671 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 672 .addImm(LROffset/4).addReg(PPC::X1); 673 674 if (HasFP) 675 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 676 .addImm(FPOffset/4).addReg(PPC::X1); 677 678 if (MustSaveLR) 679 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 680 } else { 681 if (MustSaveLR) 682 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 683 .addImm(LROffset).addReg(PPC::R1); 684 685 if (HasFP) 686 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 687 .addImm(FPOffset).addReg(PPC::R1); 688 689 if (MustSaveLR) 690 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 691 } 692 693 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 694 // call optimization 695 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 696 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 697 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 698 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 699 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 700 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 701 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 702 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 703 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 704 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 705 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 706 707 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 708 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 709 .addReg(StackReg).addImm(CallerAllocatedAmt); 710 } else { 711 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 712 .addImm(CallerAllocatedAmt >> 16); 713 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 714 .addReg(TmpReg, RegState::Kill) 715 .addImm(CallerAllocatedAmt & 0xFFFF); 716 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 717 .addReg(StackReg) 718 .addReg(FPReg) 719 .addReg(TmpReg); 720 } 721 } else if (RetOpcode == PPC::TCRETURNdi) { 722 MBBI = MBB.getLastNonDebugInstr(); 723 MachineOperand &JumpTarget = MBBI->getOperand(0); 724 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 725 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 726 } else if (RetOpcode == PPC::TCRETURNri) { 727 MBBI = MBB.getLastNonDebugInstr(); 728 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 729 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 730 } else if (RetOpcode == PPC::TCRETURNai) { 731 MBBI = MBB.getLastNonDebugInstr(); 732 MachineOperand &JumpTarget = MBBI->getOperand(0); 733 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 734 } else if (RetOpcode == PPC::TCRETURNdi8) { 735 MBBI = MBB.getLastNonDebugInstr(); 736 MachineOperand &JumpTarget = MBBI->getOperand(0); 737 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 738 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 739 } else if (RetOpcode == PPC::TCRETURNri8) { 740 MBBI = MBB.getLastNonDebugInstr(); 741 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 742 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 743 } else if (RetOpcode == PPC::TCRETURNai8) { 744 MBBI = MBB.getLastNonDebugInstr(); 745 MachineOperand &JumpTarget = MBBI->getOperand(0); 746 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 747 } 748} 749 750/// MustSaveLR - Return true if this function requires that we save the LR 751/// register onto the stack in the prolog and restore it in the epilog of the 752/// function. 753static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 754 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 755 756 // We need a save/restore of LR if there is any def of LR (which is 757 // defined by calls, including the PIC setup sequence), or if there is 758 // some use of the LR stack slot (e.g. for builtin_return_address). 759 // (LR comes in 32 and 64 bit versions.) 760 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 761 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 762} 763 764void 765PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 766 RegScavenger *RS) const { 767 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 768 769 // Save and clear the LR state. 770 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 771 unsigned LR = RegInfo->getRARegister(); 772 FI->setMustSaveLR(MustSaveLR(MF, LR)); 773 MF.getRegInfo().setPhysRegUnused(LR); 774 775 // Save R31 if necessary 776 int FPSI = FI->getFramePointerSaveIndex(); 777 bool isPPC64 = Subtarget.isPPC64(); 778 bool isDarwinABI = Subtarget.isDarwinABI(); 779 MachineFrameInfo *MFI = MF.getFrameInfo(); 780 781 // If the frame pointer save index hasn't been defined yet. 782 if (!FPSI && needsFP(MF)) { 783 // Find out what the fix offset of the frame pointer save area. 784 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 785 // Allocate the frame index for frame pointer save area. 786 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 787 // Save the result. 788 FI->setFramePointerSaveIndex(FPSI); 789 } 790 791 // Reserve stack space to move the linkage area to in case of a tail call. 792 int TCSPDelta = 0; 793 if (MF.getTarget().Options.GuaranteedTailCallOpt && 794 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 795 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 796 } 797 798 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 799 // a large stack, which will require scavenging a register to materialize a 800 // large offset. 801 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 802 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 803 // r0 for now. 804 805 if (RegInfo->requiresRegisterScavenging(MF)) 806 if (needsFP(MF) || spillsCR(MF)) { 807 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 808 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 809 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 810 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 811 RC->getAlignment(), 812 false)); 813 } 814} 815 816void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF) 817 const { 818 // Early exit if not using the SVR4 ABI. 819 if (!Subtarget.isSVR4ABI()) 820 return; 821 822 // Get callee saved register information. 823 MachineFrameInfo *FFI = MF.getFrameInfo(); 824 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 825 826 // Early exit if no callee saved registers are modified! 827 if (CSI.empty() && !needsFP(MF)) { 828 return; 829 } 830 831 unsigned MinGPR = PPC::R31; 832 unsigned MinG8R = PPC::X31; 833 unsigned MinFPR = PPC::F31; 834 unsigned MinVR = PPC::V31; 835 836 bool HasGPSaveArea = false; 837 bool HasG8SaveArea = false; 838 bool HasFPSaveArea = false; 839 bool HasVRSAVESaveArea = false; 840 bool HasVRSaveArea = false; 841 842 SmallVector<CalleeSavedInfo, 18> GPRegs; 843 SmallVector<CalleeSavedInfo, 18> G8Regs; 844 SmallVector<CalleeSavedInfo, 18> FPRegs; 845 SmallVector<CalleeSavedInfo, 18> VRegs; 846 847 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 848 unsigned Reg = CSI[i].getReg(); 849 if (PPC::GPRCRegClass.contains(Reg)) { 850 HasGPSaveArea = true; 851 852 GPRegs.push_back(CSI[i]); 853 854 if (Reg < MinGPR) { 855 MinGPR = Reg; 856 } 857 } else if (PPC::G8RCRegClass.contains(Reg)) { 858 HasG8SaveArea = true; 859 860 G8Regs.push_back(CSI[i]); 861 862 if (Reg < MinG8R) { 863 MinG8R = Reg; 864 } 865 } else if (PPC::F8RCRegClass.contains(Reg)) { 866 HasFPSaveArea = true; 867 868 FPRegs.push_back(CSI[i]); 869 870 if (Reg < MinFPR) { 871 MinFPR = Reg; 872 } 873 } else if (PPC::CRBITRCRegClass.contains(Reg) || 874 PPC::CRRCRegClass.contains(Reg)) { 875 ; // do nothing, as we already know whether CRs are spilled 876 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 877 HasVRSAVESaveArea = true; 878 } else if (PPC::VRRCRegClass.contains(Reg)) { 879 HasVRSaveArea = true; 880 881 VRegs.push_back(CSI[i]); 882 883 if (Reg < MinVR) { 884 MinVR = Reg; 885 } 886 } else { 887 llvm_unreachable("Unknown RegisterClass!"); 888 } 889 } 890 891 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 892 893 int64_t LowerBound = 0; 894 895 // Take into account stack space reserved for tail calls. 896 int TCSPDelta = 0; 897 if (MF.getTarget().Options.GuaranteedTailCallOpt && 898 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 899 LowerBound = TCSPDelta; 900 } 901 902 // The Floating-point register save area is right below the back chain word 903 // of the previous stack frame. 904 if (HasFPSaveArea) { 905 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 906 int FI = FPRegs[i].getFrameIdx(); 907 908 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 909 } 910 911 LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8; 912 } 913 914 // Check whether the frame pointer register is allocated. If so, make sure it 915 // is spilled to the correct offset. 916 if (needsFP(MF)) { 917 HasGPSaveArea = true; 918 919 int FI = PFI->getFramePointerSaveIndex(); 920 assert(FI && "No Frame Pointer Save Slot!"); 921 922 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 923 } 924 925 // General register save area starts right below the Floating-point 926 // register save area. 927 if (HasGPSaveArea || HasG8SaveArea) { 928 // Move general register save area spill slots down, taking into account 929 // the size of the Floating-point register save area. 930 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 931 int FI = GPRegs[i].getFrameIdx(); 932 933 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 934 } 935 936 // Move general register save area spill slots down, taking into account 937 // the size of the Floating-point register save area. 938 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 939 int FI = G8Regs[i].getFrameIdx(); 940 941 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 942 } 943 944 unsigned MinReg = 945 std::min<unsigned>(getPPCRegisterNumbering(MinGPR), 946 getPPCRegisterNumbering(MinG8R)); 947 948 if (Subtarget.isPPC64()) { 949 LowerBound -= (31 - MinReg + 1) * 8; 950 } else { 951 LowerBound -= (31 - MinReg + 1) * 4; 952 } 953 } 954 955 // For 32-bit only, the CR save area is below the general register 956 // save area. For 64-bit SVR4, the CR save area is addressed relative 957 // to the stack pointer and hence does not need an adjustment here. 958 // Only CR2 (the first nonvolatile spilled) has an associated frame 959 // index so that we have a single uniform save area. 960 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 961 // Adjust the frame index of the CR spill slot. 962 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 963 unsigned Reg = CSI[i].getReg(); 964 965 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 966 // Leave Darwin logic as-is. 967 || (!Subtarget.isSVR4ABI() && 968 (PPC::CRBITRCRegClass.contains(Reg) || 969 PPC::CRRCRegClass.contains(Reg)))) { 970 int FI = CSI[i].getFrameIdx(); 971 972 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 973 } 974 } 975 976 LowerBound -= 4; // The CR save area is always 4 bytes long. 977 } 978 979 if (HasVRSAVESaveArea) { 980 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 981 // which have the VRSAVE register class? 982 // Adjust the frame index of the VRSAVE spill slot. 983 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 984 unsigned Reg = CSI[i].getReg(); 985 986 if (PPC::VRSAVERCRegClass.contains(Reg)) { 987 int FI = CSI[i].getFrameIdx(); 988 989 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 990 } 991 } 992 993 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 994 } 995 996 if (HasVRSaveArea) { 997 // Insert alignment padding, we need 16-byte alignment. 998 LowerBound = (LowerBound - 15) & ~(15); 999 1000 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1001 int FI = VRegs[i].getFrameIdx(); 1002 1003 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1004 } 1005 } 1006} 1007 1008bool 1009PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1010 MachineBasicBlock::iterator MI, 1011 const std::vector<CalleeSavedInfo> &CSI, 1012 const TargetRegisterInfo *TRI) const { 1013 1014 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1015 // Return false otherwise to maintain pre-existing behavior. 1016 if (!Subtarget.isSVR4ABI()) 1017 return false; 1018 1019 MachineFunction *MF = MBB.getParent(); 1020 const PPCInstrInfo &TII = 1021 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1022 DebugLoc DL; 1023 bool CRSpilled = false; 1024 1025 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1026 unsigned Reg = CSI[i].getReg(); 1027 // CR2 through CR4 are the nonvolatile CR fields. 1028 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1029 1030 if (CRSpilled && IsCRField) 1031 continue; 1032 1033 // Add the callee-saved register as live-in; it's killed at the spill. 1034 MBB.addLiveIn(Reg); 1035 1036 // Insert the spill to the stack frame. 1037 if (IsCRField) { 1038 CRSpilled = true; 1039 // The first time we see a CR field, store the whole CR into the 1040 // save slot via GPR12 (available in the prolog for 32- and 64-bit). 1041 if (Subtarget.isPPC64()) { 1042 // 64-bit: SP+8 1043 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::X12)); 1044 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW)) 1045 .addReg(PPC::X12, 1046 getKillRegState(true)) 1047 .addImm(8) 1048 .addReg(PPC::X1)); 1049 } else { 1050 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1051 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1052 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)); 1053 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1054 .addReg(PPC::R12, 1055 getKillRegState(true)), 1056 CSI[i].getFrameIdx())); 1057 } 1058 1059 // Record that we spill the CR in this function. 1060 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1061 FuncInfo->setSpillsCR(); 1062 } else { 1063 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1064 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1065 CSI[i].getFrameIdx(), RC, TRI); 1066 } 1067 } 1068 return true; 1069} 1070 1071static void 1072restoreCRs(bool isPPC64, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1073 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1074 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1075 1076 MachineFunction *MF = MBB.getParent(); 1077 const PPCInstrInfo &TII = 1078 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1079 DebugLoc DL; 1080 unsigned RestoreOp, MoveReg; 1081 1082 if (isPPC64) { 1083 // 64-bit: SP+8 1084 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::LWZ), PPC::X12) 1085 .addImm(8) 1086 .addReg(PPC::X1)); 1087 RestoreOp = PPC::MTCRF8; 1088 MoveReg = PPC::X12; 1089 } else { 1090 // 32-bit: FP-relative 1091 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1092 PPC::R12), 1093 CSI[CSIIndex].getFrameIdx())); 1094 RestoreOp = PPC::MTCRF; 1095 MoveReg = PPC::R12; 1096 } 1097 1098 if (CR2Spilled) 1099 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1100 .addReg(MoveReg)); 1101 1102 if (CR3Spilled) 1103 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1104 .addReg(MoveReg)); 1105 1106 if (CR4Spilled) 1107 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1108 .addReg(MoveReg)); 1109} 1110 1111bool 1112PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1113 MachineBasicBlock::iterator MI, 1114 const std::vector<CalleeSavedInfo> &CSI, 1115 const TargetRegisterInfo *TRI) const { 1116 1117 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1118 // Return false otherwise to maintain pre-existing behavior. 1119 if (!Subtarget.isSVR4ABI()) 1120 return false; 1121 1122 MachineFunction *MF = MBB.getParent(); 1123 const PPCInstrInfo &TII = 1124 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1125 bool CR2Spilled = false; 1126 bool CR3Spilled = false; 1127 bool CR4Spilled = false; 1128 unsigned CSIIndex = 0; 1129 1130 // Initialize insertion-point logic; we will be restoring in reverse 1131 // order of spill. 1132 MachineBasicBlock::iterator I = MI, BeforeI = I; 1133 bool AtStart = I == MBB.begin(); 1134 1135 if (!AtStart) 1136 --BeforeI; 1137 1138 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1139 unsigned Reg = CSI[i].getReg(); 1140 1141 if (Reg == PPC::CR2) { 1142 CR2Spilled = true; 1143 // The spill slot is associated only with CR2, which is the 1144 // first nonvolatile spilled. Save it here. 1145 CSIIndex = i; 1146 continue; 1147 } else if (Reg == PPC::CR3) { 1148 CR3Spilled = true; 1149 continue; 1150 } else if (Reg == PPC::CR4) { 1151 CR4Spilled = true; 1152 continue; 1153 } else { 1154 // When we first encounter a non-CR register after seeing at 1155 // least one CR register, restore all spilled CRs together. 1156 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1157 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1158 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled, 1159 MBB, I, CSI, CSIIndex); 1160 CR2Spilled = CR3Spilled = CR4Spilled = false; 1161 } 1162 1163 // Default behavior for non-CR saves. 1164 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1165 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1166 RC, TRI); 1167 assert(I != MBB.begin() && 1168 "loadRegFromStackSlot didn't insert any code!"); 1169 } 1170 1171 // Insert in reverse order. 1172 if (AtStart) 1173 I = MBB.begin(); 1174 else { 1175 I = BeforeI; 1176 ++I; 1177 } 1178 } 1179 1180 // If we haven't yet spilled the CRs, do so now. 1181 if (CR2Spilled || CR3Spilled || CR4Spilled) 1182 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled, 1183 MBB, I, CSI, CSIIndex); 1184 1185 return true; 1186} 1187 1188