PPCISelLowering.cpp revision 0090120c2b8ac3fea5427f6fae6f36fc3dc50dca
18d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 28d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 31f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt// The LLVM Compiler Infrastructure 48d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 5c5ec7f57ead87efa365800228aa0b09a12d9e6c4Dmitry Shmidt// This file was developed by Chris Lattner and is distributed under 6c5ec7f57ead87efa365800228aa0b09a12d9e6c4Dmitry Shmidt// the University of Illinois Open Source License. See LICENSE.TXT for details. 78d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 88d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===----------------------------------------------------------------------===// 98d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// This file implements the PPCISelLowering class. 118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===----------------------------------------------------------------------===// 138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "PPCISelLowering.h" 158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "PPCTargetMachine.h" 168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "PPCPerfectShuffle.h" 178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/ADT/VectorExtras.h" 188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/Analysis/ScalarEvolutionExpressions.h" 198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/CodeGen/MachineFrameInfo.h" 201f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt#include "llvm/CodeGen/MachineFunction.h" 211f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt#include "llvm/CodeGen/MachineInstrBuilder.h" 228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/CodeGen/SelectionDAG.h" 238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/CodeGen/SSARegMap.h" 248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/Constants.h" 258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/Function.h" 268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/Intrinsics.h" 278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/Support/MathExtras.h" 288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt#include "llvm/Target/TargetOptions.h" 298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtusing namespace llvm; 308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 318d520ff1dc2da35cdca849e982051b86468016d8Dmitry ShmidtPPCTargetLowering::PPCTargetLowering(TargetMachine &TM) 328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt : TargetLowering(TM) { 338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Fold away setcc operations if possible. 358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setSetCCIsExpensive(); 368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setPow2DivIsCheap(); 378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Use _setjmp/_longjmp instead of setjmp/longjmp. 398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setUseUnderscoreSetJmpLongJmp(true); 408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Set up the register classes. 428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC has no intrinsics for these particular operations 508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::MEMSET, MVT::Other, Expand); 528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); 568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); 578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 581f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt // PowerPC has no SREM/UREM instructions 591f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt setOperationAction(ISD::SREM, MVT::i32, Expand); 601f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt setOperationAction(ISD::UREM, MVT::i32, Expand); 618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // We don't support sin/cos/sqrt/fmod 638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FSIN , MVT::f64, Expand); 648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FCOS , MVT::f64, Expand); 658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FREM , MVT::f64, Expand); 668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FSIN , MVT::f32, Expand); 678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FCOS , MVT::f32, Expand); 688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FREM , MVT::f32, Expand); 698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If we're enabling GP optimizations, use hardware square root 718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FSQRT, MVT::f64, Expand); 738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FSQRT, MVT::f32, Expand); 748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC does not have BSWAP, CTPOP or CTTZ 808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC does not have ROTR 858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::ROTR, MVT::i32 , Expand); 868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC does not have Select 888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SELECT, MVT::i32, Expand); 898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SELECT, MVT::f32, Expand); 908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SELECT, MVT::f64, Expand); 918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC wants to turn select_cc of FP into fsel when possible. 938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC wants to optimize integer setcc a bit 978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SETCC, MVT::i32, Custom); 988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC does not have BRCOND which requires SetCC 1008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::BRCOND, MVT::Other, Expand); 1018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 1038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 1048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC does not have [U|S]INT_TO_FP 1068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 1078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 1088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 1108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 1118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC does not have truncstore for i1. 1138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); 1148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Support label based line numbers. 1168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::LOCATION, MVT::Other, Expand); 1178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 1188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // FIXME - use subtarget debug flags 1198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) 1208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 1218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // We want to legalize GlobalAddress and ConstantPool nodes into the 1238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // appropriate instructions to materialize the address. 1248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 1258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 1268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // RET must be custom lowered, to meet ABI requirements 1288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::RET , MVT::Other, Custom); 1298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // VASTART needs to be custom lowered to use the VarArgsFrameIndex 1318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::VASTART , MVT::Other, Custom); 1328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Use the default implementation. 1348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::VAARG , MVT::Other, Expand); 1358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::VACOPY , MVT::Other, Expand); 1368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::VAEND , MVT::Other, Expand); 1378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 1388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 1398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 1408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // We want to custom lower some of our intrinsics. 1428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 1458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // They also have instructions for converting between i64 and fp. 1468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 1478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 1488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // FIXME: disable this lowered code. This generates 64-bit register values, 1508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // and we don't model the fact that the top part is clobbered by calls. We 1518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // need to flag these together so that the value isn't live across a call. 1528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 1538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 1558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 1568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else { 1578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // PowerPC does not have FP_TO_UINT on 32-bit implementations. 1588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 1598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 1608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) { 1628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // 64 bit PowerPC implementations can support i64 types directly 1638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 1648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 1658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 1668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else { 1678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // 32 bit PowerPC wants to expand i64 shifts itself. 1688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SHL, MVT::i64, Custom); 1698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SRL, MVT::i64, Custom); 1708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SRA, MVT::i64, Custom); 1718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 1728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 1748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // First set operation action for all vector types to expand. Then we 1758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // will selectively turn on ones that can be effectively codegen'd. 1768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 1788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // add/sub are legal for all supported vector VT's. 1798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 1808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 1818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // We promote all shuffles to v16i8. 1838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 1848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 1858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 1868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // We promote all non-typed operations to v4i32. 1878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 1888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 1898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 1908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 1918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 1928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 1938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 1948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 1958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 1968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 1978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 1988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 1998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // No other operations are legal. 2018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 2028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 2038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 2048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 2058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 2068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 2078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 2088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 2098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 2118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 2128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 2148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // with merges, splats, etc. 2158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 2168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::AND , MVT::v4i32, Legal); 2188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::OR , MVT::v4i32, Legal); 2198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::XOR , MVT::v4i32, Legal); 2208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 2218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 2228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::STORE , MVT::v4i32, Legal); 2238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 2258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 2268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 2278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 2288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::MUL, MVT::v4f32, Legal); 2308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::MUL, MVT::v4i32, Custom); 2318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::MUL, MVT::v8i16, Custom); 2328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::MUL, MVT::v16i8, Custom); 2338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 2358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 2368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 2388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 2398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 2408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 2418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 2428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setSetCCResultContents(ZeroOrOneSetCCResult); 2448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setStackPointerRegisterToSaveRestore(PPC::R1); 2458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // We have target-specific dag combine patterns for the following nodes: 2478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setTargetDAGCombine(ISD::SINT_TO_FP); 2488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setTargetDAGCombine(ISD::STORE); 2498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt setTargetDAGCombine(ISD::BR_CC); 2508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2511f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt computeRegisterProperties(); 2521f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt} 2531f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt 2548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtconst char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 2558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt switch (Opcode) { 2561f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt default: return 0; 2578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::FSEL: return "PPCISD::FSEL"; 2588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::FCFID: return "PPCISD::FCFID"; 2598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 2608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 2618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::STFIWX: return "PPCISD::STFIWX"; 2628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 2638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 2648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::VPERM: return "PPCISD::VPERM"; 2658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::Hi: return "PPCISD::Hi"; 2668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::Lo: return "PPCISD::Lo"; 2678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 2688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::SRL: return "PPCISD::SRL"; 2698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::SRA: return "PPCISD::SRA"; 2708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case PPCISD::SHL: return "PPCISD::SHL"; 2711f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 2721f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case PPCISD::STD_32: return "PPCISD::STD_32"; 2731f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case PPCISD::CALL: return "PPCISD::CALL"; 2741f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 2751f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case PPCISD::MFCR: return "PPCISD::MFCR"; 2761f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case PPCISD::VCMP: return "PPCISD::VCMP"; 2771f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case PPCISD::VCMPo: return "PPCISD::VCMPo"; 2781f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 2791f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt } 2808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 2818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===----------------------------------------------------------------------===// 2838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// Node matching predicates, for use by the tblgen matching code. 2848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===----------------------------------------------------------------------===// 2858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 2871f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidtstatic bool isFloatingPointZero(SDOperand Op) { 2888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 2908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { 2918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Maybe this has already been legalized into the constant pool? 2928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 2938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get())) 2948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 2958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 2968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 2978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 2988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 2998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 3008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// true if Op is undef or if it matches the specified value. 3018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic bool isConstantOrUndef(SDOperand Op, unsigned Val) { 3028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return Op.getOpcode() == ISD::UNDEF || 3038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt cast<ConstantSDNode>(Op)->getValue() == Val; 3048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 3058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 3078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// VPKUHUM instruction. 3088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtbool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 3098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isUnary) { 3108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 0; i != 16; ++i) 3118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 3128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 3138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else { 3148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 0; i != 8; ++i) 3158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 3168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 3178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 3188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 3198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 3208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 3218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 3238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// VPKUWUM instruction. 3248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtbool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 3258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isUnary) { 3268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 0; i != 16; i += 2) 3278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 3288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 3298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 3308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else { 3318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 0; i != 8; i += 2) 3328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 3338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 3348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 3358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 3368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 3378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 3388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 3398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 3408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// isVMerge - Common function, used to match vmrg* shuffles. 3428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// 3438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic bool isVMerge(SDNode *N, unsigned UnitSize, 3448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned LHSStart, unsigned RHSStart) { 3458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(N->getOpcode() == ISD::BUILD_VECTOR && 3468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 3478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 3488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt "Unsupported merge size!"); 3498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 3518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 3528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 3538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt LHSStart+j+i*UnitSize) || 3548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 3558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt RHSStart+j+i*UnitSize)) 3568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 3578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 3588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 3598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 3608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 3628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 3638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtbool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 3648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isUnary) 3658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return isVMerge(N, UnitSize, 8, 24); 3668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return isVMerge(N, UnitSize, 8, 8); 3678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 3688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 3708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 3718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtbool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 3728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isUnary) 3738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return isVMerge(N, UnitSize, 0, 16); 3748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return isVMerge(N, UnitSize, 0, 0); 3758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 3768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 3798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// amount, otherwise return -1. 3808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtint PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 3818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(N->getOpcode() == ISD::BUILD_VECTOR && 3828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 3838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Find the first non-undef value in the shuffle mask. 3848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned i; 3858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 3868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt /*search*/; 3878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (i == 16) return -1; // all undef. 3898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Otherwise, check to see if the rest of the elements are consequtively 3918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // numbered from this value. 3928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 3938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (ShiftAmt < i) return -1; 3948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ShiftAmt -= i; 3958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 3968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isUnary) { 3978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Check the rest of the elements to see if they are consequtive. 3988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (++i; i != 16; ++i) 3998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 4008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return -1; 4018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else { 4028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Check the rest of the elements to see if they are consequtive. 4038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (++i; i != 16; ++i) 4048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 4058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return -1; 4068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 4078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return ShiftAmt; 4098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 4108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 4128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// specifies a splat of a single element that is suitable for input to 4138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// VSPLTB/VSPLTH/VSPLTW. 4148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtbool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 4158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(N->getOpcode() == ISD::BUILD_VECTOR && 4168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt N->getNumOperands() == 16 && 4178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt (EltSize == 1 || EltSize == 2 || EltSize == 4)); 4188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // This is a splat operation if each element of the permute is the same, and 4208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // if the value doesn't reference the second vector. 4218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned ElementBase = 0; 4228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Elt = N->getOperand(0); 4238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 4248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ElementBase = EltV->getValue(); 4258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt else 4268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; // FIXME: Handle UNDEF elements too! 4278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 4298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 4308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Check that they are consequtive. 4328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 1; i != EltSize; ++i) { 4338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isa<ConstantSDNode>(N->getOperand(i)) || 4348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 4358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 4368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 4378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 4398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 4408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(isa<ConstantSDNode>(N->getOperand(i)) && 4428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt "Invalid VECTOR_SHUFFLE mask!"); 4438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned j = 0; j != EltSize; ++j) 4448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (N->getOperand(i+j) != N->getOperand(j)) 4458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 4468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 4478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 4498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 4508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 4528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 4538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtunsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 4548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(isSplatShuffleMask(N, EltSize)); 4558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 4568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 4578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 4598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// by using a vspltis[bhw] instruction of the specified element size, return 4608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// the constant being splatted. The ByteSize field indicates the number of 4618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// bytes of each element [124] -> [bhw]. 4628d520ff1dc2da35cdca849e982051b86468016d8Dmitry ShmidtSDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 4638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand OpVal(0, 0); 4648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If ByteSize of the splat is bigger than the element size of the 4668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // build_vector, then we have a case where we are checking for a splat where 4678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // multiple elements of the buildvector are folded together into a single 4688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 4698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned EltSize = 16/N->getNumOperands(); 4708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (EltSize < ByteSize) { 4718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 4728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand UniquedVals[4]; 4738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 4748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // See if all of the elements in the buildvector agree across. 4768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 4778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the element isn't a constant, bail fully out. 4798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 4808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (UniquedVals[i&(Multiple-1)].Val == 0) 4838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt UniquedVals[i&(Multiple-1)] = N->getOperand(i); 4848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 4858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return SDOperand(); // no match. 4868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 4878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 4898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // either constant or undef values that are identical for each chunk. See 4908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // if these chunks can form into a larger vspltis*. 4918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Check to see if all of the leading entries are either 0 or -1. If 4938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // neither, then this won't fit into the immediate field. 4948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt bool LeadingZero = true; 4958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt bool LeadingOnes = true; 4968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 0; i != Multiple-1; ++i) { 4978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 4988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 4998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 5008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 5018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 5028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Finally, check the least significant entry. 5038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (LeadingZero) { 5048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (UniquedVals[Multiple-1].Val == 0) 5058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 5068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 5078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Val < 16) 5088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 5098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 5108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (LeadingOnes) { 5118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (UniquedVals[Multiple-1].Val == 0) 5128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 5138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 5148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 5158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getTargetConstant(Val, MVT::i32); 5168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 5178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return SDOperand(); 5198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 5208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Check to see if this buildvec has a single non-undef value in its elements. 5228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 5238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (OpVal.Val == 0) 5258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt OpVal = N->getOperand(i); 5268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt else if (OpVal != N->getOperand(i)) 5278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return SDOperand(); 5288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 5298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 5318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned ValSizeInBytes = 0; 5338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t Value = 0; 5348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 5358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Value = CN->getValue(); 5368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 5378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 5388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 5398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Value = FloatToBits(CN->getValue()); 5408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ValSizeInBytes = 4; 5418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 5428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the splat value is larger than the element value, then we can never do 5448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // this splat. The only case that we could fit the replicated bits into our 5458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // immediate field for would be zero, and we prefer to use vxor for it. 5468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (ValSizeInBytes < ByteSize) return SDOperand(); 5478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the element value is larger than the splat value, cut it in half and 5498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // check to see if the two halves are equal. Continue doing this until we 5508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 5518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt while (ValSizeInBytes > ByteSize) { 5528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ValSizeInBytes >>= 1; 5538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the top half equals the bottom half, we're still ok. 5558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 5568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt (Value & ((1 << (8*ValSizeInBytes))-1))) 5578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return SDOperand(); 5581f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt } 5598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Properly sign extend the value. 5618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt int ShAmt = (4-ByteSize)*8; 5628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt int MaskVal = ((int)Value << ShAmt) >> ShAmt; 5638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5641f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 5658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (MaskVal == 0) return SDOperand(); 5668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Finally, if this value fits in a 5 bit sext field, return it 5688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 5698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getTargetConstant(MaskVal, MVT::i32); 5708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return SDOperand(); 5718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 5728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===----------------------------------------------------------------------===// 5748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// LowerOperation implementation 5758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===----------------------------------------------------------------------===// 5768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 5788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 5798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Constant *C = CP->get(); 5808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment()); 5818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Zero = DAG.getConstant(0, MVT::i32); 5828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt const TargetMachine &TM = DAG.getTarget(); 5848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If this is a non-darwin platform, we don't support non-static relo models 5868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // yet. 5878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (TM.getRelocationModel() == Reloc::Static || 5888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 5898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Generate non-pic code that has direct accesses to the constant pool. 5908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // The address of the global is just (hi(&g)+lo(&g)). 5918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 5928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 5938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 5948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 5958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 5968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 5978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (TM.getRelocationModel() == Reloc::PIC) { 5988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // With PIC, the first instruction is actually "GR+hi(&G)". 5998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Hi = DAG.getNode(ISD::ADD, MVT::i32, 6008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 6018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 6028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 6048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 6058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return Lo; 6068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 6078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 6098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 6108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt GlobalValue *GV = GSDN->getGlobal(); 6118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset()); 6128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Zero = DAG.getConstant(0, MVT::i32); 6138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt const TargetMachine &TM = DAG.getTarget(); 6158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If this is a non-darwin platform, we don't support non-static relo models 6178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // yet. 6188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (TM.getRelocationModel() == Reloc::Static || 6198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 6208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Generate non-pic code that has direct accesses to globals. 6218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // The address of the global is just (hi(&g)+lo(&g)). 6228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 6238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 6248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 6258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 6268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 6288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (TM.getRelocationModel() == Reloc::PIC) { 6298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // With PIC, the first instruction is actually "GR+hi(&G)". 6308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Hi = DAG.getNode(ISD::ADD, MVT::i32, 6318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 6328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 6338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 6358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 6368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && 6388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt (!GV->isExternal() || GV->hasNotBeenReadFromBytecode())) 6398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return Lo; 6408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the global is weak or external, we have to go through the lazy 6428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // resolution stub. 6438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); 6448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 6458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 6478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 6488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If we're comparing for equality to zero, expose the fact that this is 6508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // implented as a ctlz/srl pair on ppc, so that the dag combiner can 6518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // fold the new nodes. 6528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 6538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (C->isNullValue() && CC == ISD::SETEQ) { 6548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType VT = Op.getOperand(0).getValueType(); 6558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Zext = Op.getOperand(0); 6568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (VT < MVT::i32) { 6578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt VT = MVT::i32; 6588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 6598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 6608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 6618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 6628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 6638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(Log2b, MVT::i32)); 6648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 6658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 6668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Leave comparisons against 0 and -1 alone for now, since they're usually 6678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // optimized. FIXME: revisit this when we can custom lower all setcc 6688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // optimizations. 6691f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt if (C->isAllOnesValue() || C->isNullValue()) 6708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return SDOperand(); 6718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 6728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If we have an integer seteq/setne, turn it into a compare against zero 6748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // by subtracting the rhs from the lhs, which is faster than setting a 6751f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt // condition register, reading it back out, and masking the correct bit. 6768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 6778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 6788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType VT = Op.getValueType(); 6798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0), 6808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Op.getOperand(1)); 6818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 6828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 6838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return SDOperand(); 6848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 6858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 6878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned VarArgsFrameIndex) { 6888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // vastart just stores the address of the VarArgsFrameIndex slot into the 6898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // memory location argument. 6908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 6918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 6928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Op.getOperand(1), Op.getOperand(2)); 6938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 6948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 6958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 6968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Copy; 6978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt switch(Op.getNumOperands()) { 6988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt default: 6998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(0 && "Do not know how to return this many arguments!"); 7008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt abort(); 7018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case 1: 7028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return SDOperand(); // ret void is legal 7038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case 2: { 7048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 7058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned ArgReg; 7068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (MVT::isVector(ArgVT)) 7078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ArgReg = PPC::V2; 7088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt else if (MVT::isInteger(ArgVT)) 7098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ArgReg = PPC::R3; 7108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt else { 7118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(MVT::isFloatingPoint(ArgVT)); 7128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ArgReg = PPC::F1; 7138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 7148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 7158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 7168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand()); 7178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 7188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If we haven't noted the R3/F1 are live out, do so now. 7198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (DAG.getMachineFunction().liveout_empty()) 7208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getMachineFunction().addLiveOut(ArgReg); 7218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt break; 7228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 7238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case 3: 7248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), 7258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand()); 7268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); 7278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If we haven't noted the R3+R4 are live out, do so now. 7288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (DAG.getMachineFunction().liveout_empty()) { 7298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getMachineFunction().addLiveOut(PPC::R3); 7308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getMachineFunction().addLiveOut(PPC::R4); 7318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 7328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt break; 7338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 7348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 7358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 7368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 7378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 7388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// possible. 7398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 7408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Not FP? Not a fsel. 7418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 7428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 7438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return SDOperand(); 7448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 7458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 7468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 7478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Cannot handle SETEQ/SETNE. 7488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 7498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 7508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType ResVT = Op.getValueType(); 7518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 7528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 7538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 7548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 7558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the RHS of the comparison is a 0.0, we don't need to do the 7568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // subtraction at all. 7578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (isFloatingPointZero(RHS)) 7588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt switch (CC) { 7598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt default: break; // SETUO etc aren't handled by fsel. 7608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETULT: 7618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETLT: 7628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 7638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETUGE: 7641f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case ISD::SETGE: 7658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 7668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 7678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 7681f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case ISD::SETUGT: 7698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETGT: 7708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 7718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETULE: 7728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETLE: 7738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 7748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 7758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(PPCISD::FSEL, ResVT, 7768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 7778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 7781f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt 7798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Cmp; 7801f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt switch (CC) { 7811f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt default: break; // SETUO etc aren't handled by fsel. 7821f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case ISD::SETULT: 7831f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case ISD::SETLT: 7848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 7858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 7868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 7878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 7888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETUGE: 7898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETGE: 7908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 7918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 7928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 7938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 7948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETUGT: 7958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETGT: 7968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 7978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 7988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 7998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 8008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETULE: 8018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case ISD::SETLE: 8028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 8038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 8048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 8058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 8068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 8078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return SDOperand(); 8088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 8098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 8118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 8128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Src = Op.getOperand(0); 8138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Src.getValueType() == MVT::f32) 8148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 8158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp; 8178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt switch (Op.getValueType()) { 8188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 8198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt case MVT::i32: 8208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 8218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt break; 8221f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt case MVT::i64: 8238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 8248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt break; 8258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 8268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Convert the FP value to an int value through memory. 8281f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 8298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Op.getValueType() == MVT::i32) 8308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 8318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return Bits; 8328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 8338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 8358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Op.getOperand(0).getValueType() == MVT::i64) { 8368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 8378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 8381f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt if (Op.getValueType() == MVT::f32) 8398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 8408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return FP; 8418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 8428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(Op.getOperand(0).getValueType() == MVT::i32 && 8448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt "Unhandled SINT_TO_FP type in custom expander!"); 8458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Since we only generate this in 64-bit mode, we can take advantage of 8468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // 64-bit registers. In particular, sign extend the input value into the 8478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 8488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // then lfd it and fcfid it. 8498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 8508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt int FrameIdx = FrameInfo->CreateStackObject(8, 8); 8518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); 8528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 8548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Op.getOperand(0)); 8558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // STD the extended value into the stack slot. 8578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 8588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getEntryNode(), Ext64, FIdx, 8598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getSrcValue(NULL)); 8608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Load the value as a double. 8618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL)); 8628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // FCFID it and return it. 8648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 8658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Op.getValueType() == MVT::f32) 8668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 8678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return FP; 8688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 8698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG) { 8718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(Op.getValueType() == MVT::i64 && 8728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 8738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // The generic code does a fine job expanding shift by a constant. 8748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand(); 8758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Otherwise, expand into a bunch of logical ops. Note that these ops 8778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // depend on the PPC behavior for oversized shift amounts. 8788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 8798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(0, MVT::i32)); 8808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 8818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(1, MVT::i32)); 8828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Amt = Op.getOperand(1); 8838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 8858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(32, MVT::i32), Amt); 8868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 8878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 8888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 8898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 8908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(-32U, MVT::i32)); 8918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 8928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 8938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 8948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 8958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 8968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 8978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG) { 8988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(Op.getValueType() == MVT::i64 && 8998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 9008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // The generic code does a fine job expanding shift by a constant. 9018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand(); 9028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Otherwise, expand into a bunch of logical ops. Note that these ops 9048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // depend on the PPC behavior for oversized shift amounts. 9058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 9068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(0, MVT::i32)); 9078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 9088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(1, MVT::i32)); 9098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Amt = Op.getOperand(1); 9108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 9128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(32, MVT::i32), Amt); 9138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 9148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 9158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 9168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 9178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(-32U, MVT::i32)); 9188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 9198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 9208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 9218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 9228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 9238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG) { 9258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(Op.getValueType() == MVT::i64 && 9268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 9278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // The generic code does a fine job expanding shift by a constant. 9288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand(); 9298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9301f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 9318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 9328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(0, MVT::i32)); 9338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 9348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(1, MVT::i32)); 9358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Amt = Op.getOperand(1); 9368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 9388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(32, MVT::i32), Amt); 9398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 9408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 9418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 9428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 9438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(-32U, MVT::i32)); 9448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 9458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 9468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 9478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Tmp4, Tmp6, ISD::SETLE); 9488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 9498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 9508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt//===----------------------------------------------------------------------===// 9528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// Vector related lowering. 9538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 9548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// If this is a vector of constants or undefs, get the bits. A bit in 9568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// UndefBits is set if the corresponding element of the vector is an 9578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 9588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// zero. Return true if this is not an array of constants, false if it is. 9598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// 9608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 9618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t UndefBits[2]) { 9628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Start with zero'd results. 9638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 9648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 9668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 9678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand OpVal = BV->getOperand(i); 9688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned PartNo = i >= e/2; // In the upper 128 bits? 9708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 9718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t EltBits = 0; 9738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (OpVal.getOpcode() == ISD::UNDEF) { 9748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 9758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 9768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt continue; 9778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 9788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 9798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 9808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(CN->getValueType(0) == MVT::f32 && 9818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt "Only one legal FP vector type!"); 9828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt EltBits = FloatToBits(CN->getValue()); 9838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } else { 9848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Nonconstant element. 9858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 9868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 9878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 9898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 9908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt //printf("%llx %llx %llx %llx\n", 9928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 9938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; 9948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 9958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 9968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// If this is a splat (repetition) of a value across the whole vector, return 9978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// the smallest size that splats it. For example, "0x01010101010101..." is a 9988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 9998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// SplatSize = 1 byte. 10008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic bool isConstantSplat(const uint64_t Bits128[2], 10018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt const uint64_t Undef128[2], 10028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned &SplatBits, unsigned &SplatUndef, 10038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned &SplatSize) { 10041f69aa52ea2e0a73ac502565df8c666ee49cab6aDmitry Shmidt 10058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Don't let undefs prevent splats from matching. See if the top 64-bits are 10068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // the same as the lower 64-bits, ignoring undefs. 10078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 10088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; // Can't be a splat if two pieces don't match. 10098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t Bits64 = Bits128[0] | Bits128[1]; 10118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t Undef64 = Undef128[0] & Undef128[1]; 10128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Check that the top 32-bits are the same as the lower 32-bits, ignoring 10148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // undefs. 10158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 10168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return false; // Can't be a splat if two pieces don't match. 10178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 10198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 10208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the top 16-bits are different than the lower 16-bits, ignoring 10228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // undefs, we have an i32 splat. 10238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 10248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SplatBits = Bits32; 10258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SplatUndef = Undef32; 10268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SplatSize = 4; 10278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 10288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 10298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 10318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 10328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the top 8-bits are different than the lower 8-bits, ignoring 10348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // undefs, we have an i16 splat. 10358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 10368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SplatBits = Bits16; 10378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SplatUndef = Undef16; 10388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SplatSize = 2; 10398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 10408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 10418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Otherwise, we have an 8-bit splat. 10438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 10448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 10458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SplatSize = 1; 10468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return true; 10478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 10488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// BuildSplatI - Build a canonical splati of Val with an element size of 10508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// SplatSize. Cast the result to VT. 10518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 10528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SelectionDAG &DAG) { 10538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 10548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Force vspltis[hw] -1 to vspltisb -1. 10568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Val == -1) SplatSize = 1; 10578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 10598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 10608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt }; 10618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 10628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Build a canonical splat for this value. 10648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT)); 10658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt); 10668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops); 10678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::BIT_CONVERT, VT, Res); 10688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 10698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 10718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// specified intrinsic ID. 10728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 10738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SelectionDAG &DAG, 10748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType DestVT = MVT::Other) { 10758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 10768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 10778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(IID, MVT::i32), LHS, RHS); 10788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 10798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 10818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// specified intrinsic ID. 10828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 10838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Op2, SelectionDAG &DAG, 10848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType DestVT = MVT::Other) { 10858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 10868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 10878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 10888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 10898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 10928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt/// amount. The result has the specified value type. 10938d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 10948d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt MVT::ValueType VT, SelectionDAG &DAG) { 10958d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Force LHS/RHS to be the right type. 10968d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 10978d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 10988d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 10998d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt std::vector<SDOperand> Ops; 11008d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned i = 0; i != 16; ++i) 11018d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Ops.push_back(DAG.getConstant(i+Amt, MVT::i32)); 11028d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 11038d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops)); 11048d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::BIT_CONVERT, VT, T); 11058d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt} 11068d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11078d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// If this is a case we can't handle, return null and let the default 11088d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// expansion code take care of it. If we CAN select this case, and if it 11098d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// selects to a single instruction, return Op. Otherwise, if we can codegen 11108d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// this case more efficiently than a constant pool load, lower it to the 11118d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt// sequence of ops that should be used. 11128d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidtstatic SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 11138d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If this is a vector of constants or undefs, get the bits. A bit in 11148d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // UndefBits is set if the corresponding element of the vector is an 11158d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 11168d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // zero. 11178d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t VectorBits[2]; 11188d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt uint64_t UndefBits[2]; 11198d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 11208d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return SDOperand(); // Not a constant vector. 11218d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11228d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If this is a splat (repetition) of a value across the whole vector, return 11238d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // the smallest size that splats it. For example, "0x01010101010101..." is a 11248d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 11258d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // SplatSize = 1 byte. 11268d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned SplatBits, SplatUndef, SplatSize; 11278d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 11288d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 11298d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11308d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // First, handle single instruction cases. 11318d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11328d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // All zeros? 11338d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (SplatBits == 0) { 11348d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Canonicalize all zero vectors to be v4i32. 11358d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 11368d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Z = DAG.getConstant(0, MVT::i32); 11378d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 11388d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 11398d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 11408d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return Op; 11418d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 11428d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11438d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 11448d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 11458d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (SextVal >= -16 && SextVal <= 15) 11468d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 11478d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11488d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11498d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Two instruction sequences. 11508d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11518d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If this value is in the range [-32,30] and is even, use: 11528d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // tmp = VSPLTI[bhw], result = add tmp, tmp 11538d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 11548d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 11558d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 11568d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 11578d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11588d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 11598d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 11608d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // for fneg/fabs. 11618d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 11628d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Make -1 and vspltisw -1: 11638d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 11648d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11658d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Make the VSLW intrinsic, computing 0x8000_0000. 11668d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 11678d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt OnesV, DAG); 11688d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11698d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // xor by OnesV to invert it. 11708d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 11718d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 11728d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt } 11738d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11748d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Check to see if this is a wide variety of vsplti*, binop self cases. 11758d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned SplatBitSize = SplatSize*8; 11768d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt static const char SplatCsts[] = { 11778d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 11788d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 11798d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt }; 11808d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){ 11818d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 11828d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 11838d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt int i = SplatCsts[idx]; 11848d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11858d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // Figure out what shift amount will be used by altivec if shifted by i in 11868d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // this splat size. 11878d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt unsigned TypeShiftAmt = i & (SplatBitSize-1); 11888d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt 11898d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt // vsplti + shl self. 11908d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt if (SextVal == (i << (int)TypeShiftAmt)) { 11918d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 11928d520ff1dc2da35cdca849e982051b86468016d8Dmitry Shmidt static const unsigned IIDs[] = { // Intrinsic to use for each size. 1193 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 1194 Intrinsic::ppc_altivec_vslw 1195 }; 1196 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 1197 } 1198 1199 // vsplti + srl self. 1200 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 1201 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 1202 static const unsigned IIDs[] = { // Intrinsic to use for each size. 1203 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 1204 Intrinsic::ppc_altivec_vsrw 1205 }; 1206 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 1207 } 1208 1209 // vsplti + sra self. 1210 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 1211 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 1212 static const unsigned IIDs[] = { // Intrinsic to use for each size. 1213 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 1214 Intrinsic::ppc_altivec_vsraw 1215 }; 1216 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 1217 } 1218 1219 // vsplti + rol self. 1220 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 1221 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 1222 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG); 1223 static const unsigned IIDs[] = { // Intrinsic to use for each size. 1224 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 1225 Intrinsic::ppc_altivec_vrlw 1226 }; 1227 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG); 1228 } 1229 1230 // t = vsplti c, result = vsldoi t, t, 1 1231 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 1232 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 1233 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 1234 } 1235 // t = vsplti c, result = vsldoi t, t, 2 1236 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 1237 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 1238 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 1239 } 1240 // t = vsplti c, result = vsldoi t, t, 3 1241 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 1242 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 1243 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 1244 } 1245 } 1246 1247 // Three instruction sequences. 1248 1249 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 1250 if (SextVal >= 0 && SextVal <= 31) { 1251 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG); 1252 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG); 1253 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS); 1254 } 1255 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 1256 if (SextVal >= -31 && SextVal <= 0) { 1257 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG); 1258 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG); 1259 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS); 1260 } 1261 } 1262 1263 return SDOperand(); 1264} 1265 1266/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 1267/// the specified operations to build the shuffle. 1268static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 1269 SDOperand RHS, SelectionDAG &DAG) { 1270 unsigned OpNum = (PFEntry >> 26) & 0x0F; 1271 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 1272 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 1273 1274 enum { 1275 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 1276 OP_VMRGHW, 1277 OP_VMRGLW, 1278 OP_VSPLTISW0, 1279 OP_VSPLTISW1, 1280 OP_VSPLTISW2, 1281 OP_VSPLTISW3, 1282 OP_VSLDOI4, 1283 OP_VSLDOI8, 1284 OP_VSLDOI12, 1285 }; 1286 1287 if (OpNum == OP_COPY) { 1288 if (LHSID == (1*9+2)*9+3) return LHS; 1289 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 1290 return RHS; 1291 } 1292 1293 SDOperand OpLHS, OpRHS; 1294 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 1295 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 1296 1297 unsigned ShufIdxs[16]; 1298 switch (OpNum) { 1299 default: assert(0 && "Unknown i32 permute!"); 1300 case OP_VMRGHW: 1301 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 1302 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 1303 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 1304 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 1305 break; 1306 case OP_VMRGLW: 1307 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 1308 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 1309 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 1310 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 1311 break; 1312 case OP_VSPLTISW0: 1313 for (unsigned i = 0; i != 16; ++i) 1314 ShufIdxs[i] = (i&3)+0; 1315 break; 1316 case OP_VSPLTISW1: 1317 for (unsigned i = 0; i != 16; ++i) 1318 ShufIdxs[i] = (i&3)+4; 1319 break; 1320 case OP_VSPLTISW2: 1321 for (unsigned i = 0; i != 16; ++i) 1322 ShufIdxs[i] = (i&3)+8; 1323 break; 1324 case OP_VSPLTISW3: 1325 for (unsigned i = 0; i != 16; ++i) 1326 ShufIdxs[i] = (i&3)+12; 1327 break; 1328 case OP_VSLDOI4: 1329 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 1330 case OP_VSLDOI8: 1331 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 1332 case OP_VSLDOI12: 1333 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 1334 } 1335 std::vector<SDOperand> Ops; 1336 for (unsigned i = 0; i != 16; ++i) 1337 Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32)); 1338 1339 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 1340 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops)); 1341} 1342 1343/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 1344/// is a shuffle we can handle in a single instruction, return it. Otherwise, 1345/// return the code it can be lowered into. Worst case, it can always be 1346/// lowered into a vperm. 1347static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 1348 SDOperand V1 = Op.getOperand(0); 1349 SDOperand V2 = Op.getOperand(1); 1350 SDOperand PermMask = Op.getOperand(2); 1351 1352 // Cases that are handled by instructions that take permute immediates 1353 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 1354 // selected by the instruction selector. 1355 if (V2.getOpcode() == ISD::UNDEF) { 1356 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 1357 PPC::isSplatShuffleMask(PermMask.Val, 2) || 1358 PPC::isSplatShuffleMask(PermMask.Val, 4) || 1359 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 1360 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 1361 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 1362 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 1363 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 1364 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 1365 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 1366 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 1367 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 1368 return Op; 1369 } 1370 } 1371 1372 // Altivec has a variety of "shuffle immediates" that take two vector inputs 1373 // and produce a fixed permutation. If any of these match, do not lower to 1374 // VPERM. 1375 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 1376 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 1377 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 1378 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 1379 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 1380 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 1381 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 1382 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 1383 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 1384 return Op; 1385 1386 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 1387 // perfect shuffle table to emit an optimal matching sequence. 1388 unsigned PFIndexes[4]; 1389 bool isFourElementShuffle = true; 1390 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 1391 unsigned EltNo = 8; // Start out undef. 1392 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 1393 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 1394 continue; // Undef, ignore it. 1395 1396 unsigned ByteSource = 1397 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 1398 if ((ByteSource & 3) != j) { 1399 isFourElementShuffle = false; 1400 break; 1401 } 1402 1403 if (EltNo == 8) { 1404 EltNo = ByteSource/4; 1405 } else if (EltNo != ByteSource/4) { 1406 isFourElementShuffle = false; 1407 break; 1408 } 1409 } 1410 PFIndexes[i] = EltNo; 1411 } 1412 1413 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 1414 // perfect shuffle vector to determine if it is cost effective to do this as 1415 // discrete instructions, or whether we should use a vperm. 1416 if (isFourElementShuffle) { 1417 // Compute the index in the perfect shuffle table. 1418 unsigned PFTableIndex = 1419 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 1420 1421 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 1422 unsigned Cost = (PFEntry >> 30); 1423 1424 // Determining when to avoid vperm is tricky. Many things affect the cost 1425 // of vperm, particularly how many times the perm mask needs to be computed. 1426 // For example, if the perm mask can be hoisted out of a loop or is already 1427 // used (perhaps because there are multiple permutes with the same shuffle 1428 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 1429 // the loop requires an extra register. 1430 // 1431 // As a compromise, we only emit discrete instructions if the shuffle can be 1432 // generated in 3 or fewer operations. When we have loop information 1433 // available, if this block is within a loop, we should avoid using vperm 1434 // for 3-operation perms and use a constant pool load instead. 1435 if (Cost < 3) 1436 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 1437 } 1438 1439 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 1440 // vector that will get spilled to the constant pool. 1441 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 1442 1443 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 1444 // that it is in input element units, not in bytes. Convert now. 1445 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType()); 1446 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 1447 1448 std::vector<SDOperand> ResultMask; 1449 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 1450 unsigned SrcElt; 1451 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 1452 SrcElt = 0; 1453 else 1454 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 1455 1456 for (unsigned j = 0; j != BytesPerElement; ++j) 1457 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 1458 MVT::i8)); 1459 } 1460 1461 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask); 1462 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 1463} 1464 1465/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 1466/// altivec comparison. If it is, return true and fill in Opc/isDot with 1467/// information about the intrinsic. 1468static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 1469 bool &isDot) { 1470 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 1471 CompareOpc = -1; 1472 isDot = false; 1473 switch (IntrinsicID) { 1474 default: return false; 1475 // Comparison predicates. 1476 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 1477 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 1478 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 1479 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 1480 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 1481 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 1482 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 1483 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 1484 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 1485 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 1486 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 1487 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 1488 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 1489 1490 // Normal Comparisons. 1491 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 1492 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 1493 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 1494 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 1495 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 1496 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 1497 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 1498 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 1499 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 1500 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 1501 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 1502 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 1503 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 1504 } 1505 return true; 1506} 1507 1508/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 1509/// lower, do it, otherwise return null. 1510static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 1511 // If this is a lowered altivec predicate compare, CompareOpc is set to the 1512 // opcode number of the comparison. 1513 int CompareOpc; 1514 bool isDot; 1515 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 1516 return SDOperand(); // Don't custom lower most intrinsics. 1517 1518 // If this is a non-dot comparison, make the VCMP node and we are done. 1519 if (!isDot) { 1520 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 1521 Op.getOperand(1), Op.getOperand(2), 1522 DAG.getConstant(CompareOpc, MVT::i32)); 1523 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 1524 } 1525 1526 // Create the PPCISD altivec 'dot' comparison node. 1527 std::vector<SDOperand> Ops; 1528 std::vector<MVT::ValueType> VTs; 1529 Ops.push_back(Op.getOperand(2)); // LHS 1530 Ops.push_back(Op.getOperand(3)); // RHS 1531 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32)); 1532 VTs.push_back(Op.getOperand(2).getValueType()); 1533 VTs.push_back(MVT::Flag); 1534 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops); 1535 1536 // Now that we have the comparison, emit a copy from the CR to a GPR. 1537 // This is flagged to the above dot comparison. 1538 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 1539 DAG.getRegister(PPC::CR6, MVT::i32), 1540 CompNode.getValue(1)); 1541 1542 // Unpack the result based on how the target uses it. 1543 unsigned BitNo; // Bit # of CR6. 1544 bool InvertBit; // Invert result? 1545 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 1546 default: // Can't happen, don't crash on invalid number though. 1547 case 0: // Return the value of the EQ bit of CR6. 1548 BitNo = 0; InvertBit = false; 1549 break; 1550 case 1: // Return the inverted value of the EQ bit of CR6. 1551 BitNo = 0; InvertBit = true; 1552 break; 1553 case 2: // Return the value of the LT bit of CR6. 1554 BitNo = 2; InvertBit = false; 1555 break; 1556 case 3: // Return the inverted value of the LT bit of CR6. 1557 BitNo = 2; InvertBit = true; 1558 break; 1559 } 1560 1561 // Shift the bit into the low position. 1562 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 1563 DAG.getConstant(8-(3-BitNo), MVT::i32)); 1564 // Isolate the bit. 1565 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 1566 DAG.getConstant(1, MVT::i32)); 1567 1568 // If we are supposed to, toggle the bit. 1569 if (InvertBit) 1570 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 1571 DAG.getConstant(1, MVT::i32)); 1572 return Flags; 1573} 1574 1575static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 1576 // Create a stack slot that is 16-byte aligned. 1577 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 1578 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 1579 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); 1580 1581 // Store the input value into Value#0 of the stack slot. 1582 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 1583 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL)); 1584 // Load it out. 1585 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL)); 1586} 1587 1588static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 1589 if (Op.getValueType() == MVT::v4i32) { 1590 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 1591 1592 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 1593 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 1594 1595 SDOperand RHSSwap = // = vrlw RHS, 16 1596 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 1597 1598 // Shrinkify inputs to v8i16. 1599 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 1600 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 1601 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 1602 1603 // Low parts multiplied together, generating 32-bit results (we ignore the 1604 // top parts). 1605 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 1606 LHS, RHS, DAG, MVT::v4i32); 1607 1608 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 1609 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 1610 // Shift the high parts up 16 bits. 1611 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 1612 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 1613 } else if (Op.getValueType() == MVT::v8i16) { 1614 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 1615 1616 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 1617 1618 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 1619 LHS, RHS, Zero, DAG); 1620 } else if (Op.getValueType() == MVT::v16i8) { 1621 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 1622 1623 // Multiply the even 8-bit parts, producing 16-bit sums. 1624 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 1625 LHS, RHS, DAG, MVT::v8i16); 1626 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 1627 1628 // Multiply the odd 8-bit parts, producing 16-bit sums. 1629 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 1630 LHS, RHS, DAG, MVT::v8i16); 1631 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 1632 1633 // Merge the results together. 1634 std::vector<SDOperand> Ops; 1635 for (unsigned i = 0; i != 8; ++i) { 1636 Ops.push_back(DAG.getConstant(2*i+1, MVT::i8)); 1637 Ops.push_back(DAG.getConstant(2*i+1+16, MVT::i8)); 1638 } 1639 1640 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 1641 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops)); 1642 } else { 1643 assert(0 && "Unknown mul to lower!"); 1644 abort(); 1645 } 1646} 1647 1648/// LowerOperation - Provide custom lowering hooks for some operations. 1649/// 1650SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 1651 switch (Op.getOpcode()) { 1652 default: assert(0 && "Wasn't expecting to be able to lower this!"); 1653 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1654 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 1655 case ISD::SETCC: return LowerSETCC(Op, DAG); 1656 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 1657 case ISD::RET: return LowerRET(Op, DAG); 1658 1659 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1660 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 1661 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 1662 1663 // Lower 64-bit shifts. 1664 case ISD::SHL: return LowerSHL(Op, DAG); 1665 case ISD::SRL: return LowerSRL(Op, DAG); 1666 case ISD::SRA: return LowerSRA(Op, DAG); 1667 1668 // Vector-related lowering. 1669 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 1670 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 1671 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 1672 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 1673 case ISD::MUL: return LowerMUL(Op, DAG); 1674 } 1675 return SDOperand(); 1676} 1677 1678//===----------------------------------------------------------------------===// 1679// Other Lowering Code 1680//===----------------------------------------------------------------------===// 1681 1682std::vector<SDOperand> 1683PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 1684 // 1685 // add beautiful description of PPC stack frame format, or at least some docs 1686 // 1687 MachineFunction &MF = DAG.getMachineFunction(); 1688 MachineFrameInfo *MFI = MF.getFrameInfo(); 1689 MachineBasicBlock& BB = MF.front(); 1690 SSARegMap *RegMap = MF.getSSARegMap(); 1691 std::vector<SDOperand> ArgValues; 1692 1693 unsigned ArgOffset = 24; 1694 unsigned GPR_remaining = 8; 1695 unsigned FPR_remaining = 13; 1696 unsigned GPR_idx = 0, FPR_idx = 0; 1697 static const unsigned GPR[] = { 1698 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1699 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1700 }; 1701 static const unsigned FPR[] = { 1702 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1703 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1704 }; 1705 1706 // Add DAG nodes to load the arguments... On entry to a function on PPC, 1707 // the arguments start at offset 24, although they are likely to be passed 1708 // in registers. 1709 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 1710 SDOperand newroot, argt; 1711 unsigned ObjSize; 1712 bool needsLoad = false; 1713 bool ArgLive = !I->use_empty(); 1714 MVT::ValueType ObjectVT = getValueType(I->getType()); 1715 1716 switch (ObjectVT) { 1717 default: assert(0 && "Unhandled argument type!"); 1718 case MVT::i1: 1719 case MVT::i8: 1720 case MVT::i16: 1721 case MVT::i32: 1722 ObjSize = 4; 1723 if (!ArgLive) break; 1724 if (GPR_remaining > 0) { 1725 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1726 MF.addLiveIn(GPR[GPR_idx], VReg); 1727 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 1728 if (ObjectVT != MVT::i32) { 1729 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 1730 : ISD::AssertZext; 1731 argt = DAG.getNode(AssertOp, MVT::i32, argt, 1732 DAG.getValueType(ObjectVT)); 1733 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt); 1734 } 1735 } else { 1736 needsLoad = true; 1737 } 1738 break; 1739 case MVT::i64: 1740 ObjSize = 8; 1741 if (!ArgLive) break; 1742 if (GPR_remaining > 0) { 1743 SDOperand argHi, argLo; 1744 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1745 MF.addLiveIn(GPR[GPR_idx], VReg); 1746 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 1747 // If we have two or more remaining argument registers, then both halves 1748 // of the i64 can be sourced from there. Otherwise, the lower half will 1749 // have to come off the stack. This can happen when an i64 is preceded 1750 // by 28 bytes of arguments. 1751 if (GPR_remaining > 1) { 1752 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1753 MF.addLiveIn(GPR[GPR_idx+1], VReg); 1754 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32); 1755 } else { 1756 int FI = MFI->CreateFixedObject(4, ArgOffset+4); 1757 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 1758 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 1759 DAG.getSrcValue(NULL)); 1760 } 1761 // Build the outgoing arg thingy 1762 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi); 1763 newroot = argLo; 1764 } else { 1765 needsLoad = true; 1766 } 1767 break; 1768 case MVT::f32: 1769 case MVT::f64: 1770 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4; 1771 if (!ArgLive) { 1772 if (FPR_remaining > 0) { 1773 --FPR_remaining; 1774 ++FPR_idx; 1775 } 1776 break; 1777 } 1778 if (FPR_remaining > 0) { 1779 unsigned VReg; 1780 if (ObjectVT == MVT::f32) 1781 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 1782 else 1783 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 1784 MF.addLiveIn(FPR[FPR_idx], VReg); 1785 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT); 1786 --FPR_remaining; 1787 ++FPR_idx; 1788 } else { 1789 needsLoad = true; 1790 } 1791 break; 1792 } 1793 1794 // We need to load the argument to a virtual register if we determined above 1795 // that we ran out of physical registers of the appropriate type 1796 if (needsLoad) { 1797 unsigned SubregOffset = 0; 1798 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3; 1799 if (ObjectVT == MVT::i16) SubregOffset = 2; 1800 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 1801 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 1802 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, 1803 DAG.getConstant(SubregOffset, MVT::i32)); 1804 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 1805 DAG.getSrcValue(NULL)); 1806 } 1807 1808 // Every 4 bytes of argument space consumes one of the GPRs available for 1809 // argument passing. 1810 if (GPR_remaining > 0) { 1811 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; 1812 GPR_remaining -= delta; 1813 GPR_idx += delta; 1814 } 1815 ArgOffset += ObjSize; 1816 if (newroot.Val) 1817 DAG.setRoot(newroot.getValue(1)); 1818 1819 ArgValues.push_back(argt); 1820 } 1821 1822 // If the function takes variable number of arguments, make a frame index for 1823 // the start of the first vararg value... for expansion of llvm.va_start. 1824 if (F.isVarArg()) { 1825 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1826 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 1827 // If this function is vararg, store any remaining integer argument regs 1828 // to their spots on the stack so that they may be loaded by deferencing the 1829 // result of va_next. 1830 std::vector<SDOperand> MemOps; 1831 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { 1832 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1833 MF.addLiveIn(GPR[GPR_idx], VReg); 1834 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 1835 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 1836 Val, FIN, DAG.getSrcValue(NULL)); 1837 MemOps.push_back(Store); 1838 // Increment the address by four for the next argument to store 1839 SDOperand PtrOff = DAG.getConstant(4, getPointerTy()); 1840 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff); 1841 } 1842 if (!MemOps.empty()) { 1843 MemOps.push_back(DAG.getRoot()); 1844 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps)); 1845 } 1846 } 1847 1848 return ArgValues; 1849} 1850 1851std::pair<SDOperand, SDOperand> 1852PPCTargetLowering::LowerCallTo(SDOperand Chain, 1853 const Type *RetTy, bool isVarArg, 1854 unsigned CallingConv, bool isTailCall, 1855 SDOperand Callee, ArgListTy &Args, 1856 SelectionDAG &DAG) { 1857 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1858 // SelectExpr to use to put the arguments in the appropriate registers. 1859 std::vector<SDOperand> args_to_use; 1860 1861 // Count how many bytes are to be pushed on the stack, including the linkage 1862 // area, and parameter passing area. 1863 unsigned NumBytes = 24; 1864 1865 if (Args.empty()) { 1866 Chain = DAG.getCALLSEQ_START(Chain, 1867 DAG.getConstant(NumBytes, getPointerTy())); 1868 } else { 1869 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 1870 switch (getValueType(Args[i].second)) { 1871 default: assert(0 && "Unknown value type!"); 1872 case MVT::i1: 1873 case MVT::i8: 1874 case MVT::i16: 1875 case MVT::i32: 1876 case MVT::f32: 1877 NumBytes += 4; 1878 break; 1879 case MVT::i64: 1880 case MVT::f64: 1881 NumBytes += 8; 1882 break; 1883 } 1884 } 1885 1886 // Just to be safe, we'll always reserve the full 24 bytes of linkage area 1887 // plus 32 bytes of argument space in case any called code gets funky on us. 1888 // (Required by ABI to support var arg) 1889 if (NumBytes < 56) NumBytes = 56; 1890 1891 // Adjust the stack pointer for the new arguments... 1892 // These operations are automatically eliminated by the prolog/epilog pass 1893 Chain = DAG.getCALLSEQ_START(Chain, 1894 DAG.getConstant(NumBytes, getPointerTy())); 1895 1896 // Set up a copy of the stack pointer for use loading and storing any 1897 // arguments that may not fit in the registers available for argument 1898 // passing. 1899 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1900 1901 // Figure out which arguments are going to go in registers, and which in 1902 // memory. Also, if this is a vararg function, floating point operations 1903 // must be stored to our stack, and loaded into integer regs as well, if 1904 // any integer regs are available for argument passing. 1905 unsigned ArgOffset = 24; 1906 unsigned GPR_remaining = 8; 1907 unsigned FPR_remaining = 13; 1908 1909 std::vector<SDOperand> MemOps; 1910 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 1911 // PtrOff will be used to store the current argument to the stack if a 1912 // register cannot be found for it. 1913 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1914 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 1915 MVT::ValueType ArgVT = getValueType(Args[i].second); 1916 1917 switch (ArgVT) { 1918 default: assert(0 && "Unexpected ValueType for argument!"); 1919 case MVT::i1: 1920 case MVT::i8: 1921 case MVT::i16: 1922 // Promote the integer to 32 bits. If the input type is signed use a 1923 // sign extend, otherwise use a zero extend. 1924 if (Args[i].second->isSigned()) 1925 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 1926 else 1927 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 1928 // FALL THROUGH 1929 case MVT::i32: 1930 if (GPR_remaining > 0) { 1931 args_to_use.push_back(Args[i].first); 1932 --GPR_remaining; 1933 } else { 1934 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1935 Args[i].first, PtrOff, 1936 DAG.getSrcValue(NULL))); 1937 } 1938 ArgOffset += 4; 1939 break; 1940 case MVT::i64: 1941 // If we have one free GPR left, we can place the upper half of the i64 1942 // in it, and store the other half to the stack. If we have two or more 1943 // free GPRs, then we can pass both halves of the i64 in registers. 1944 if (GPR_remaining > 0) { 1945 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 1946 Args[i].first, DAG.getConstant(1, MVT::i32)); 1947 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 1948 Args[i].first, DAG.getConstant(0, MVT::i32)); 1949 args_to_use.push_back(Hi); 1950 --GPR_remaining; 1951 if (GPR_remaining > 0) { 1952 args_to_use.push_back(Lo); 1953 --GPR_remaining; 1954 } else { 1955 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 1956 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 1957 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1958 Lo, PtrOff, DAG.getSrcValue(NULL))); 1959 } 1960 } else { 1961 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1962 Args[i].first, PtrOff, 1963 DAG.getSrcValue(NULL))); 1964 } 1965 ArgOffset += 8; 1966 break; 1967 case MVT::f32: 1968 case MVT::f64: 1969 if (FPR_remaining > 0) { 1970 args_to_use.push_back(Args[i].first); 1971 --FPR_remaining; 1972 if (isVarArg) { 1973 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 1974 Args[i].first, PtrOff, 1975 DAG.getSrcValue(NULL)); 1976 MemOps.push_back(Store); 1977 // Float varargs are always shadowed in available integer registers 1978 if (GPR_remaining > 0) { 1979 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 1980 DAG.getSrcValue(NULL)); 1981 MemOps.push_back(Load.getValue(1)); 1982 args_to_use.push_back(Load); 1983 --GPR_remaining; 1984 } 1985 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 1986 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 1987 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 1988 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 1989 DAG.getSrcValue(NULL)); 1990 MemOps.push_back(Load.getValue(1)); 1991 args_to_use.push_back(Load); 1992 --GPR_remaining; 1993 } 1994 } else { 1995 // If we have any FPRs remaining, we may also have GPRs remaining. 1996 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1997 // GPRs. 1998 if (GPR_remaining > 0) { 1999 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 2000 --GPR_remaining; 2001 } 2002 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 2003 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 2004 --GPR_remaining; 2005 } 2006 } 2007 } else { 2008 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 2009 Args[i].first, PtrOff, 2010 DAG.getSrcValue(NULL))); 2011 } 2012 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8; 2013 break; 2014 } 2015 } 2016 if (!MemOps.empty()) 2017 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); 2018 } 2019 2020 std::vector<MVT::ValueType> RetVals; 2021 MVT::ValueType RetTyVT = getValueType(RetTy); 2022 MVT::ValueType ActualRetTyVT = RetTyVT; 2023 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 2024 ActualRetTyVT = MVT::i32; // Promote result to i32. 2025 2026 if (RetTyVT == MVT::i64) { 2027 RetVals.push_back(MVT::i32); 2028 RetVals.push_back(MVT::i32); 2029 } else if (RetTyVT != MVT::isVoid) { 2030 RetVals.push_back(ActualRetTyVT); 2031 } 2032 RetVals.push_back(MVT::Other); 2033 2034 // If the callee is a GlobalAddress node (quite common, every direct call is) 2035 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 2036 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2037 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 2038 2039 std::vector<SDOperand> Ops; 2040 Ops.push_back(Chain); 2041 Ops.push_back(Callee); 2042 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); 2043 SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops); 2044 Chain = TheCall.getValue(TheCall.Val->getNumValues()-1); 2045 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 2046 DAG.getConstant(NumBytes, getPointerTy())); 2047 SDOperand RetVal = TheCall; 2048 2049 // If the result is a small value, add a note so that we keep track of the 2050 // information about whether it is sign or zero extended. 2051 if (RetTyVT != ActualRetTyVT) { 2052 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext, 2053 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 2054 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 2055 } else if (RetTyVT == MVT::i64) { 2056 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, RetVal, RetVal.getValue(1)); 2057 } 2058 2059 return std::make_pair(RetVal, Chain); 2060} 2061 2062MachineBasicBlock * 2063PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 2064 MachineBasicBlock *BB) { 2065 assert((MI->getOpcode() == PPC::SELECT_CC_Int || 2066 MI->getOpcode() == PPC::SELECT_CC_F4 || 2067 MI->getOpcode() == PPC::SELECT_CC_F8 || 2068 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 2069 "Unexpected instr type to insert"); 2070 2071 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 2072 // control-flow pattern. The incoming instruction knows the destination vreg 2073 // to set, the condition code register to branch on, the true/false values to 2074 // select between, and a branch opcode to use. 2075 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2076 ilist<MachineBasicBlock>::iterator It = BB; 2077 ++It; 2078 2079 // thisMBB: 2080 // ... 2081 // TrueVal = ... 2082 // cmpTY ccX, r1, r2 2083 // bCC copy1MBB 2084 // fallthrough --> copy0MBB 2085 MachineBasicBlock *thisMBB = BB; 2086 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 2087 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 2088 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2) 2089 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 2090 MachineFunction *F = BB->getParent(); 2091 F->getBasicBlockList().insert(It, copy0MBB); 2092 F->getBasicBlockList().insert(It, sinkMBB); 2093 // Update machine-CFG edges by first adding all successors of the current 2094 // block to the new block which will contain the Phi node for the select. 2095 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 2096 e = BB->succ_end(); i != e; ++i) 2097 sinkMBB->addSuccessor(*i); 2098 // Next, remove all successors of the current block, and add the true 2099 // and fallthrough blocks as its successors. 2100 while(!BB->succ_empty()) 2101 BB->removeSuccessor(BB->succ_begin()); 2102 BB->addSuccessor(copy0MBB); 2103 BB->addSuccessor(sinkMBB); 2104 2105 // copy0MBB: 2106 // %FalseValue = ... 2107 // # fallthrough to sinkMBB 2108 BB = copy0MBB; 2109 2110 // Update machine-CFG edges 2111 BB->addSuccessor(sinkMBB); 2112 2113 // sinkMBB: 2114 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 2115 // ... 2116 BB = sinkMBB; 2117 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg()) 2118 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 2119 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 2120 2121 delete MI; // The pseudo instruction is gone now. 2122 return BB; 2123} 2124 2125//===----------------------------------------------------------------------===// 2126// Target Optimization Hooks 2127//===----------------------------------------------------------------------===// 2128 2129SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 2130 DAGCombinerInfo &DCI) const { 2131 TargetMachine &TM = getTargetMachine(); 2132 SelectionDAG &DAG = DCI.DAG; 2133 switch (N->getOpcode()) { 2134 default: break; 2135 case ISD::SINT_TO_FP: 2136 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 2137 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 2138 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 2139 // We allow the src/dst to be either f32/f64, but the intermediate 2140 // type must be i64. 2141 if (N->getOperand(0).getValueType() == MVT::i64) { 2142 SDOperand Val = N->getOperand(0).getOperand(0); 2143 if (Val.getValueType() == MVT::f32) { 2144 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 2145 DCI.AddToWorklist(Val.Val); 2146 } 2147 2148 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 2149 DCI.AddToWorklist(Val.Val); 2150 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 2151 DCI.AddToWorklist(Val.Val); 2152 if (N->getValueType(0) == MVT::f32) { 2153 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); 2154 DCI.AddToWorklist(Val.Val); 2155 } 2156 return Val; 2157 } else if (N->getOperand(0).getValueType() == MVT::i32) { 2158 // If the intermediate type is i32, we can avoid the load/store here 2159 // too. 2160 } 2161 } 2162 } 2163 break; 2164 case ISD::STORE: 2165 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 2166 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 2167 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 2168 N->getOperand(1).getValueType() == MVT::i32) { 2169 SDOperand Val = N->getOperand(1).getOperand(0); 2170 if (Val.getValueType() == MVT::f32) { 2171 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 2172 DCI.AddToWorklist(Val.Val); 2173 } 2174 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 2175 DCI.AddToWorklist(Val.Val); 2176 2177 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 2178 N->getOperand(2), N->getOperand(3)); 2179 DCI.AddToWorklist(Val.Val); 2180 return Val; 2181 } 2182 break; 2183 case PPCISD::VCMP: { 2184 // If a VCMPo node already exists with exactly the same operands as this 2185 // node, use its result instead of this node (VCMPo computes both a CR6 and 2186 // a normal output). 2187 // 2188 if (!N->getOperand(0).hasOneUse() && 2189 !N->getOperand(1).hasOneUse() && 2190 !N->getOperand(2).hasOneUse()) { 2191 2192 // Scan all of the users of the LHS, looking for VCMPo's that match. 2193 SDNode *VCMPoNode = 0; 2194 2195 SDNode *LHSN = N->getOperand(0).Val; 2196 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 2197 UI != E; ++UI) 2198 if ((*UI)->getOpcode() == PPCISD::VCMPo && 2199 (*UI)->getOperand(1) == N->getOperand(1) && 2200 (*UI)->getOperand(2) == N->getOperand(2) && 2201 (*UI)->getOperand(0) == N->getOperand(0)) { 2202 VCMPoNode = *UI; 2203 break; 2204 } 2205 2206 // If there is no VCMPo node, or if the flag value has a single use, don't 2207 // transform this. 2208 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 2209 break; 2210 2211 // Look at the (necessarily single) use of the flag value. If it has a 2212 // chain, this transformation is more complex. Note that multiple things 2213 // could use the value result, which we should ignore. 2214 SDNode *FlagUser = 0; 2215 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 2216 FlagUser == 0; ++UI) { 2217 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 2218 SDNode *User = *UI; 2219 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2220 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 2221 FlagUser = User; 2222 break; 2223 } 2224 } 2225 } 2226 2227 // If the user is a MFCR instruction, we know this is safe. Otherwise we 2228 // give up for right now. 2229 if (FlagUser->getOpcode() == PPCISD::MFCR) 2230 return SDOperand(VCMPoNode, 0); 2231 } 2232 break; 2233 } 2234 case ISD::BR_CC: { 2235 // If this is a branch on an altivec predicate comparison, lower this so 2236 // that we don't have to do a MFCR: instead, branch directly on CR6. This 2237 // lowering is done pre-legalize, because the legalizer lowers the predicate 2238 // compare down to code that is difficult to reassemble. 2239 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2240 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 2241 int CompareOpc; 2242 bool isDot; 2243 2244 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 2245 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 2246 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 2247 assert(isDot && "Can't compare against a vector result!"); 2248 2249 // If this is a comparison against something other than 0/1, then we know 2250 // that the condition is never/always true. 2251 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 2252 if (Val != 0 && Val != 1) { 2253 if (CC == ISD::SETEQ) // Cond never true, remove branch. 2254 return N->getOperand(0); 2255 // Always !=, turn it into an unconditional branch. 2256 return DAG.getNode(ISD::BR, MVT::Other, 2257 N->getOperand(0), N->getOperand(4)); 2258 } 2259 2260 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 2261 2262 // Create the PPCISD altivec 'dot' comparison node. 2263 std::vector<SDOperand> Ops; 2264 std::vector<MVT::ValueType> VTs; 2265 Ops.push_back(LHS.getOperand(2)); // LHS of compare 2266 Ops.push_back(LHS.getOperand(3)); // RHS of compare 2267 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32)); 2268 VTs.push_back(LHS.getOperand(2).getValueType()); 2269 VTs.push_back(MVT::Flag); 2270 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops); 2271 2272 // Unpack the result based on how the target uses it. 2273 unsigned CompOpc; 2274 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 2275 default: // Can't happen, don't crash on invalid number though. 2276 case 0: // Branch on the value of the EQ bit of CR6. 2277 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE; 2278 break; 2279 case 1: // Branch on the inverted value of the EQ bit of CR6. 2280 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ; 2281 break; 2282 case 2: // Branch on the value of the LT bit of CR6. 2283 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE; 2284 break; 2285 case 3: // Branch on the inverted value of the LT bit of CR6. 2286 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT; 2287 break; 2288 } 2289 2290 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 2291 DAG.getRegister(PPC::CR6, MVT::i32), 2292 DAG.getConstant(CompOpc, MVT::i32), 2293 N->getOperand(4), CompNode.getValue(1)); 2294 } 2295 break; 2296 } 2297 } 2298 2299 return SDOperand(); 2300} 2301 2302//===----------------------------------------------------------------------===// 2303// Inline Assembly Support 2304//===----------------------------------------------------------------------===// 2305 2306void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 2307 uint64_t Mask, 2308 uint64_t &KnownZero, 2309 uint64_t &KnownOne, 2310 unsigned Depth) const { 2311 KnownZero = 0; 2312 KnownOne = 0; 2313 switch (Op.getOpcode()) { 2314 default: break; 2315 case ISD::INTRINSIC_WO_CHAIN: { 2316 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 2317 default: break; 2318 case Intrinsic::ppc_altivec_vcmpbfp_p: 2319 case Intrinsic::ppc_altivec_vcmpeqfp_p: 2320 case Intrinsic::ppc_altivec_vcmpequb_p: 2321 case Intrinsic::ppc_altivec_vcmpequh_p: 2322 case Intrinsic::ppc_altivec_vcmpequw_p: 2323 case Intrinsic::ppc_altivec_vcmpgefp_p: 2324 case Intrinsic::ppc_altivec_vcmpgtfp_p: 2325 case Intrinsic::ppc_altivec_vcmpgtsb_p: 2326 case Intrinsic::ppc_altivec_vcmpgtsh_p: 2327 case Intrinsic::ppc_altivec_vcmpgtsw_p: 2328 case Intrinsic::ppc_altivec_vcmpgtub_p: 2329 case Intrinsic::ppc_altivec_vcmpgtuh_p: 2330 case Intrinsic::ppc_altivec_vcmpgtuw_p: 2331 KnownZero = ~1U; // All bits but the low one are known to be zero. 2332 break; 2333 } 2334 } 2335 } 2336} 2337 2338 2339/// getConstraintType - Given a constraint letter, return the type of 2340/// constraint it is for this target. 2341PPCTargetLowering::ConstraintType 2342PPCTargetLowering::getConstraintType(char ConstraintLetter) const { 2343 switch (ConstraintLetter) { 2344 default: break; 2345 case 'b': 2346 case 'r': 2347 case 'f': 2348 case 'v': 2349 case 'y': 2350 return C_RegisterClass; 2351 } 2352 return TargetLowering::getConstraintType(ConstraintLetter); 2353} 2354 2355 2356std::vector<unsigned> PPCTargetLowering:: 2357getRegClassForInlineAsmConstraint(const std::string &Constraint, 2358 MVT::ValueType VT) const { 2359 if (Constraint.size() == 1) { 2360 switch (Constraint[0]) { // GCC RS6000 Constraint Letters 2361 default: break; // Unknown constriant letter 2362 case 'b': 2363 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 , 2364 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , 2365 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 2366 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 2367 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 2368 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 2369 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 2370 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 2371 0); 2372 case 'r': 2373 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 , 2374 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , 2375 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 2376 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 2377 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 2378 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 2379 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 2380 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 2381 0); 2382 case 'f': 2383 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 , 2384 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 , 2385 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11, 2386 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 2387 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 2388 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 2389 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 2390 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 2391 0); 2392 case 'v': 2393 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , 2394 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 2395 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, 2396 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 2397 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 2398 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 2399 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 2400 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 2401 0); 2402 case 'y': 2403 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 2404 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 2405 0); 2406 } 2407 } 2408 2409 return std::vector<unsigned>(); 2410} 2411 2412// isOperandValidForConstraint 2413bool PPCTargetLowering:: 2414isOperandValidForConstraint(SDOperand Op, char Letter) { 2415 switch (Letter) { 2416 default: break; 2417 case 'I': 2418 case 'J': 2419 case 'K': 2420 case 'L': 2421 case 'M': 2422 case 'N': 2423 case 'O': 2424 case 'P': { 2425 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate. 2426 unsigned Value = cast<ConstantSDNode>(Op)->getValue(); 2427 switch (Letter) { 2428 default: assert(0 && "Unknown constraint letter!"); 2429 case 'I': // "I" is a signed 16-bit constant. 2430 return (short)Value == (int)Value; 2431 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 2432 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 2433 return (short)Value == 0; 2434 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 2435 return (Value >> 16) == 0; 2436 case 'M': // "M" is a constant that is greater than 31. 2437 return Value > 31; 2438 case 'N': // "N" is a positive constant that is an exact power of two. 2439 return (int)Value > 0 && isPowerOf2_32(Value); 2440 case 'O': // "O" is the constant zero. 2441 return Value == 0; 2442 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 2443 return (short)-Value == (int)-Value; 2444 } 2445 break; 2446 } 2447 } 2448 2449 // Handle standard constraint letters. 2450 return TargetLowering::isOperandValidForConstraint(Op, Letter); 2451} 2452 2453/// isLegalAddressImmediate - Return true if the integer value can be used 2454/// as the offset of the target addressing mode. 2455bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const { 2456 // PPC allows a sign-extended 16-bit immediate field. 2457 return (V > -(1 << 16) && V < (1 << 16)-1); 2458} 2459