PPCISelLowering.cpp revision 0882fd6c4f90f1cbaa4bb6f6ceec289428cca734
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "MCTargetDesc/PPCPredicates.h" 16#include "PPCMachineFunctionInfo.h" 17#include "PPCPerfectShuffle.h" 18#include "PPCTargetMachine.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/CodeGen/CallingConvLower.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/CodeGen/SelectionDAG.h" 26#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 27#include "llvm/IR/CallingConv.h" 28#include "llvm/IR/Constants.h" 29#include "llvm/IR/DerivedTypes.h" 30#include "llvm/IR/Function.h" 31#include "llvm/IR/Intrinsics.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/Target/TargetOptions.h" 37using namespace llvm; 38 39static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 40 CCValAssign::LocInfo &LocInfo, 41 ISD::ArgFlagsTy &ArgFlags, 42 CCState &State); 43static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 44 MVT &LocVT, 45 CCValAssign::LocInfo &LocInfo, 46 ISD::ArgFlagsTy &ArgFlags, 47 CCState &State); 48static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 49 MVT &LocVT, 50 CCValAssign::LocInfo &LocInfo, 51 ISD::ArgFlagsTy &ArgFlags, 52 CCState &State); 53 54static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", 55cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden); 56 57static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", 58cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden); 59 60static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned", 61cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden); 62 63static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 64 if (TM.getSubtargetImpl()->isDarwin()) 65 return new TargetLoweringObjectFileMachO(); 66 67 return new TargetLoweringObjectFileELF(); 68} 69 70PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 71 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 72 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>(); 73 PPCRegInfo = TM.getRegisterInfo(); 74 75 setPow2DivIsCheap(); 76 77 // Use _setjmp/_longjmp instead of setjmp/longjmp. 78 setUseUnderscoreSetJmp(true); 79 setUseUnderscoreLongJmp(true); 80 81 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all 82 // arguments are at least 4/8 bytes aligned. 83 bool isPPC64 = Subtarget->isPPC64(); 84 setMinStackArgumentAlignment(isPPC64 ? 8:4); 85 86 // Set up the register classes. 87 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); 88 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); 89 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); 90 91 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 92 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 93 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 94 95 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 96 97 // PowerPC has pre-inc load and store's. 98 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 99 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 100 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 101 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 102 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 103 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 104 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 105 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 106 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 107 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 108 109 // This is used in the ppcf128->int sequence. Note it has different semantics 110 // from FP_ROUND: that rounds to nearest, this rounds to zero. 111 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 112 113 // We do not currently implement these libm ops for PowerPC. 114 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); 115 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); 116 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); 117 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); 118 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); 119 120 // PowerPC has no SREM/UREM instructions 121 setOperationAction(ISD::SREM, MVT::i32, Expand); 122 setOperationAction(ISD::UREM, MVT::i32, Expand); 123 setOperationAction(ISD::SREM, MVT::i64, Expand); 124 setOperationAction(ISD::UREM, MVT::i64, Expand); 125 126 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 127 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 128 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 129 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 130 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 131 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 132 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 133 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 134 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 135 136 // We don't support sin/cos/sqrt/fmod/pow 137 setOperationAction(ISD::FSIN , MVT::f64, Expand); 138 setOperationAction(ISD::FCOS , MVT::f64, Expand); 139 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 140 setOperationAction(ISD::FREM , MVT::f64, Expand); 141 setOperationAction(ISD::FPOW , MVT::f64, Expand); 142 setOperationAction(ISD::FMA , MVT::f64, Legal); 143 setOperationAction(ISD::FSIN , MVT::f32, Expand); 144 setOperationAction(ISD::FCOS , MVT::f32, Expand); 145 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 146 setOperationAction(ISD::FREM , MVT::f32, Expand); 147 setOperationAction(ISD::FPOW , MVT::f32, Expand); 148 setOperationAction(ISD::FMA , MVT::f32, Legal); 149 150 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 151 152 // If we're enabling GP optimizations, use hardware square root 153 if (!Subtarget->hasFSQRT()) { 154 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 155 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 156 } 157 158 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 159 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 160 161 if (Subtarget->hasFPRND()) { 162 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 163 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 164 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 165 166 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 167 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 168 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 169 170 // frin does not implement "ties to even." Thus, this is safe only in 171 // fast-math mode. 172 if (TM.Options.UnsafeFPMath) { 173 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 174 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 175 176 // These need to set FE_INEXACT, and use a custom inserter. 177 setOperationAction(ISD::FRINT, MVT::f64, Legal); 178 setOperationAction(ISD::FRINT, MVT::f32, Legal); 179 } 180 } 181 182 // PowerPC does not have BSWAP, CTPOP or CTTZ 183 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 184 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 185 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 186 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 187 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 188 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 189 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 190 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 191 192 if (Subtarget->hasPOPCNTD()) { 193 setOperationAction(ISD::CTPOP, MVT::i32 , Promote); 194 setOperationAction(ISD::CTPOP, MVT::i64 , Legal); 195 } else { 196 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 197 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 198 } 199 200 // PowerPC does not have ROTR 201 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 202 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 203 204 // PowerPC does not have Select 205 setOperationAction(ISD::SELECT, MVT::i32, Expand); 206 setOperationAction(ISD::SELECT, MVT::i64, Expand); 207 setOperationAction(ISD::SELECT, MVT::f32, Expand); 208 setOperationAction(ISD::SELECT, MVT::f64, Expand); 209 210 // PowerPC wants to turn select_cc of FP into fsel when possible. 211 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 212 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 213 214 // PowerPC wants to optimize integer setcc a bit 215 setOperationAction(ISD::SETCC, MVT::i32, Custom); 216 217 // PowerPC does not have BRCOND which requires SetCC 218 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 219 220 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 221 222 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 223 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 224 225 // PowerPC does not have [U|S]INT_TO_FP 226 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 227 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 228 229 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 230 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 231 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 232 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 233 234 // We cannot sextinreg(i1). Expand to shifts. 235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 236 237 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 238 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 239 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 240 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 241 242 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support 243 // SjLj exception handling but a light-weight setjmp/longjmp replacement to 244 // support continuation, user-level threading, and etc.. As a result, no 245 // other SjLj exception interfaces are implemented and please don't build 246 // your own exception handling based on them. 247 // LLVM/Clang supports zero-cost DWARF exception handling. 248 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 249 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 250 251 // We want to legalize GlobalAddress and ConstantPool nodes into the 252 // appropriate instructions to materialize the address. 253 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 254 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 255 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 256 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 257 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 258 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 259 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 260 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 261 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 262 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 263 264 // TRAP is legal. 265 setOperationAction(ISD::TRAP, MVT::Other, Legal); 266 267 // TRAMPOLINE is custom lowered. 268 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 269 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 270 271 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 272 setOperationAction(ISD::VASTART , MVT::Other, Custom); 273 274 if (Subtarget->isSVR4ABI()) { 275 if (isPPC64) { 276 // VAARG always uses double-word chunks, so promote anything smaller. 277 setOperationAction(ISD::VAARG, MVT::i1, Promote); 278 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); 279 setOperationAction(ISD::VAARG, MVT::i8, Promote); 280 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); 281 setOperationAction(ISD::VAARG, MVT::i16, Promote); 282 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); 283 setOperationAction(ISD::VAARG, MVT::i32, Promote); 284 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); 285 setOperationAction(ISD::VAARG, MVT::Other, Expand); 286 } else { 287 // VAARG is custom lowered with the 32-bit SVR4 ABI. 288 setOperationAction(ISD::VAARG, MVT::Other, Custom); 289 setOperationAction(ISD::VAARG, MVT::i64, Custom); 290 } 291 } else 292 setOperationAction(ISD::VAARG, MVT::Other, Expand); 293 294 // Use the default implementation. 295 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 296 setOperationAction(ISD::VAEND , MVT::Other, Expand); 297 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 298 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 299 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 300 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 301 302 // We want to custom lower some of our intrinsics. 303 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 304 305 // Comparisons that require checking two conditions. 306 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 307 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 308 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 309 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 310 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 311 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 312 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 313 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 314 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 315 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 316 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 317 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 318 319 if (Subtarget->has64BitSupport()) { 320 // They also have instructions for converting between i64 and fp. 321 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 322 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 323 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 324 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 325 // This is just the low 32 bits of a (signed) fp->i64 conversion. 326 // We cannot do this with Promote because i64 is not a legal type. 327 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 328 329 // FIXME: disable this lowered code. This generates 64-bit register values, 330 // and we don't model the fact that the top part is clobbered by calls. We 331 // need to flag these together so that the value isn't live across a call. 332 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 333 } else { 334 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 335 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 336 } 337 338 if (Subtarget->use64BitRegs()) { 339 // 64-bit PowerPC implementations can support i64 types directly 340 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); 341 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 342 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 343 // 64-bit PowerPC wants to expand i128 shifts itself. 344 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 345 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 346 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 347 } else { 348 // 32-bit PowerPC wants to expand i64 shifts itself. 349 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 350 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 351 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 352 } 353 354 if (Subtarget->hasAltivec()) { 355 // First set operation action for all vector types to expand. Then we 356 // will selectively turn on ones that can be effectively codegen'd. 357 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 358 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 359 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 360 361 // add/sub are legal for all supported vector VT's. 362 setOperationAction(ISD::ADD , VT, Legal); 363 setOperationAction(ISD::SUB , VT, Legal); 364 365 // We promote all shuffles to v16i8. 366 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 367 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 368 369 // We promote all non-typed operations to v4i32. 370 setOperationAction(ISD::AND , VT, Promote); 371 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 372 setOperationAction(ISD::OR , VT, Promote); 373 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 374 setOperationAction(ISD::XOR , VT, Promote); 375 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 376 setOperationAction(ISD::LOAD , VT, Promote); 377 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 378 setOperationAction(ISD::SELECT, VT, Promote); 379 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 380 setOperationAction(ISD::STORE, VT, Promote); 381 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 382 383 // No other operations are legal. 384 setOperationAction(ISD::MUL , VT, Expand); 385 setOperationAction(ISD::SDIV, VT, Expand); 386 setOperationAction(ISD::SREM, VT, Expand); 387 setOperationAction(ISD::UDIV, VT, Expand); 388 setOperationAction(ISD::UREM, VT, Expand); 389 setOperationAction(ISD::FDIV, VT, Expand); 390 setOperationAction(ISD::FNEG, VT, Expand); 391 setOperationAction(ISD::FSQRT, VT, Expand); 392 setOperationAction(ISD::FLOG, VT, Expand); 393 setOperationAction(ISD::FLOG10, VT, Expand); 394 setOperationAction(ISD::FLOG2, VT, Expand); 395 setOperationAction(ISD::FEXP, VT, Expand); 396 setOperationAction(ISD::FEXP2, VT, Expand); 397 setOperationAction(ISD::FSIN, VT, Expand); 398 setOperationAction(ISD::FCOS, VT, Expand); 399 setOperationAction(ISD::FABS, VT, Expand); 400 setOperationAction(ISD::FPOWI, VT, Expand); 401 setOperationAction(ISD::FFLOOR, VT, Expand); 402 setOperationAction(ISD::FCEIL, VT, Expand); 403 setOperationAction(ISD::FTRUNC, VT, Expand); 404 setOperationAction(ISD::FRINT, VT, Expand); 405 setOperationAction(ISD::FNEARBYINT, VT, Expand); 406 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 407 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 408 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 409 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 410 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 411 setOperationAction(ISD::UDIVREM, VT, Expand); 412 setOperationAction(ISD::SDIVREM, VT, Expand); 413 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 414 setOperationAction(ISD::FPOW, VT, Expand); 415 setOperationAction(ISD::CTPOP, VT, Expand); 416 setOperationAction(ISD::CTLZ, VT, Expand); 417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 418 setOperationAction(ISD::CTTZ, VT, Expand); 419 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 420 setOperationAction(ISD::VSELECT, VT, Expand); 421 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 422 423 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 424 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) { 425 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j; 426 setTruncStoreAction(VT, InnerVT, Expand); 427 } 428 setLoadExtAction(ISD::SEXTLOAD, VT, Expand); 429 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand); 430 setLoadExtAction(ISD::EXTLOAD, VT, Expand); 431 } 432 433 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 434 // with merges, splats, etc. 435 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 436 437 setOperationAction(ISD::AND , MVT::v4i32, Legal); 438 setOperationAction(ISD::OR , MVT::v4i32, Legal); 439 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 440 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 441 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 442 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 443 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 444 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); 445 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 446 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); 447 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); 448 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); 449 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); 450 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); 451 452 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); 453 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); 454 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); 455 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); 456 457 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 458 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 459 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 460 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 461 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 462 463 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 464 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 465 466 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 467 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 468 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 469 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 470 471 // Altivec does not contain unordered floating-point compare instructions 472 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); 473 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); 474 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand); 475 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand); 476 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand); 477 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand); 478 } 479 480 if (Subtarget->has64BitSupport()) { 481 setOperationAction(ISD::PREFETCH, MVT::Other, Legal); 482 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal); 483 } 484 485 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 486 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 487 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 488 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 489 490 setBooleanContents(ZeroOrOneBooleanContent); 491 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 492 493 if (isPPC64) { 494 setStackPointerRegisterToSaveRestore(PPC::X1); 495 setExceptionPointerRegister(PPC::X3); 496 setExceptionSelectorRegister(PPC::X4); 497 } else { 498 setStackPointerRegisterToSaveRestore(PPC::R1); 499 setExceptionPointerRegister(PPC::R3); 500 setExceptionSelectorRegister(PPC::R4); 501 } 502 503 // We have target-specific dag combine patterns for the following nodes: 504 setTargetDAGCombine(ISD::SINT_TO_FP); 505 setTargetDAGCombine(ISD::STORE); 506 setTargetDAGCombine(ISD::BR_CC); 507 setTargetDAGCombine(ISD::BSWAP); 508 509 // Darwin long double math library functions have $LDBL128 appended. 510 if (Subtarget->isDarwin()) { 511 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 512 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 513 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 514 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 515 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 516 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 517 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 518 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 519 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 520 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 521 } 522 523 setMinFunctionAlignment(2); 524 if (PPCSubTarget.isDarwin()) 525 setPrefFunctionAlignment(4); 526 527 if (isPPC64 && Subtarget->isJITCodeModel()) 528 // Temporary workaround for the inability of PPC64 JIT to handle jump 529 // tables. 530 setSupportJumpTables(false); 531 532 setInsertFencesForAtomic(true); 533 534 setSchedulingPreference(Sched::Hybrid); 535 536 computeRegisterProperties(); 537 538 // The Freescale cores does better with aggressive inlining of memcpy and 539 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores). 540 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc || 541 Subtarget->getDarwinDirective() == PPC::DIR_E5500) { 542 MaxStoresPerMemset = 32; 543 MaxStoresPerMemsetOptSize = 16; 544 MaxStoresPerMemcpy = 32; 545 MaxStoresPerMemcpyOptSize = 8; 546 MaxStoresPerMemmove = 32; 547 MaxStoresPerMemmoveOptSize = 8; 548 549 setPrefFunctionAlignment(4); 550 } 551} 552 553/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 554/// function arguments in the caller parameter area. 555unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const { 556 const TargetMachine &TM = getTargetMachine(); 557 // Darwin passes everything on 4 byte boundary. 558 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 559 return 4; 560 561 // 16byte and wider vectors are passed on 16byte boundary. 562 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) 563 if (VTy->getBitWidth() >= 128) 564 return 16; 565 566 // The rest is 8 on PPC64 and 4 on PPC32 boundary. 567 if (PPCSubTarget.isPPC64()) 568 return 8; 569 570 return 4; 571} 572 573const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 574 switch (Opcode) { 575 default: return 0; 576 case PPCISD::FSEL: return "PPCISD::FSEL"; 577 case PPCISD::FCFID: return "PPCISD::FCFID"; 578 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 579 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 580 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 581 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 582 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 583 case PPCISD::VPERM: return "PPCISD::VPERM"; 584 case PPCISD::Hi: return "PPCISD::Hi"; 585 case PPCISD::Lo: return "PPCISD::Lo"; 586 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 587 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 588 case PPCISD::LOAD: return "PPCISD::LOAD"; 589 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 590 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 591 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 592 case PPCISD::SRL: return "PPCISD::SRL"; 593 case PPCISD::SRA: return "PPCISD::SRA"; 594 case PPCISD::SHL: return "PPCISD::SHL"; 595 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 596 case PPCISD::STD_32: return "PPCISD::STD_32"; 597 case PPCISD::CALL: return "PPCISD::CALL"; 598 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP"; 599 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 600 case PPCISD::BCTRL: return "PPCISD::BCTRL"; 601 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 602 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP"; 603 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP"; 604 case PPCISD::MFCR: return "PPCISD::MFCR"; 605 case PPCISD::VCMP: return "PPCISD::VCMP"; 606 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 607 case PPCISD::LBRX: return "PPCISD::LBRX"; 608 case PPCISD::STBRX: return "PPCISD::STBRX"; 609 case PPCISD::LARX: return "PPCISD::LARX"; 610 case PPCISD::STCX: return "PPCISD::STCX"; 611 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 612 case PPCISD::MFFS: return "PPCISD::MFFS"; 613 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 614 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 615 case PPCISD::CR6SET: return "PPCISD::CR6SET"; 616 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET"; 617 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA"; 618 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L"; 619 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L"; 620 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA"; 621 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L"; 622 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS"; 623 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA"; 624 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L"; 625 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR"; 626 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA"; 627 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L"; 628 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR"; 629 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA"; 630 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L"; 631 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT"; 632 } 633} 634 635EVT PPCTargetLowering::getSetCCResultType(EVT VT) const { 636 if (!VT.isVector()) 637 return MVT::i32; 638 return VT.changeVectorElementTypeToInteger(); 639} 640 641//===----------------------------------------------------------------------===// 642// Node matching predicates, for use by the tblgen matching code. 643//===----------------------------------------------------------------------===// 644 645/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 646static bool isFloatingPointZero(SDValue Op) { 647 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 648 return CFP->getValueAPF().isZero(); 649 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 650 // Maybe this has already been legalized into the constant pool? 651 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 652 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 653 return CFP->getValueAPF().isZero(); 654 } 655 return false; 656} 657 658/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 659/// true if Op is undef or if it matches the specified value. 660static bool isConstantOrUndef(int Op, int Val) { 661 return Op < 0 || Op == Val; 662} 663 664/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 665/// VPKUHUM instruction. 666bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 667 if (!isUnary) { 668 for (unsigned i = 0; i != 16; ++i) 669 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 670 return false; 671 } else { 672 for (unsigned i = 0; i != 8; ++i) 673 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 674 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 675 return false; 676 } 677 return true; 678} 679 680/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 681/// VPKUWUM instruction. 682bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 683 if (!isUnary) { 684 for (unsigned i = 0; i != 16; i += 2) 685 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 686 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 687 return false; 688 } else { 689 for (unsigned i = 0; i != 8; i += 2) 690 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 691 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 692 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 693 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 694 return false; 695 } 696 return true; 697} 698 699/// isVMerge - Common function, used to match vmrg* shuffles. 700/// 701static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 702 unsigned LHSStart, unsigned RHSStart) { 703 assert(N->getValueType(0) == MVT::v16i8 && 704 "PPC only supports shuffles by bytes!"); 705 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 706 "Unsupported merge size!"); 707 708 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 709 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 710 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 711 LHSStart+j+i*UnitSize) || 712 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 713 RHSStart+j+i*UnitSize)) 714 return false; 715 } 716 return true; 717} 718 719/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 720/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 721bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 722 bool isUnary) { 723 if (!isUnary) 724 return isVMerge(N, UnitSize, 8, 24); 725 return isVMerge(N, UnitSize, 8, 8); 726} 727 728/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 729/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 730bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 731 bool isUnary) { 732 if (!isUnary) 733 return isVMerge(N, UnitSize, 0, 16); 734 return isVMerge(N, UnitSize, 0, 0); 735} 736 737 738/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 739/// amount, otherwise return -1. 740int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 741 assert(N->getValueType(0) == MVT::v16i8 && 742 "PPC only supports shuffles by bytes!"); 743 744 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 745 746 // Find the first non-undef value in the shuffle mask. 747 unsigned i; 748 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 749 /*search*/; 750 751 if (i == 16) return -1; // all undef. 752 753 // Otherwise, check to see if the rest of the elements are consecutively 754 // numbered from this value. 755 unsigned ShiftAmt = SVOp->getMaskElt(i); 756 if (ShiftAmt < i) return -1; 757 ShiftAmt -= i; 758 759 if (!isUnary) { 760 // Check the rest of the elements to see if they are consecutive. 761 for (++i; i != 16; ++i) 762 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 763 return -1; 764 } else { 765 // Check the rest of the elements to see if they are consecutive. 766 for (++i; i != 16; ++i) 767 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 768 return -1; 769 } 770 return ShiftAmt; 771} 772 773/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 774/// specifies a splat of a single element that is suitable for input to 775/// VSPLTB/VSPLTH/VSPLTW. 776bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 777 assert(N->getValueType(0) == MVT::v16i8 && 778 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 779 780 // This is a splat operation if each element of the permute is the same, and 781 // if the value doesn't reference the second vector. 782 unsigned ElementBase = N->getMaskElt(0); 783 784 // FIXME: Handle UNDEF elements too! 785 if (ElementBase >= 16) 786 return false; 787 788 // Check that the indices are consecutive, in the case of a multi-byte element 789 // splatted with a v16i8 mask. 790 for (unsigned i = 1; i != EltSize; ++i) 791 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 792 return false; 793 794 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 795 if (N->getMaskElt(i) < 0) continue; 796 for (unsigned j = 0; j != EltSize; ++j) 797 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 798 return false; 799 } 800 return true; 801} 802 803/// isAllNegativeZeroVector - Returns true if all elements of build_vector 804/// are -0.0. 805bool PPC::isAllNegativeZeroVector(SDNode *N) { 806 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 807 808 APInt APVal, APUndef; 809 unsigned BitSize; 810 bool HasAnyUndefs; 811 812 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 813 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 814 return CFP->getValueAPF().isNegZero(); 815 816 return false; 817} 818 819/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 820/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 821unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 822 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 823 assert(isSplatShuffleMask(SVOp, EltSize)); 824 return SVOp->getMaskElt(0) / EltSize; 825} 826 827/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 828/// by using a vspltis[bhw] instruction of the specified element size, return 829/// the constant being splatted. The ByteSize field indicates the number of 830/// bytes of each element [124] -> [bhw]. 831SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 832 SDValue OpVal(0, 0); 833 834 // If ByteSize of the splat is bigger than the element size of the 835 // build_vector, then we have a case where we are checking for a splat where 836 // multiple elements of the buildvector are folded together into a single 837 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 838 unsigned EltSize = 16/N->getNumOperands(); 839 if (EltSize < ByteSize) { 840 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 841 SDValue UniquedVals[4]; 842 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 843 844 // See if all of the elements in the buildvector agree across. 845 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 846 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 847 // If the element isn't a constant, bail fully out. 848 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 849 850 851 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 852 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 853 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 854 return SDValue(); // no match. 855 } 856 857 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 858 // either constant or undef values that are identical for each chunk. See 859 // if these chunks can form into a larger vspltis*. 860 861 // Check to see if all of the leading entries are either 0 or -1. If 862 // neither, then this won't fit into the immediate field. 863 bool LeadingZero = true; 864 bool LeadingOnes = true; 865 for (unsigned i = 0; i != Multiple-1; ++i) { 866 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 867 868 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 869 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 870 } 871 // Finally, check the least significant entry. 872 if (LeadingZero) { 873 if (UniquedVals[Multiple-1].getNode() == 0) 874 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 875 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 876 if (Val < 16) 877 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 878 } 879 if (LeadingOnes) { 880 if (UniquedVals[Multiple-1].getNode() == 0) 881 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 882 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 883 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 884 return DAG.getTargetConstant(Val, MVT::i32); 885 } 886 887 return SDValue(); 888 } 889 890 // Check to see if this buildvec has a single non-undef value in its elements. 891 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 892 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 893 if (OpVal.getNode() == 0) 894 OpVal = N->getOperand(i); 895 else if (OpVal != N->getOperand(i)) 896 return SDValue(); 897 } 898 899 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 900 901 unsigned ValSizeInBytes = EltSize; 902 uint64_t Value = 0; 903 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 904 Value = CN->getZExtValue(); 905 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 906 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 907 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 908 } 909 910 // If the splat value is larger than the element value, then we can never do 911 // this splat. The only case that we could fit the replicated bits into our 912 // immediate field for would be zero, and we prefer to use vxor for it. 913 if (ValSizeInBytes < ByteSize) return SDValue(); 914 915 // If the element value is larger than the splat value, cut it in half and 916 // check to see if the two halves are equal. Continue doing this until we 917 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 918 while (ValSizeInBytes > ByteSize) { 919 ValSizeInBytes >>= 1; 920 921 // If the top half equals the bottom half, we're still ok. 922 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 923 (Value & ((1 << (8*ValSizeInBytes))-1))) 924 return SDValue(); 925 } 926 927 // Properly sign extend the value. 928 int MaskVal = SignExtend32(Value, ByteSize * 8); 929 930 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 931 if (MaskVal == 0) return SDValue(); 932 933 // Finally, if this value fits in a 5 bit sext field, return it 934 if (SignExtend32<5>(MaskVal) == MaskVal) 935 return DAG.getTargetConstant(MaskVal, MVT::i32); 936 return SDValue(); 937} 938 939//===----------------------------------------------------------------------===// 940// Addressing Mode Selection 941//===----------------------------------------------------------------------===// 942 943/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 944/// or 64-bit immediate, and if the value can be accurately represented as a 945/// sign extension from a 16-bit value. If so, this returns true and the 946/// immediate. 947static bool isIntS16Immediate(SDNode *N, short &Imm) { 948 if (N->getOpcode() != ISD::Constant) 949 return false; 950 951 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 952 if (N->getValueType(0) == MVT::i32) 953 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 954 else 955 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 956} 957static bool isIntS16Immediate(SDValue Op, short &Imm) { 958 return isIntS16Immediate(Op.getNode(), Imm); 959} 960 961 962/// SelectAddressRegReg - Given the specified addressed, check to see if it 963/// can be represented as an indexed [r+r] operation. Returns false if it 964/// can be more efficiently represented with [r+imm]. 965bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 966 SDValue &Index, 967 SelectionDAG &DAG) const { 968 short imm = 0; 969 if (N.getOpcode() == ISD::ADD) { 970 if (isIntS16Immediate(N.getOperand(1), imm)) 971 return false; // r+i 972 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 973 return false; // r+i 974 975 Base = N.getOperand(0); 976 Index = N.getOperand(1); 977 return true; 978 } else if (N.getOpcode() == ISD::OR) { 979 if (isIntS16Immediate(N.getOperand(1), imm)) 980 return false; // r+i can fold it if we can. 981 982 // If this is an or of disjoint bitfields, we can codegen this as an add 983 // (for better address arithmetic) if the LHS and RHS of the OR are provably 984 // disjoint. 985 APInt LHSKnownZero, LHSKnownOne; 986 APInt RHSKnownZero, RHSKnownOne; 987 DAG.ComputeMaskedBits(N.getOperand(0), 988 LHSKnownZero, LHSKnownOne); 989 990 if (LHSKnownZero.getBoolValue()) { 991 DAG.ComputeMaskedBits(N.getOperand(1), 992 RHSKnownZero, RHSKnownOne); 993 // If all of the bits are known zero on the LHS or RHS, the add won't 994 // carry. 995 if (~(LHSKnownZero | RHSKnownZero) == 0) { 996 Base = N.getOperand(0); 997 Index = N.getOperand(1); 998 return true; 999 } 1000 } 1001 } 1002 1003 return false; 1004} 1005 1006/// Returns true if the address N can be represented by a base register plus 1007/// a signed 16-bit displacement [r+imm], and if it is not better 1008/// represented as reg+reg. 1009bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 1010 SDValue &Base, 1011 SelectionDAG &DAG) const { 1012 // FIXME dl should come from parent load or store, not from address 1013 DebugLoc dl = N.getDebugLoc(); 1014 // If this can be more profitably realized as r+r, fail. 1015 if (SelectAddressRegReg(N, Disp, Base, DAG)) 1016 return false; 1017 1018 if (N.getOpcode() == ISD::ADD) { 1019 short imm = 0; 1020 if (isIntS16Immediate(N.getOperand(1), imm)) { 1021 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 1022 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 1023 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1024 } else { 1025 Base = N.getOperand(0); 1026 } 1027 return true; // [r+i] 1028 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 1029 // Match LOAD (ADD (X, Lo(G))). 1030 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 1031 && "Cannot handle constant offsets yet!"); 1032 Disp = N.getOperand(1).getOperand(0); // The global address. 1033 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 1034 Disp.getOpcode() == ISD::TargetGlobalTLSAddress || 1035 Disp.getOpcode() == ISD::TargetConstantPool || 1036 Disp.getOpcode() == ISD::TargetJumpTable); 1037 Base = N.getOperand(0); 1038 return true; // [&g+r] 1039 } 1040 } else if (N.getOpcode() == ISD::OR) { 1041 short imm = 0; 1042 if (isIntS16Immediate(N.getOperand(1), imm)) { 1043 // If this is an or of disjoint bitfields, we can codegen this as an add 1044 // (for better address arithmetic) if the LHS and RHS of the OR are 1045 // provably disjoint. 1046 APInt LHSKnownZero, LHSKnownOne; 1047 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); 1048 1049 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1050 // If all of the bits are known zero on the LHS or RHS, the add won't 1051 // carry. 1052 Base = N.getOperand(0); 1053 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 1054 return true; 1055 } 1056 } 1057 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1058 // Loading from a constant address. 1059 1060 // If this address fits entirely in a 16-bit sext immediate field, codegen 1061 // this as "d, 0" 1062 short Imm; 1063 if (isIntS16Immediate(CN, Imm)) { 1064 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 1065 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, 1066 CN->getValueType(0)); 1067 return true; 1068 } 1069 1070 // Handle 32-bit sext immediates with LIS + addr mode. 1071 if (CN->getValueType(0) == MVT::i32 || 1072 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1073 int Addr = (int)CN->getZExtValue(); 1074 1075 // Otherwise, break this down into an LIS + disp. 1076 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 1077 1078 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 1079 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1080 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 1081 return true; 1082 } 1083 } 1084 1085 Disp = DAG.getTargetConstant(0, getPointerTy()); 1086 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1087 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1088 else 1089 Base = N; 1090 return true; // [r+0] 1091} 1092 1093/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 1094/// represented as an indexed [r+r] operation. 1095bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 1096 SDValue &Index, 1097 SelectionDAG &DAG) const { 1098 // Check to see if we can easily represent this as an [r+r] address. This 1099 // will fail if it thinks that the address is more profitably represented as 1100 // reg+imm, e.g. where imm = 0. 1101 if (SelectAddressRegReg(N, Base, Index, DAG)) 1102 return true; 1103 1104 // If the operand is an addition, always emit this as [r+r], since this is 1105 // better (for code size, and execution, as the memop does the add for free) 1106 // than emitting an explicit add. 1107 if (N.getOpcode() == ISD::ADD) { 1108 Base = N.getOperand(0); 1109 Index = N.getOperand(1); 1110 return true; 1111 } 1112 1113 // Otherwise, do it the hard way, using R0 as the base register. 1114 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, 1115 N.getValueType()); 1116 Index = N; 1117 return true; 1118} 1119 1120/// SelectAddressRegImmShift - Returns true if the address N can be 1121/// represented by a base register plus a signed 14-bit displacement 1122/// [r+imm*4]. Suitable for use by STD and friends. 1123bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 1124 SDValue &Base, 1125 SelectionDAG &DAG) const { 1126 // FIXME dl should come from the parent load or store, not the address 1127 DebugLoc dl = N.getDebugLoc(); 1128 // If this can be more profitably realized as r+r, fail. 1129 if (SelectAddressRegReg(N, Disp, Base, DAG)) 1130 return false; 1131 1132 if (N.getOpcode() == ISD::ADD) { 1133 short imm = 0; 1134 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 1135 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1136 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 1137 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1138 } else { 1139 Base = N.getOperand(0); 1140 } 1141 return true; // [r+i] 1142 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 1143 // Match LOAD (ADD (X, Lo(G))). 1144 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 1145 && "Cannot handle constant offsets yet!"); 1146 Disp = N.getOperand(1).getOperand(0); // The global address. 1147 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 1148 Disp.getOpcode() == ISD::TargetConstantPool || 1149 Disp.getOpcode() == ISD::TargetJumpTable); 1150 Base = N.getOperand(0); 1151 return true; // [&g+r] 1152 } 1153 } else if (N.getOpcode() == ISD::OR) { 1154 short imm = 0; 1155 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 1156 // If this is an or of disjoint bitfields, we can codegen this as an add 1157 // (for better address arithmetic) if the LHS and RHS of the OR are 1158 // provably disjoint. 1159 APInt LHSKnownZero, LHSKnownOne; 1160 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); 1161 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1162 // If all of the bits are known zero on the LHS or RHS, the add won't 1163 // carry. 1164 Base = N.getOperand(0); 1165 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1166 return true; 1167 } 1168 } 1169 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1170 // Loading from a constant address. Verify low two bits are clear. 1171 if ((CN->getZExtValue() & 3) == 0) { 1172 // If this address fits entirely in a 14-bit sext immediate field, codegen 1173 // this as "d, 0" 1174 short Imm; 1175 if (isIntS16Immediate(CN, Imm)) { 1176 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1177 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, 1178 CN->getValueType(0)); 1179 return true; 1180 } 1181 1182 // Fold the low-part of 32-bit absolute addresses into addr mode. 1183 if (CN->getValueType(0) == MVT::i32 || 1184 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1185 int Addr = (int)CN->getZExtValue(); 1186 1187 // Otherwise, break this down into an LIS + disp. 1188 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1189 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1190 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1191 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1192 return true; 1193 } 1194 } 1195 } 1196 1197 Disp = DAG.getTargetConstant(0, getPointerTy()); 1198 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1199 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1200 else 1201 Base = N; 1202 return true; // [r+0] 1203} 1204 1205 1206/// getPreIndexedAddressParts - returns true by value, base pointer and 1207/// offset pointer and addressing mode by reference if the node's address 1208/// can be legally represented as pre-indexed load / store address. 1209bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1210 SDValue &Offset, 1211 ISD::MemIndexedMode &AM, 1212 SelectionDAG &DAG) const { 1213 if (DisablePPCPreinc) return false; 1214 1215 bool isLoad = true; 1216 SDValue Ptr; 1217 EVT VT; 1218 unsigned Alignment; 1219 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1220 Ptr = LD->getBasePtr(); 1221 VT = LD->getMemoryVT(); 1222 Alignment = LD->getAlignment(); 1223 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1224 Ptr = ST->getBasePtr(); 1225 VT = ST->getMemoryVT(); 1226 Alignment = ST->getAlignment(); 1227 isLoad = false; 1228 } else 1229 return false; 1230 1231 // PowerPC doesn't have preinc load/store instructions for vectors. 1232 if (VT.isVector()) 1233 return false; 1234 1235 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) { 1236 1237 // Common code will reject creating a pre-inc form if the base pointer 1238 // is a frame index, or if N is a store and the base pointer is either 1239 // the same as or a predecessor of the value being stored. Check for 1240 // those situations here, and try with swapped Base/Offset instead. 1241 bool Swap = false; 1242 1243 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base)) 1244 Swap = true; 1245 else if (!isLoad) { 1246 SDValue Val = cast<StoreSDNode>(N)->getValue(); 1247 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode())) 1248 Swap = true; 1249 } 1250 1251 if (Swap) 1252 std::swap(Base, Offset); 1253 1254 AM = ISD::PRE_INC; 1255 return true; 1256 } 1257 1258 // LDU/STU use reg+imm*4, others use reg+imm. 1259 if (VT != MVT::i64) { 1260 // reg + imm 1261 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1262 return false; 1263 } else { 1264 // LDU/STU need an address with at least 4-byte alignment. 1265 if (Alignment < 4) 1266 return false; 1267 1268 // reg + imm * 4. 1269 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1270 return false; 1271 } 1272 1273 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1274 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1275 // sext i32 to i64 when addr mode is r+i. 1276 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1277 LD->getExtensionType() == ISD::SEXTLOAD && 1278 isa<ConstantSDNode>(Offset)) 1279 return false; 1280 } 1281 1282 AM = ISD::PRE_INC; 1283 return true; 1284} 1285 1286//===----------------------------------------------------------------------===// 1287// LowerOperation implementation 1288//===----------------------------------------------------------------------===// 1289 1290/// GetLabelAccessInfo - Return true if we should reference labels using a 1291/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. 1292static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, 1293 unsigned &LoOpFlags, const GlobalValue *GV = 0) { 1294 HiOpFlags = PPCII::MO_HA16; 1295 LoOpFlags = PPCII::MO_LO16; 1296 1297 // Don't use the pic base if not in PIC relocation model. Or if we are on a 1298 // non-darwin platform. We don't support PIC on other platforms yet. 1299 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ && 1300 TM.getSubtarget<PPCSubtarget>().isDarwin(); 1301 if (isPIC) { 1302 HiOpFlags |= PPCII::MO_PIC_FLAG; 1303 LoOpFlags |= PPCII::MO_PIC_FLAG; 1304 } 1305 1306 // If this is a reference to a global value that requires a non-lazy-ptr, make 1307 // sure that instruction lowering adds it. 1308 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) { 1309 HiOpFlags |= PPCII::MO_NLP_FLAG; 1310 LoOpFlags |= PPCII::MO_NLP_FLAG; 1311 1312 if (GV->hasHiddenVisibility()) { 1313 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1314 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1315 } 1316 } 1317 1318 return isPIC; 1319} 1320 1321static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, 1322 SelectionDAG &DAG) { 1323 EVT PtrVT = HiPart.getValueType(); 1324 SDValue Zero = DAG.getConstant(0, PtrVT); 1325 DebugLoc DL = HiPart.getDebugLoc(); 1326 1327 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); 1328 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero); 1329 1330 // With PIC, the first instruction is actually "GR+hi(&G)". 1331 if (isPIC) 1332 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1333 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi); 1334 1335 // Generate non-pic code that has direct accesses to the constant pool. 1336 // The address of the global is just (hi(&g)+lo(&g)). 1337 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1338} 1339 1340SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1341 SelectionDAG &DAG) const { 1342 EVT PtrVT = Op.getValueType(); 1343 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1344 const Constant *C = CP->getConstVal(); 1345 1346 // 64-bit SVR4 ABI code is always position-independent. 1347 // The actual address of the GlobalValue is stored in the TOC. 1348 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1349 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0); 1350 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA, 1351 DAG.getRegister(PPC::X2, MVT::i64)); 1352 } 1353 1354 unsigned MOHiFlag, MOLoFlag; 1355 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1356 SDValue CPIHi = 1357 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag); 1358 SDValue CPILo = 1359 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag); 1360 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG); 1361} 1362 1363SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1364 EVT PtrVT = Op.getValueType(); 1365 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1366 1367 // 64-bit SVR4 ABI code is always position-independent. 1368 // The actual address of the GlobalValue is stored in the TOC. 1369 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1370 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1371 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA, 1372 DAG.getRegister(PPC::X2, MVT::i64)); 1373 } 1374 1375 unsigned MOHiFlag, MOLoFlag; 1376 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1377 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag); 1378 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag); 1379 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG); 1380} 1381 1382SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1383 SelectionDAG &DAG) const { 1384 EVT PtrVT = Op.getValueType(); 1385 1386 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1387 1388 unsigned MOHiFlag, MOLoFlag; 1389 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1390 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag); 1391 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag); 1392 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG); 1393} 1394 1395SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1396 SelectionDAG &DAG) const { 1397 1398 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1399 DebugLoc dl = GA->getDebugLoc(); 1400 const GlobalValue *GV = GA->getGlobal(); 1401 EVT PtrVT = getPointerTy(); 1402 bool is64bit = PPCSubTarget.isPPC64(); 1403 1404 TLSModel::Model Model = getTargetMachine().getTLSModel(GV); 1405 1406 if (Model == TLSModel::LocalExec) { 1407 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1408 PPCII::MO_TPREL16_HA); 1409 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 1410 PPCII::MO_TPREL16_LO); 1411 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2, 1412 is64bit ? MVT::i64 : MVT::i32); 1413 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg); 1414 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi); 1415 } 1416 1417 if (!is64bit) 1418 llvm_unreachable("only local-exec is currently supported for ppc32"); 1419 1420 if (Model == TLSModel::InitialExec) { 1421 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1422 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1423 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, 1424 PtrVT, GOTReg, TGA); 1425 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, 1426 PtrVT, TGA, TPOffsetHi); 1427 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA); 1428 } 1429 1430 if (Model == TLSModel::GeneralDynamic) { 1431 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1432 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1433 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT, 1434 GOTReg, TGA); 1435 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT, 1436 GOTEntryHi, TGA); 1437 1438 // We need a chain node, and don't have one handy. The underlying 1439 // call has no side effects, so using the function entry node 1440 // suffices. 1441 SDValue Chain = DAG.getEntryNode(); 1442 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry); 1443 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64); 1444 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl, 1445 PtrVT, ParmReg, TGA); 1446 // The return value from GET_TLS_ADDR really is in X3 already, but 1447 // some hacks are needed here to tie everything together. The extra 1448 // copies dissolve during subsequent transforms. 1449 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr); 1450 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT); 1451 } 1452 1453 if (Model == TLSModel::LocalDynamic) { 1454 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0); 1455 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); 1456 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT, 1457 GOTReg, TGA); 1458 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT, 1459 GOTEntryHi, TGA); 1460 1461 // We need a chain node, and don't have one handy. The underlying 1462 // call has no side effects, so using the function entry node 1463 // suffices. 1464 SDValue Chain = DAG.getEntryNode(); 1465 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry); 1466 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64); 1467 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl, 1468 PtrVT, ParmReg, TGA); 1469 // The return value from GET_TLSLD_ADDR really is in X3 already, but 1470 // some hacks are needed here to tie everything together. The extra 1471 // copies dissolve during subsequent transforms. 1472 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr); 1473 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT, 1474 Chain, ParmReg, TGA); 1475 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA); 1476 } 1477 1478 llvm_unreachable("Unknown TLS model!"); 1479} 1480 1481SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1482 SelectionDAG &DAG) const { 1483 EVT PtrVT = Op.getValueType(); 1484 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1485 DebugLoc DL = GSDN->getDebugLoc(); 1486 const GlobalValue *GV = GSDN->getGlobal(); 1487 1488 // 64-bit SVR4 ABI code is always position-independent. 1489 // The actual address of the GlobalValue is stored in the TOC. 1490 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1491 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset()); 1492 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA, 1493 DAG.getRegister(PPC::X2, MVT::i64)); 1494 } 1495 1496 unsigned MOHiFlag, MOLoFlag; 1497 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV); 1498 1499 SDValue GAHi = 1500 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag); 1501 SDValue GALo = 1502 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); 1503 1504 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG); 1505 1506 // If the global reference is actually to a non-lazy-pointer, we have to do an 1507 // extra load to get the address of the global. 1508 if (MOHiFlag & PPCII::MO_NLP_FLAG) 1509 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(), 1510 false, false, false, 0); 1511 return Ptr; 1512} 1513 1514SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1515 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1516 DebugLoc dl = Op.getDebugLoc(); 1517 1518 // If we're comparing for equality to zero, expose the fact that this is 1519 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1520 // fold the new nodes. 1521 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1522 if (C->isNullValue() && CC == ISD::SETEQ) { 1523 EVT VT = Op.getOperand(0).getValueType(); 1524 SDValue Zext = Op.getOperand(0); 1525 if (VT.bitsLT(MVT::i32)) { 1526 VT = MVT::i32; 1527 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1528 } 1529 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1530 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1531 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1532 DAG.getConstant(Log2b, MVT::i32)); 1533 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1534 } 1535 // Leave comparisons against 0 and -1 alone for now, since they're usually 1536 // optimized. FIXME: revisit this when we can custom lower all setcc 1537 // optimizations. 1538 if (C->isAllOnesValue() || C->isNullValue()) 1539 return SDValue(); 1540 } 1541 1542 // If we have an integer seteq/setne, turn it into a compare against zero 1543 // by xor'ing the rhs with the lhs, which is faster than setting a 1544 // condition register, reading it back out, and masking the correct bit. The 1545 // normal approach here uses sub to do this instead of xor. Using xor exposes 1546 // the result to other bit-twiddling opportunities. 1547 EVT LHSVT = Op.getOperand(0).getValueType(); 1548 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1549 EVT VT = Op.getValueType(); 1550 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1551 Op.getOperand(1)); 1552 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1553 } 1554 return SDValue(); 1555} 1556 1557SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1558 const PPCSubtarget &Subtarget) const { 1559 SDNode *Node = Op.getNode(); 1560 EVT VT = Node->getValueType(0); 1561 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1562 SDValue InChain = Node->getOperand(0); 1563 SDValue VAListPtr = Node->getOperand(1); 1564 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1565 DebugLoc dl = Node->getDebugLoc(); 1566 1567 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); 1568 1569 // gpr_index 1570 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1571 VAListPtr, MachinePointerInfo(SV), MVT::i8, 1572 false, false, 0); 1573 InChain = GprIndex.getValue(1); 1574 1575 if (VT == MVT::i64) { 1576 // Check if GprIndex is even 1577 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, 1578 DAG.getConstant(1, MVT::i32)); 1579 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, 1580 DAG.getConstant(0, MVT::i32), ISD::SETNE); 1581 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, 1582 DAG.getConstant(1, MVT::i32)); 1583 // Align GprIndex to be even if it isn't 1584 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, 1585 GprIndex); 1586 } 1587 1588 // fpr index is 1 byte after gpr 1589 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1590 DAG.getConstant(1, MVT::i32)); 1591 1592 // fpr 1593 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1594 FprPtr, MachinePointerInfo(SV), MVT::i8, 1595 false, false, 0); 1596 InChain = FprIndex.getValue(1); 1597 1598 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1599 DAG.getConstant(8, MVT::i32)); 1600 1601 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1602 DAG.getConstant(4, MVT::i32)); 1603 1604 // areas 1605 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, 1606 MachinePointerInfo(), false, false, 1607 false, 0); 1608 InChain = OverflowArea.getValue(1); 1609 1610 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, 1611 MachinePointerInfo(), false, false, 1612 false, 0); 1613 InChain = RegSaveArea.getValue(1); 1614 1615 // select overflow_area if index > 8 1616 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, 1617 DAG.getConstant(8, MVT::i32), ISD::SETLT); 1618 1619 // adjustment constant gpr_index * 4/8 1620 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, 1621 VT.isInteger() ? GprIndex : FprIndex, 1622 DAG.getConstant(VT.isInteger() ? 4 : 8, 1623 MVT::i32)); 1624 1625 // OurReg = RegSaveArea + RegConstant 1626 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea, 1627 RegConstant); 1628 1629 // Floating types are 32 bytes into RegSaveArea 1630 if (VT.isFloatingPoint()) 1631 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg, 1632 DAG.getConstant(32, MVT::i32)); 1633 1634 // increase {f,g}pr_index by 1 (or 2 if VT is i64) 1635 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, 1636 VT.isInteger() ? GprIndex : FprIndex, 1637 DAG.getConstant(VT == MVT::i64 ? 2 : 1, 1638 MVT::i32)); 1639 1640 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1, 1641 VT.isInteger() ? VAListPtr : FprPtr, 1642 MachinePointerInfo(SV), 1643 MVT::i8, false, false, 0); 1644 1645 // determine if we should load from reg_save_area or overflow_area 1646 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea); 1647 1648 // increase overflow_area by 4/8 if gpr/fpr > 8 1649 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea, 1650 DAG.getConstant(VT.isInteger() ? 4 : 8, 1651 MVT::i32)); 1652 1653 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, 1654 OverflowAreaPlusN); 1655 1656 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, 1657 OverflowAreaPtr, 1658 MachinePointerInfo(), 1659 MVT::i32, false, false, 0); 1660 1661 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), 1662 false, false, false, 0); 1663} 1664 1665SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 1666 SelectionDAG &DAG) const { 1667 return Op.getOperand(0); 1668} 1669 1670SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 1671 SelectionDAG &DAG) const { 1672 SDValue Chain = Op.getOperand(0); 1673 SDValue Trmp = Op.getOperand(1); // trampoline 1674 SDValue FPtr = Op.getOperand(2); // nested function 1675 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1676 DebugLoc dl = Op.getDebugLoc(); 1677 1678 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1679 bool isPPC64 = (PtrVT == MVT::i64); 1680 Type *IntPtrTy = 1681 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType( 1682 *DAG.getContext()); 1683 1684 TargetLowering::ArgListTy Args; 1685 TargetLowering::ArgListEntry Entry; 1686 1687 Entry.Ty = IntPtrTy; 1688 Entry.Node = Trmp; Args.push_back(Entry); 1689 1690 // TrampSize == (isPPC64 ? 48 : 40); 1691 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1692 isPPC64 ? MVT::i64 : MVT::i32); 1693 Args.push_back(Entry); 1694 1695 Entry.Node = FPtr; Args.push_back(Entry); 1696 Entry.Node = Nest; Args.push_back(Entry); 1697 1698 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1699 TargetLowering::CallLoweringInfo CLI(Chain, 1700 Type::getVoidTy(*DAG.getContext()), 1701 false, false, false, false, 0, 1702 CallingConv::C, 1703 /*isTailCall=*/false, 1704 /*doesNotRet=*/false, 1705 /*isReturnValueUsed=*/true, 1706 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1707 Args, DAG, dl); 1708 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1709 1710 return CallResult.second; 1711} 1712 1713SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1714 const PPCSubtarget &Subtarget) const { 1715 MachineFunction &MF = DAG.getMachineFunction(); 1716 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1717 1718 DebugLoc dl = Op.getDebugLoc(); 1719 1720 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1721 // vastart just stores the address of the VarArgsFrameIndex slot into the 1722 // memory location argument. 1723 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1724 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1725 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1726 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 1727 MachinePointerInfo(SV), 1728 false, false, 0); 1729 } 1730 1731 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1732 // We suppose the given va_list is already allocated. 1733 // 1734 // typedef struct { 1735 // char gpr; /* index into the array of 8 GPRs 1736 // * stored in the register save area 1737 // * gpr=0 corresponds to r3, 1738 // * gpr=1 to r4, etc. 1739 // */ 1740 // char fpr; /* index into the array of 8 FPRs 1741 // * stored in the register save area 1742 // * fpr=0 corresponds to f1, 1743 // * fpr=1 to f2, etc. 1744 // */ 1745 // char *overflow_arg_area; 1746 // /* location on stack that holds 1747 // * the next overflow argument 1748 // */ 1749 // char *reg_save_area; 1750 // /* where r3:r10 and f1:f8 (if saved) 1751 // * are stored 1752 // */ 1753 // } va_list[1]; 1754 1755 1756 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1757 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1758 1759 1760 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1761 1762 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1763 PtrVT); 1764 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1765 PtrVT); 1766 1767 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1768 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1769 1770 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1771 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1772 1773 uint64_t FPROffset = 1; 1774 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1775 1776 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1777 1778 // Store first byte : number of int regs 1779 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1780 Op.getOperand(1), 1781 MachinePointerInfo(SV), 1782 MVT::i8, false, false, 0); 1783 uint64_t nextOffset = FPROffset; 1784 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1785 ConstFPROffset); 1786 1787 // Store second byte : number of float regs 1788 SDValue secondStore = 1789 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, 1790 MachinePointerInfo(SV, nextOffset), MVT::i8, 1791 false, false, 0); 1792 nextOffset += StackOffset; 1793 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1794 1795 // Store second word : arguments given on stack 1796 SDValue thirdStore = 1797 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, 1798 MachinePointerInfo(SV, nextOffset), 1799 false, false, 0); 1800 nextOffset += FrameOffset; 1801 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1802 1803 // Store third word : arguments given in registers 1804 return DAG.getStore(thirdStore, dl, FR, nextPtr, 1805 MachinePointerInfo(SV, nextOffset), 1806 false, false, 0); 1807 1808} 1809 1810#include "PPCGenCallingConv.inc" 1811 1812static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 1813 CCValAssign::LocInfo &LocInfo, 1814 ISD::ArgFlagsTy &ArgFlags, 1815 CCState &State) { 1816 return true; 1817} 1818 1819static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 1820 MVT &LocVT, 1821 CCValAssign::LocInfo &LocInfo, 1822 ISD::ArgFlagsTy &ArgFlags, 1823 CCState &State) { 1824 static const uint16_t ArgRegs[] = { 1825 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1826 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1827 }; 1828 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1829 1830 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1831 1832 // Skip one register if the first unallocated register has an even register 1833 // number and there are still argument registers available which have not been 1834 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1835 // need to skip a register if RegNum is odd. 1836 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1837 State.AllocateReg(ArgRegs[RegNum]); 1838 } 1839 1840 // Always return false here, as this function only makes sure that the first 1841 // unallocated register has an odd register number and does not actually 1842 // allocate a register for the current argument. 1843 return false; 1844} 1845 1846static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 1847 MVT &LocVT, 1848 CCValAssign::LocInfo &LocInfo, 1849 ISD::ArgFlagsTy &ArgFlags, 1850 CCState &State) { 1851 static const uint16_t ArgRegs[] = { 1852 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1853 PPC::F8 1854 }; 1855 1856 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1857 1858 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1859 1860 // If there is only one Floating-point register left we need to put both f64 1861 // values of a split ppc_fp128 value on the stack. 1862 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1863 State.AllocateReg(ArgRegs[RegNum]); 1864 } 1865 1866 // Always return false here, as this function only makes sure that the two f64 1867 // values a ppc_fp128 value is split into are both passed in registers or both 1868 // passed on the stack and does not actually allocate a register for the 1869 // current argument. 1870 return false; 1871} 1872 1873/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1874/// on Darwin. 1875static const uint16_t *GetFPR() { 1876 static const uint16_t FPR[] = { 1877 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1878 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1879 }; 1880 1881 return FPR; 1882} 1883 1884/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1885/// the stack. 1886static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1887 unsigned PtrByteSize) { 1888 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1889 if (Flags.isByVal()) 1890 ArgSize = Flags.getByValSize(); 1891 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1892 1893 return ArgSize; 1894} 1895 1896SDValue 1897PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1898 CallingConv::ID CallConv, bool isVarArg, 1899 const SmallVectorImpl<ISD::InputArg> 1900 &Ins, 1901 DebugLoc dl, SelectionDAG &DAG, 1902 SmallVectorImpl<SDValue> &InVals) 1903 const { 1904 if (PPCSubTarget.isSVR4ABI()) { 1905 if (PPCSubTarget.isPPC64()) 1906 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, 1907 dl, DAG, InVals); 1908 else 1909 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, 1910 dl, DAG, InVals); 1911 } else { 1912 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1913 dl, DAG, InVals); 1914 } 1915} 1916 1917SDValue 1918PPCTargetLowering::LowerFormalArguments_32SVR4( 1919 SDValue Chain, 1920 CallingConv::ID CallConv, bool isVarArg, 1921 const SmallVectorImpl<ISD::InputArg> 1922 &Ins, 1923 DebugLoc dl, SelectionDAG &DAG, 1924 SmallVectorImpl<SDValue> &InVals) const { 1925 1926 // 32-bit SVR4 ABI Stack Frame Layout: 1927 // +-----------------------------------+ 1928 // +--> | Back chain | 1929 // | +-----------------------------------+ 1930 // | | Floating-point register save area | 1931 // | +-----------------------------------+ 1932 // | | General register save area | 1933 // | +-----------------------------------+ 1934 // | | CR save word | 1935 // | +-----------------------------------+ 1936 // | | VRSAVE save word | 1937 // | +-----------------------------------+ 1938 // | | Alignment padding | 1939 // | +-----------------------------------+ 1940 // | | Vector register save area | 1941 // | +-----------------------------------+ 1942 // | | Local variable space | 1943 // | +-----------------------------------+ 1944 // | | Parameter list area | 1945 // | +-----------------------------------+ 1946 // | | LR save word | 1947 // | +-----------------------------------+ 1948 // SP--> +--- | Back chain | 1949 // +-----------------------------------+ 1950 // 1951 // Specifications: 1952 // System V Application Binary Interface PowerPC Processor Supplement 1953 // AltiVec Technology Programming Interface Manual 1954 1955 MachineFunction &MF = DAG.getMachineFunction(); 1956 MachineFrameInfo *MFI = MF.getFrameInfo(); 1957 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1958 1959 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1960 // Potential tail calls could cause overwriting of argument stack slots. 1961 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 1962 (CallConv == CallingConv::Fast)); 1963 unsigned PtrByteSize = 4; 1964 1965 // Assign locations to all of the incoming arguments. 1966 SmallVector<CCValAssign, 16> ArgLocs; 1967 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1968 getTargetMachine(), ArgLocs, *DAG.getContext()); 1969 1970 // Reserve space for the linkage area on the stack. 1971 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 1972 1973 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4); 1974 1975 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1976 CCValAssign &VA = ArgLocs[i]; 1977 1978 // Arguments stored in registers. 1979 if (VA.isRegLoc()) { 1980 const TargetRegisterClass *RC; 1981 EVT ValVT = VA.getValVT(); 1982 1983 switch (ValVT.getSimpleVT().SimpleTy) { 1984 default: 1985 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1986 case MVT::i32: 1987 RC = &PPC::GPRCRegClass; 1988 break; 1989 case MVT::f32: 1990 RC = &PPC::F4RCRegClass; 1991 break; 1992 case MVT::f64: 1993 RC = &PPC::F8RCRegClass; 1994 break; 1995 case MVT::v16i8: 1996 case MVT::v8i16: 1997 case MVT::v4i32: 1998 case MVT::v4f32: 1999 RC = &PPC::VRRCRegClass; 2000 break; 2001 } 2002 2003 // Transform the arguments stored in physical registers into virtual ones. 2004 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2005 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 2006 2007 InVals.push_back(ArgValue); 2008 } else { 2009 // Argument stored in memory. 2010 assert(VA.isMemLoc()); 2011 2012 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 2013 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 2014 isImmutable); 2015 2016 // Create load nodes to retrieve arguments from the stack. 2017 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2018 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2019 MachinePointerInfo(), 2020 false, false, false, 0)); 2021 } 2022 } 2023 2024 // Assign locations to all of the incoming aggregate by value arguments. 2025 // Aggregates passed by value are stored in the local variable space of the 2026 // caller's stack frame, right above the parameter list area. 2027 SmallVector<CCValAssign, 16> ByValArgLocs; 2028 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2029 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 2030 2031 // Reserve stack space for the allocations in CCInfo. 2032 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 2033 2034 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal); 2035 2036 // Area that is at least reserved in the caller of this function. 2037 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 2038 2039 // Set the size that is at least reserved in caller of this function. Tail 2040 // call optimized function's reserved stack space needs to be aligned so that 2041 // taking the difference between two stack areas will result in an aligned 2042 // stack. 2043 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2044 2045 MinReservedArea = 2046 std::max(MinReservedArea, 2047 PPCFrameLowering::getMinCallFrameSize(false, false)); 2048 2049 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2050 getStackAlignment(); 2051 unsigned AlignMask = TargetAlign-1; 2052 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2053 2054 FI->setMinReservedArea(MinReservedArea); 2055 2056 SmallVector<SDValue, 8> MemOps; 2057 2058 // If the function takes variable number of arguments, make a frame index for 2059 // the start of the first vararg value... for expansion of llvm.va_start. 2060 if (isVarArg) { 2061 static const uint16_t GPArgRegs[] = { 2062 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2063 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2064 }; 2065 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 2066 2067 static const uint16_t FPArgRegs[] = { 2068 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 2069 PPC::F8 2070 }; 2071 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 2072 2073 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 2074 NumGPArgRegs)); 2075 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 2076 NumFPArgRegs)); 2077 2078 // Make room for NumGPArgRegs and NumFPArgRegs. 2079 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 2080 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 2081 2082 FuncInfo->setVarArgsStackOffset( 2083 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2084 CCInfo.getNextStackOffset(), true)); 2085 2086 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 2087 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2088 2089 // The fixed integer arguments of a variadic function are stored to the 2090 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing 2091 // the result of va_next. 2092 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) { 2093 // Get an existing live-in vreg, or add a new one. 2094 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); 2095 if (!VReg) 2096 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 2097 2098 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2099 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2100 MachinePointerInfo(), false, false, 0); 2101 MemOps.push_back(Store); 2102 // Increment the address by four for the next argument to store 2103 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2104 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2105 } 2106 2107 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 2108 // is set. 2109 // The double arguments are stored to the VarArgsFrameIndex 2110 // on the stack. 2111 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) { 2112 // Get an existing live-in vreg, or add a new one. 2113 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); 2114 if (!VReg) 2115 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 2116 2117 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 2118 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2119 MachinePointerInfo(), false, false, 0); 2120 MemOps.push_back(Store); 2121 // Increment the address by eight for the next argument to store 2122 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 2123 PtrVT); 2124 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2125 } 2126 } 2127 2128 if (!MemOps.empty()) 2129 Chain = DAG.getNode(ISD::TokenFactor, dl, 2130 MVT::Other, &MemOps[0], MemOps.size()); 2131 2132 return Chain; 2133} 2134 2135// PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2136// value to MVT::i64 and then truncate to the correct register size. 2137SDValue 2138PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, 2139 SelectionDAG &DAG, SDValue ArgVal, 2140 DebugLoc dl) const { 2141 if (Flags.isSExt()) 2142 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 2143 DAG.getValueType(ObjectVT)); 2144 else if (Flags.isZExt()) 2145 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 2146 DAG.getValueType(ObjectVT)); 2147 2148 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 2149} 2150 2151// Set the size that is at least reserved in caller of this function. Tail 2152// call optimized functions' reserved stack space needs to be aligned so that 2153// taking the difference between two stack areas will result in an aligned 2154// stack. 2155void 2156PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG, 2157 unsigned nAltivecParamsAtEnd, 2158 unsigned MinReservedArea, 2159 bool isPPC64) const { 2160 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2161 // Add the Altivec parameters at the end, if needed. 2162 if (nAltivecParamsAtEnd) { 2163 MinReservedArea = ((MinReservedArea+15)/16)*16; 2164 MinReservedArea += 16*nAltivecParamsAtEnd; 2165 } 2166 MinReservedArea = 2167 std::max(MinReservedArea, 2168 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2169 unsigned TargetAlign 2170 = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2171 getStackAlignment(); 2172 unsigned AlignMask = TargetAlign-1; 2173 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2174 FI->setMinReservedArea(MinReservedArea); 2175} 2176 2177SDValue 2178PPCTargetLowering::LowerFormalArguments_64SVR4( 2179 SDValue Chain, 2180 CallingConv::ID CallConv, bool isVarArg, 2181 const SmallVectorImpl<ISD::InputArg> 2182 &Ins, 2183 DebugLoc dl, SelectionDAG &DAG, 2184 SmallVectorImpl<SDValue> &InVals) const { 2185 // TODO: add description of PPC stack frame format, or at least some docs. 2186 // 2187 MachineFunction &MF = DAG.getMachineFunction(); 2188 MachineFrameInfo *MFI = MF.getFrameInfo(); 2189 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 2190 2191 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2192 // Potential tail calls could cause overwriting of argument stack slots. 2193 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 2194 (CallConv == CallingConv::Fast)); 2195 unsigned PtrByteSize = 8; 2196 2197 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); 2198 // Area that is at least reserved in caller of this function. 2199 unsigned MinReservedArea = ArgOffset; 2200 2201 static const uint16_t GPR[] = { 2202 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2203 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2204 }; 2205 2206 static const uint16_t *FPR = GetFPR(); 2207 2208 static const uint16_t VR[] = { 2209 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2210 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2211 }; 2212 2213 const unsigned Num_GPR_Regs = array_lengthof(GPR); 2214 const unsigned Num_FPR_Regs = 13; 2215 const unsigned Num_VR_Regs = array_lengthof(VR); 2216 2217 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2218 2219 // Add DAG nodes to load the arguments or copy them out of registers. On 2220 // entry to a function on PPC, the arguments start after the linkage area, 2221 // although the first ones are often in registers. 2222 2223 SmallVector<SDValue, 8> MemOps; 2224 unsigned nAltivecParamsAtEnd = 0; 2225 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); 2226 unsigned CurArgIdx = 0; 2227 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 2228 SDValue ArgVal; 2229 bool needsLoad = false; 2230 EVT ObjectVT = Ins[ArgNo].VT; 2231 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 2232 unsigned ArgSize = ObjSize; 2233 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2234 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx); 2235 CurArgIdx = Ins[ArgNo].OrigArgIndex; 2236 2237 unsigned CurArgOffset = ArgOffset; 2238 2239 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 2240 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 2241 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 2242 if (isVarArg) { 2243 MinReservedArea = ((MinReservedArea+15)/16)*16; 2244 MinReservedArea += CalculateStackSlotSize(ObjectVT, 2245 Flags, 2246 PtrByteSize); 2247 } else 2248 nAltivecParamsAtEnd++; 2249 } else 2250 // Calculate min reserved area. 2251 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 2252 Flags, 2253 PtrByteSize); 2254 2255 // FIXME the codegen can be much improved in some cases. 2256 // We do not have to keep everything in memory. 2257 if (Flags.isByVal()) { 2258 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 2259 ObjSize = Flags.getByValSize(); 2260 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2261 // Empty aggregate parameters do not take up registers. Examples: 2262 // struct { } a; 2263 // union { } b; 2264 // int c[0]; 2265 // etc. However, we have to provide a place-holder in InVals, so 2266 // pretend we have an 8-byte item at the current address for that 2267 // purpose. 2268 if (!ObjSize) { 2269 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2270 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2271 InVals.push_back(FIN); 2272 continue; 2273 } 2274 // All aggregates smaller than 8 bytes must be passed right-justified. 2275 if (ObjSize < PtrByteSize) 2276 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize); 2277 // The value of the object is its address. 2278 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 2279 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2280 InVals.push_back(FIN); 2281 2282 if (ObjSize < 8) { 2283 if (GPR_idx != Num_GPR_Regs) { 2284 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2285 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2286 SDValue Store; 2287 2288 if (ObjSize==1 || ObjSize==2 || ObjSize==4) { 2289 EVT ObjType = (ObjSize == 1 ? MVT::i8 : 2290 (ObjSize == 2 ? MVT::i16 : MVT::i32)); 2291 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 2292 MachinePointerInfo(FuncArg, CurArgOffset), 2293 ObjType, false, false, 0); 2294 } else { 2295 // For sizes that don't fit a truncating store (3, 5, 6, 7), 2296 // store the whole register as-is to the parameter save area 2297 // slot. The address of the parameter was already calculated 2298 // above (InVals.push_back(FIN)) to be the right-justified 2299 // offset within the slot. For this store, we need a new 2300 // frame index that points at the beginning of the slot. 2301 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2302 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2303 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2304 MachinePointerInfo(FuncArg, ArgOffset), 2305 false, false, 0); 2306 } 2307 2308 MemOps.push_back(Store); 2309 ++GPR_idx; 2310 } 2311 // Whether we copied from a register or not, advance the offset 2312 // into the parameter save area by a full doubleword. 2313 ArgOffset += PtrByteSize; 2314 continue; 2315 } 2316 2317 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2318 // Store whatever pieces of the object are in registers 2319 // to memory. ArgOffset will be the address of the beginning 2320 // of the object. 2321 if (GPR_idx != Num_GPR_Regs) { 2322 unsigned VReg; 2323 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2324 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2325 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2326 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2327 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2328 MachinePointerInfo(FuncArg, ArgOffset), 2329 false, false, 0); 2330 MemOps.push_back(Store); 2331 ++GPR_idx; 2332 ArgOffset += PtrByteSize; 2333 } else { 2334 ArgOffset += ArgSize - j; 2335 break; 2336 } 2337 } 2338 continue; 2339 } 2340 2341 switch (ObjectVT.getSimpleVT().SimpleTy) { 2342 default: llvm_unreachable("Unhandled argument type!"); 2343 case MVT::i32: 2344 case MVT::i64: 2345 if (GPR_idx != Num_GPR_Regs) { 2346 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2347 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2348 2349 if (ObjectVT == MVT::i32) 2350 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2351 // value to MVT::i64 and then truncate to the correct register size. 2352 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl); 2353 2354 ++GPR_idx; 2355 } else { 2356 needsLoad = true; 2357 ArgSize = PtrByteSize; 2358 } 2359 ArgOffset += 8; 2360 break; 2361 2362 case MVT::f32: 2363 case MVT::f64: 2364 // Every 8 bytes of argument space consumes one of the GPRs available for 2365 // argument passing. 2366 if (GPR_idx != Num_GPR_Regs) { 2367 ++GPR_idx; 2368 } 2369 if (FPR_idx != Num_FPR_Regs) { 2370 unsigned VReg; 2371 2372 if (ObjectVT == MVT::f32) 2373 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2374 else 2375 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2376 2377 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2378 ++FPR_idx; 2379 } else { 2380 needsLoad = true; 2381 ArgSize = PtrByteSize; 2382 } 2383 2384 ArgOffset += 8; 2385 break; 2386 case MVT::v4f32: 2387 case MVT::v4i32: 2388 case MVT::v8i16: 2389 case MVT::v16i8: 2390 // Note that vector arguments in registers don't reserve stack space, 2391 // except in varargs functions. 2392 if (VR_idx != Num_VR_Regs) { 2393 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2394 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2395 if (isVarArg) { 2396 while ((ArgOffset % 16) != 0) { 2397 ArgOffset += PtrByteSize; 2398 if (GPR_idx != Num_GPR_Regs) 2399 GPR_idx++; 2400 } 2401 ArgOffset += 16; 2402 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2403 } 2404 ++VR_idx; 2405 } else { 2406 // Vectors are aligned. 2407 ArgOffset = ((ArgOffset+15)/16)*16; 2408 CurArgOffset = ArgOffset; 2409 ArgOffset += 16; 2410 needsLoad = true; 2411 } 2412 break; 2413 } 2414 2415 // We need to load the argument to a virtual register if we determined 2416 // above that we ran out of physical registers of the appropriate type. 2417 if (needsLoad) { 2418 int FI = MFI->CreateFixedObject(ObjSize, 2419 CurArgOffset + (ArgSize - ObjSize), 2420 isImmutable); 2421 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2422 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2423 false, false, false, 0); 2424 } 2425 2426 InVals.push_back(ArgVal); 2427 } 2428 2429 // Set the size that is at least reserved in caller of this function. Tail 2430 // call optimized functions' reserved stack space needs to be aligned so that 2431 // taking the difference between two stack areas will result in an aligned 2432 // stack. 2433 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true); 2434 2435 // If the function takes variable number of arguments, make a frame index for 2436 // the start of the first vararg value... for expansion of llvm.va_start. 2437 if (isVarArg) { 2438 int Depth = ArgOffset; 2439 2440 FuncInfo->setVarArgsFrameIndex( 2441 MFI->CreateFixedObject(PtrByteSize, Depth, true)); 2442 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2443 2444 // If this function is vararg, store any remaining integer argument regs 2445 // to their spots on the stack so that they may be loaded by deferencing the 2446 // result of va_next. 2447 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2448 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2449 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2450 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2451 MachinePointerInfo(), false, false, 0); 2452 MemOps.push_back(Store); 2453 // Increment the address by four for the next argument to store 2454 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT); 2455 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2456 } 2457 } 2458 2459 if (!MemOps.empty()) 2460 Chain = DAG.getNode(ISD::TokenFactor, dl, 2461 MVT::Other, &MemOps[0], MemOps.size()); 2462 2463 return Chain; 2464} 2465 2466SDValue 2467PPCTargetLowering::LowerFormalArguments_Darwin( 2468 SDValue Chain, 2469 CallingConv::ID CallConv, bool isVarArg, 2470 const SmallVectorImpl<ISD::InputArg> 2471 &Ins, 2472 DebugLoc dl, SelectionDAG &DAG, 2473 SmallVectorImpl<SDValue> &InVals) const { 2474 // TODO: add description of PPC stack frame format, or at least some docs. 2475 // 2476 MachineFunction &MF = DAG.getMachineFunction(); 2477 MachineFrameInfo *MFI = MF.getFrameInfo(); 2478 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 2479 2480 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2481 bool isPPC64 = PtrVT == MVT::i64; 2482 // Potential tail calls could cause overwriting of argument stack slots. 2483 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt && 2484 (CallConv == CallingConv::Fast)); 2485 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2486 2487 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 2488 // Area that is at least reserved in caller of this function. 2489 unsigned MinReservedArea = ArgOffset; 2490 2491 static const uint16_t GPR_32[] = { // 32-bit registers. 2492 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 2493 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 2494 }; 2495 static const uint16_t GPR_64[] = { // 64-bit registers. 2496 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 2497 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 2498 }; 2499 2500 static const uint16_t *FPR = GetFPR(); 2501 2502 static const uint16_t VR[] = { 2503 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 2504 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 2505 }; 2506 2507 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 2508 const unsigned Num_FPR_Regs = 13; 2509 const unsigned Num_VR_Regs = array_lengthof( VR); 2510 2511 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2512 2513 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 2514 2515 // In 32-bit non-varargs functions, the stack space for vectors is after the 2516 // stack space for non-vectors. We do not use this space unless we have 2517 // too many vectors to fit in registers, something that only occurs in 2518 // constructed examples:), but we have to walk the arglist to figure 2519 // that out...for the pathological case, compute VecArgOffset as the 2520 // start of the vector parameter area. Computing VecArgOffset is the 2521 // entire point of the following loop. 2522 unsigned VecArgOffset = ArgOffset; 2523 if (!isVarArg && !isPPC64) { 2524 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 2525 ++ArgNo) { 2526 EVT ObjectVT = Ins[ArgNo].VT; 2527 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2528 2529 if (Flags.isByVal()) { 2530 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 2531 unsigned ObjSize = Flags.getByValSize(); 2532 unsigned ArgSize = 2533 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2534 VecArgOffset += ArgSize; 2535 continue; 2536 } 2537 2538 switch(ObjectVT.getSimpleVT().SimpleTy) { 2539 default: llvm_unreachable("Unhandled argument type!"); 2540 case MVT::i32: 2541 case MVT::f32: 2542 VecArgOffset += 4; 2543 break; 2544 case MVT::i64: // PPC64 2545 case MVT::f64: 2546 // FIXME: We are guaranteed to be !isPPC64 at this point. 2547 // Does MVT::i64 apply? 2548 VecArgOffset += 8; 2549 break; 2550 case MVT::v4f32: 2551 case MVT::v4i32: 2552 case MVT::v8i16: 2553 case MVT::v16i8: 2554 // Nothing to do, we're only looking at Nonvector args here. 2555 break; 2556 } 2557 } 2558 } 2559 // We've found where the vector parameter area in memory is. Skip the 2560 // first 12 parameters; these don't use that memory. 2561 VecArgOffset = ((VecArgOffset+15)/16)*16; 2562 VecArgOffset += 12*16; 2563 2564 // Add DAG nodes to load the arguments or copy them out of registers. On 2565 // entry to a function on PPC, the arguments start after the linkage area, 2566 // although the first ones are often in registers. 2567 2568 SmallVector<SDValue, 8> MemOps; 2569 unsigned nAltivecParamsAtEnd = 0; 2570 // FIXME: FuncArg and Ins[ArgNo] must reference the same argument. 2571 // When passing anonymous aggregates, this is currently not true. 2572 // See LowerFormalArguments_64SVR4 for a fix. 2573 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); 2574 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) { 2575 SDValue ArgVal; 2576 bool needsLoad = false; 2577 EVT ObjectVT = Ins[ArgNo].VT; 2578 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 2579 unsigned ArgSize = ObjSize; 2580 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 2581 2582 unsigned CurArgOffset = ArgOffset; 2583 2584 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 2585 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 2586 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 2587 if (isVarArg || isPPC64) { 2588 MinReservedArea = ((MinReservedArea+15)/16)*16; 2589 MinReservedArea += CalculateStackSlotSize(ObjectVT, 2590 Flags, 2591 PtrByteSize); 2592 } else nAltivecParamsAtEnd++; 2593 } else 2594 // Calculate min reserved area. 2595 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 2596 Flags, 2597 PtrByteSize); 2598 2599 // FIXME the codegen can be much improved in some cases. 2600 // We do not have to keep everything in memory. 2601 if (Flags.isByVal()) { 2602 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 2603 ObjSize = Flags.getByValSize(); 2604 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 2605 // Objects of size 1 and 2 are right justified, everything else is 2606 // left justified. This means the memory address is adjusted forwards. 2607 if (ObjSize==1 || ObjSize==2) { 2608 CurArgOffset = CurArgOffset + (4 - ObjSize); 2609 } 2610 // The value of the object is its address. 2611 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 2612 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2613 InVals.push_back(FIN); 2614 if (ObjSize==1 || ObjSize==2) { 2615 if (GPR_idx != Num_GPR_Regs) { 2616 unsigned VReg; 2617 if (isPPC64) 2618 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2619 else 2620 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2621 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2622 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16; 2623 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 2624 MachinePointerInfo(FuncArg, 2625 CurArgOffset), 2626 ObjType, false, false, 0); 2627 MemOps.push_back(Store); 2628 ++GPR_idx; 2629 } 2630 2631 ArgOffset += PtrByteSize; 2632 2633 continue; 2634 } 2635 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 2636 // Store whatever pieces of the object are in registers 2637 // to memory. ArgOffset will be the address of the beginning 2638 // of the object. 2639 if (GPR_idx != Num_GPR_Regs) { 2640 unsigned VReg; 2641 if (isPPC64) 2642 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2643 else 2644 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2645 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2646 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2647 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2648 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2649 MachinePointerInfo(FuncArg, ArgOffset), 2650 false, false, 0); 2651 MemOps.push_back(Store); 2652 ++GPR_idx; 2653 ArgOffset += PtrByteSize; 2654 } else { 2655 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 2656 break; 2657 } 2658 } 2659 continue; 2660 } 2661 2662 switch (ObjectVT.getSimpleVT().SimpleTy) { 2663 default: llvm_unreachable("Unhandled argument type!"); 2664 case MVT::i32: 2665 if (!isPPC64) { 2666 if (GPR_idx != Num_GPR_Regs) { 2667 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2668 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2669 ++GPR_idx; 2670 } else { 2671 needsLoad = true; 2672 ArgSize = PtrByteSize; 2673 } 2674 // All int arguments reserve stack space in the Darwin ABI. 2675 ArgOffset += PtrByteSize; 2676 break; 2677 } 2678 // FALLTHROUGH 2679 case MVT::i64: // PPC64 2680 if (GPR_idx != Num_GPR_Regs) { 2681 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2682 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2683 2684 if (ObjectVT == MVT::i32) 2685 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2686 // value to MVT::i64 and then truncate to the correct register size. 2687 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl); 2688 2689 ++GPR_idx; 2690 } else { 2691 needsLoad = true; 2692 ArgSize = PtrByteSize; 2693 } 2694 // All int arguments reserve stack space in the Darwin ABI. 2695 ArgOffset += 8; 2696 break; 2697 2698 case MVT::f32: 2699 case MVT::f64: 2700 // Every 4 bytes of argument space consumes one of the GPRs available for 2701 // argument passing. 2702 if (GPR_idx != Num_GPR_Regs) { 2703 ++GPR_idx; 2704 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 2705 ++GPR_idx; 2706 } 2707 if (FPR_idx != Num_FPR_Regs) { 2708 unsigned VReg; 2709 2710 if (ObjectVT == MVT::f32) 2711 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2712 else 2713 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2714 2715 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2716 ++FPR_idx; 2717 } else { 2718 needsLoad = true; 2719 } 2720 2721 // All FP arguments reserve stack space in the Darwin ABI. 2722 ArgOffset += isPPC64 ? 8 : ObjSize; 2723 break; 2724 case MVT::v4f32: 2725 case MVT::v4i32: 2726 case MVT::v8i16: 2727 case MVT::v16i8: 2728 // Note that vector arguments in registers don't reserve stack space, 2729 // except in varargs functions. 2730 if (VR_idx != Num_VR_Regs) { 2731 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2732 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2733 if (isVarArg) { 2734 while ((ArgOffset % 16) != 0) { 2735 ArgOffset += PtrByteSize; 2736 if (GPR_idx != Num_GPR_Regs) 2737 GPR_idx++; 2738 } 2739 ArgOffset += 16; 2740 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2741 } 2742 ++VR_idx; 2743 } else { 2744 if (!isVarArg && !isPPC64) { 2745 // Vectors go after all the nonvectors. 2746 CurArgOffset = VecArgOffset; 2747 VecArgOffset += 16; 2748 } else { 2749 // Vectors are aligned. 2750 ArgOffset = ((ArgOffset+15)/16)*16; 2751 CurArgOffset = ArgOffset; 2752 ArgOffset += 16; 2753 } 2754 needsLoad = true; 2755 } 2756 break; 2757 } 2758 2759 // We need to load the argument to a virtual register if we determined above 2760 // that we ran out of physical registers of the appropriate type. 2761 if (needsLoad) { 2762 int FI = MFI->CreateFixedObject(ObjSize, 2763 CurArgOffset + (ArgSize - ObjSize), 2764 isImmutable); 2765 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2766 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2767 false, false, false, 0); 2768 } 2769 2770 InVals.push_back(ArgVal); 2771 } 2772 2773 // Set the size that is at least reserved in caller of this function. Tail 2774 // call optimized functions' reserved stack space needs to be aligned so that 2775 // taking the difference between two stack areas will result in an aligned 2776 // stack. 2777 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64); 2778 2779 // If the function takes variable number of arguments, make a frame index for 2780 // the start of the first vararg value... for expansion of llvm.va_start. 2781 if (isVarArg) { 2782 int Depth = ArgOffset; 2783 2784 FuncInfo->setVarArgsFrameIndex( 2785 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2786 Depth, true)); 2787 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2788 2789 // If this function is vararg, store any remaining integer argument regs 2790 // to their spots on the stack so that they may be loaded by deferencing the 2791 // result of va_next. 2792 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2793 unsigned VReg; 2794 2795 if (isPPC64) 2796 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2797 else 2798 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2799 2800 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2801 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2802 MachinePointerInfo(), false, false, 0); 2803 MemOps.push_back(Store); 2804 // Increment the address by four for the next argument to store 2805 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2806 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2807 } 2808 } 2809 2810 if (!MemOps.empty()) 2811 Chain = DAG.getNode(ISD::TokenFactor, dl, 2812 MVT::Other, &MemOps[0], MemOps.size()); 2813 2814 return Chain; 2815} 2816 2817/// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus 2818/// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI. 2819static unsigned 2820CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2821 bool isPPC64, 2822 bool isVarArg, 2823 unsigned CC, 2824 const SmallVectorImpl<ISD::OutputArg> 2825 &Outs, 2826 const SmallVectorImpl<SDValue> &OutVals, 2827 unsigned &nAltivecParamsAtEnd) { 2828 // Count how many bytes are to be pushed on the stack, including the linkage 2829 // area, and parameter passing area. We start with 24/48 bytes, which is 2830 // prereserved space for [SP][CR][LR][3 x unused]. 2831 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true); 2832 unsigned NumOps = Outs.size(); 2833 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2834 2835 // Add up all the space actually used. 2836 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2837 // they all go in registers, but we must reserve stack space for them for 2838 // possible use by the caller. In varargs or 64-bit calls, parameters are 2839 // assigned stack space in order, with padding so Altivec parameters are 2840 // 16-byte aligned. 2841 nAltivecParamsAtEnd = 0; 2842 for (unsigned i = 0; i != NumOps; ++i) { 2843 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2844 EVT ArgVT = Outs[i].VT; 2845 // Varargs Altivec parameters are padded to a 16 byte boundary. 2846 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2847 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2848 if (!isVarArg && !isPPC64) { 2849 // Non-varargs Altivec parameters go after all the non-Altivec 2850 // parameters; handle those later so we know how much padding we need. 2851 nAltivecParamsAtEnd++; 2852 continue; 2853 } 2854 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2855 NumBytes = ((NumBytes+15)/16)*16; 2856 } 2857 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2858 } 2859 2860 // Allow for Altivec parameters at the end, if needed. 2861 if (nAltivecParamsAtEnd) { 2862 NumBytes = ((NumBytes+15)/16)*16; 2863 NumBytes += 16*nAltivecParamsAtEnd; 2864 } 2865 2866 // The prolog code of the callee may store up to 8 GPR argument registers to 2867 // the stack, allowing va_start to index over them in memory if its varargs. 2868 // Because we cannot tell if this is needed on the caller side, we have to 2869 // conservatively assume that it is needed. As such, make sure we have at 2870 // least enough stack space for the caller to store the 8 GPRs. 2871 NumBytes = std::max(NumBytes, 2872 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2873 2874 // Tail call needs the stack to be aligned. 2875 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){ 2876 unsigned TargetAlign = DAG.getMachineFunction().getTarget(). 2877 getFrameLowering()->getStackAlignment(); 2878 unsigned AlignMask = TargetAlign-1; 2879 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2880 } 2881 2882 return NumBytes; 2883} 2884 2885/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2886/// adjusted to accommodate the arguments for the tailcall. 2887static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2888 unsigned ParamSize) { 2889 2890 if (!isTailCall) return 0; 2891 2892 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2893 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2894 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2895 // Remember only if the new adjustement is bigger. 2896 if (SPDiff < FI->getTailCallSPDelta()) 2897 FI->setTailCallSPDelta(SPDiff); 2898 2899 return SPDiff; 2900} 2901 2902/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2903/// for tail call optimization. Targets which want to do tail call 2904/// optimization should implement this function. 2905bool 2906PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2907 CallingConv::ID CalleeCC, 2908 bool isVarArg, 2909 const SmallVectorImpl<ISD::InputArg> &Ins, 2910 SelectionDAG& DAG) const { 2911 if (!getTargetMachine().Options.GuaranteedTailCallOpt) 2912 return false; 2913 2914 // Variable argument functions are not supported. 2915 if (isVarArg) 2916 return false; 2917 2918 MachineFunction &MF = DAG.getMachineFunction(); 2919 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2920 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2921 // Functions containing by val parameters are not supported. 2922 for (unsigned i = 0; i != Ins.size(); i++) { 2923 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2924 if (Flags.isByVal()) return false; 2925 } 2926 2927 // Non PIC/GOT tail calls are supported. 2928 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2929 return true; 2930 2931 // At the moment we can only do local tail calls (in same module, hidden 2932 // or protected) if we are generating PIC. 2933 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2934 return G->getGlobal()->hasHiddenVisibility() 2935 || G->getGlobal()->hasProtectedVisibility(); 2936 } 2937 2938 return false; 2939} 2940 2941/// isCallCompatibleAddress - Return the immediate to use if the specified 2942/// 32-bit value is representable in the immediate field of a BxA instruction. 2943static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2944 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2945 if (!C) return 0; 2946 2947 int Addr = C->getZExtValue(); 2948 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2949 SignExtend32<26>(Addr) != Addr) 2950 return 0; // Top 6 bits have to be sext of immediate. 2951 2952 return DAG.getConstant((int)C->getZExtValue() >> 2, 2953 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2954} 2955 2956namespace { 2957 2958struct TailCallArgumentInfo { 2959 SDValue Arg; 2960 SDValue FrameIdxOp; 2961 int FrameIdx; 2962 2963 TailCallArgumentInfo() : FrameIdx(0) {} 2964}; 2965 2966} 2967 2968/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2969static void 2970StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2971 SDValue Chain, 2972 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2973 SmallVector<SDValue, 8> &MemOpChains, 2974 DebugLoc dl) { 2975 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2976 SDValue Arg = TailCallArgs[i].Arg; 2977 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2978 int FI = TailCallArgs[i].FrameIdx; 2979 // Store relative to framepointer. 2980 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2981 MachinePointerInfo::getFixedStack(FI), 2982 false, false, 0)); 2983 } 2984} 2985 2986/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2987/// the appropriate stack slot for the tail call optimized function call. 2988static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2989 MachineFunction &MF, 2990 SDValue Chain, 2991 SDValue OldRetAddr, 2992 SDValue OldFP, 2993 int SPDiff, 2994 bool isPPC64, 2995 bool isDarwinABI, 2996 DebugLoc dl) { 2997 if (SPDiff) { 2998 // Calculate the new stack slot for the return address. 2999 int SlotSize = isPPC64 ? 8 : 4; 3000 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64, 3001 isDarwinABI); 3002 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 3003 NewRetAddrLoc, true); 3004 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 3005 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 3006 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 3007 MachinePointerInfo::getFixedStack(NewRetAddr), 3008 false, false, 0); 3009 3010 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 3011 // slot as the FP is never overwritten. 3012 if (isDarwinABI) { 3013 int NewFPLoc = 3014 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 3015 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 3016 true); 3017 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 3018 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 3019 MachinePointerInfo::getFixedStack(NewFPIdx), 3020 false, false, 0); 3021 } 3022 } 3023 return Chain; 3024} 3025 3026/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 3027/// the position of the argument. 3028static void 3029CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 3030 SDValue Arg, int SPDiff, unsigned ArgOffset, 3031 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 3032 int Offset = ArgOffset + SPDiff; 3033 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 3034 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 3035 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 3036 SDValue FIN = DAG.getFrameIndex(FI, VT); 3037 TailCallArgumentInfo Info; 3038 Info.Arg = Arg; 3039 Info.FrameIdxOp = FIN; 3040 Info.FrameIdx = FI; 3041 TailCallArguments.push_back(Info); 3042} 3043 3044/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 3045/// stack slot. Returns the chain as result and the loaded frame pointers in 3046/// LROpOut/FPOpout. Used when tail calling. 3047SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 3048 int SPDiff, 3049 SDValue Chain, 3050 SDValue &LROpOut, 3051 SDValue &FPOpOut, 3052 bool isDarwinABI, 3053 DebugLoc dl) const { 3054 if (SPDiff) { 3055 // Load the LR and FP stack slot for later adjusting. 3056 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 3057 LROpOut = getReturnAddrFrameIndex(DAG); 3058 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), 3059 false, false, false, 0); 3060 Chain = SDValue(LROpOut.getNode(), 1); 3061 3062 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 3063 // slot as the FP is never overwritten. 3064 if (isDarwinABI) { 3065 FPOpOut = getFramePointerFrameIndex(DAG); 3066 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), 3067 false, false, false, 0); 3068 Chain = SDValue(FPOpOut.getNode(), 1); 3069 } 3070 } 3071 return Chain; 3072} 3073 3074/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 3075/// by "Src" to address "Dst" of size "Size". Alignment information is 3076/// specified by the specific parameter attribute. The copy will be passed as 3077/// a byval function parameter. 3078/// Sometimes what we are copying is the end of a larger object, the part that 3079/// does not fit in registers. 3080static SDValue 3081CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 3082 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 3083 DebugLoc dl) { 3084 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 3085 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 3086 false, false, MachinePointerInfo(0), 3087 MachinePointerInfo(0)); 3088} 3089 3090/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 3091/// tail calls. 3092static void 3093LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 3094 SDValue Arg, SDValue PtrOff, int SPDiff, 3095 unsigned ArgOffset, bool isPPC64, bool isTailCall, 3096 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 3097 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, 3098 DebugLoc dl) { 3099 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3100 if (!isTailCall) { 3101 if (isVector) { 3102 SDValue StackPtr; 3103 if (isPPC64) 3104 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3105 else 3106 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3107 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3108 DAG.getConstant(ArgOffset, PtrVT)); 3109 } 3110 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3111 MachinePointerInfo(), false, false, 0)); 3112 // Calculate and remember argument location. 3113 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 3114 TailCallArguments); 3115} 3116 3117static 3118void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 3119 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 3120 SDValue LROp, SDValue FPOp, bool isDarwinABI, 3121 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 3122 MachineFunction &MF = DAG.getMachineFunction(); 3123 3124 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 3125 // might overwrite each other in case of tail call optimization. 3126 SmallVector<SDValue, 8> MemOpChains2; 3127 // Do not flag preceding copytoreg stuff together with the following stuff. 3128 InFlag = SDValue(); 3129 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 3130 MemOpChains2, dl); 3131 if (!MemOpChains2.empty()) 3132 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3133 &MemOpChains2[0], MemOpChains2.size()); 3134 3135 // Store the return address to the appropriate stack slot. 3136 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 3137 isPPC64, isDarwinABI, dl); 3138 3139 // Emit callseq_end just before tailcall node. 3140 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 3141 DAG.getIntPtrConstant(0, true), InFlag); 3142 InFlag = Chain.getValue(1); 3143} 3144 3145static 3146unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 3147 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 3148 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 3149 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 3150 const PPCSubtarget &PPCSubTarget) { 3151 3152 bool isPPC64 = PPCSubTarget.isPPC64(); 3153 bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); 3154 3155 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3156 NodeTys.push_back(MVT::Other); // Returns a chain 3157 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. 3158 3159 unsigned CallOpc = PPCISD::CALL; 3160 3161 bool needIndirectCall = true; 3162 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 3163 // If this is an absolute destination address, use the munged value. 3164 Callee = SDValue(Dest, 0); 3165 needIndirectCall = false; 3166 } 3167 3168 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3169 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 3170 // Use indirect calls for ALL functions calls in JIT mode, since the 3171 // far-call stubs may be outside relocation limits for a BL instruction. 3172 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) { 3173 unsigned OpFlags = 0; 3174 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 3175 (PPCSubTarget.getTargetTriple().isMacOSX() && 3176 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) && 3177 (G->getGlobal()->isDeclaration() || 3178 G->getGlobal()->isWeakForLinker())) { 3179 // PC-relative references to external symbols should go through $stub, 3180 // unless we're building with the leopard linker or later, which 3181 // automatically synthesizes these stubs. 3182 OpFlags = PPCII::MO_DARWIN_STUB; 3183 } 3184 3185 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, 3186 // every direct call is) turn it into a TargetGlobalAddress / 3187 // TargetExternalSymbol node so that legalize doesn't hack it. 3188 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 3189 Callee.getValueType(), 3190 0, OpFlags); 3191 needIndirectCall = false; 3192 } 3193 } 3194 3195 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 3196 unsigned char OpFlags = 0; 3197 3198 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 3199 (PPCSubTarget.getTargetTriple().isMacOSX() && 3200 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) { 3201 // PC-relative references to external symbols should go through $stub, 3202 // unless we're building with the leopard linker or later, which 3203 // automatically synthesizes these stubs. 3204 OpFlags = PPCII::MO_DARWIN_STUB; 3205 } 3206 3207 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(), 3208 OpFlags); 3209 needIndirectCall = false; 3210 } 3211 3212 if (needIndirectCall) { 3213 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 3214 // to do the call, we can't use PPCISD::CALL. 3215 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 3216 3217 if (isSVR4ABI && isPPC64) { 3218 // Function pointers in the 64-bit SVR4 ABI do not point to the function 3219 // entry point, but to the function descriptor (the function entry point 3220 // address is part of the function descriptor though). 3221 // The function descriptor is a three doubleword structure with the 3222 // following fields: function entry point, TOC base address and 3223 // environment pointer. 3224 // Thus for a call through a function pointer, the following actions need 3225 // to be performed: 3226 // 1. Save the TOC of the caller in the TOC save area of its stack 3227 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()). 3228 // 2. Load the address of the function entry point from the function 3229 // descriptor. 3230 // 3. Load the TOC of the callee from the function descriptor into r2. 3231 // 4. Load the environment pointer from the function descriptor into 3232 // r11. 3233 // 5. Branch to the function entry point address. 3234 // 6. On return of the callee, the TOC of the caller needs to be 3235 // restored (this is done in FinishCall()). 3236 // 3237 // All those operations are flagged together to ensure that no other 3238 // operations can be scheduled in between. E.g. without flagging the 3239 // operations together, a TOC access in the caller could be scheduled 3240 // between the load of the callee TOC and the branch to the callee, which 3241 // results in the TOC access going through the TOC of the callee instead 3242 // of going through the TOC of the caller, which leads to incorrect code. 3243 3244 // Load the address of the function entry point from the function 3245 // descriptor. 3246 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue); 3247 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 3248 InFlag.getNode() ? 3 : 2); 3249 Chain = LoadFuncPtr.getValue(1); 3250 InFlag = LoadFuncPtr.getValue(2); 3251 3252 // Load environment pointer into r11. 3253 // Offset of the environment pointer within the function descriptor. 3254 SDValue PtrOff = DAG.getIntPtrConstant(16); 3255 3256 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 3257 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 3258 InFlag); 3259 Chain = LoadEnvPtr.getValue(1); 3260 InFlag = LoadEnvPtr.getValue(2); 3261 3262 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 3263 InFlag); 3264 Chain = EnvVal.getValue(0); 3265 InFlag = EnvVal.getValue(1); 3266 3267 // Load TOC of the callee into r2. We are using a target-specific load 3268 // with r2 hard coded, because the result of a target-independent load 3269 // would never go directly into r2, since r2 is a reserved register (which 3270 // prevents the register allocator from allocating it), resulting in an 3271 // additional register being allocated and an unnecessary move instruction 3272 // being generated. 3273 VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3274 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 3275 Callee, InFlag); 3276 Chain = LoadTOCPtr.getValue(0); 3277 InFlag = LoadTOCPtr.getValue(1); 3278 3279 MTCTROps[0] = Chain; 3280 MTCTROps[1] = LoadFuncPtr; 3281 MTCTROps[2] = InFlag; 3282 } 3283 3284 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 3285 2 + (InFlag.getNode() != 0)); 3286 InFlag = Chain.getValue(1); 3287 3288 NodeTys.clear(); 3289 NodeTys.push_back(MVT::Other); 3290 NodeTys.push_back(MVT::Glue); 3291 Ops.push_back(Chain); 3292 CallOpc = PPCISD::BCTRL; 3293 Callee.setNode(0); 3294 // Add use of X11 (holding environment pointer) 3295 if (isSVR4ABI && isPPC64) 3296 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT)); 3297 // Add CTR register as callee so a bctr can be emitted later. 3298 if (isTailCall) 3299 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); 3300 } 3301 3302 // If this is a direct call, pass the chain and the callee. 3303 if (Callee.getNode()) { 3304 Ops.push_back(Chain); 3305 Ops.push_back(Callee); 3306 } 3307 // If this is a tail call add stack pointer delta. 3308 if (isTailCall) 3309 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 3310 3311 // Add argument registers to the end of the list so that they are known live 3312 // into the call. 3313 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 3314 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 3315 RegsToPass[i].second.getValueType())); 3316 3317 return CallOpc; 3318} 3319 3320static 3321bool isLocalCall(const SDValue &Callee) 3322{ 3323 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 3324 return !G->getGlobal()->isDeclaration() && 3325 !G->getGlobal()->isWeakForLinker(); 3326 return false; 3327} 3328 3329SDValue 3330PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 3331 CallingConv::ID CallConv, bool isVarArg, 3332 const SmallVectorImpl<ISD::InputArg> &Ins, 3333 DebugLoc dl, SelectionDAG &DAG, 3334 SmallVectorImpl<SDValue> &InVals) const { 3335 3336 SmallVector<CCValAssign, 16> RVLocs; 3337 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3338 getTargetMachine(), RVLocs, *DAG.getContext()); 3339 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 3340 3341 // Copy all of the result registers out of their specified physreg. 3342 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 3343 CCValAssign &VA = RVLocs[i]; 3344 assert(VA.isRegLoc() && "Can only return in registers!"); 3345 3346 SDValue Val = DAG.getCopyFromReg(Chain, dl, 3347 VA.getLocReg(), VA.getLocVT(), InFlag); 3348 Chain = Val.getValue(1); 3349 InFlag = Val.getValue(2); 3350 3351 switch (VA.getLocInfo()) { 3352 default: llvm_unreachable("Unknown loc info!"); 3353 case CCValAssign::Full: break; 3354 case CCValAssign::AExt: 3355 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3356 break; 3357 case CCValAssign::ZExt: 3358 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val, 3359 DAG.getValueType(VA.getValVT())); 3360 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3361 break; 3362 case CCValAssign::SExt: 3363 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val, 3364 DAG.getValueType(VA.getValVT())); 3365 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); 3366 break; 3367 } 3368 3369 InVals.push_back(Val); 3370 } 3371 3372 return Chain; 3373} 3374 3375SDValue 3376PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 3377 bool isTailCall, bool isVarArg, 3378 SelectionDAG &DAG, 3379 SmallVector<std::pair<unsigned, SDValue>, 8> 3380 &RegsToPass, 3381 SDValue InFlag, SDValue Chain, 3382 SDValue &Callee, 3383 int SPDiff, unsigned NumBytes, 3384 const SmallVectorImpl<ISD::InputArg> &Ins, 3385 SmallVectorImpl<SDValue> &InVals) const { 3386 std::vector<EVT> NodeTys; 3387 SmallVector<SDValue, 8> Ops; 3388 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 3389 isTailCall, RegsToPass, Ops, NodeTys, 3390 PPCSubTarget); 3391 3392 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls 3393 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) 3394 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); 3395 3396 // When performing tail call optimization the callee pops its arguments off 3397 // the stack. Account for this here so these bytes can be pushed back on in 3398 // PPCFrameLowering::eliminateCallFramePseudoInstr. 3399 int BytesCalleePops = 3400 (CallConv == CallingConv::Fast && 3401 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0; 3402 3403 // Add a register mask operand representing the call-preserved registers. 3404 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 3405 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv); 3406 assert(Mask && "Missing call preserved mask for calling convention"); 3407 Ops.push_back(DAG.getRegisterMask(Mask)); 3408 3409 if (InFlag.getNode()) 3410 Ops.push_back(InFlag); 3411 3412 // Emit tail call. 3413 if (isTailCall) { 3414 assert(((Callee.getOpcode() == ISD::Register && 3415 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 3416 Callee.getOpcode() == ISD::TargetExternalSymbol || 3417 Callee.getOpcode() == ISD::TargetGlobalAddress || 3418 isa<ConstantSDNode>(Callee)) && 3419 "Expecting an global address, external symbol, absolute value or register"); 3420 3421 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 3422 } 3423 3424 // Add a NOP immediately after the branch instruction when using the 64-bit 3425 // SVR4 ABI. At link time, if caller and callee are in a different module and 3426 // thus have a different TOC, the call will be replaced with a call to a stub 3427 // function which saves the current TOC, loads the TOC of the callee and 3428 // branches to the callee. The NOP will be replaced with a load instruction 3429 // which restores the TOC of the caller from the TOC save slot of the current 3430 // stack frame. If caller and callee belong to the same module (and have the 3431 // same TOC), the NOP will remain unchanged. 3432 3433 bool needsTOCRestore = false; 3434 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 3435 if (CallOpc == PPCISD::BCTRL) { 3436 // This is a call through a function pointer. 3437 // Restore the caller TOC from the save area into R2. 3438 // See PrepareCall() for more information about calls through function 3439 // pointers in the 64-bit SVR4 ABI. 3440 // We are using a target-specific load with r2 hard coded, because the 3441 // result of a target-independent load would never go directly into r2, 3442 // since r2 is a reserved register (which prevents the register allocator 3443 // from allocating it), resulting in an additional register being 3444 // allocated and an unnecessary move instruction being generated. 3445 needsTOCRestore = true; 3446 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) { 3447 // Otherwise insert NOP for non-local calls. 3448 CallOpc = PPCISD::CALL_NOP; 3449 } 3450 } 3451 3452 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 3453 InFlag = Chain.getValue(1); 3454 3455 if (needsTOCRestore) { 3456 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3457 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 3458 InFlag = Chain.getValue(1); 3459 } 3460 3461 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 3462 DAG.getIntPtrConstant(BytesCalleePops, true), 3463 InFlag); 3464 if (!Ins.empty()) 3465 InFlag = Chain.getValue(1); 3466 3467 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 3468 Ins, dl, DAG, InVals); 3469} 3470 3471SDValue 3472PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 3473 SmallVectorImpl<SDValue> &InVals) const { 3474 SelectionDAG &DAG = CLI.DAG; 3475 DebugLoc &dl = CLI.DL; 3476 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 3477 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 3478 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 3479 SDValue Chain = CLI.Chain; 3480 SDValue Callee = CLI.Callee; 3481 bool &isTailCall = CLI.IsTailCall; 3482 CallingConv::ID CallConv = CLI.CallConv; 3483 bool isVarArg = CLI.IsVarArg; 3484 3485 if (isTailCall) 3486 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 3487 Ins, DAG); 3488 3489 if (PPCSubTarget.isSVR4ABI()) { 3490 if (PPCSubTarget.isPPC64()) 3491 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg, 3492 isTailCall, Outs, OutVals, Ins, 3493 dl, DAG, InVals); 3494 else 3495 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg, 3496 isTailCall, Outs, OutVals, Ins, 3497 dl, DAG, InVals); 3498 } 3499 3500 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 3501 isTailCall, Outs, OutVals, Ins, 3502 dl, DAG, InVals); 3503} 3504 3505SDValue 3506PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee, 3507 CallingConv::ID CallConv, bool isVarArg, 3508 bool isTailCall, 3509 const SmallVectorImpl<ISD::OutputArg> &Outs, 3510 const SmallVectorImpl<SDValue> &OutVals, 3511 const SmallVectorImpl<ISD::InputArg> &Ins, 3512 DebugLoc dl, SelectionDAG &DAG, 3513 SmallVectorImpl<SDValue> &InVals) const { 3514 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description 3515 // of the 32-bit SVR4 ABI stack frame layout. 3516 3517 assert((CallConv == CallingConv::C || 3518 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 3519 3520 unsigned PtrByteSize = 4; 3521 3522 MachineFunction &MF = DAG.getMachineFunction(); 3523 3524 // Mark this function as potentially containing a function that contains a 3525 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3526 // and restoring the callers stack pointer in this functions epilog. This is 3527 // done because by tail calling the called function might overwrite the value 3528 // in this function's (MF) stack pointer stack slot 0(SP). 3529 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3530 CallConv == CallingConv::Fast) 3531 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3532 3533 // Count how many bytes are to be pushed on the stack, including the linkage 3534 // area, parameter list area and the part of the local variable space which 3535 // contains copies of aggregates which are passed by value. 3536 3537 // Assign locations to all of the outgoing arguments. 3538 SmallVector<CCValAssign, 16> ArgLocs; 3539 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3540 getTargetMachine(), ArgLocs, *DAG.getContext()); 3541 3542 // Reserve space for the linkage area on the stack. 3543 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 3544 3545 if (isVarArg) { 3546 // Handle fixed and variable vector arguments differently. 3547 // Fixed vector arguments go into registers as long as registers are 3548 // available. Variable vector arguments always go into memory. 3549 unsigned NumArgs = Outs.size(); 3550 3551 for (unsigned i = 0; i != NumArgs; ++i) { 3552 MVT ArgVT = Outs[i].VT; 3553 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 3554 bool Result; 3555 3556 if (Outs[i].IsFixed) { 3557 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 3558 CCInfo); 3559 } else { 3560 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 3561 ArgFlags, CCInfo); 3562 } 3563 3564 if (Result) { 3565#ifndef NDEBUG 3566 errs() << "Call operand #" << i << " has unhandled type " 3567 << EVT(ArgVT).getEVTString() << "\n"; 3568#endif 3569 llvm_unreachable(0); 3570 } 3571 } 3572 } else { 3573 // All arguments are treated the same. 3574 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4); 3575 } 3576 3577 // Assign locations to all of the outgoing aggregate by value arguments. 3578 SmallVector<CCValAssign, 16> ByValArgLocs; 3579 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3580 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 3581 3582 // Reserve stack space for the allocations in CCInfo. 3583 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 3584 3585 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal); 3586 3587 // Size of the linkage area, parameter list area and the part of the local 3588 // space variable where copies of aggregates which are passed by value are 3589 // stored. 3590 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 3591 3592 // Calculate by how many bytes the stack has to be adjusted in case of tail 3593 // call optimization. 3594 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3595 3596 // Adjust the stack pointer for the new arguments... 3597 // These operations are automatically eliminated by the prolog/epilog pass 3598 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3599 SDValue CallSeqStart = Chain; 3600 3601 // Load the return address and frame pointer so it can be moved somewhere else 3602 // later. 3603 SDValue LROp, FPOp; 3604 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 3605 dl); 3606 3607 // Set up a copy of the stack pointer for use loading and storing any 3608 // arguments that may not fit in the registers available for argument 3609 // passing. 3610 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3611 3612 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3613 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3614 SmallVector<SDValue, 8> MemOpChains; 3615 3616 bool seenFloatArg = false; 3617 // Walk the register/memloc assignments, inserting copies/loads. 3618 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 3619 i != e; 3620 ++i) { 3621 CCValAssign &VA = ArgLocs[i]; 3622 SDValue Arg = OutVals[i]; 3623 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3624 3625 if (Flags.isByVal()) { 3626 // Argument is an aggregate which is passed by value, thus we need to 3627 // create a copy of it in the local variable space of the current stack 3628 // frame (which is the stack frame of the caller) and pass the address of 3629 // this copy to the callee. 3630 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 3631 CCValAssign &ByValVA = ByValArgLocs[j++]; 3632 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 3633 3634 // Memory reserved in the local variable space of the callers stack frame. 3635 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 3636 3637 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3638 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3639 3640 // Create a copy of the argument in the local area of the current 3641 // stack frame. 3642 SDValue MemcpyCall = 3643 CreateCopyOfByValArgument(Arg, PtrOff, 3644 CallSeqStart.getNode()->getOperand(0), 3645 Flags, DAG, dl); 3646 3647 // This must go outside the CALLSEQ_START..END. 3648 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3649 CallSeqStart.getNode()->getOperand(1)); 3650 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3651 NewCallSeqStart.getNode()); 3652 Chain = CallSeqStart = NewCallSeqStart; 3653 3654 // Pass the address of the aggregate copy on the stack either in a 3655 // physical register or in the parameter list area of the current stack 3656 // frame to the callee. 3657 Arg = PtrOff; 3658 } 3659 3660 if (VA.isRegLoc()) { 3661 seenFloatArg |= VA.getLocVT().isFloatingPoint(); 3662 // Put argument in a physical register. 3663 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 3664 } else { 3665 // Put argument in the parameter list area of the current stack frame. 3666 assert(VA.isMemLoc()); 3667 unsigned LocMemOffset = VA.getLocMemOffset(); 3668 3669 if (!isTailCall) { 3670 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3671 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3672 3673 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3674 MachinePointerInfo(), 3675 false, false, 0)); 3676 } else { 3677 // Calculate and remember argument location. 3678 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 3679 TailCallArguments); 3680 } 3681 } 3682 } 3683 3684 if (!MemOpChains.empty()) 3685 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3686 &MemOpChains[0], MemOpChains.size()); 3687 3688 // Build a sequence of copy-to-reg nodes chained together with token chain 3689 // and flag operands which copy the outgoing args into the appropriate regs. 3690 SDValue InFlag; 3691 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3692 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3693 RegsToPass[i].second, InFlag); 3694 InFlag = Chain.getValue(1); 3695 } 3696 3697 // Set CR bit 6 to true if this is a vararg call with floating args passed in 3698 // registers. 3699 if (isVarArg) { 3700 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 3701 SDValue Ops[] = { Chain, InFlag }; 3702 3703 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET, 3704 dl, VTs, Ops, InFlag.getNode() ? 2 : 1); 3705 3706 InFlag = Chain.getValue(1); 3707 } 3708 3709 if (isTailCall) 3710 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 3711 false, TailCallArguments); 3712 3713 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3714 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3715 Ins, InVals); 3716} 3717 3718// Copy an argument into memory, being careful to do this outside the 3719// call sequence for the call to which the argument belongs. 3720SDValue 3721PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 3722 SDValue CallSeqStart, 3723 ISD::ArgFlagsTy Flags, 3724 SelectionDAG &DAG, 3725 DebugLoc dl) const { 3726 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3727 CallSeqStart.getNode()->getOperand(0), 3728 Flags, DAG, dl); 3729 // The MEMCPY must go outside the CALLSEQ_START..END. 3730 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3731 CallSeqStart.getNode()->getOperand(1)); 3732 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3733 NewCallSeqStart.getNode()); 3734 return NewCallSeqStart; 3735} 3736 3737SDValue 3738PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee, 3739 CallingConv::ID CallConv, bool isVarArg, 3740 bool isTailCall, 3741 const SmallVectorImpl<ISD::OutputArg> &Outs, 3742 const SmallVectorImpl<SDValue> &OutVals, 3743 const SmallVectorImpl<ISD::InputArg> &Ins, 3744 DebugLoc dl, SelectionDAG &DAG, 3745 SmallVectorImpl<SDValue> &InVals) const { 3746 3747 unsigned NumOps = Outs.size(); 3748 3749 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3750 unsigned PtrByteSize = 8; 3751 3752 MachineFunction &MF = DAG.getMachineFunction(); 3753 3754 // Mark this function as potentially containing a function that contains a 3755 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3756 // and restoring the callers stack pointer in this functions epilog. This is 3757 // done because by tail calling the called function might overwrite the value 3758 // in this function's (MF) stack pointer stack slot 0(SP). 3759 if (getTargetMachine().Options.GuaranteedTailCallOpt && 3760 CallConv == CallingConv::Fast) 3761 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3762 3763 unsigned nAltivecParamsAtEnd = 0; 3764 3765 // Count how many bytes are to be pushed on the stack, including the linkage 3766 // area, and parameter passing area. We start with at least 48 bytes, which 3767 // is reserved space for [SP][CR][LR][3 x unused]. 3768 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result 3769 // of this call. 3770 unsigned NumBytes = 3771 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv, 3772 Outs, OutVals, nAltivecParamsAtEnd); 3773 3774 // Calculate by how many bytes the stack has to be adjusted in case of tail 3775 // call optimization. 3776 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3777 3778 // To protect arguments on the stack from being clobbered in a tail call, 3779 // force all the loads to happen before doing any other lowering. 3780 if (isTailCall) 3781 Chain = DAG.getStackArgumentTokenFactor(Chain); 3782 3783 // Adjust the stack pointer for the new arguments... 3784 // These operations are automatically eliminated by the prolog/epilog pass 3785 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3786 SDValue CallSeqStart = Chain; 3787 3788 // Load the return address and frame pointer so it can be move somewhere else 3789 // later. 3790 SDValue LROp, FPOp; 3791 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 3792 dl); 3793 3794 // Set up a copy of the stack pointer for use loading and storing any 3795 // arguments that may not fit in the registers available for argument 3796 // passing. 3797 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3798 3799 // Figure out which arguments are going to go in registers, and which in 3800 // memory. Also, if this is a vararg function, floating point operations 3801 // must be stored to our stack, and loaded into integer regs as well, if 3802 // any integer regs are available for argument passing. 3803 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true); 3804 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 3805 3806 static const uint16_t GPR[] = { 3807 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3808 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3809 }; 3810 static const uint16_t *FPR = GetFPR(); 3811 3812 static const uint16_t VR[] = { 3813 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3814 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3815 }; 3816 const unsigned NumGPRs = array_lengthof(GPR); 3817 const unsigned NumFPRs = 13; 3818 const unsigned NumVRs = array_lengthof(VR); 3819 3820 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3821 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3822 3823 SmallVector<SDValue, 8> MemOpChains; 3824 for (unsigned i = 0; i != NumOps; ++i) { 3825 SDValue Arg = OutVals[i]; 3826 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3827 3828 // PtrOff will be used to store the current argument to the stack if a 3829 // register cannot be found for it. 3830 SDValue PtrOff; 3831 3832 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3833 3834 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3835 3836 // Promote integers to 64-bit values. 3837 if (Arg.getValueType() == MVT::i32) { 3838 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3839 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3840 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3841 } 3842 3843 // FIXME memcpy is used way more than necessary. Correctness first. 3844 // Note: "by value" is code for passing a structure by value, not 3845 // basic types. 3846 if (Flags.isByVal()) { 3847 // Note: Size includes alignment padding, so 3848 // struct x { short a; char b; } 3849 // will have Size = 4. With #pragma pack(1), it will have Size = 3. 3850 // These are the proper values we need for right-justifying the 3851 // aggregate in a parameter register. 3852 unsigned Size = Flags.getByValSize(); 3853 3854 // An empty aggregate parameter takes up no storage and no 3855 // registers. 3856 if (Size == 0) 3857 continue; 3858 3859 // All aggregates smaller than 8 bytes must be passed right-justified. 3860 if (Size==1 || Size==2 || Size==4) { 3861 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); 3862 if (GPR_idx != NumGPRs) { 3863 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3864 MachinePointerInfo(), VT, 3865 false, false, 0); 3866 MemOpChains.push_back(Load.getValue(1)); 3867 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3868 3869 ArgOffset += PtrByteSize; 3870 continue; 3871 } 3872 } 3873 3874 if (GPR_idx == NumGPRs && Size < 8) { 3875 SDValue Const = DAG.getConstant(PtrByteSize - Size, 3876 PtrOff.getValueType()); 3877 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3878 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 3879 CallSeqStart, 3880 Flags, DAG, dl); 3881 ArgOffset += PtrByteSize; 3882 continue; 3883 } 3884 // Copy entire object into memory. There are cases where gcc-generated 3885 // code assumes it is there, even if it could be put entirely into 3886 // registers. (This is not what the doc says.) 3887 3888 // FIXME: The above statement is likely due to a misunderstanding of the 3889 // documents. All arguments must be copied into the parameter area BY 3890 // THE CALLEE in the event that the callee takes the address of any 3891 // formal argument. That has not yet been implemented. However, it is 3892 // reasonable to use the stack area as a staging area for the register 3893 // load. 3894 3895 // Skip this for small aggregates, as we will use the same slot for a 3896 // right-justified copy, below. 3897 if (Size >= 8) 3898 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, 3899 CallSeqStart, 3900 Flags, DAG, dl); 3901 3902 // When a register is available, pass a small aggregate right-justified. 3903 if (Size < 8 && GPR_idx != NumGPRs) { 3904 // The easiest way to get this right-justified in a register 3905 // is to copy the structure into the rightmost portion of a 3906 // local variable slot, then load the whole slot into the 3907 // register. 3908 // FIXME: The memcpy seems to produce pretty awful code for 3909 // small aggregates, particularly for packed ones. 3910 // FIXME: It would be preferable to use the slot in the 3911 // parameter save area instead of a new local variable. 3912 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType()); 3913 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3914 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 3915 CallSeqStart, 3916 Flags, DAG, dl); 3917 3918 // Load the slot into the register. 3919 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff, 3920 MachinePointerInfo(), 3921 false, false, false, 0); 3922 MemOpChains.push_back(Load.getValue(1)); 3923 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3924 3925 // Done with this argument. 3926 ArgOffset += PtrByteSize; 3927 continue; 3928 } 3929 3930 // For aggregates larger than PtrByteSize, copy the pieces of the 3931 // object that fit into registers from the parameter save area. 3932 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3933 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3934 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3935 if (GPR_idx != NumGPRs) { 3936 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 3937 MachinePointerInfo(), 3938 false, false, false, 0); 3939 MemOpChains.push_back(Load.getValue(1)); 3940 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3941 ArgOffset += PtrByteSize; 3942 } else { 3943 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3944 break; 3945 } 3946 } 3947 continue; 3948 } 3949 3950 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3951 default: llvm_unreachable("Unexpected ValueType for argument!"); 3952 case MVT::i32: 3953 case MVT::i64: 3954 if (GPR_idx != NumGPRs) { 3955 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3956 } else { 3957 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3958 true, isTailCall, false, MemOpChains, 3959 TailCallArguments, dl); 3960 } 3961 ArgOffset += PtrByteSize; 3962 break; 3963 case MVT::f32: 3964 case MVT::f64: 3965 if (FPR_idx != NumFPRs) { 3966 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3967 3968 if (isVarArg) { 3969 // A single float or an aggregate containing only a single float 3970 // must be passed right-justified in the stack doubleword, and 3971 // in the GPR, if one is available. 3972 SDValue StoreOff; 3973 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) { 3974 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3975 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3976 } else 3977 StoreOff = PtrOff; 3978 3979 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff, 3980 MachinePointerInfo(), false, false, 0); 3981 MemOpChains.push_back(Store); 3982 3983 // Float varargs are always shadowed in available integer registers 3984 if (GPR_idx != NumGPRs) { 3985 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3986 MachinePointerInfo(), false, false, 3987 false, 0); 3988 MemOpChains.push_back(Load.getValue(1)); 3989 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3990 } 3991 } else if (GPR_idx != NumGPRs) 3992 // If we have any FPRs remaining, we may also have GPRs remaining. 3993 ++GPR_idx; 3994 } else { 3995 // Single-precision floating-point values are mapped to the 3996 // second (rightmost) word of the stack doubleword. 3997 if (Arg.getValueType() == MVT::f32) { 3998 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3999 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 4000 } 4001 4002 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4003 true, isTailCall, false, MemOpChains, 4004 TailCallArguments, dl); 4005 } 4006 ArgOffset += 8; 4007 break; 4008 case MVT::v4f32: 4009 case MVT::v4i32: 4010 case MVT::v8i16: 4011 case MVT::v16i8: 4012 if (isVarArg) { 4013 // These go aligned on the stack, or in the corresponding R registers 4014 // when within range. The Darwin PPC ABI doc claims they also go in 4015 // V registers; in fact gcc does this only for arguments that are 4016 // prototyped, not for those that match the ... We do it for all 4017 // arguments, seems to work. 4018 while (ArgOffset % 16 !=0) { 4019 ArgOffset += PtrByteSize; 4020 if (GPR_idx != NumGPRs) 4021 GPR_idx++; 4022 } 4023 // We could elide this store in the case where the object fits 4024 // entirely in R registers. Maybe later. 4025 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 4026 DAG.getConstant(ArgOffset, PtrVT)); 4027 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 4028 MachinePointerInfo(), false, false, 0); 4029 MemOpChains.push_back(Store); 4030 if (VR_idx != NumVRs) { 4031 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 4032 MachinePointerInfo(), 4033 false, false, false, 0); 4034 MemOpChains.push_back(Load.getValue(1)); 4035 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 4036 } 4037 ArgOffset += 16; 4038 for (unsigned i=0; i<16; i+=PtrByteSize) { 4039 if (GPR_idx == NumGPRs) 4040 break; 4041 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 4042 DAG.getConstant(i, PtrVT)); 4043 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 4044 false, false, false, 0); 4045 MemOpChains.push_back(Load.getValue(1)); 4046 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4047 } 4048 break; 4049 } 4050 4051 // Non-varargs Altivec params generally go in registers, but have 4052 // stack space allocated at the end. 4053 if (VR_idx != NumVRs) { 4054 // Doesn't have GPR space allocated. 4055 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 4056 } else { 4057 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4058 true, isTailCall, true, MemOpChains, 4059 TailCallArguments, dl); 4060 ArgOffset += 16; 4061 } 4062 break; 4063 } 4064 } 4065 4066 if (!MemOpChains.empty()) 4067 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4068 &MemOpChains[0], MemOpChains.size()); 4069 4070 // Check if this is an indirect call (MTCTR/BCTRL). 4071 // See PrepareCall() for more information about calls through function 4072 // pointers in the 64-bit SVR4 ABI. 4073 if (!isTailCall && 4074 !dyn_cast<GlobalAddressSDNode>(Callee) && 4075 !dyn_cast<ExternalSymbolSDNode>(Callee) && 4076 !isBLACompatibleAddress(Callee, DAG)) { 4077 // Load r2 into a virtual register and store it to the TOC save area. 4078 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 4079 // TOC save area offset. 4080 SDValue PtrOff = DAG.getIntPtrConstant(40); 4081 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 4082 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), 4083 false, false, 0); 4084 // R12 must contain the address of an indirect callee. This does not 4085 // mean the MTCTR instruction must use R12; it's easier to model this 4086 // as an extra parameter, so do that. 4087 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee)); 4088 } 4089 4090 // Build a sequence of copy-to-reg nodes chained together with token chain 4091 // and flag operands which copy the outgoing args into the appropriate regs. 4092 SDValue InFlag; 4093 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 4094 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 4095 RegsToPass[i].second, InFlag); 4096 InFlag = Chain.getValue(1); 4097 } 4098 4099 if (isTailCall) 4100 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp, 4101 FPOp, true, TailCallArguments); 4102 4103 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 4104 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 4105 Ins, InVals); 4106} 4107 4108SDValue 4109PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 4110 CallingConv::ID CallConv, bool isVarArg, 4111 bool isTailCall, 4112 const SmallVectorImpl<ISD::OutputArg> &Outs, 4113 const SmallVectorImpl<SDValue> &OutVals, 4114 const SmallVectorImpl<ISD::InputArg> &Ins, 4115 DebugLoc dl, SelectionDAG &DAG, 4116 SmallVectorImpl<SDValue> &InVals) const { 4117 4118 unsigned NumOps = Outs.size(); 4119 4120 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4121 bool isPPC64 = PtrVT == MVT::i64; 4122 unsigned PtrByteSize = isPPC64 ? 8 : 4; 4123 4124 MachineFunction &MF = DAG.getMachineFunction(); 4125 4126 // Mark this function as potentially containing a function that contains a 4127 // tail call. As a consequence the frame pointer will be used for dynamicalloc 4128 // and restoring the callers stack pointer in this functions epilog. This is 4129 // done because by tail calling the called function might overwrite the value 4130 // in this function's (MF) stack pointer stack slot 0(SP). 4131 if (getTargetMachine().Options.GuaranteedTailCallOpt && 4132 CallConv == CallingConv::Fast) 4133 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 4134 4135 unsigned nAltivecParamsAtEnd = 0; 4136 4137 // Count how many bytes are to be pushed on the stack, including the linkage 4138 // area, and parameter passing area. We start with 24/48 bytes, which is 4139 // prereserved space for [SP][CR][LR][3 x unused]. 4140 unsigned NumBytes = 4141 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 4142 Outs, OutVals, 4143 nAltivecParamsAtEnd); 4144 4145 // Calculate by how many bytes the stack has to be adjusted in case of tail 4146 // call optimization. 4147 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 4148 4149 // To protect arguments on the stack from being clobbered in a tail call, 4150 // force all the loads to happen before doing any other lowering. 4151 if (isTailCall) 4152 Chain = DAG.getStackArgumentTokenFactor(Chain); 4153 4154 // Adjust the stack pointer for the new arguments... 4155 // These operations are automatically eliminated by the prolog/epilog pass 4156 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 4157 SDValue CallSeqStart = Chain; 4158 4159 // Load the return address and frame pointer so it can be move somewhere else 4160 // later. 4161 SDValue LROp, FPOp; 4162 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 4163 dl); 4164 4165 // Set up a copy of the stack pointer for use loading and storing any 4166 // arguments that may not fit in the registers available for argument 4167 // passing. 4168 SDValue StackPtr; 4169 if (isPPC64) 4170 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 4171 else 4172 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 4173 4174 // Figure out which arguments are going to go in registers, and which in 4175 // memory. Also, if this is a vararg function, floating point operations 4176 // must be stored to our stack, and loaded into integer regs as well, if 4177 // any integer regs are available for argument passing. 4178 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 4179 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 4180 4181 static const uint16_t GPR_32[] = { // 32-bit registers. 4182 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 4183 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 4184 }; 4185 static const uint16_t GPR_64[] = { // 64-bit registers. 4186 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 4187 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 4188 }; 4189 static const uint16_t *FPR = GetFPR(); 4190 4191 static const uint16_t VR[] = { 4192 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 4193 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 4194 }; 4195 const unsigned NumGPRs = array_lengthof(GPR_32); 4196 const unsigned NumFPRs = 13; 4197 const unsigned NumVRs = array_lengthof(VR); 4198 4199 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32; 4200 4201 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 4202 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 4203 4204 SmallVector<SDValue, 8> MemOpChains; 4205 for (unsigned i = 0; i != NumOps; ++i) { 4206 SDValue Arg = OutVals[i]; 4207 ISD::ArgFlagsTy Flags = Outs[i].Flags; 4208 4209 // PtrOff will be used to store the current argument to the stack if a 4210 // register cannot be found for it. 4211 SDValue PtrOff; 4212 4213 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 4214 4215 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 4216 4217 // On PPC64, promote integers to 64-bit values. 4218 if (isPPC64 && Arg.getValueType() == MVT::i32) { 4219 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 4220 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 4221 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 4222 } 4223 4224 // FIXME memcpy is used way more than necessary. Correctness first. 4225 // Note: "by value" is code for passing a structure by value, not 4226 // basic types. 4227 if (Flags.isByVal()) { 4228 unsigned Size = Flags.getByValSize(); 4229 // Very small objects are passed right-justified. Everything else is 4230 // passed left-justified. 4231 if (Size==1 || Size==2) { 4232 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 4233 if (GPR_idx != NumGPRs) { 4234 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 4235 MachinePointerInfo(), VT, 4236 false, false, 0); 4237 MemOpChains.push_back(Load.getValue(1)); 4238 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4239 4240 ArgOffset += PtrByteSize; 4241 } else { 4242 SDValue Const = DAG.getConstant(PtrByteSize - Size, 4243 PtrOff.getValueType()); 4244 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 4245 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, 4246 CallSeqStart, 4247 Flags, DAG, dl); 4248 ArgOffset += PtrByteSize; 4249 } 4250 continue; 4251 } 4252 // Copy entire object into memory. There are cases where gcc-generated 4253 // code assumes it is there, even if it could be put entirely into 4254 // registers. (This is not what the doc says.) 4255 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, 4256 CallSeqStart, 4257 Flags, DAG, dl); 4258 4259 // For small aggregates (Darwin only) and aggregates >= PtrByteSize, 4260 // copy the pieces of the object that fit into registers from the 4261 // parameter save area. 4262 for (unsigned j=0; j<Size; j+=PtrByteSize) { 4263 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 4264 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 4265 if (GPR_idx != NumGPRs) { 4266 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 4267 MachinePointerInfo(), 4268 false, false, false, 0); 4269 MemOpChains.push_back(Load.getValue(1)); 4270 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4271 ArgOffset += PtrByteSize; 4272 } else { 4273 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 4274 break; 4275 } 4276 } 4277 continue; 4278 } 4279 4280 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 4281 default: llvm_unreachable("Unexpected ValueType for argument!"); 4282 case MVT::i32: 4283 case MVT::i64: 4284 if (GPR_idx != NumGPRs) { 4285 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 4286 } else { 4287 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4288 isPPC64, isTailCall, false, MemOpChains, 4289 TailCallArguments, dl); 4290 } 4291 ArgOffset += PtrByteSize; 4292 break; 4293 case MVT::f32: 4294 case MVT::f64: 4295 if (FPR_idx != NumFPRs) { 4296 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 4297 4298 if (isVarArg) { 4299 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 4300 MachinePointerInfo(), false, false, 0); 4301 MemOpChains.push_back(Store); 4302 4303 // Float varargs are always shadowed in available integer registers 4304 if (GPR_idx != NumGPRs) { 4305 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 4306 MachinePointerInfo(), false, false, 4307 false, 0); 4308 MemOpChains.push_back(Load.getValue(1)); 4309 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4310 } 4311 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 4312 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 4313 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 4314 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 4315 MachinePointerInfo(), 4316 false, false, false, 0); 4317 MemOpChains.push_back(Load.getValue(1)); 4318 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4319 } 4320 } else { 4321 // If we have any FPRs remaining, we may also have GPRs remaining. 4322 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 4323 // GPRs. 4324 if (GPR_idx != NumGPRs) 4325 ++GPR_idx; 4326 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 4327 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 4328 ++GPR_idx; 4329 } 4330 } else 4331 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4332 isPPC64, isTailCall, false, MemOpChains, 4333 TailCallArguments, dl); 4334 if (isPPC64) 4335 ArgOffset += 8; 4336 else 4337 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 4338 break; 4339 case MVT::v4f32: 4340 case MVT::v4i32: 4341 case MVT::v8i16: 4342 case MVT::v16i8: 4343 if (isVarArg) { 4344 // These go aligned on the stack, or in the corresponding R registers 4345 // when within range. The Darwin PPC ABI doc claims they also go in 4346 // V registers; in fact gcc does this only for arguments that are 4347 // prototyped, not for those that match the ... We do it for all 4348 // arguments, seems to work. 4349 while (ArgOffset % 16 !=0) { 4350 ArgOffset += PtrByteSize; 4351 if (GPR_idx != NumGPRs) 4352 GPR_idx++; 4353 } 4354 // We could elide this store in the case where the object fits 4355 // entirely in R registers. Maybe later. 4356 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 4357 DAG.getConstant(ArgOffset, PtrVT)); 4358 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 4359 MachinePointerInfo(), false, false, 0); 4360 MemOpChains.push_back(Store); 4361 if (VR_idx != NumVRs) { 4362 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 4363 MachinePointerInfo(), 4364 false, false, false, 0); 4365 MemOpChains.push_back(Load.getValue(1)); 4366 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 4367 } 4368 ArgOffset += 16; 4369 for (unsigned i=0; i<16; i+=PtrByteSize) { 4370 if (GPR_idx == NumGPRs) 4371 break; 4372 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 4373 DAG.getConstant(i, PtrVT)); 4374 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 4375 false, false, false, 0); 4376 MemOpChains.push_back(Load.getValue(1)); 4377 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 4378 } 4379 break; 4380 } 4381 4382 // Non-varargs Altivec params generally go in registers, but have 4383 // stack space allocated at the end. 4384 if (VR_idx != NumVRs) { 4385 // Doesn't have GPR space allocated. 4386 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 4387 } else if (nAltivecParamsAtEnd==0) { 4388 // We are emitting Altivec params in order. 4389 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4390 isPPC64, isTailCall, true, MemOpChains, 4391 TailCallArguments, dl); 4392 ArgOffset += 16; 4393 } 4394 break; 4395 } 4396 } 4397 // If all Altivec parameters fit in registers, as they usually do, 4398 // they get stack space following the non-Altivec parameters. We 4399 // don't track this here because nobody below needs it. 4400 // If there are more Altivec parameters than fit in registers emit 4401 // the stores here. 4402 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 4403 unsigned j = 0; 4404 // Offset is aligned; skip 1st 12 params which go in V registers. 4405 ArgOffset = ((ArgOffset+15)/16)*16; 4406 ArgOffset += 12*16; 4407 for (unsigned i = 0; i != NumOps; ++i) { 4408 SDValue Arg = OutVals[i]; 4409 EVT ArgType = Outs[i].VT; 4410 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 4411 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 4412 if (++j > NumVRs) { 4413 SDValue PtrOff; 4414 // We are emitting Altivec params in order. 4415 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 4416 isPPC64, isTailCall, true, MemOpChains, 4417 TailCallArguments, dl); 4418 ArgOffset += 16; 4419 } 4420 } 4421 } 4422 } 4423 4424 if (!MemOpChains.empty()) 4425 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 4426 &MemOpChains[0], MemOpChains.size()); 4427 4428 // On Darwin, R12 must contain the address of an indirect callee. This does 4429 // not mean the MTCTR instruction must use R12; it's easier to model this as 4430 // an extra parameter, so do that. 4431 if (!isTailCall && 4432 !dyn_cast<GlobalAddressSDNode>(Callee) && 4433 !dyn_cast<ExternalSymbolSDNode>(Callee) && 4434 !isBLACompatibleAddress(Callee, DAG)) 4435 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 4436 PPC::R12), Callee)); 4437 4438 // Build a sequence of copy-to-reg nodes chained together with token chain 4439 // and flag operands which copy the outgoing args into the appropriate regs. 4440 SDValue InFlag; 4441 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 4442 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 4443 RegsToPass[i].second, InFlag); 4444 InFlag = Chain.getValue(1); 4445 } 4446 4447 if (isTailCall) 4448 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 4449 FPOp, true, TailCallArguments); 4450 4451 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 4452 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 4453 Ins, InVals); 4454} 4455 4456bool 4457PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 4458 MachineFunction &MF, bool isVarArg, 4459 const SmallVectorImpl<ISD::OutputArg> &Outs, 4460 LLVMContext &Context) const { 4461 SmallVector<CCValAssign, 16> RVLocs; 4462 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 4463 RVLocs, Context); 4464 return CCInfo.CheckReturn(Outs, RetCC_PPC); 4465} 4466 4467SDValue 4468PPCTargetLowering::LowerReturn(SDValue Chain, 4469 CallingConv::ID CallConv, bool isVarArg, 4470 const SmallVectorImpl<ISD::OutputArg> &Outs, 4471 const SmallVectorImpl<SDValue> &OutVals, 4472 DebugLoc dl, SelectionDAG &DAG) const { 4473 4474 SmallVector<CCValAssign, 16> RVLocs; 4475 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 4476 getTargetMachine(), RVLocs, *DAG.getContext()); 4477 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 4478 4479 SDValue Flag; 4480 SmallVector<SDValue, 4> RetOps(1, Chain); 4481 4482 // Copy the result values into the output registers. 4483 for (unsigned i = 0; i != RVLocs.size(); ++i) { 4484 CCValAssign &VA = RVLocs[i]; 4485 assert(VA.isRegLoc() && "Can only return in registers!"); 4486 4487 SDValue Arg = OutVals[i]; 4488 4489 switch (VA.getLocInfo()) { 4490 default: llvm_unreachable("Unknown loc info!"); 4491 case CCValAssign::Full: break; 4492 case CCValAssign::AExt: 4493 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 4494 break; 4495 case CCValAssign::ZExt: 4496 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 4497 break; 4498 case CCValAssign::SExt: 4499 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 4500 break; 4501 } 4502 4503 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 4504 Flag = Chain.getValue(1); 4505 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 4506 } 4507 4508 RetOps[0] = Chain; // Update chain. 4509 4510 // Add the flag if we have it. 4511 if (Flag.getNode()) 4512 RetOps.push_back(Flag); 4513 4514 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, 4515 &RetOps[0], RetOps.size()); 4516} 4517 4518SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 4519 const PPCSubtarget &Subtarget) const { 4520 // When we pop the dynamic allocation we need to restore the SP link. 4521 DebugLoc dl = Op.getDebugLoc(); 4522 4523 // Get the corect type for pointers. 4524 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4525 4526 // Construct the stack pointer operand. 4527 bool isPPC64 = Subtarget.isPPC64(); 4528 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 4529 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 4530 4531 // Get the operands for the STACKRESTORE. 4532 SDValue Chain = Op.getOperand(0); 4533 SDValue SaveSP = Op.getOperand(1); 4534 4535 // Load the old link SP. 4536 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, 4537 MachinePointerInfo(), 4538 false, false, false, 0); 4539 4540 // Restore the stack pointer. 4541 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 4542 4543 // Store the old link SP. 4544 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(), 4545 false, false, 0); 4546} 4547 4548 4549 4550SDValue 4551PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 4552 MachineFunction &MF = DAG.getMachineFunction(); 4553 bool isPPC64 = PPCSubTarget.isPPC64(); 4554 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 4555 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4556 4557 // Get current frame pointer save index. The users of this index will be 4558 // primarily DYNALLOC instructions. 4559 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 4560 int RASI = FI->getReturnAddrSaveIndex(); 4561 4562 // If the frame pointer save index hasn't been defined yet. 4563 if (!RASI) { 4564 // Find out what the fix offset of the frame pointer save area. 4565 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 4566 // Allocate the frame index for frame pointer save area. 4567 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 4568 // Save the result. 4569 FI->setReturnAddrSaveIndex(RASI); 4570 } 4571 return DAG.getFrameIndex(RASI, PtrVT); 4572} 4573 4574SDValue 4575PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 4576 MachineFunction &MF = DAG.getMachineFunction(); 4577 bool isPPC64 = PPCSubTarget.isPPC64(); 4578 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 4579 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4580 4581 // Get current frame pointer save index. The users of this index will be 4582 // primarily DYNALLOC instructions. 4583 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 4584 int FPSI = FI->getFramePointerSaveIndex(); 4585 4586 // If the frame pointer save index hasn't been defined yet. 4587 if (!FPSI) { 4588 // Find out what the fix offset of the frame pointer save area. 4589 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, 4590 isDarwinABI); 4591 4592 // Allocate the frame index for frame pointer save area. 4593 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 4594 // Save the result. 4595 FI->setFramePointerSaveIndex(FPSI); 4596 } 4597 return DAG.getFrameIndex(FPSI, PtrVT); 4598} 4599 4600SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 4601 SelectionDAG &DAG, 4602 const PPCSubtarget &Subtarget) const { 4603 // Get the inputs. 4604 SDValue Chain = Op.getOperand(0); 4605 SDValue Size = Op.getOperand(1); 4606 DebugLoc dl = Op.getDebugLoc(); 4607 4608 // Get the corect type for pointers. 4609 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4610 // Negate the size. 4611 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 4612 DAG.getConstant(0, PtrVT), Size); 4613 // Construct a node for the frame pointer save index. 4614 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 4615 // Build a DYNALLOC node. 4616 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 4617 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 4618 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 4619} 4620 4621SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op, 4622 SelectionDAG &DAG) const { 4623 DebugLoc DL = Op.getDebugLoc(); 4624 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL, 4625 DAG.getVTList(MVT::i32, MVT::Other), 4626 Op.getOperand(0), Op.getOperand(1)); 4627} 4628 4629SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op, 4630 SelectionDAG &DAG) const { 4631 DebugLoc DL = Op.getDebugLoc(); 4632 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other, 4633 Op.getOperand(0), Op.getOperand(1)); 4634} 4635 4636/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 4637/// possible. 4638SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 4639 // Not FP? Not a fsel. 4640 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 4641 !Op.getOperand(2).getValueType().isFloatingPoint()) 4642 return Op; 4643 4644 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 4645 4646 // Cannot handle SETEQ/SETNE. 4647 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 4648 4649 EVT ResVT = Op.getValueType(); 4650 EVT CmpVT = Op.getOperand(0).getValueType(); 4651 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4652 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 4653 DebugLoc dl = Op.getDebugLoc(); 4654 4655 // If the RHS of the comparison is a 0.0, we don't need to do the 4656 // subtraction at all. 4657 if (isFloatingPointZero(RHS)) 4658 switch (CC) { 4659 default: break; // SETUO etc aren't handled by fsel. 4660 case ISD::SETULT: 4661 case ISD::SETLT: 4662 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 4663 case ISD::SETOGE: 4664 case ISD::SETGE: 4665 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 4666 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 4667 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 4668 case ISD::SETUGT: 4669 case ISD::SETGT: 4670 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 4671 case ISD::SETOLE: 4672 case ISD::SETLE: 4673 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 4674 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 4675 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 4676 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 4677 } 4678 4679 SDValue Cmp; 4680 switch (CC) { 4681 default: break; // SETUO etc aren't handled by fsel. 4682 case ISD::SETULT: 4683 case ISD::SETLT: 4684 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 4685 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4686 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4687 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 4688 case ISD::SETOGE: 4689 case ISD::SETGE: 4690 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 4691 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4692 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4693 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 4694 case ISD::SETUGT: 4695 case ISD::SETGT: 4696 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 4697 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4698 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4699 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 4700 case ISD::SETOLE: 4701 case ISD::SETLE: 4702 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 4703 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 4704 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 4705 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 4706 } 4707 return Op; 4708} 4709 4710// FIXME: Split this code up when LegalizeDAGTypes lands. 4711SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 4712 DebugLoc dl) const { 4713 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 4714 SDValue Src = Op.getOperand(0); 4715 if (Src.getValueType() == MVT::f32) 4716 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 4717 4718 SDValue Tmp; 4719 switch (Op.getValueType().getSimpleVT().SimpleTy) { 4720 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 4721 case MVT::i32: 4722 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 4723 PPCISD::FCTIDZ, 4724 dl, MVT::f64, Src); 4725 break; 4726 case MVT::i64: 4727 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 4728 break; 4729 } 4730 4731 // Convert the FP value to an int value through memory. 4732 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 4733 4734 // Emit a store to the stack slot. 4735 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, 4736 MachinePointerInfo(), false, false, 0); 4737 4738 // Result is a load from the stack slot. If loading 4 bytes, make sure to 4739 // add in a bias. 4740 if (Op.getValueType() == MVT::i32) 4741 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 4742 DAG.getConstant(4, FIPtr.getValueType())); 4743 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(), 4744 false, false, false, 0); 4745} 4746 4747SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, 4748 SelectionDAG &DAG) const { 4749 DebugLoc dl = Op.getDebugLoc(); 4750 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 4751 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 4752 return SDValue(); 4753 4754 if (Op.getOperand(0).getValueType() == MVT::i64) { 4755 SDValue SINT = Op.getOperand(0); 4756 // When converting to single-precision, we actually need to convert 4757 // to double-precision first and then round to single-precision. 4758 // To avoid double-rounding effects during that operation, we have 4759 // to prepare the input operand. Bits that might be truncated when 4760 // converting to double-precision are replaced by a bit that won't 4761 // be lost at this stage, but is below the single-precision rounding 4762 // position. 4763 // 4764 // However, if -enable-unsafe-fp-math is in effect, accept double 4765 // rounding to avoid the extra overhead. 4766 if (Op.getValueType() == MVT::f32 && 4767 !DAG.getTarget().Options.UnsafeFPMath) { 4768 4769 // Twiddle input to make sure the low 11 bits are zero. (If this 4770 // is the case, we are guaranteed the value will fit into the 53 bit 4771 // mantissa of an IEEE double-precision value without rounding.) 4772 // If any of those low 11 bits were not zero originally, make sure 4773 // bit 12 (value 2048) is set instead, so that the final rounding 4774 // to single-precision gets the correct result. 4775 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, 4776 SINT, DAG.getConstant(2047, MVT::i64)); 4777 Round = DAG.getNode(ISD::ADD, dl, MVT::i64, 4778 Round, DAG.getConstant(2047, MVT::i64)); 4779 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); 4780 Round = DAG.getNode(ISD::AND, dl, MVT::i64, 4781 Round, DAG.getConstant(-2048, MVT::i64)); 4782 4783 // However, we cannot use that value unconditionally: if the magnitude 4784 // of the input value is small, the bit-twiddling we did above might 4785 // end up visibly changing the output. Fortunately, in that case, we 4786 // don't need to twiddle bits since the original input will convert 4787 // exactly to double-precision floating-point already. Therefore, 4788 // construct a conditional to use the original value if the top 11 4789 // bits are all sign-bit copies, and use the rounded value computed 4790 // above otherwise. 4791 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, 4792 SINT, DAG.getConstant(53, MVT::i32)); 4793 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, 4794 Cond, DAG.getConstant(1, MVT::i64)); 4795 Cond = DAG.getSetCC(dl, MVT::i32, 4796 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT); 4797 4798 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT); 4799 } 4800 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT); 4801 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 4802 if (Op.getValueType() == MVT::f32) 4803 FP = DAG.getNode(ISD::FP_ROUND, dl, 4804 MVT::f32, FP, DAG.getIntPtrConstant(0)); 4805 return FP; 4806 } 4807 4808 assert(Op.getOperand(0).getValueType() == MVT::i32 && 4809 "Unhandled SINT_TO_FP type in custom expander!"); 4810 // Since we only generate this in 64-bit mode, we can take advantage of 4811 // 64-bit registers. In particular, sign extend the input value into the 4812 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 4813 // then lfd it and fcfid it. 4814 MachineFunction &MF = DAG.getMachineFunction(); 4815 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 4816 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 4817 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4818 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4819 4820 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 4821 Op.getOperand(0)); 4822 4823 // STD the extended value into the stack slot. 4824 MachineMemOperand *MMO = 4825 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 4826 MachineMemOperand::MOStore, 8, 8); 4827 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 4828 SDValue Store = 4829 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 4830 Ops, 4, MVT::i64, MMO); 4831 // Load the value as a double. 4832 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(), 4833 false, false, false, 0); 4834 4835 // FCFID it and return it. 4836 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 4837 if (Op.getValueType() == MVT::f32) 4838 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 4839 return FP; 4840} 4841 4842SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 4843 SelectionDAG &DAG) const { 4844 DebugLoc dl = Op.getDebugLoc(); 4845 /* 4846 The rounding mode is in bits 30:31 of FPSR, and has the following 4847 settings: 4848 00 Round to nearest 4849 01 Round to 0 4850 10 Round to +inf 4851 11 Round to -inf 4852 4853 FLT_ROUNDS, on the other hand, expects the following: 4854 -1 Undefined 4855 0 Round to 0 4856 1 Round to nearest 4857 2 Round to +inf 4858 3 Round to -inf 4859 4860 To perform the conversion, we do: 4861 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 4862 */ 4863 4864 MachineFunction &MF = DAG.getMachineFunction(); 4865 EVT VT = Op.getValueType(); 4866 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 4867 SDValue MFFSreg, InFlag; 4868 4869 // Save FP Control Word to register 4870 EVT NodeTys[] = { 4871 MVT::f64, // return register 4872 MVT::Glue // unused in this context 4873 }; 4874 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4875 4876 // Save FP register to stack slot 4877 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 4878 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 4879 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 4880 StackSlot, MachinePointerInfo(), false, false,0); 4881 4882 // Load FP Control Word from low 32 bits of stack slot. 4883 SDValue Four = DAG.getConstant(4, PtrVT); 4884 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 4885 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), 4886 false, false, false, 0); 4887 4888 // Transform as necessary 4889 SDValue CWD1 = 4890 DAG.getNode(ISD::AND, dl, MVT::i32, 4891 CWD, DAG.getConstant(3, MVT::i32)); 4892 SDValue CWD2 = 4893 DAG.getNode(ISD::SRL, dl, MVT::i32, 4894 DAG.getNode(ISD::AND, dl, MVT::i32, 4895 DAG.getNode(ISD::XOR, dl, MVT::i32, 4896 CWD, DAG.getConstant(3, MVT::i32)), 4897 DAG.getConstant(3, MVT::i32)), 4898 DAG.getConstant(1, MVT::i32)); 4899 4900 SDValue RetVal = 4901 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 4902 4903 return DAG.getNode((VT.getSizeInBits() < 16 ? 4904 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 4905} 4906 4907SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4908 EVT VT = Op.getValueType(); 4909 unsigned BitWidth = VT.getSizeInBits(); 4910 DebugLoc dl = Op.getDebugLoc(); 4911 assert(Op.getNumOperands() == 3 && 4912 VT == Op.getOperand(1).getValueType() && 4913 "Unexpected SHL!"); 4914 4915 // Expand into a bunch of logical ops. Note that these ops 4916 // depend on the PPC behavior for oversized shift amounts. 4917 SDValue Lo = Op.getOperand(0); 4918 SDValue Hi = Op.getOperand(1); 4919 SDValue Amt = Op.getOperand(2); 4920 EVT AmtVT = Amt.getValueType(); 4921 4922 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4923 DAG.getConstant(BitWidth, AmtVT), Amt); 4924 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 4925 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 4926 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 4927 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4928 DAG.getConstant(-BitWidth, AmtVT)); 4929 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 4930 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 4931 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 4932 SDValue OutOps[] = { OutLo, OutHi }; 4933 return DAG.getMergeValues(OutOps, 2, dl); 4934} 4935 4936SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 4937 EVT VT = Op.getValueType(); 4938 DebugLoc dl = Op.getDebugLoc(); 4939 unsigned BitWidth = VT.getSizeInBits(); 4940 assert(Op.getNumOperands() == 3 && 4941 VT == Op.getOperand(1).getValueType() && 4942 "Unexpected SRL!"); 4943 4944 // Expand into a bunch of logical ops. Note that these ops 4945 // depend on the PPC behavior for oversized shift amounts. 4946 SDValue Lo = Op.getOperand(0); 4947 SDValue Hi = Op.getOperand(1); 4948 SDValue Amt = Op.getOperand(2); 4949 EVT AmtVT = Amt.getValueType(); 4950 4951 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4952 DAG.getConstant(BitWidth, AmtVT), Amt); 4953 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 4954 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 4955 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 4956 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4957 DAG.getConstant(-BitWidth, AmtVT)); 4958 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 4959 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 4960 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 4961 SDValue OutOps[] = { OutLo, OutHi }; 4962 return DAG.getMergeValues(OutOps, 2, dl); 4963} 4964 4965SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 4966 DebugLoc dl = Op.getDebugLoc(); 4967 EVT VT = Op.getValueType(); 4968 unsigned BitWidth = VT.getSizeInBits(); 4969 assert(Op.getNumOperands() == 3 && 4970 VT == Op.getOperand(1).getValueType() && 4971 "Unexpected SRA!"); 4972 4973 // Expand into a bunch of logical ops, followed by a select_cc. 4974 SDValue Lo = Op.getOperand(0); 4975 SDValue Hi = Op.getOperand(1); 4976 SDValue Amt = Op.getOperand(2); 4977 EVT AmtVT = Amt.getValueType(); 4978 4979 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 4980 DAG.getConstant(BitWidth, AmtVT), Amt); 4981 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 4982 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 4983 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 4984 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 4985 DAG.getConstant(-BitWidth, AmtVT)); 4986 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 4987 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 4988 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 4989 Tmp4, Tmp6, ISD::SETLE); 4990 SDValue OutOps[] = { OutLo, OutHi }; 4991 return DAG.getMergeValues(OutOps, 2, dl); 4992} 4993 4994//===----------------------------------------------------------------------===// 4995// Vector related lowering. 4996// 4997 4998/// BuildSplatI - Build a canonical splati of Val with an element size of 4999/// SplatSize. Cast the result to VT. 5000static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 5001 SelectionDAG &DAG, DebugLoc dl) { 5002 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 5003 5004 static const EVT VTys[] = { // canonical VT to use for each size. 5005 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 5006 }; 5007 5008 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 5009 5010 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 5011 if (Val == -1) 5012 SplatSize = 1; 5013 5014 EVT CanonicalVT = VTys[SplatSize-1]; 5015 5016 // Build a canonical splat for this value. 5017 SDValue Elt = DAG.getConstant(Val, MVT::i32); 5018 SmallVector<SDValue, 8> Ops; 5019 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 5020 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 5021 &Ops[0], Ops.size()); 5022 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res); 5023} 5024 5025/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 5026/// specified intrinsic ID. 5027static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 5028 SelectionDAG &DAG, DebugLoc dl, 5029 EVT DestVT = MVT::Other) { 5030 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 5031 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 5032 DAG.getConstant(IID, MVT::i32), LHS, RHS); 5033} 5034 5035/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 5036/// specified intrinsic ID. 5037static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 5038 SDValue Op2, SelectionDAG &DAG, 5039 DebugLoc dl, EVT DestVT = MVT::Other) { 5040 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 5041 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 5042 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 5043} 5044 5045 5046/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 5047/// amount. The result has the specified value type. 5048static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 5049 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 5050 // Force LHS/RHS to be the right type. 5051 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); 5052 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); 5053 5054 int Ops[16]; 5055 for (unsigned i = 0; i != 16; ++i) 5056 Ops[i] = i + Amt; 5057 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 5058 return DAG.getNode(ISD::BITCAST, dl, VT, T); 5059} 5060 5061// If this is a case we can't handle, return null and let the default 5062// expansion code take care of it. If we CAN select this case, and if it 5063// selects to a single instruction, return Op. Otherwise, if we can codegen 5064// this case more efficiently than a constant pool load, lower it to the 5065// sequence of ops that should be used. 5066SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 5067 SelectionDAG &DAG) const { 5068 DebugLoc dl = Op.getDebugLoc(); 5069 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 5070 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 5071 5072 // Check if this is a splat of a constant value. 5073 APInt APSplatBits, APSplatUndef; 5074 unsigned SplatBitSize; 5075 bool HasAnyUndefs; 5076 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 5077 HasAnyUndefs, 0, true) || SplatBitSize > 32) 5078 return SDValue(); 5079 5080 unsigned SplatBits = APSplatBits.getZExtValue(); 5081 unsigned SplatUndef = APSplatUndef.getZExtValue(); 5082 unsigned SplatSize = SplatBitSize / 8; 5083 5084 // First, handle single instruction cases. 5085 5086 // All zeros? 5087 if (SplatBits == 0) { 5088 // Canonicalize all zero vectors to be v4i32. 5089 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 5090 SDValue Z = DAG.getConstant(0, MVT::i32); 5091 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 5092 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z); 5093 } 5094 return Op; 5095 } 5096 5097 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 5098 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 5099 (32-SplatBitSize)); 5100 if (SextVal >= -16 && SextVal <= 15) 5101 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 5102 5103 5104 // Two instruction sequences. 5105 5106 // If this value is in the range [-32,30] and is even, use: 5107 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2) 5108 // If this value is in the range [17,31] and is odd, use: 5109 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16) 5110 // If this value is in the range [-31,-17] and is odd, use: 5111 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16) 5112 // Note the last two are three-instruction sequences. 5113 if (SextVal >= -32 && SextVal <= 31) { 5114 // To avoid having these optimizations undone by constant folding, 5115 // we convert to a pseudo that will be expanded later into one of 5116 // the above forms. 5117 SDValue Elt = DAG.getConstant(SextVal, MVT::i32); 5118 EVT VT = Op.getValueType(); 5119 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4); 5120 SDValue EltSize = DAG.getConstant(Size, MVT::i32); 5121 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize); 5122 } 5123 5124 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 5125 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 5126 // for fneg/fabs. 5127 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 5128 // Make -1 and vspltisw -1: 5129 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 5130 5131 // Make the VSLW intrinsic, computing 0x8000_0000. 5132 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 5133 OnesV, DAG, dl); 5134 5135 // xor by OnesV to invert it. 5136 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 5137 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5138 } 5139 5140 // Check to see if this is a wide variety of vsplti*, binop self cases. 5141 static const signed char SplatCsts[] = { 5142 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 5143 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 5144 }; 5145 5146 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 5147 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 5148 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 5149 int i = SplatCsts[idx]; 5150 5151 // Figure out what shift amount will be used by altivec if shifted by i in 5152 // this splat size. 5153 unsigned TypeShiftAmt = i & (SplatBitSize-1); 5154 5155 // vsplti + shl self. 5156 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) { 5157 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5158 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5159 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 5160 Intrinsic::ppc_altivec_vslw 5161 }; 5162 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5163 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5164 } 5165 5166 // vsplti + srl self. 5167 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 5168 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5169 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5170 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 5171 Intrinsic::ppc_altivec_vsrw 5172 }; 5173 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5174 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5175 } 5176 5177 // vsplti + sra self. 5178 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 5179 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5180 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5181 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 5182 Intrinsic::ppc_altivec_vsraw 5183 }; 5184 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5185 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5186 } 5187 5188 // vsplti + rol self. 5189 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 5190 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 5191 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 5192 static const unsigned IIDs[] = { // Intrinsic to use for each size. 5193 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 5194 Intrinsic::ppc_altivec_vrlw 5195 }; 5196 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 5197 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 5198 } 5199 5200 // t = vsplti c, result = vsldoi t, t, 1 5201 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) { 5202 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5203 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 5204 } 5205 // t = vsplti c, result = vsldoi t, t, 2 5206 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) { 5207 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5208 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 5209 } 5210 // t = vsplti c, result = vsldoi t, t, 3 5211 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) { 5212 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 5213 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 5214 } 5215 } 5216 5217 return SDValue(); 5218} 5219 5220/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 5221/// the specified operations to build the shuffle. 5222static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 5223 SDValue RHS, SelectionDAG &DAG, 5224 DebugLoc dl) { 5225 unsigned OpNum = (PFEntry >> 26) & 0x0F; 5226 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 5227 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 5228 5229 enum { 5230 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 5231 OP_VMRGHW, 5232 OP_VMRGLW, 5233 OP_VSPLTISW0, 5234 OP_VSPLTISW1, 5235 OP_VSPLTISW2, 5236 OP_VSPLTISW3, 5237 OP_VSLDOI4, 5238 OP_VSLDOI8, 5239 OP_VSLDOI12 5240 }; 5241 5242 if (OpNum == OP_COPY) { 5243 if (LHSID == (1*9+2)*9+3) return LHS; 5244 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 5245 return RHS; 5246 } 5247 5248 SDValue OpLHS, OpRHS; 5249 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 5250 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 5251 5252 int ShufIdxs[16]; 5253 switch (OpNum) { 5254 default: llvm_unreachable("Unknown i32 permute!"); 5255 case OP_VMRGHW: 5256 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 5257 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 5258 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 5259 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 5260 break; 5261 case OP_VMRGLW: 5262 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 5263 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 5264 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 5265 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 5266 break; 5267 case OP_VSPLTISW0: 5268 for (unsigned i = 0; i != 16; ++i) 5269 ShufIdxs[i] = (i&3)+0; 5270 break; 5271 case OP_VSPLTISW1: 5272 for (unsigned i = 0; i != 16; ++i) 5273 ShufIdxs[i] = (i&3)+4; 5274 break; 5275 case OP_VSPLTISW2: 5276 for (unsigned i = 0; i != 16; ++i) 5277 ShufIdxs[i] = (i&3)+8; 5278 break; 5279 case OP_VSPLTISW3: 5280 for (unsigned i = 0; i != 16; ++i) 5281 ShufIdxs[i] = (i&3)+12; 5282 break; 5283 case OP_VSLDOI4: 5284 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 5285 case OP_VSLDOI8: 5286 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 5287 case OP_VSLDOI12: 5288 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 5289 } 5290 EVT VT = OpLHS.getValueType(); 5291 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); 5292 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); 5293 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 5294 return DAG.getNode(ISD::BITCAST, dl, VT, T); 5295} 5296 5297/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 5298/// is a shuffle we can handle in a single instruction, return it. Otherwise, 5299/// return the code it can be lowered into. Worst case, it can always be 5300/// lowered into a vperm. 5301SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 5302 SelectionDAG &DAG) const { 5303 DebugLoc dl = Op.getDebugLoc(); 5304 SDValue V1 = Op.getOperand(0); 5305 SDValue V2 = Op.getOperand(1); 5306 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5307 EVT VT = Op.getValueType(); 5308 5309 // Cases that are handled by instructions that take permute immediates 5310 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 5311 // selected by the instruction selector. 5312 if (V2.getOpcode() == ISD::UNDEF) { 5313 if (PPC::isSplatShuffleMask(SVOp, 1) || 5314 PPC::isSplatShuffleMask(SVOp, 2) || 5315 PPC::isSplatShuffleMask(SVOp, 4) || 5316 PPC::isVPKUWUMShuffleMask(SVOp, true) || 5317 PPC::isVPKUHUMShuffleMask(SVOp, true) || 5318 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 5319 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 5320 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 5321 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 5322 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 5323 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 5324 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 5325 return Op; 5326 } 5327 } 5328 5329 // Altivec has a variety of "shuffle immediates" that take two vector inputs 5330 // and produce a fixed permutation. If any of these match, do not lower to 5331 // VPERM. 5332 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 5333 PPC::isVPKUHUMShuffleMask(SVOp, false) || 5334 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 5335 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 5336 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 5337 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 5338 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 5339 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 5340 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 5341 return Op; 5342 5343 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 5344 // perfect shuffle table to emit an optimal matching sequence. 5345 ArrayRef<int> PermMask = SVOp->getMask(); 5346 5347 unsigned PFIndexes[4]; 5348 bool isFourElementShuffle = true; 5349 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 5350 unsigned EltNo = 8; // Start out undef. 5351 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 5352 if (PermMask[i*4+j] < 0) 5353 continue; // Undef, ignore it. 5354 5355 unsigned ByteSource = PermMask[i*4+j]; 5356 if ((ByteSource & 3) != j) { 5357 isFourElementShuffle = false; 5358 break; 5359 } 5360 5361 if (EltNo == 8) { 5362 EltNo = ByteSource/4; 5363 } else if (EltNo != ByteSource/4) { 5364 isFourElementShuffle = false; 5365 break; 5366 } 5367 } 5368 PFIndexes[i] = EltNo; 5369 } 5370 5371 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 5372 // perfect shuffle vector to determine if it is cost effective to do this as 5373 // discrete instructions, or whether we should use a vperm. 5374 if (isFourElementShuffle) { 5375 // Compute the index in the perfect shuffle table. 5376 unsigned PFTableIndex = 5377 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 5378 5379 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 5380 unsigned Cost = (PFEntry >> 30); 5381 5382 // Determining when to avoid vperm is tricky. Many things affect the cost 5383 // of vperm, particularly how many times the perm mask needs to be computed. 5384 // For example, if the perm mask can be hoisted out of a loop or is already 5385 // used (perhaps because there are multiple permutes with the same shuffle 5386 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 5387 // the loop requires an extra register. 5388 // 5389 // As a compromise, we only emit discrete instructions if the shuffle can be 5390 // generated in 3 or fewer operations. When we have loop information 5391 // available, if this block is within a loop, we should avoid using vperm 5392 // for 3-operation perms and use a constant pool load instead. 5393 if (Cost < 3) 5394 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 5395 } 5396 5397 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 5398 // vector that will get spilled to the constant pool. 5399 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 5400 5401 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 5402 // that it is in input element units, not in bytes. Convert now. 5403 EVT EltVT = V1.getValueType().getVectorElementType(); 5404 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 5405 5406 SmallVector<SDValue, 16> ResultMask; 5407 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 5408 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 5409 5410 for (unsigned j = 0; j != BytesPerElement; ++j) 5411 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 5412 MVT::i32)); 5413 } 5414 5415 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 5416 &ResultMask[0], ResultMask.size()); 5417 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 5418} 5419 5420/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 5421/// altivec comparison. If it is, return true and fill in Opc/isDot with 5422/// information about the intrinsic. 5423static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 5424 bool &isDot) { 5425 unsigned IntrinsicID = 5426 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 5427 CompareOpc = -1; 5428 isDot = false; 5429 switch (IntrinsicID) { 5430 default: return false; 5431 // Comparison predicates. 5432 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 5433 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 5434 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 5435 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 5436 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 5437 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 5438 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 5439 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 5440 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 5441 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 5442 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 5443 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 5444 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 5445 5446 // Normal Comparisons. 5447 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 5448 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 5449 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 5450 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 5451 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 5452 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 5453 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 5454 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 5455 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 5456 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 5457 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 5458 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 5459 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 5460 } 5461 return true; 5462} 5463 5464/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 5465/// lower, do it, otherwise return null. 5466SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 5467 SelectionDAG &DAG) const { 5468 // If this is a lowered altivec predicate compare, CompareOpc is set to the 5469 // opcode number of the comparison. 5470 DebugLoc dl = Op.getDebugLoc(); 5471 int CompareOpc; 5472 bool isDot; 5473 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 5474 return SDValue(); // Don't custom lower most intrinsics. 5475 5476 // If this is a non-dot comparison, make the VCMP node and we are done. 5477 if (!isDot) { 5478 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 5479 Op.getOperand(1), Op.getOperand(2), 5480 DAG.getConstant(CompareOpc, MVT::i32)); 5481 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp); 5482 } 5483 5484 // Create the PPCISD altivec 'dot' comparison node. 5485 SDValue Ops[] = { 5486 Op.getOperand(2), // LHS 5487 Op.getOperand(3), // RHS 5488 DAG.getConstant(CompareOpc, MVT::i32) 5489 }; 5490 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue }; 5491 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5492 5493 // Now that we have the comparison, emit a copy from the CR to a GPR. 5494 // This is flagged to the above dot comparison. 5495 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 5496 DAG.getRegister(PPC::CR6, MVT::i32), 5497 CompNode.getValue(1)); 5498 5499 // Unpack the result based on how the target uses it. 5500 unsigned BitNo; // Bit # of CR6. 5501 bool InvertBit; // Invert result? 5502 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 5503 default: // Can't happen, don't crash on invalid number though. 5504 case 0: // Return the value of the EQ bit of CR6. 5505 BitNo = 0; InvertBit = false; 5506 break; 5507 case 1: // Return the inverted value of the EQ bit of CR6. 5508 BitNo = 0; InvertBit = true; 5509 break; 5510 case 2: // Return the value of the LT bit of CR6. 5511 BitNo = 2; InvertBit = false; 5512 break; 5513 case 3: // Return the inverted value of the LT bit of CR6. 5514 BitNo = 2; InvertBit = true; 5515 break; 5516 } 5517 5518 // Shift the bit into the low position. 5519 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 5520 DAG.getConstant(8-(3-BitNo), MVT::i32)); 5521 // Isolate the bit. 5522 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 5523 DAG.getConstant(1, MVT::i32)); 5524 5525 // If we are supposed to, toggle the bit. 5526 if (InvertBit) 5527 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 5528 DAG.getConstant(1, MVT::i32)); 5529 return Flags; 5530} 5531 5532SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 5533 SelectionDAG &DAG) const { 5534 DebugLoc dl = Op.getDebugLoc(); 5535 // Create a stack slot that is 16-byte aligned. 5536 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 5537 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 5538 EVT PtrVT = getPointerTy(); 5539 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 5540 5541 // Store the input value into Value#0 of the stack slot. 5542 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 5543 Op.getOperand(0), FIdx, MachinePointerInfo(), 5544 false, false, 0); 5545 // Load it out. 5546 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), 5547 false, false, false, 0); 5548} 5549 5550SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 5551 DebugLoc dl = Op.getDebugLoc(); 5552 if (Op.getValueType() == MVT::v4i32) { 5553 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5554 5555 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 5556 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 5557 5558 SDValue RHSSwap = // = vrlw RHS, 16 5559 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 5560 5561 // Shrinkify inputs to v8i16. 5562 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); 5563 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); 5564 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); 5565 5566 // Low parts multiplied together, generating 32-bit results (we ignore the 5567 // top parts). 5568 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 5569 LHS, RHS, DAG, dl, MVT::v4i32); 5570 5571 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 5572 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 5573 // Shift the high parts up 16 bits. 5574 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 5575 Neg16, DAG, dl); 5576 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 5577 } else if (Op.getValueType() == MVT::v8i16) { 5578 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5579 5580 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 5581 5582 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 5583 LHS, RHS, Zero, DAG, dl); 5584 } else if (Op.getValueType() == MVT::v16i8) { 5585 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 5586 5587 // Multiply the even 8-bit parts, producing 16-bit sums. 5588 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 5589 LHS, RHS, DAG, dl, MVT::v8i16); 5590 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); 5591 5592 // Multiply the odd 8-bit parts, producing 16-bit sums. 5593 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 5594 LHS, RHS, DAG, dl, MVT::v8i16); 5595 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); 5596 5597 // Merge the results together. 5598 int Ops[16]; 5599 for (unsigned i = 0; i != 8; ++i) { 5600 Ops[i*2 ] = 2*i+1; 5601 Ops[i*2+1] = 2*i+1+16; 5602 } 5603 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 5604 } else { 5605 llvm_unreachable("Unknown mul to lower!"); 5606 } 5607} 5608 5609/// LowerOperation - Provide custom lowering hooks for some operations. 5610/// 5611SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5612 switch (Op.getOpcode()) { 5613 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 5614 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 5615 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 5616 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 5617 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 5618 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 5619 case ISD::SETCC: return LowerSETCC(Op, DAG); 5620 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 5621 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 5622 case ISD::VASTART: 5623 return LowerVASTART(Op, DAG, PPCSubTarget); 5624 5625 case ISD::VAARG: 5626 return LowerVAARG(Op, DAG, PPCSubTarget); 5627 5628 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 5629 case ISD::DYNAMIC_STACKALLOC: 5630 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 5631 5632 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG); 5633 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG); 5634 5635 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 5636 case ISD::FP_TO_UINT: 5637 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 5638 Op.getDebugLoc()); 5639 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 5640 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 5641 5642 // Lower 64-bit shifts. 5643 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 5644 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 5645 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 5646 5647 // Vector-related lowering. 5648 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 5649 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 5650 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 5651 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 5652 case ISD::MUL: return LowerMUL(Op, DAG); 5653 5654 // Frame & Return address. 5655 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 5656 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 5657 } 5658} 5659 5660void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 5661 SmallVectorImpl<SDValue>&Results, 5662 SelectionDAG &DAG) const { 5663 const TargetMachine &TM = getTargetMachine(); 5664 DebugLoc dl = N->getDebugLoc(); 5665 switch (N->getOpcode()) { 5666 default: 5667 llvm_unreachable("Do not know how to custom type legalize this operation!"); 5668 case ISD::VAARG: { 5669 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 5670 || TM.getSubtarget<PPCSubtarget>().isPPC64()) 5671 return; 5672 5673 EVT VT = N->getValueType(0); 5674 5675 if (VT == MVT::i64) { 5676 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget); 5677 5678 Results.push_back(NewNode); 5679 Results.push_back(NewNode.getValue(1)); 5680 } 5681 return; 5682 } 5683 case ISD::FP_ROUND_INREG: { 5684 assert(N->getValueType(0) == MVT::ppcf128); 5685 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 5686 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 5687 MVT::f64, N->getOperand(0), 5688 DAG.getIntPtrConstant(0)); 5689 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 5690 MVT::f64, N->getOperand(0), 5691 DAG.getIntPtrConstant(1)); 5692 5693 // Add the two halves of the long double in round-to-zero mode. 5694 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi); 5695 5696 // We know the low half is about to be thrown away, so just use something 5697 // convenient. 5698 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 5699 FPreg, FPreg)); 5700 return; 5701 } 5702 case ISD::FP_TO_SINT: 5703 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 5704 return; 5705 } 5706} 5707 5708 5709//===----------------------------------------------------------------------===// 5710// Other Lowering Code 5711//===----------------------------------------------------------------------===// 5712 5713MachineBasicBlock * 5714PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5715 bool is64bit, unsigned BinOpcode) const { 5716 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5717 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5718 5719 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5720 MachineFunction *F = BB->getParent(); 5721 MachineFunction::iterator It = BB; 5722 ++It; 5723 5724 unsigned dest = MI->getOperand(0).getReg(); 5725 unsigned ptrA = MI->getOperand(1).getReg(); 5726 unsigned ptrB = MI->getOperand(2).getReg(); 5727 unsigned incr = MI->getOperand(3).getReg(); 5728 DebugLoc dl = MI->getDebugLoc(); 5729 5730 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 5731 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5732 F->insert(It, loopMBB); 5733 F->insert(It, exitMBB); 5734 exitMBB->splice(exitMBB->begin(), BB, 5735 llvm::next(MachineBasicBlock::iterator(MI)), 5736 BB->end()); 5737 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5738 5739 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5740 unsigned TmpReg = (!BinOpcode) ? incr : 5741 RegInfo.createVirtualRegister( 5742 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5743 (const TargetRegisterClass *) &PPC::GPRCRegClass); 5744 5745 // thisMBB: 5746 // ... 5747 // fallthrough --> loopMBB 5748 BB->addSuccessor(loopMBB); 5749 5750 // loopMBB: 5751 // l[wd]arx dest, ptr 5752 // add r0, dest, incr 5753 // st[wd]cx. r0, ptr 5754 // bne- loopMBB 5755 // fallthrough --> exitMBB 5756 BB = loopMBB; 5757 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 5758 .addReg(ptrA).addReg(ptrB); 5759 if (BinOpcode) 5760 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 5761 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5762 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 5763 BuildMI(BB, dl, TII->get(PPC::BCC)) 5764 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5765 BB->addSuccessor(loopMBB); 5766 BB->addSuccessor(exitMBB); 5767 5768 // exitMBB: 5769 // ... 5770 BB = exitMBB; 5771 return BB; 5772} 5773 5774MachineBasicBlock * 5775PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 5776 MachineBasicBlock *BB, 5777 bool is8bit, // operation 5778 unsigned BinOpcode) const { 5779 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5780 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5781 // In 64 bit mode we have to use 64 bits for addresses, even though the 5782 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 5783 // registers without caring whether they're 32 or 64, but here we're 5784 // doing actual arithmetic on the addresses. 5785 bool is64bit = PPCSubTarget.isPPC64(); 5786 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; 5787 5788 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5789 MachineFunction *F = BB->getParent(); 5790 MachineFunction::iterator It = BB; 5791 ++It; 5792 5793 unsigned dest = MI->getOperand(0).getReg(); 5794 unsigned ptrA = MI->getOperand(1).getReg(); 5795 unsigned ptrB = MI->getOperand(2).getReg(); 5796 unsigned incr = MI->getOperand(3).getReg(); 5797 DebugLoc dl = MI->getDebugLoc(); 5798 5799 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 5800 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5801 F->insert(It, loopMBB); 5802 F->insert(It, exitMBB); 5803 exitMBB->splice(exitMBB->begin(), BB, 5804 llvm::next(MachineBasicBlock::iterator(MI)), 5805 BB->end()); 5806 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5807 5808 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5809 const TargetRegisterClass *RC = 5810 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5811 (const TargetRegisterClass *) &PPC::GPRCRegClass; 5812 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 5813 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 5814 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 5815 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 5816 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 5817 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 5818 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 5819 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 5820 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 5821 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 5822 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 5823 unsigned Ptr1Reg; 5824 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 5825 5826 // thisMBB: 5827 // ... 5828 // fallthrough --> loopMBB 5829 BB->addSuccessor(loopMBB); 5830 5831 // The 4-byte load must be aligned, while a char or short may be 5832 // anywhere in the word. Hence all this nasty bookkeeping code. 5833 // add ptr1, ptrA, ptrB [copy if ptrA==0] 5834 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 5835 // xori shift, shift1, 24 [16] 5836 // rlwinm ptr, ptr1, 0, 0, 29 5837 // slw incr2, incr, shift 5838 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 5839 // slw mask, mask2, shift 5840 // loopMBB: 5841 // lwarx tmpDest, ptr 5842 // add tmp, tmpDest, incr2 5843 // andc tmp2, tmpDest, mask 5844 // and tmp3, tmp, mask 5845 // or tmp4, tmp3, tmp2 5846 // stwcx. tmp4, ptr 5847 // bne- loopMBB 5848 // fallthrough --> exitMBB 5849 // srw dest, tmpDest, shift 5850 if (ptrA != ZeroReg) { 5851 Ptr1Reg = RegInfo.createVirtualRegister(RC); 5852 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 5853 .addReg(ptrA).addReg(ptrB); 5854 } else { 5855 Ptr1Reg = ptrB; 5856 } 5857 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 5858 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 5859 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 5860 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 5861 if (is64bit) 5862 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 5863 .addReg(Ptr1Reg).addImm(0).addImm(61); 5864 else 5865 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 5866 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 5867 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 5868 .addReg(incr).addReg(ShiftReg); 5869 if (is8bit) 5870 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 5871 else { 5872 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 5873 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 5874 } 5875 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5876 .addReg(Mask2Reg).addReg(ShiftReg); 5877 5878 BB = loopMBB; 5879 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5880 .addReg(ZeroReg).addReg(PtrReg); 5881 if (BinOpcode) 5882 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 5883 .addReg(Incr2Reg).addReg(TmpDestReg); 5884 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 5885 .addReg(TmpDestReg).addReg(MaskReg); 5886 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 5887 .addReg(TmpReg).addReg(MaskReg); 5888 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 5889 .addReg(Tmp3Reg).addReg(Tmp2Reg); 5890 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5891 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg); 5892 BuildMI(BB, dl, TII->get(PPC::BCC)) 5893 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 5894 BB->addSuccessor(loopMBB); 5895 BB->addSuccessor(exitMBB); 5896 5897 // exitMBB: 5898 // ... 5899 BB = exitMBB; 5900 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg) 5901 .addReg(ShiftReg); 5902 return BB; 5903} 5904 5905llvm::MachineBasicBlock* 5906PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI, 5907 MachineBasicBlock *MBB) const { 5908 DebugLoc DL = MI->getDebugLoc(); 5909 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5910 5911 MachineFunction *MF = MBB->getParent(); 5912 MachineRegisterInfo &MRI = MF->getRegInfo(); 5913 5914 const BasicBlock *BB = MBB->getBasicBlock(); 5915 MachineFunction::iterator I = MBB; 5916 ++I; 5917 5918 // Memory Reference 5919 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 5920 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 5921 5922 unsigned DstReg = MI->getOperand(0).getReg(); 5923 const TargetRegisterClass *RC = MRI.getRegClass(DstReg); 5924 assert(RC->hasType(MVT::i32) && "Invalid destination!"); 5925 unsigned mainDstReg = MRI.createVirtualRegister(RC); 5926 unsigned restoreDstReg = MRI.createVirtualRegister(RC); 5927 5928 MVT PVT = getPointerTy(); 5929 assert((PVT == MVT::i64 || PVT == MVT::i32) && 5930 "Invalid Pointer Size!"); 5931 // For v = setjmp(buf), we generate 5932 // 5933 // thisMBB: 5934 // SjLjSetup mainMBB 5935 // bl mainMBB 5936 // v_restore = 1 5937 // b sinkMBB 5938 // 5939 // mainMBB: 5940 // buf[LabelOffset] = LR 5941 // v_main = 0 5942 // 5943 // sinkMBB: 5944 // v = phi(main, restore) 5945 // 5946 5947 MachineBasicBlock *thisMBB = MBB; 5948 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB); 5949 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB); 5950 MF->insert(I, mainMBB); 5951 MF->insert(I, sinkMBB); 5952 5953 MachineInstrBuilder MIB; 5954 5955 // Transfer the remainder of BB and its successor edges to sinkMBB. 5956 sinkMBB->splice(sinkMBB->begin(), MBB, 5957 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end()); 5958 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); 5959 5960 // Note that the structure of the jmp_buf used here is not compatible 5961 // with that used by libc, and is not designed to be. Specifically, it 5962 // stores only those 'reserved' registers that LLVM does not otherwise 5963 // understand how to spill. Also, by convention, by the time this 5964 // intrinsic is called, Clang has already stored the frame address in the 5965 // first slot of the buffer and stack address in the third. Following the 5966 // X86 target code, we'll store the jump address in the second slot. We also 5967 // need to save the TOC pointer (R2) to handle jumps between shared 5968 // libraries, and that will be stored in the fourth slot. The thread 5969 // identifier (R13) is not affected. 5970 5971 // thisMBB: 5972 const int64_t LabelOffset = 1 * PVT.getStoreSize(); 5973 const int64_t TOCOffset = 3 * PVT.getStoreSize(); 5974 5975 // Prepare IP either in reg. 5976 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); 5977 unsigned LabelReg = MRI.createVirtualRegister(PtrRC); 5978 unsigned BufReg = MI->getOperand(1).getReg(); 5979 5980 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) { 5981 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD)) 5982 .addReg(PPC::X2) 5983 .addImm(TOCOffset / 4) 5984 .addReg(BufReg); 5985 5986 MIB.setMemRefs(MMOBegin, MMOEnd); 5987 } 5988 5989 // Setup 5990 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCL)).addMBB(mainMBB); 5991 MIB.addRegMask(PPCRegInfo->getNoPreservedMask()); 5992 5993 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1); 5994 5995 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup)) 5996 .addMBB(mainMBB); 5997 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB); 5998 5999 thisMBB->addSuccessor(mainMBB, /* weight */ 0); 6000 thisMBB->addSuccessor(sinkMBB, /* weight */ 1); 6001 6002 // mainMBB: 6003 // mainDstReg = 0 6004 MIB = BuildMI(mainMBB, DL, 6005 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); 6006 6007 // Store IP 6008 if (PPCSubTarget.isPPC64()) { 6009 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD)) 6010 .addReg(LabelReg) 6011 .addImm(LabelOffset / 4) 6012 .addReg(BufReg); 6013 } else { 6014 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW)) 6015 .addReg(LabelReg) 6016 .addImm(LabelOffset) 6017 .addReg(BufReg); 6018 } 6019 6020 MIB.setMemRefs(MMOBegin, MMOEnd); 6021 6022 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0); 6023 mainMBB->addSuccessor(sinkMBB); 6024 6025 // sinkMBB: 6026 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 6027 TII->get(PPC::PHI), DstReg) 6028 .addReg(mainDstReg).addMBB(mainMBB) 6029 .addReg(restoreDstReg).addMBB(thisMBB); 6030 6031 MI->eraseFromParent(); 6032 return sinkMBB; 6033} 6034 6035MachineBasicBlock * 6036PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI, 6037 MachineBasicBlock *MBB) const { 6038 DebugLoc DL = MI->getDebugLoc(); 6039 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6040 6041 MachineFunction *MF = MBB->getParent(); 6042 MachineRegisterInfo &MRI = MF->getRegInfo(); 6043 6044 // Memory Reference 6045 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 6046 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 6047 6048 MVT PVT = getPointerTy(); 6049 assert((PVT == MVT::i64 || PVT == MVT::i32) && 6050 "Invalid Pointer Size!"); 6051 6052 const TargetRegisterClass *RC = 6053 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; 6054 unsigned Tmp = MRI.createVirtualRegister(RC); 6055 // Since FP is only updated here but NOT referenced, it's treated as GPR. 6056 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31; 6057 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1; 6058 6059 MachineInstrBuilder MIB; 6060 6061 const int64_t LabelOffset = 1 * PVT.getStoreSize(); 6062 const int64_t SPOffset = 2 * PVT.getStoreSize(); 6063 const int64_t TOCOffset = 3 * PVT.getStoreSize(); 6064 6065 unsigned BufReg = MI->getOperand(0).getReg(); 6066 6067 // Reload FP (the jumped-to function may not have had a 6068 // frame pointer, and if so, then its r31 will be restored 6069 // as necessary). 6070 if (PVT == MVT::i64) { 6071 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP) 6072 .addImm(0) 6073 .addReg(BufReg); 6074 } else { 6075 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP) 6076 .addImm(0) 6077 .addReg(BufReg); 6078 } 6079 MIB.setMemRefs(MMOBegin, MMOEnd); 6080 6081 // Reload IP 6082 if (PVT == MVT::i64) { 6083 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp) 6084 .addImm(LabelOffset / 4) 6085 .addReg(BufReg); 6086 } else { 6087 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp) 6088 .addImm(LabelOffset) 6089 .addReg(BufReg); 6090 } 6091 MIB.setMemRefs(MMOBegin, MMOEnd); 6092 6093 // Reload SP 6094 if (PVT == MVT::i64) { 6095 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP) 6096 .addImm(SPOffset / 4) 6097 .addReg(BufReg); 6098 } else { 6099 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP) 6100 .addImm(SPOffset) 6101 .addReg(BufReg); 6102 } 6103 MIB.setMemRefs(MMOBegin, MMOEnd); 6104 6105 // FIXME: When we also support base pointers, that register must also be 6106 // restored here. 6107 6108 // Reload TOC 6109 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) { 6110 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2) 6111 .addImm(TOCOffset / 4) 6112 .addReg(BufReg); 6113 6114 MIB.setMemRefs(MMOBegin, MMOEnd); 6115 } 6116 6117 // Jump 6118 BuildMI(*MBB, MI, DL, 6119 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp); 6120 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR)); 6121 6122 MI->eraseFromParent(); 6123 return MBB; 6124} 6125 6126MachineBasicBlock * 6127PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 6128 MachineBasicBlock *BB) const { 6129 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 || 6130 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) { 6131 return emitEHSjLjSetJmp(MI, BB); 6132 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 || 6133 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) { 6134 return emitEHSjLjLongJmp(MI, BB); 6135 } 6136 6137 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6138 6139 // To "insert" these instructions we actually have to insert their 6140 // control-flow patterns. 6141 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6142 MachineFunction::iterator It = BB; 6143 ++It; 6144 6145 MachineFunction *F = BB->getParent(); 6146 6147 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 || 6148 MI->getOpcode() == PPC::SELECT_CC_I8)) { 6149 unsigned OpCode = MI->getOpcode() == PPC::SELECT_CC_I8 ? 6150 PPC::ISEL8 : PPC::ISEL; 6151 unsigned SelectPred = MI->getOperand(4).getImm(); 6152 DebugLoc dl = MI->getDebugLoc(); 6153 6154 unsigned SubIdx; 6155 bool SwapOps; 6156 switch (SelectPred) { 6157 default: llvm_unreachable("invalid predicate for isel"); 6158 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break; 6159 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break; 6160 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break; 6161 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break; 6162 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break; 6163 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break; 6164 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break; 6165 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break; 6166 } 6167 6168 BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg()) 6169 .addReg(MI->getOperand(SwapOps? 3 : 2).getReg()) 6170 .addReg(MI->getOperand(SwapOps? 2 : 3).getReg()) 6171 .addReg(MI->getOperand(1).getReg(), 0, SubIdx); 6172 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 || 6173 MI->getOpcode() == PPC::SELECT_CC_I8 || 6174 MI->getOpcode() == PPC::SELECT_CC_F4 || 6175 MI->getOpcode() == PPC::SELECT_CC_F8 || 6176 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 6177 6178 6179 // The incoming instruction knows the destination vreg to set, the 6180 // condition code register to branch on, the true/false values to 6181 // select between, and a branch opcode to use. 6182 6183 // thisMBB: 6184 // ... 6185 // TrueVal = ... 6186 // cmpTY ccX, r1, r2 6187 // bCC copy1MBB 6188 // fallthrough --> copy0MBB 6189 MachineBasicBlock *thisMBB = BB; 6190 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 6191 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 6192 unsigned SelectPred = MI->getOperand(4).getImm(); 6193 DebugLoc dl = MI->getDebugLoc(); 6194 F->insert(It, copy0MBB); 6195 F->insert(It, sinkMBB); 6196 6197 // Transfer the remainder of BB and its successor edges to sinkMBB. 6198 sinkMBB->splice(sinkMBB->begin(), BB, 6199 llvm::next(MachineBasicBlock::iterator(MI)), 6200 BB->end()); 6201 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 6202 6203 // Next, add the true and fallthrough blocks as its successors. 6204 BB->addSuccessor(copy0MBB); 6205 BB->addSuccessor(sinkMBB); 6206 6207 BuildMI(BB, dl, TII->get(PPC::BCC)) 6208 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 6209 6210 // copy0MBB: 6211 // %FalseValue = ... 6212 // # fallthrough to sinkMBB 6213 BB = copy0MBB; 6214 6215 // Update machine-CFG edges 6216 BB->addSuccessor(sinkMBB); 6217 6218 // sinkMBB: 6219 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 6220 // ... 6221 BB = sinkMBB; 6222 BuildMI(*BB, BB->begin(), dl, 6223 TII->get(PPC::PHI), MI->getOperand(0).getReg()) 6224 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 6225 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 6226 } 6227 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 6228 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 6229 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 6230 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 6231 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 6232 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 6233 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 6234 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 6235 6236 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 6237 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 6238 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 6239 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 6240 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 6241 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 6242 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 6243 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 6244 6245 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 6246 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 6247 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 6248 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 6249 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 6250 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 6251 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 6252 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 6253 6254 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 6255 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 6256 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 6257 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 6258 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 6259 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 6260 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 6261 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 6262 6263 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 6264 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 6265 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 6266 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 6267 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 6268 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 6269 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 6270 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 6271 6272 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 6273 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 6274 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 6275 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 6276 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 6277 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 6278 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 6279 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 6280 6281 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 6282 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 6283 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 6284 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 6285 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 6286 BB = EmitAtomicBinary(MI, BB, false, 0); 6287 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 6288 BB = EmitAtomicBinary(MI, BB, true, 0); 6289 6290 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 6291 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 6292 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 6293 6294 unsigned dest = MI->getOperand(0).getReg(); 6295 unsigned ptrA = MI->getOperand(1).getReg(); 6296 unsigned ptrB = MI->getOperand(2).getReg(); 6297 unsigned oldval = MI->getOperand(3).getReg(); 6298 unsigned newval = MI->getOperand(4).getReg(); 6299 DebugLoc dl = MI->getDebugLoc(); 6300 6301 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 6302 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 6303 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6304 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6305 F->insert(It, loop1MBB); 6306 F->insert(It, loop2MBB); 6307 F->insert(It, midMBB); 6308 F->insert(It, exitMBB); 6309 exitMBB->splice(exitMBB->begin(), BB, 6310 llvm::next(MachineBasicBlock::iterator(MI)), 6311 BB->end()); 6312 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6313 6314 // thisMBB: 6315 // ... 6316 // fallthrough --> loopMBB 6317 BB->addSuccessor(loop1MBB); 6318 6319 // loop1MBB: 6320 // l[wd]arx dest, ptr 6321 // cmp[wd] dest, oldval 6322 // bne- midMBB 6323 // loop2MBB: 6324 // st[wd]cx. newval, ptr 6325 // bne- loopMBB 6326 // b exitBB 6327 // midMBB: 6328 // st[wd]cx. dest, ptr 6329 // exitBB: 6330 BB = loop1MBB; 6331 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 6332 .addReg(ptrA).addReg(ptrB); 6333 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 6334 .addReg(oldval).addReg(dest); 6335 BuildMI(BB, dl, TII->get(PPC::BCC)) 6336 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 6337 BB->addSuccessor(loop2MBB); 6338 BB->addSuccessor(midMBB); 6339 6340 BB = loop2MBB; 6341 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 6342 .addReg(newval).addReg(ptrA).addReg(ptrB); 6343 BuildMI(BB, dl, TII->get(PPC::BCC)) 6344 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 6345 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6346 BB->addSuccessor(loop1MBB); 6347 BB->addSuccessor(exitMBB); 6348 6349 BB = midMBB; 6350 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 6351 .addReg(dest).addReg(ptrA).addReg(ptrB); 6352 BB->addSuccessor(exitMBB); 6353 6354 // exitMBB: 6355 // ... 6356 BB = exitMBB; 6357 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 6358 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 6359 // We must use 64-bit registers for addresses when targeting 64-bit, 6360 // since we're actually doing arithmetic on them. Other registers 6361 // can be 32-bit. 6362 bool is64bit = PPCSubTarget.isPPC64(); 6363 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 6364 6365 unsigned dest = MI->getOperand(0).getReg(); 6366 unsigned ptrA = MI->getOperand(1).getReg(); 6367 unsigned ptrB = MI->getOperand(2).getReg(); 6368 unsigned oldval = MI->getOperand(3).getReg(); 6369 unsigned newval = MI->getOperand(4).getReg(); 6370 DebugLoc dl = MI->getDebugLoc(); 6371 6372 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 6373 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 6374 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6375 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6376 F->insert(It, loop1MBB); 6377 F->insert(It, loop2MBB); 6378 F->insert(It, midMBB); 6379 F->insert(It, exitMBB); 6380 exitMBB->splice(exitMBB->begin(), BB, 6381 llvm::next(MachineBasicBlock::iterator(MI)), 6382 BB->end()); 6383 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6384 6385 MachineRegisterInfo &RegInfo = F->getRegInfo(); 6386 const TargetRegisterClass *RC = 6387 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 6388 (const TargetRegisterClass *) &PPC::GPRCRegClass; 6389 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 6390 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 6391 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 6392 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 6393 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 6394 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 6395 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 6396 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 6397 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 6398 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 6399 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 6400 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 6401 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 6402 unsigned Ptr1Reg; 6403 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 6404 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; 6405 // thisMBB: 6406 // ... 6407 // fallthrough --> loopMBB 6408 BB->addSuccessor(loop1MBB); 6409 6410 // The 4-byte load must be aligned, while a char or short may be 6411 // anywhere in the word. Hence all this nasty bookkeeping code. 6412 // add ptr1, ptrA, ptrB [copy if ptrA==0] 6413 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 6414 // xori shift, shift1, 24 [16] 6415 // rlwinm ptr, ptr1, 0, 0, 29 6416 // slw newval2, newval, shift 6417 // slw oldval2, oldval,shift 6418 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 6419 // slw mask, mask2, shift 6420 // and newval3, newval2, mask 6421 // and oldval3, oldval2, mask 6422 // loop1MBB: 6423 // lwarx tmpDest, ptr 6424 // and tmp, tmpDest, mask 6425 // cmpw tmp, oldval3 6426 // bne- midMBB 6427 // loop2MBB: 6428 // andc tmp2, tmpDest, mask 6429 // or tmp4, tmp2, newval3 6430 // stwcx. tmp4, ptr 6431 // bne- loop1MBB 6432 // b exitBB 6433 // midMBB: 6434 // stwcx. tmpDest, ptr 6435 // exitBB: 6436 // srw dest, tmpDest, shift 6437 if (ptrA != ZeroReg) { 6438 Ptr1Reg = RegInfo.createVirtualRegister(RC); 6439 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 6440 .addReg(ptrA).addReg(ptrB); 6441 } else { 6442 Ptr1Reg = ptrB; 6443 } 6444 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 6445 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 6446 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 6447 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 6448 if (is64bit) 6449 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 6450 .addReg(Ptr1Reg).addImm(0).addImm(61); 6451 else 6452 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 6453 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 6454 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 6455 .addReg(newval).addReg(ShiftReg); 6456 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 6457 .addReg(oldval).addReg(ShiftReg); 6458 if (is8bit) 6459 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 6460 else { 6461 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 6462 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 6463 .addReg(Mask3Reg).addImm(65535); 6464 } 6465 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 6466 .addReg(Mask2Reg).addReg(ShiftReg); 6467 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 6468 .addReg(NewVal2Reg).addReg(MaskReg); 6469 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 6470 .addReg(OldVal2Reg).addReg(MaskReg); 6471 6472 BB = loop1MBB; 6473 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 6474 .addReg(ZeroReg).addReg(PtrReg); 6475 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 6476 .addReg(TmpDestReg).addReg(MaskReg); 6477 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 6478 .addReg(TmpReg).addReg(OldVal3Reg); 6479 BuildMI(BB, dl, TII->get(PPC::BCC)) 6480 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 6481 BB->addSuccessor(loop2MBB); 6482 BB->addSuccessor(midMBB); 6483 6484 BB = loop2MBB; 6485 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 6486 .addReg(TmpDestReg).addReg(MaskReg); 6487 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 6488 .addReg(Tmp2Reg).addReg(NewVal3Reg); 6489 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 6490 .addReg(ZeroReg).addReg(PtrReg); 6491 BuildMI(BB, dl, TII->get(PPC::BCC)) 6492 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 6493 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6494 BB->addSuccessor(loop1MBB); 6495 BB->addSuccessor(exitMBB); 6496 6497 BB = midMBB; 6498 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 6499 .addReg(ZeroReg).addReg(PtrReg); 6500 BB->addSuccessor(exitMBB); 6501 6502 // exitMBB: 6503 // ... 6504 BB = exitMBB; 6505 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) 6506 .addReg(ShiftReg); 6507 } else if (MI->getOpcode() == PPC::FADDrtz) { 6508 // This pseudo performs an FADD with rounding mode temporarily forced 6509 // to round-to-zero. We emit this via custom inserter since the FPSCR 6510 // is not modeled at the SelectionDAG level. 6511 unsigned Dest = MI->getOperand(0).getReg(); 6512 unsigned Src1 = MI->getOperand(1).getReg(); 6513 unsigned Src2 = MI->getOperand(2).getReg(); 6514 DebugLoc dl = MI->getDebugLoc(); 6515 6516 MachineRegisterInfo &RegInfo = F->getRegInfo(); 6517 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 6518 6519 // Save FPSCR value. 6520 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg); 6521 6522 // Set rounding mode to round-to-zero. 6523 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31); 6524 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30); 6525 6526 // Perform addition. 6527 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2); 6528 6529 // Restore FPSCR value. 6530 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg); 6531 } else if (MI->getOpcode() == PPC::FRINDrint || 6532 MI->getOpcode() == PPC::FRINSrint) { 6533 bool isf32 = MI->getOpcode() == PPC::FRINSrint; 6534 unsigned Dest = MI->getOperand(0).getReg(); 6535 unsigned Src = MI->getOperand(1).getReg(); 6536 DebugLoc dl = MI->getDebugLoc(); 6537 6538 MachineRegisterInfo &RegInfo = F->getRegInfo(); 6539 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass); 6540 6541 // Perform the rounding. 6542 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FRINS : PPC::FRIND), Dest) 6543 .addReg(Src); 6544 6545 // Compare the results. 6546 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FCMPUS : PPC::FCMPUD), CRReg) 6547 .addReg(Dest).addReg(Src); 6548 6549 // If the results were not equal, then set the FPSCR XX bit. 6550 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 6551 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 6552 F->insert(It, midMBB); 6553 F->insert(It, exitMBB); 6554 exitMBB->splice(exitMBB->begin(), BB, 6555 llvm::next(MachineBasicBlock::iterator(MI)), 6556 BB->end()); 6557 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 6558 6559 BuildMI(*BB, MI, dl, TII->get(PPC::BCC)) 6560 .addImm(PPC::PRED_EQ).addReg(CRReg).addMBB(exitMBB); 6561 6562 BB->addSuccessor(midMBB); 6563 BB->addSuccessor(exitMBB); 6564 6565 BB = midMBB; 6566 6567 // Set the FPSCR XX bit (FE_INEXACT). Note that we cannot just set 6568 // the FI bit here because that will not automatically set XX also, 6569 // and XX is what libm interprets as the FE_INEXACT flag. 6570 BuildMI(BB, dl, TII->get(PPC::MTFSB1)).addImm(/* 38 - 32 = */ 6); 6571 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 6572 6573 BB->addSuccessor(exitMBB); 6574 6575 BB = exitMBB; 6576 } else { 6577 llvm_unreachable("Unexpected instr type to insert"); 6578 } 6579 6580 MI->eraseFromParent(); // The pseudo instruction is gone now. 6581 return BB; 6582} 6583 6584//===----------------------------------------------------------------------===// 6585// Target Optimization Hooks 6586//===----------------------------------------------------------------------===// 6587 6588SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 6589 DAGCombinerInfo &DCI) const { 6590 const TargetMachine &TM = getTargetMachine(); 6591 SelectionDAG &DAG = DCI.DAG; 6592 DebugLoc dl = N->getDebugLoc(); 6593 switch (N->getOpcode()) { 6594 default: break; 6595 case PPCISD::SHL: 6596 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6597 if (C->isNullValue()) // 0 << V -> 0. 6598 return N->getOperand(0); 6599 } 6600 break; 6601 case PPCISD::SRL: 6602 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6603 if (C->isNullValue()) // 0 >>u V -> 0. 6604 return N->getOperand(0); 6605 } 6606 break; 6607 case PPCISD::SRA: 6608 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 6609 if (C->isNullValue() || // 0 >>s V -> 0. 6610 C->isAllOnesValue()) // -1 >>s V -> -1. 6611 return N->getOperand(0); 6612 } 6613 break; 6614 6615 case ISD::SINT_TO_FP: 6616 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 6617 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 6618 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 6619 // We allow the src/dst to be either f32/f64, but the intermediate 6620 // type must be i64. 6621 if (N->getOperand(0).getValueType() == MVT::i64 && 6622 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 6623 SDValue Val = N->getOperand(0).getOperand(0); 6624 if (Val.getValueType() == MVT::f32) { 6625 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 6626 DCI.AddToWorklist(Val.getNode()); 6627 } 6628 6629 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 6630 DCI.AddToWorklist(Val.getNode()); 6631 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 6632 DCI.AddToWorklist(Val.getNode()); 6633 if (N->getValueType(0) == MVT::f32) { 6634 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 6635 DAG.getIntPtrConstant(0)); 6636 DCI.AddToWorklist(Val.getNode()); 6637 } 6638 return Val; 6639 } else if (N->getOperand(0).getValueType() == MVT::i32) { 6640 // If the intermediate type is i32, we can avoid the load/store here 6641 // too. 6642 } 6643 } 6644 } 6645 break; 6646 case ISD::STORE: 6647 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 6648 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 6649 !cast<StoreSDNode>(N)->isTruncatingStore() && 6650 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 6651 N->getOperand(1).getValueType() == MVT::i32 && 6652 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 6653 SDValue Val = N->getOperand(1).getOperand(0); 6654 if (Val.getValueType() == MVT::f32) { 6655 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 6656 DCI.AddToWorklist(Val.getNode()); 6657 } 6658 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 6659 DCI.AddToWorklist(Val.getNode()); 6660 6661 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 6662 N->getOperand(2), N->getOperand(3)); 6663 DCI.AddToWorklist(Val.getNode()); 6664 return Val; 6665 } 6666 6667 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 6668 if (cast<StoreSDNode>(N)->isUnindexed() && 6669 N->getOperand(1).getOpcode() == ISD::BSWAP && 6670 N->getOperand(1).getNode()->hasOneUse() && 6671 (N->getOperand(1).getValueType() == MVT::i32 || 6672 N->getOperand(1).getValueType() == MVT::i16 || 6673 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() && 6674 TM.getSubtarget<PPCSubtarget>().isPPC64() && 6675 N->getOperand(1).getValueType() == MVT::i64))) { 6676 SDValue BSwapOp = N->getOperand(1).getOperand(0); 6677 // Do an any-extend to 32-bits if this is a half-word input. 6678 if (BSwapOp.getValueType() == MVT::i16) 6679 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 6680 6681 SDValue Ops[] = { 6682 N->getOperand(0), BSwapOp, N->getOperand(2), 6683 DAG.getValueType(N->getOperand(1).getValueType()) 6684 }; 6685 return 6686 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 6687 Ops, array_lengthof(Ops), 6688 cast<StoreSDNode>(N)->getMemoryVT(), 6689 cast<StoreSDNode>(N)->getMemOperand()); 6690 } 6691 break; 6692 case ISD::BSWAP: 6693 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 6694 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 6695 N->getOperand(0).hasOneUse() && 6696 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 || 6697 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() && 6698 TM.getSubtarget<PPCSubtarget>().isPPC64() && 6699 N->getValueType(0) == MVT::i64))) { 6700 SDValue Load = N->getOperand(0); 6701 LoadSDNode *LD = cast<LoadSDNode>(Load); 6702 // Create the byte-swapping load. 6703 SDValue Ops[] = { 6704 LD->getChain(), // Chain 6705 LD->getBasePtr(), // Ptr 6706 DAG.getValueType(N->getValueType(0)) // VT 6707 }; 6708 SDValue BSLoad = 6709 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 6710 DAG.getVTList(N->getValueType(0) == MVT::i64 ? 6711 MVT::i64 : MVT::i32, MVT::Other), 6712 Ops, 3, LD->getMemoryVT(), LD->getMemOperand()); 6713 6714 // If this is an i16 load, insert the truncate. 6715 SDValue ResVal = BSLoad; 6716 if (N->getValueType(0) == MVT::i16) 6717 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 6718 6719 // First, combine the bswap away. This makes the value produced by the 6720 // load dead. 6721 DCI.CombineTo(N, ResVal); 6722 6723 // Next, combine the load away, we give it a bogus result value but a real 6724 // chain result. The result value is dead because the bswap is dead. 6725 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 6726 6727 // Return N so it doesn't get rechecked! 6728 return SDValue(N, 0); 6729 } 6730 6731 break; 6732 case PPCISD::VCMP: { 6733 // If a VCMPo node already exists with exactly the same operands as this 6734 // node, use its result instead of this node (VCMPo computes both a CR6 and 6735 // a normal output). 6736 // 6737 if (!N->getOperand(0).hasOneUse() && 6738 !N->getOperand(1).hasOneUse() && 6739 !N->getOperand(2).hasOneUse()) { 6740 6741 // Scan all of the users of the LHS, looking for VCMPo's that match. 6742 SDNode *VCMPoNode = 0; 6743 6744 SDNode *LHSN = N->getOperand(0).getNode(); 6745 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 6746 UI != E; ++UI) 6747 if (UI->getOpcode() == PPCISD::VCMPo && 6748 UI->getOperand(1) == N->getOperand(1) && 6749 UI->getOperand(2) == N->getOperand(2) && 6750 UI->getOperand(0) == N->getOperand(0)) { 6751 VCMPoNode = *UI; 6752 break; 6753 } 6754 6755 // If there is no VCMPo node, or if the flag value has a single use, don't 6756 // transform this. 6757 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 6758 break; 6759 6760 // Look at the (necessarily single) use of the flag value. If it has a 6761 // chain, this transformation is more complex. Note that multiple things 6762 // could use the value result, which we should ignore. 6763 SDNode *FlagUser = 0; 6764 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 6765 FlagUser == 0; ++UI) { 6766 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 6767 SDNode *User = *UI; 6768 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 6769 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 6770 FlagUser = User; 6771 break; 6772 } 6773 } 6774 } 6775 6776 // If the user is a MFCR instruction, we know this is safe. Otherwise we 6777 // give up for right now. 6778 if (FlagUser->getOpcode() == PPCISD::MFCR) 6779 return SDValue(VCMPoNode, 0); 6780 } 6781 break; 6782 } 6783 case ISD::BR_CC: { 6784 // If this is a branch on an altivec predicate comparison, lower this so 6785 // that we don't have to do a MFCR: instead, branch directly on CR6. This 6786 // lowering is done pre-legalize, because the legalizer lowers the predicate 6787 // compare down to code that is difficult to reassemble. 6788 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 6789 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 6790 int CompareOpc; 6791 bool isDot; 6792 6793 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 6794 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 6795 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 6796 assert(isDot && "Can't compare against a vector result!"); 6797 6798 // If this is a comparison against something other than 0/1, then we know 6799 // that the condition is never/always true. 6800 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 6801 if (Val != 0 && Val != 1) { 6802 if (CC == ISD::SETEQ) // Cond never true, remove branch. 6803 return N->getOperand(0); 6804 // Always !=, turn it into an unconditional branch. 6805 return DAG.getNode(ISD::BR, dl, MVT::Other, 6806 N->getOperand(0), N->getOperand(4)); 6807 } 6808 6809 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 6810 6811 // Create the PPCISD altivec 'dot' comparison node. 6812 SDValue Ops[] = { 6813 LHS.getOperand(2), // LHS of compare 6814 LHS.getOperand(3), // RHS of compare 6815 DAG.getConstant(CompareOpc, MVT::i32) 6816 }; 6817 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue }; 6818 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 6819 6820 // Unpack the result based on how the target uses it. 6821 PPC::Predicate CompOpc; 6822 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 6823 default: // Can't happen, don't crash on invalid number though. 6824 case 0: // Branch on the value of the EQ bit of CR6. 6825 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 6826 break; 6827 case 1: // Branch on the inverted value of the EQ bit of CR6. 6828 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 6829 break; 6830 case 2: // Branch on the value of the LT bit of CR6. 6831 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 6832 break; 6833 case 3: // Branch on the inverted value of the LT bit of CR6. 6834 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 6835 break; 6836 } 6837 6838 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 6839 DAG.getConstant(CompOpc, MVT::i32), 6840 DAG.getRegister(PPC::CR6, MVT::i32), 6841 N->getOperand(4), CompNode.getValue(1)); 6842 } 6843 break; 6844 } 6845 } 6846 6847 return SDValue(); 6848} 6849 6850//===----------------------------------------------------------------------===// 6851// Inline Assembly Support 6852//===----------------------------------------------------------------------===// 6853 6854void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 6855 APInt &KnownZero, 6856 APInt &KnownOne, 6857 const SelectionDAG &DAG, 6858 unsigned Depth) const { 6859 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 6860 switch (Op.getOpcode()) { 6861 default: break; 6862 case PPCISD::LBRX: { 6863 // lhbrx is known to have the top bits cleared out. 6864 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 6865 KnownZero = 0xFFFF0000; 6866 break; 6867 } 6868 case ISD::INTRINSIC_WO_CHAIN: { 6869 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 6870 default: break; 6871 case Intrinsic::ppc_altivec_vcmpbfp_p: 6872 case Intrinsic::ppc_altivec_vcmpeqfp_p: 6873 case Intrinsic::ppc_altivec_vcmpequb_p: 6874 case Intrinsic::ppc_altivec_vcmpequh_p: 6875 case Intrinsic::ppc_altivec_vcmpequw_p: 6876 case Intrinsic::ppc_altivec_vcmpgefp_p: 6877 case Intrinsic::ppc_altivec_vcmpgtfp_p: 6878 case Intrinsic::ppc_altivec_vcmpgtsb_p: 6879 case Intrinsic::ppc_altivec_vcmpgtsh_p: 6880 case Intrinsic::ppc_altivec_vcmpgtsw_p: 6881 case Intrinsic::ppc_altivec_vcmpgtub_p: 6882 case Intrinsic::ppc_altivec_vcmpgtuh_p: 6883 case Intrinsic::ppc_altivec_vcmpgtuw_p: 6884 KnownZero = ~1U; // All bits but the low one are known to be zero. 6885 break; 6886 } 6887 } 6888 } 6889} 6890 6891 6892/// getConstraintType - Given a constraint, return the type of 6893/// constraint it is for this target. 6894PPCTargetLowering::ConstraintType 6895PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 6896 if (Constraint.size() == 1) { 6897 switch (Constraint[0]) { 6898 default: break; 6899 case 'b': 6900 case 'r': 6901 case 'f': 6902 case 'v': 6903 case 'y': 6904 return C_RegisterClass; 6905 case 'Z': 6906 // FIXME: While Z does indicate a memory constraint, it specifically 6907 // indicates an r+r address (used in conjunction with the 'y' modifier 6908 // in the replacement string). Currently, we're forcing the base 6909 // register to be r0 in the asm printer (which is interpreted as zero) 6910 // and forming the complete address in the second register. This is 6911 // suboptimal. 6912 return C_Memory; 6913 } 6914 } 6915 return TargetLowering::getConstraintType(Constraint); 6916} 6917 6918/// Examine constraint type and operand type and determine a weight value. 6919/// This object must already have been set up with the operand type 6920/// and the current alternative constraint selected. 6921TargetLowering::ConstraintWeight 6922PPCTargetLowering::getSingleConstraintMatchWeight( 6923 AsmOperandInfo &info, const char *constraint) const { 6924 ConstraintWeight weight = CW_Invalid; 6925 Value *CallOperandVal = info.CallOperandVal; 6926 // If we don't have a value, we can't do a match, 6927 // but allow it at the lowest weight. 6928 if (CallOperandVal == NULL) 6929 return CW_Default; 6930 Type *type = CallOperandVal->getType(); 6931 // Look at the constraint type. 6932 switch (*constraint) { 6933 default: 6934 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 6935 break; 6936 case 'b': 6937 if (type->isIntegerTy()) 6938 weight = CW_Register; 6939 break; 6940 case 'f': 6941 if (type->isFloatTy()) 6942 weight = CW_Register; 6943 break; 6944 case 'd': 6945 if (type->isDoubleTy()) 6946 weight = CW_Register; 6947 break; 6948 case 'v': 6949 if (type->isVectorTy()) 6950 weight = CW_Register; 6951 break; 6952 case 'y': 6953 weight = CW_Register; 6954 break; 6955 case 'Z': 6956 weight = CW_Memory; 6957 break; 6958 } 6959 return weight; 6960} 6961 6962std::pair<unsigned, const TargetRegisterClass*> 6963PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 6964 EVT VT) const { 6965 if (Constraint.size() == 1) { 6966 // GCC RS6000 Constraint Letters 6967 switch (Constraint[0]) { 6968 case 'b': // R1-R31 6969 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 6970 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass); 6971 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass); 6972 case 'r': // R0-R31 6973 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 6974 return std::make_pair(0U, &PPC::G8RCRegClass); 6975 return std::make_pair(0U, &PPC::GPRCRegClass); 6976 case 'f': 6977 if (VT == MVT::f32 || VT == MVT::i32) 6978 return std::make_pair(0U, &PPC::F4RCRegClass); 6979 if (VT == MVT::f64 || VT == MVT::i64) 6980 return std::make_pair(0U, &PPC::F8RCRegClass); 6981 break; 6982 case 'v': 6983 return std::make_pair(0U, &PPC::VRRCRegClass); 6984 case 'y': // crrc 6985 return std::make_pair(0U, &PPC::CRRCRegClass); 6986 } 6987 } 6988 6989 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 6990} 6991 6992 6993/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 6994/// vector. If it is invalid, don't add anything to Ops. 6995void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 6996 std::string &Constraint, 6997 std::vector<SDValue>&Ops, 6998 SelectionDAG &DAG) const { 6999 SDValue Result(0,0); 7000 7001 // Only support length 1 constraints. 7002 if (Constraint.length() > 1) return; 7003 7004 char Letter = Constraint[0]; 7005 switch (Letter) { 7006 default: break; 7007 case 'I': 7008 case 'J': 7009 case 'K': 7010 case 'L': 7011 case 'M': 7012 case 'N': 7013 case 'O': 7014 case 'P': { 7015 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 7016 if (!CST) return; // Must be an immediate to match. 7017 unsigned Value = CST->getZExtValue(); 7018 switch (Letter) { 7019 default: llvm_unreachable("Unknown constraint letter!"); 7020 case 'I': // "I" is a signed 16-bit constant. 7021 if ((short)Value == (int)Value) 7022 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7023 break; 7024 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 7025 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 7026 if ((short)Value == 0) 7027 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7028 break; 7029 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 7030 if ((Value >> 16) == 0) 7031 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7032 break; 7033 case 'M': // "M" is a constant that is greater than 31. 7034 if (Value > 31) 7035 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7036 break; 7037 case 'N': // "N" is a positive constant that is an exact power of two. 7038 if ((int)Value > 0 && isPowerOf2_32(Value)) 7039 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7040 break; 7041 case 'O': // "O" is the constant zero. 7042 if (Value == 0) 7043 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7044 break; 7045 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 7046 if ((short)-Value == (int)-Value) 7047 Result = DAG.getTargetConstant(Value, Op.getValueType()); 7048 break; 7049 } 7050 break; 7051 } 7052 } 7053 7054 if (Result.getNode()) { 7055 Ops.push_back(Result); 7056 return; 7057 } 7058 7059 // Handle standard constraint letters. 7060 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 7061} 7062 7063// isLegalAddressingMode - Return true if the addressing mode represented 7064// by AM is legal for this target, for a load/store of the specified type. 7065bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 7066 Type *Ty) const { 7067 // FIXME: PPC does not allow r+i addressing modes for vectors! 7068 7069 // PPC allows a sign-extended 16-bit immediate field. 7070 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 7071 return false; 7072 7073 // No global is ever allowed as a base. 7074 if (AM.BaseGV) 7075 return false; 7076 7077 // PPC only support r+r, 7078 switch (AM.Scale) { 7079 case 0: // "r+i" or just "i", depending on HasBaseReg. 7080 break; 7081 case 1: 7082 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 7083 return false; 7084 // Otherwise we have r+r or r+i. 7085 break; 7086 case 2: 7087 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 7088 return false; 7089 // Allow 2*r as r+r. 7090 break; 7091 default: 7092 // No other scales are supported. 7093 return false; 7094 } 7095 7096 return true; 7097} 7098 7099/// isLegalAddressImmediate - Return true if the integer value can be used 7100/// as the offset of the target addressing mode for load / store of the 7101/// given type. 7102bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{ 7103 // PPC allows a sign-extended 16-bit immediate field. 7104 return (V > -(1 << 16) && V < (1 << 16)-1); 7105} 7106 7107bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const { 7108 return false; 7109} 7110 7111SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 7112 SelectionDAG &DAG) const { 7113 MachineFunction &MF = DAG.getMachineFunction(); 7114 MachineFrameInfo *MFI = MF.getFrameInfo(); 7115 MFI->setReturnAddressIsTaken(true); 7116 7117 DebugLoc dl = Op.getDebugLoc(); 7118 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7119 7120 // Make sure the function does not optimize away the store of the RA to 7121 // the stack. 7122 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 7123 FuncInfo->setLRStoreRequired(); 7124 bool isPPC64 = PPCSubTarget.isPPC64(); 7125 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 7126 7127 if (Depth > 0) { 7128 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 7129 SDValue Offset = 7130 7131 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI), 7132 isPPC64? MVT::i64 : MVT::i32); 7133 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7134 DAG.getNode(ISD::ADD, dl, getPointerTy(), 7135 FrameAddr, Offset), 7136 MachinePointerInfo(), false, false, false, 0); 7137 } 7138 7139 // Just load the return address off the stack. 7140 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 7141 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 7142 RetAddrFI, MachinePointerInfo(), false, false, false, 0); 7143} 7144 7145SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 7146 SelectionDAG &DAG) const { 7147 DebugLoc dl = Op.getDebugLoc(); 7148 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7149 7150 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 7151 bool isPPC64 = PtrVT == MVT::i64; 7152 7153 MachineFunction &MF = DAG.getMachineFunction(); 7154 MachineFrameInfo *MFI = MF.getFrameInfo(); 7155 MFI->setFrameAddressIsTaken(true); 7156 7157 // Naked functions never have a frame pointer, and so we use r1. For all 7158 // other functions, this decision must be delayed until during PEI. 7159 unsigned FrameReg; 7160 if (MF.getFunction()->getAttributes().hasAttribute( 7161 AttributeSet::FunctionIndex, Attribute::Naked)) 7162 FrameReg = isPPC64 ? PPC::X1 : PPC::R1; 7163 else 7164 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP; 7165 7166 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 7167 PtrVT); 7168 while (Depth--) 7169 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 7170 FrameAddr, MachinePointerInfo(), false, false, 7171 false, 0); 7172 return FrameAddr; 7173} 7174 7175bool 7176PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 7177 // The PowerPC target isn't yet aware of offsets. 7178 return false; 7179} 7180 7181/// getOptimalMemOpType - Returns the target specific optimal type for load 7182/// and store operations as a result of memset, memcpy, and memmove 7183/// lowering. If DstAlign is zero that means it's safe to destination 7184/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 7185/// means there isn't a need to check it against alignment requirement, 7186/// probably because the source does not need to be loaded. If 'IsMemset' is 7187/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 7188/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 7189/// source is constant so it does not need to be loaded. 7190/// It returns EVT::Other if the type should be determined using generic 7191/// target-independent logic. 7192EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 7193 unsigned DstAlign, unsigned SrcAlign, 7194 bool IsMemset, bool ZeroMemset, 7195 bool MemcpyStrSrc, 7196 MachineFunction &MF) const { 7197 if (this->PPCSubTarget.isPPC64()) { 7198 return MVT::i64; 7199 } else { 7200 return MVT::i32; 7201 } 7202} 7203 7204bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, 7205 bool *Fast) const { 7206 if (DisablePPCUnaligned) 7207 return false; 7208 7209 // PowerPC supports unaligned memory access for simple non-vector types. 7210 // Although accessing unaligned addresses is not as efficient as accessing 7211 // aligned addresses, it is generally more efficient than manual expansion, 7212 // and generally only traps for software emulation when crossing page 7213 // boundaries. 7214 7215 if (!VT.isSimple()) 7216 return false; 7217 7218 if (VT.getSimpleVT().isVector()) 7219 return false; 7220 7221 if (VT == MVT::ppcf128) 7222 return false; 7223 7224 if (Fast) 7225 *Fast = true; 7226 7227 return true; 7228} 7229 7230/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 7231/// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 7232/// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 7233/// is expanded to mul + add. 7234bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const { 7235 if (!VT.isSimple()) 7236 return false; 7237 7238 switch (VT.getSimpleVT().SimpleTy) { 7239 case MVT::f32: 7240 case MVT::f64: 7241 case MVT::v4f32: 7242 return true; 7243 default: 7244 break; 7245 } 7246 7247 return false; 7248} 7249 7250Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const { 7251 if (DisableILPPref) 7252 return TargetLowering::getSchedulingPreference(N); 7253 7254 return Sched::ILP; 7255} 7256 7257