PPCISelLowering.cpp revision 1a0248690aaa9f7baaf1247e5f65a1c0c9e3783c
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPredicates.h" 17#include "PPCTargetMachine.h" 18#include "PPCPerfectShuffle.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/Analysis/ScalarEvolutionExpressions.h" 22#include "llvm/CodeGen/CallingConvLower.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineRegisterInfo.h" 27#include "llvm/CodeGen/PseudoSourceValue.h" 28#include "llvm/CodeGen/SelectionDAG.h" 29#include "llvm/Constants.h" 30#include "llvm/Function.h" 31#include "llvm/Intrinsics.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Target/TargetOptions.h" 34#include "llvm/Support/CommandLine.h" 35using namespace llvm; 36 37static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 38cl::desc("enable preincrement load/store generation on PPC (experimental)"), 39 cl::Hidden); 40 41PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) { 43 44 setPow2DivIsCheap(); 45 46 // Use _setjmp/_longjmp instead of setjmp/longjmp. 47 setUseUnderscoreSetJmp(true); 48 setUseUnderscoreLongJmp(true); 49 50 // Set up the register classes. 51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 54 55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 56 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 57 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); 58 59 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 60 61 // PowerPC has pre-inc load and store's. 62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 72 73 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 74 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 75 76 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg) 77 setConvertAction(MVT::ppcf128, MVT::f64, Expand); 78 setConvertAction(MVT::ppcf128, MVT::f32, Expand); 79 // This is used in the ppcf128->int sequence. Note it has different semantics 80 // from FP_ROUND: that rounds to nearest, this rounds to zero. 81 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 82 83 // PowerPC has no intrinsics for these particular operations 84 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 85 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 86 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 87 88 // PowerPC has no SREM/UREM instructions 89 setOperationAction(ISD::SREM, MVT::i32, Expand); 90 setOperationAction(ISD::UREM, MVT::i32, Expand); 91 setOperationAction(ISD::SREM, MVT::i64, Expand); 92 setOperationAction(ISD::UREM, MVT::i64, Expand); 93 94 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 95 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 96 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 97 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 98 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 99 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 100 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 101 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 102 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 103 104 // We don't support sin/cos/sqrt/fmod/pow 105 setOperationAction(ISD::FSIN , MVT::f64, Expand); 106 setOperationAction(ISD::FCOS , MVT::f64, Expand); 107 setOperationAction(ISD::FREM , MVT::f64, Expand); 108 setOperationAction(ISD::FPOW , MVT::f64, Expand); 109 setOperationAction(ISD::FSIN , MVT::f32, Expand); 110 setOperationAction(ISD::FCOS , MVT::f32, Expand); 111 setOperationAction(ISD::FREM , MVT::f32, Expand); 112 setOperationAction(ISD::FPOW , MVT::f32, Expand); 113 114 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 115 116 // If we're enabling GP optimizations, use hardware square root 117 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 118 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 119 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 120 } 121 122 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 123 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 124 125 // PowerPC does not have BSWAP, CTPOP or CTTZ 126 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 127 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 128 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 129 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 130 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 131 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 132 133 // PowerPC does not have ROTR 134 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 135 136 // PowerPC does not have Select 137 setOperationAction(ISD::SELECT, MVT::i32, Expand); 138 setOperationAction(ISD::SELECT, MVT::i64, Expand); 139 setOperationAction(ISD::SELECT, MVT::f32, Expand); 140 setOperationAction(ISD::SELECT, MVT::f64, Expand); 141 142 // PowerPC wants to turn select_cc of FP into fsel when possible. 143 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 144 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 145 146 // PowerPC wants to optimize integer setcc a bit 147 setOperationAction(ISD::SETCC, MVT::i32, Custom); 148 149 // PowerPC does not have BRCOND which requires SetCC 150 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 151 152 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 153 154 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 155 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 156 157 // PowerPC does not have [U|S]INT_TO_FP 158 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 159 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 160 161 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 162 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 163 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 164 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 165 166 // We cannot sextinreg(i1). Expand to shifts. 167 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 168 169 // Support label based line numbers. 170 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 171 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 172 173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 174 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 175 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 176 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 177 178 179 // We want to legalize GlobalAddress and ConstantPool nodes into the 180 // appropriate instructions to materialize the address. 181 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 182 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 183 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 184 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 185 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 186 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 187 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 188 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 189 190 // RET must be custom lowered, to meet ABI requirements 191 setOperationAction(ISD::RET , MVT::Other, Custom); 192 193 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 194 setOperationAction(ISD::VASTART , MVT::Other, Custom); 195 196 // VAARG is custom lowered with ELF 32 ABI 197 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI()) 198 setOperationAction(ISD::VAARG, MVT::Other, Custom); 199 else 200 setOperationAction(ISD::VAARG, MVT::Other, Expand); 201 202 // Use the default implementation. 203 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 204 setOperationAction(ISD::VAEND , MVT::Other, Expand); 205 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 206 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 208 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 209 210 // We want to custom lower some of our intrinsics. 211 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 212 213 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 214 // They also have instructions for converting between i64 and fp. 215 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 216 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 217 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 218 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 219 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 220 221 // FIXME: disable this lowered code. This generates 64-bit register values, 222 // and we don't model the fact that the top part is clobbered by calls. We 223 // need to flag these together so that the value isn't live across a call. 224 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 225 226 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 227 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 228 } else { 229 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 230 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 231 } 232 233 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 234 // 64-bit PowerPC implementations can support i64 types directly 235 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 236 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 237 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 238 } else { 239 // 32-bit PowerPC wants to expand i64 shifts itself. 240 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 241 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 242 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 243 } 244 245 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 246 // First set operation action for all vector types to expand. Then we 247 // will selectively turn on ones that can be effectively codegen'd. 248 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 249 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 250 // add/sub are legal for all supported vector VT's. 251 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); 252 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); 253 254 // We promote all shuffles to v16i8. 255 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote); 256 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8); 257 258 // We promote all non-typed operations to v4i32. 259 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote); 260 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32); 261 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote); 262 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32); 263 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote); 264 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32); 265 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote); 266 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32); 267 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote); 268 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32); 269 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote); 270 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32); 271 272 // No other operations are legal. 273 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 274 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand); 275 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand); 276 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand); 277 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand); 278 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand); 279 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand); 280 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 281 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 282 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 283 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand); 284 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand); 285 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand); 286 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand); 287 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand); 288 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand); 289 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand); 290 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand); 291 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand); 292 } 293 294 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 295 // with merges, splats, etc. 296 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 297 298 setOperationAction(ISD::AND , MVT::v4i32, Legal); 299 setOperationAction(ISD::OR , MVT::v4i32, Legal); 300 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 301 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 302 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 303 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 304 305 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 306 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 307 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 308 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 309 310 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 311 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 312 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 313 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 314 315 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 316 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 317 318 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 319 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 320 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 321 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 322 } 323 324 setSetCCResultType(MVT::i32); 325 setShiftAmountType(MVT::i32); 326 setSetCCResultContents(ZeroOrOneSetCCResult); 327 328 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 329 setStackPointerRegisterToSaveRestore(PPC::X1); 330 setExceptionPointerRegister(PPC::X3); 331 setExceptionSelectorRegister(PPC::X4); 332 } else { 333 setStackPointerRegisterToSaveRestore(PPC::R1); 334 setExceptionPointerRegister(PPC::R3); 335 setExceptionSelectorRegister(PPC::R4); 336 } 337 338 // We have target-specific dag combine patterns for the following nodes: 339 setTargetDAGCombine(ISD::SINT_TO_FP); 340 setTargetDAGCombine(ISD::STORE); 341 setTargetDAGCombine(ISD::BR_CC); 342 setTargetDAGCombine(ISD::BSWAP); 343 344 // Darwin long double math library functions have $LDBL128 appended. 345 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 346 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 347 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 348 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 349 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 350 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 351 } 352 353 computeRegisterProperties(); 354} 355 356const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 357 switch (Opcode) { 358 default: return 0; 359 case PPCISD::FSEL: return "PPCISD::FSEL"; 360 case PPCISD::FCFID: return "PPCISD::FCFID"; 361 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 362 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 363 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 364 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 365 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 366 case PPCISD::VPERM: return "PPCISD::VPERM"; 367 case PPCISD::Hi: return "PPCISD::Hi"; 368 case PPCISD::Lo: return "PPCISD::Lo"; 369 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 370 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 371 case PPCISD::SRL: return "PPCISD::SRL"; 372 case PPCISD::SRA: return "PPCISD::SRA"; 373 case PPCISD::SHL: return "PPCISD::SHL"; 374 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 375 case PPCISD::STD_32: return "PPCISD::STD_32"; 376 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF"; 377 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho"; 378 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 379 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; 380 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; 381 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 382 case PPCISD::MFCR: return "PPCISD::MFCR"; 383 case PPCISD::VCMP: return "PPCISD::VCMP"; 384 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 385 case PPCISD::LBRX: return "PPCISD::LBRX"; 386 case PPCISD::STBRX: return "PPCISD::STBRX"; 387 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 388 case PPCISD::MFFS: return "PPCISD::MFFS"; 389 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 390 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 391 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 392 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 393 } 394} 395 396//===----------------------------------------------------------------------===// 397// Node matching predicates, for use by the tblgen matching code. 398//===----------------------------------------------------------------------===// 399 400/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 401static bool isFloatingPointZero(SDOperand Op) { 402 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 403 return CFP->getValueAPF().isZero(); 404 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 405 // Maybe this has already been legalized into the constant pool? 406 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 407 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 408 return CFP->getValueAPF().isZero(); 409 } 410 return false; 411} 412 413/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 414/// true if Op is undef or if it matches the specified value. 415static bool isConstantOrUndef(SDOperand Op, unsigned Val) { 416 return Op.getOpcode() == ISD::UNDEF || 417 cast<ConstantSDNode>(Op)->getValue() == Val; 418} 419 420/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 421/// VPKUHUM instruction. 422bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) { 423 if (!isUnary) { 424 for (unsigned i = 0; i != 16; ++i) 425 if (!isConstantOrUndef(N->getOperand(i), i*2+1)) 426 return false; 427 } else { 428 for (unsigned i = 0; i != 8; ++i) 429 if (!isConstantOrUndef(N->getOperand(i), i*2+1) || 430 !isConstantOrUndef(N->getOperand(i+8), i*2+1)) 431 return false; 432 } 433 return true; 434} 435 436/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 437/// VPKUWUM instruction. 438bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) { 439 if (!isUnary) { 440 for (unsigned i = 0; i != 16; i += 2) 441 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 442 !isConstantOrUndef(N->getOperand(i+1), i*2+3)) 443 return false; 444 } else { 445 for (unsigned i = 0; i != 8; i += 2) 446 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) || 447 !isConstantOrUndef(N->getOperand(i+1), i*2+3) || 448 !isConstantOrUndef(N->getOperand(i+8), i*2+2) || 449 !isConstantOrUndef(N->getOperand(i+9), i*2+3)) 450 return false; 451 } 452 return true; 453} 454 455/// isVMerge - Common function, used to match vmrg* shuffles. 456/// 457static bool isVMerge(SDNode *N, unsigned UnitSize, 458 unsigned LHSStart, unsigned RHSStart) { 459 assert(N->getOpcode() == ISD::BUILD_VECTOR && 460 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 461 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 462 "Unsupported merge size!"); 463 464 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 465 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 466 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j), 467 LHSStart+j+i*UnitSize) || 468 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j), 469 RHSStart+j+i*UnitSize)) 470 return false; 471 } 472 return true; 473} 474 475/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 476/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 477bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 478 if (!isUnary) 479 return isVMerge(N, UnitSize, 8, 24); 480 return isVMerge(N, UnitSize, 8, 8); 481} 482 483/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 484/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 485bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) { 486 if (!isUnary) 487 return isVMerge(N, UnitSize, 0, 16); 488 return isVMerge(N, UnitSize, 0, 0); 489} 490 491 492/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 493/// amount, otherwise return -1. 494int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 495 assert(N->getOpcode() == ISD::BUILD_VECTOR && 496 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!"); 497 // Find the first non-undef value in the shuffle mask. 498 unsigned i; 499 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i) 500 /*search*/; 501 502 if (i == 16) return -1; // all undef. 503 504 // Otherwise, check to see if the rest of the elements are consequtively 505 // numbered from this value. 506 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue(); 507 if (ShiftAmt < i) return -1; 508 ShiftAmt -= i; 509 510 if (!isUnary) { 511 // Check the rest of the elements to see if they are consequtive. 512 for (++i; i != 16; ++i) 513 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i)) 514 return -1; 515 } else { 516 // Check the rest of the elements to see if they are consequtive. 517 for (++i; i != 16; ++i) 518 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15)) 519 return -1; 520 } 521 522 return ShiftAmt; 523} 524 525/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 526/// specifies a splat of a single element that is suitable for input to 527/// VSPLTB/VSPLTH/VSPLTW. 528bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) { 529 assert(N->getOpcode() == ISD::BUILD_VECTOR && 530 N->getNumOperands() == 16 && 531 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 532 533 // This is a splat operation if each element of the permute is the same, and 534 // if the value doesn't reference the second vector. 535 unsigned ElementBase = 0; 536 SDOperand Elt = N->getOperand(0); 537 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt)) 538 ElementBase = EltV->getValue(); 539 else 540 return false; // FIXME: Handle UNDEF elements too! 541 542 if (cast<ConstantSDNode>(Elt)->getValue() >= 16) 543 return false; 544 545 // Check that they are consequtive. 546 for (unsigned i = 1; i != EltSize; ++i) { 547 if (!isa<ConstantSDNode>(N->getOperand(i)) || 548 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase) 549 return false; 550 } 551 552 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 553 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 554 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 555 assert(isa<ConstantSDNode>(N->getOperand(i)) && 556 "Invalid VECTOR_SHUFFLE mask!"); 557 for (unsigned j = 0; j != EltSize; ++j) 558 if (N->getOperand(i+j) != N->getOperand(j)) 559 return false; 560 } 561 562 return true; 563} 564 565/// isAllNegativeZeroVector - Returns true if all elements of build_vector 566/// are -0.0. 567bool PPC::isAllNegativeZeroVector(SDNode *N) { 568 assert(N->getOpcode() == ISD::BUILD_VECTOR); 569 if (PPC::isSplatShuffleMask(N, N->getNumOperands())) 570 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N)) 571 return CFP->getValueAPF().isNegZero(); 572 return false; 573} 574 575/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 576/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 577unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 578 assert(isSplatShuffleMask(N, EltSize)); 579 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize; 580} 581 582/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 583/// by using a vspltis[bhw] instruction of the specified element size, return 584/// the constant being splatted. The ByteSize field indicates the number of 585/// bytes of each element [124] -> [bhw]. 586SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 587 SDOperand OpVal(0, 0); 588 589 // If ByteSize of the splat is bigger than the element size of the 590 // build_vector, then we have a case where we are checking for a splat where 591 // multiple elements of the buildvector are folded together into a single 592 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 593 unsigned EltSize = 16/N->getNumOperands(); 594 if (EltSize < ByteSize) { 595 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 596 SDOperand UniquedVals[4]; 597 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 598 599 // See if all of the elements in the buildvector agree across. 600 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 601 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 602 // If the element isn't a constant, bail fully out. 603 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand(); 604 605 606 if (UniquedVals[i&(Multiple-1)].Val == 0) 607 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 608 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 609 return SDOperand(); // no match. 610 } 611 612 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 613 // either constant or undef values that are identical for each chunk. See 614 // if these chunks can form into a larger vspltis*. 615 616 // Check to see if all of the leading entries are either 0 or -1. If 617 // neither, then this won't fit into the immediate field. 618 bool LeadingZero = true; 619 bool LeadingOnes = true; 620 for (unsigned i = 0; i != Multiple-1; ++i) { 621 if (UniquedVals[i].Val == 0) continue; // Must have been undefs. 622 623 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 624 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 625 } 626 // Finally, check the least significant entry. 627 if (LeadingZero) { 628 if (UniquedVals[Multiple-1].Val == 0) 629 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 630 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue(); 631 if (Val < 16) 632 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 633 } 634 if (LeadingOnes) { 635 if (UniquedVals[Multiple-1].Val == 0) 636 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 637 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended(); 638 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 639 return DAG.getTargetConstant(Val, MVT::i32); 640 } 641 642 return SDOperand(); 643 } 644 645 // Check to see if this buildvec has a single non-undef value in its elements. 646 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 647 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 648 if (OpVal.Val == 0) 649 OpVal = N->getOperand(i); 650 else if (OpVal != N->getOperand(i)) 651 return SDOperand(); 652 } 653 654 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def. 655 656 unsigned ValSizeInBytes = 0; 657 uint64_t Value = 0; 658 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 659 Value = CN->getValue(); 660 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 661 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 662 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 663 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 664 ValSizeInBytes = 4; 665 } 666 667 // If the splat value is larger than the element value, then we can never do 668 // this splat. The only case that we could fit the replicated bits into our 669 // immediate field for would be zero, and we prefer to use vxor for it. 670 if (ValSizeInBytes < ByteSize) return SDOperand(); 671 672 // If the element value is larger than the splat value, cut it in half and 673 // check to see if the two halves are equal. Continue doing this until we 674 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 675 while (ValSizeInBytes > ByteSize) { 676 ValSizeInBytes >>= 1; 677 678 // If the top half equals the bottom half, we're still ok. 679 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 680 (Value & ((1 << (8*ValSizeInBytes))-1))) 681 return SDOperand(); 682 } 683 684 // Properly sign extend the value. 685 int ShAmt = (4-ByteSize)*8; 686 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 687 688 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 689 if (MaskVal == 0) return SDOperand(); 690 691 // Finally, if this value fits in a 5 bit sext field, return it 692 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 693 return DAG.getTargetConstant(MaskVal, MVT::i32); 694 return SDOperand(); 695} 696 697//===----------------------------------------------------------------------===// 698// Addressing Mode Selection 699//===----------------------------------------------------------------------===// 700 701/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 702/// or 64-bit immediate, and if the value can be accurately represented as a 703/// sign extension from a 16-bit value. If so, this returns true and the 704/// immediate. 705static bool isIntS16Immediate(SDNode *N, short &Imm) { 706 if (N->getOpcode() != ISD::Constant) 707 return false; 708 709 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 710 if (N->getValueType(0) == MVT::i32) 711 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 712 else 713 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 714} 715static bool isIntS16Immediate(SDOperand Op, short &Imm) { 716 return isIntS16Immediate(Op.Val, Imm); 717} 718 719 720/// SelectAddressRegReg - Given the specified addressed, check to see if it 721/// can be represented as an indexed [r+r] operation. Returns false if it 722/// can be more efficiently represented with [r+imm]. 723bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base, 724 SDOperand &Index, 725 SelectionDAG &DAG) { 726 short imm = 0; 727 if (N.getOpcode() == ISD::ADD) { 728 if (isIntS16Immediate(N.getOperand(1), imm)) 729 return false; // r+i 730 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 731 return false; // r+i 732 733 Base = N.getOperand(0); 734 Index = N.getOperand(1); 735 return true; 736 } else if (N.getOpcode() == ISD::OR) { 737 if (isIntS16Immediate(N.getOperand(1), imm)) 738 return false; // r+i can fold it if we can. 739 740 // If this is an or of disjoint bitfields, we can codegen this as an add 741 // (for better address arithmetic) if the LHS and RHS of the OR are provably 742 // disjoint. 743 uint64_t LHSKnownZero, LHSKnownOne; 744 uint64_t RHSKnownZero, RHSKnownOne; 745 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 746 747 if (LHSKnownZero) { 748 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne); 749 // If all of the bits are known zero on the LHS or RHS, the add won't 750 // carry. 751 if ((LHSKnownZero | RHSKnownZero) == ~0U) { 752 Base = N.getOperand(0); 753 Index = N.getOperand(1); 754 return true; 755 } 756 } 757 } 758 759 return false; 760} 761 762/// Returns true if the address N can be represented by a base register plus 763/// a signed 16-bit displacement [r+imm], and if it is not better 764/// represented as reg+reg. 765bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp, 766 SDOperand &Base, SelectionDAG &DAG){ 767 // If this can be more profitably realized as r+r, fail. 768 if (SelectAddressRegReg(N, Disp, Base, DAG)) 769 return false; 770 771 if (N.getOpcode() == ISD::ADD) { 772 short imm = 0; 773 if (isIntS16Immediate(N.getOperand(1), imm)) { 774 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 775 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 776 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 777 } else { 778 Base = N.getOperand(0); 779 } 780 return true; // [r+i] 781 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 782 // Match LOAD (ADD (X, Lo(G))). 783 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 784 && "Cannot handle constant offsets yet!"); 785 Disp = N.getOperand(1).getOperand(0); // The global address. 786 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 787 Disp.getOpcode() == ISD::TargetConstantPool || 788 Disp.getOpcode() == ISD::TargetJumpTable); 789 Base = N.getOperand(0); 790 return true; // [&g+r] 791 } 792 } else if (N.getOpcode() == ISD::OR) { 793 short imm = 0; 794 if (isIntS16Immediate(N.getOperand(1), imm)) { 795 // If this is an or of disjoint bitfields, we can codegen this as an add 796 // (for better address arithmetic) if the LHS and RHS of the OR are 797 // provably disjoint. 798 uint64_t LHSKnownZero, LHSKnownOne; 799 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 800 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 801 // If all of the bits are known zero on the LHS or RHS, the add won't 802 // carry. 803 Base = N.getOperand(0); 804 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 805 return true; 806 } 807 } 808 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 809 // Loading from a constant address. 810 811 // If this address fits entirely in a 16-bit sext immediate field, codegen 812 // this as "d, 0" 813 short Imm; 814 if (isIntS16Immediate(CN, Imm)) { 815 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 816 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 817 return true; 818 } 819 820 // Handle 32-bit sext immediates with LIS + addr mode. 821 if (CN->getValueType(0) == MVT::i32 || 822 (int64_t)CN->getValue() == (int)CN->getValue()) { 823 int Addr = (int)CN->getValue(); 824 825 // Otherwise, break this down into an LIS + disp. 826 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 827 828 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 829 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 830 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 831 return true; 832 } 833 } 834 835 Disp = DAG.getTargetConstant(0, getPointerTy()); 836 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 837 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 838 else 839 Base = N; 840 return true; // [r+0] 841} 842 843/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 844/// represented as an indexed [r+r] operation. 845bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, 846 SDOperand &Index, 847 SelectionDAG &DAG) { 848 // Check to see if we can easily represent this as an [r+r] address. This 849 // will fail if it thinks that the address is more profitably represented as 850 // reg+imm, e.g. where imm = 0. 851 if (SelectAddressRegReg(N, Base, Index, DAG)) 852 return true; 853 854 // If the operand is an addition, always emit this as [r+r], since this is 855 // better (for code size, and execution, as the memop does the add for free) 856 // than emitting an explicit add. 857 if (N.getOpcode() == ISD::ADD) { 858 Base = N.getOperand(0); 859 Index = N.getOperand(1); 860 return true; 861 } 862 863 // Otherwise, do it the hard way, using R0 as the base register. 864 Base = DAG.getRegister(PPC::R0, N.getValueType()); 865 Index = N; 866 return true; 867} 868 869/// SelectAddressRegImmShift - Returns true if the address N can be 870/// represented by a base register plus a signed 14-bit displacement 871/// [r+imm*4]. Suitable for use by STD and friends. 872bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, 873 SDOperand &Base, 874 SelectionDAG &DAG) { 875 // If this can be more profitably realized as r+r, fail. 876 if (SelectAddressRegReg(N, Disp, Base, DAG)) 877 return false; 878 879 if (N.getOpcode() == ISD::ADD) { 880 short imm = 0; 881 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 882 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 883 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 884 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 885 } else { 886 Base = N.getOperand(0); 887 } 888 return true; // [r+i] 889 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 890 // Match LOAD (ADD (X, Lo(G))). 891 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() 892 && "Cannot handle constant offsets yet!"); 893 Disp = N.getOperand(1).getOperand(0); // The global address. 894 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 895 Disp.getOpcode() == ISD::TargetConstantPool || 896 Disp.getOpcode() == ISD::TargetJumpTable); 897 Base = N.getOperand(0); 898 return true; // [&g+r] 899 } 900 } else if (N.getOpcode() == ISD::OR) { 901 short imm = 0; 902 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 903 // If this is an or of disjoint bitfields, we can codegen this as an add 904 // (for better address arithmetic) if the LHS and RHS of the OR are 905 // provably disjoint. 906 uint64_t LHSKnownZero, LHSKnownOne; 907 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne); 908 if ((LHSKnownZero|~(unsigned)imm) == ~0U) { 909 // If all of the bits are known zero on the LHS or RHS, the add won't 910 // carry. 911 Base = N.getOperand(0); 912 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 913 return true; 914 } 915 } 916 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 917 // Loading from a constant address. Verify low two bits are clear. 918 if ((CN->getValue() & 3) == 0) { 919 // If this address fits entirely in a 14-bit sext immediate field, codegen 920 // this as "d, 0" 921 short Imm; 922 if (isIntS16Immediate(CN, Imm)) { 923 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 924 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 925 return true; 926 } 927 928 // Fold the low-part of 32-bit absolute addresses into addr mode. 929 if (CN->getValueType(0) == MVT::i32 || 930 (int64_t)CN->getValue() == (int)CN->getValue()) { 931 int Addr = (int)CN->getValue(); 932 933 // Otherwise, break this down into an LIS + disp. 934 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 935 936 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 937 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 938 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0); 939 return true; 940 } 941 } 942 } 943 944 Disp = DAG.getTargetConstant(0, getPointerTy()); 945 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 946 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 947 else 948 Base = N; 949 return true; // [r+0] 950} 951 952 953/// getPreIndexedAddressParts - returns true by value, base pointer and 954/// offset pointer and addressing mode by reference if the node's address 955/// can be legally represented as pre-indexed load / store address. 956bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 957 SDOperand &Offset, 958 ISD::MemIndexedMode &AM, 959 SelectionDAG &DAG) { 960 // Disabled by default for now. 961 if (!EnablePPCPreinc) return false; 962 963 SDOperand Ptr; 964 MVT::ValueType VT; 965 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 966 Ptr = LD->getBasePtr(); 967 VT = LD->getMemoryVT(); 968 969 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 970 ST = ST; 971 Ptr = ST->getBasePtr(); 972 VT = ST->getMemoryVT(); 973 } else 974 return false; 975 976 // PowerPC doesn't have preinc load/store instructions for vectors. 977 if (MVT::isVector(VT)) 978 return false; 979 980 // TODO: Check reg+reg first. 981 982 // LDU/STU use reg+imm*4, others use reg+imm. 983 if (VT != MVT::i64) { 984 // reg + imm 985 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 986 return false; 987 } else { 988 // reg + imm * 4. 989 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 990 return false; 991 } 992 993 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 994 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 995 // sext i32 to i64 when addr mode is r+i. 996 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 997 LD->getExtensionType() == ISD::SEXTLOAD && 998 isa<ConstantSDNode>(Offset)) 999 return false; 1000 } 1001 1002 AM = ISD::PRE_INC; 1003 return true; 1004} 1005 1006//===----------------------------------------------------------------------===// 1007// LowerOperation implementation 1008//===----------------------------------------------------------------------===// 1009 1010static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 1011 MVT::ValueType PtrVT = Op.getValueType(); 1012 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1013 Constant *C = CP->getConstVal(); 1014 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1015 SDOperand Zero = DAG.getConstant(0, PtrVT); 1016 1017 const TargetMachine &TM = DAG.getTarget(); 1018 1019 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero); 1020 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero); 1021 1022 // If this is a non-darwin platform, we don't support non-static relo models 1023 // yet. 1024 if (TM.getRelocationModel() == Reloc::Static || 1025 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1026 // Generate non-pic code that has direct accesses to the constant pool. 1027 // The address of the global is just (hi(&g)+lo(&g)). 1028 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1029 } 1030 1031 if (TM.getRelocationModel() == Reloc::PIC_) { 1032 // With PIC, the first instruction is actually "GR+hi(&G)". 1033 Hi = DAG.getNode(ISD::ADD, PtrVT, 1034 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1035 } 1036 1037 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1038 return Lo; 1039} 1040 1041static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) { 1042 MVT::ValueType PtrVT = Op.getValueType(); 1043 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1044 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1045 SDOperand Zero = DAG.getConstant(0, PtrVT); 1046 1047 const TargetMachine &TM = DAG.getTarget(); 1048 1049 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero); 1050 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero); 1051 1052 // If this is a non-darwin platform, we don't support non-static relo models 1053 // yet. 1054 if (TM.getRelocationModel() == Reloc::Static || 1055 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1056 // Generate non-pic code that has direct accesses to the constant pool. 1057 // The address of the global is just (hi(&g)+lo(&g)). 1058 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1059 } 1060 1061 if (TM.getRelocationModel() == Reloc::PIC_) { 1062 // With PIC, the first instruction is actually "GR+hi(&G)". 1063 Hi = DAG.getNode(ISD::ADD, PtrVT, 1064 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1065 } 1066 1067 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1068 return Lo; 1069} 1070 1071static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 1072 assert(0 && "TLS not implemented for PPC."); 1073} 1074 1075static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) { 1076 MVT::ValueType PtrVT = Op.getValueType(); 1077 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1078 GlobalValue *GV = GSDN->getGlobal(); 1079 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1080 SDOperand Zero = DAG.getConstant(0, PtrVT); 1081 1082 const TargetMachine &TM = DAG.getTarget(); 1083 1084 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero); 1085 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero); 1086 1087 // If this is a non-darwin platform, we don't support non-static relo models 1088 // yet. 1089 if (TM.getRelocationModel() == Reloc::Static || 1090 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1091 // Generate non-pic code that has direct accesses to globals. 1092 // The address of the global is just (hi(&g)+lo(&g)). 1093 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1094 } 1095 1096 if (TM.getRelocationModel() == Reloc::PIC_) { 1097 // With PIC, the first instruction is actually "GR+hi(&G)". 1098 Hi = DAG.getNode(ISD::ADD, PtrVT, 1099 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi); 1100 } 1101 1102 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo); 1103 1104 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV)) 1105 return Lo; 1106 1107 // If the global is weak or external, we have to go through the lazy 1108 // resolution stub. 1109 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0); 1110} 1111 1112static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) { 1113 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1114 1115 // If we're comparing for equality to zero, expose the fact that this is 1116 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1117 // fold the new nodes. 1118 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1119 if (C->isNullValue() && CC == ISD::SETEQ) { 1120 MVT::ValueType VT = Op.getOperand(0).getValueType(); 1121 SDOperand Zext = Op.getOperand(0); 1122 if (VT < MVT::i32) { 1123 VT = MVT::i32; 1124 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 1125 } 1126 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 1127 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 1128 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 1129 DAG.getConstant(Log2b, MVT::i32)); 1130 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); 1131 } 1132 // Leave comparisons against 0 and -1 alone for now, since they're usually 1133 // optimized. FIXME: revisit this when we can custom lower all setcc 1134 // optimizations. 1135 if (C->isAllOnesValue() || C->isNullValue()) 1136 return SDOperand(); 1137 } 1138 1139 // If we have an integer seteq/setne, turn it into a compare against zero 1140 // by xor'ing the rhs with the lhs, which is faster than setting a 1141 // condition register, reading it back out, and masking the correct bit. The 1142 // normal approach here uses sub to do this instead of xor. Using xor exposes 1143 // the result to other bit-twiddling opportunities. 1144 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 1145 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1146 MVT::ValueType VT = Op.getValueType(); 1147 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), 1148 Op.getOperand(1)); 1149 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 1150 } 1151 return SDOperand(); 1152} 1153 1154static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, 1155 int VarArgsFrameIndex, 1156 int VarArgsStackOffset, 1157 unsigned VarArgsNumGPR, 1158 unsigned VarArgsNumFPR, 1159 const PPCSubtarget &Subtarget) { 1160 1161 assert(0 && "VAARG in ELF32 ABI not implemented yet!"); 1162} 1163 1164static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 1165 int VarArgsFrameIndex, 1166 int VarArgsStackOffset, 1167 unsigned VarArgsNumGPR, 1168 unsigned VarArgsNumFPR, 1169 const PPCSubtarget &Subtarget) { 1170 1171 if (Subtarget.isMachoABI()) { 1172 // vastart just stores the address of the VarArgsFrameIndex slot into the 1173 // memory location argument. 1174 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1175 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1176 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1177 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); 1178 } 1179 1180 // For ELF 32 ABI we follow the layout of the va_list struct. 1181 // We suppose the given va_list is already allocated. 1182 // 1183 // typedef struct { 1184 // char gpr; /* index into the array of 8 GPRs 1185 // * stored in the register save area 1186 // * gpr=0 corresponds to r3, 1187 // * gpr=1 to r4, etc. 1188 // */ 1189 // char fpr; /* index into the array of 8 FPRs 1190 // * stored in the register save area 1191 // * fpr=0 corresponds to f1, 1192 // * fpr=1 to f2, etc. 1193 // */ 1194 // char *overflow_arg_area; 1195 // /* location on stack that holds 1196 // * the next overflow argument 1197 // */ 1198 // char *reg_save_area; 1199 // /* where r3:r10 and f1:f8 (if saved) 1200 // * are stored 1201 // */ 1202 // } va_list[1]; 1203 1204 1205 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8); 1206 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8); 1207 1208 1209 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1210 1211 SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); 1212 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1213 1214 uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8; 1215 SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1216 1217 uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1; 1218 SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1219 1220 uint64_t FPROffset = 1; 1221 SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1222 1223 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1224 1225 // Store first byte : number of int regs 1226 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR, 1227 Op.getOperand(1), SV, 0); 1228 uint64_t nextOffset = FPROffset; 1229 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1), 1230 ConstFPROffset); 1231 1232 // Store second byte : number of float regs 1233 SDOperand secondStore = 1234 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset); 1235 nextOffset += StackOffset; 1236 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset); 1237 1238 // Store second word : arguments given on stack 1239 SDOperand thirdStore = 1240 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset); 1241 nextOffset += FrameOffset; 1242 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset); 1243 1244 // Store third word : arguments given in registers 1245 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset); 1246 1247} 1248 1249#include "PPCGenCallingConv.inc" 1250 1251/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1252/// depending on which subtarget is selected. 1253static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { 1254 if (Subtarget.isMachoABI()) { 1255 static const unsigned FPR[] = { 1256 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1257 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1258 }; 1259 return FPR; 1260 } 1261 1262 1263 static const unsigned FPR[] = { 1264 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1265 PPC::F8 1266 }; 1267 return FPR; 1268} 1269 1270static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, 1271 int &VarArgsFrameIndex, 1272 int &VarArgsStackOffset, 1273 unsigned &VarArgsNumGPR, 1274 unsigned &VarArgsNumFPR, 1275 const PPCSubtarget &Subtarget) { 1276 // TODO: add description of PPC stack frame format, or at least some docs. 1277 // 1278 MachineFunction &MF = DAG.getMachineFunction(); 1279 MachineFrameInfo *MFI = MF.getFrameInfo(); 1280 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1281 SmallVector<SDOperand, 8> ArgValues; 1282 SDOperand Root = Op.getOperand(0); 1283 1284 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1285 bool isPPC64 = PtrVT == MVT::i64; 1286 bool isMachoABI = Subtarget.isMachoABI(); 1287 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1288 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1289 1290 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1291 1292 static const unsigned GPR_32[] = { // 32-bit registers. 1293 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1294 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1295 }; 1296 static const unsigned GPR_64[] = { // 64-bit registers. 1297 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1298 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1299 }; 1300 1301 static const unsigned *FPR = GetFPR(Subtarget); 1302 1303 static const unsigned VR[] = { 1304 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1305 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1306 }; 1307 1308 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1309 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8; 1310 const unsigned Num_VR_Regs = array_lengthof( VR); 1311 1312 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1313 1314 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1315 1316 // Add DAG nodes to load the arguments or copy them out of registers. On 1317 // entry to a function on PPC, the arguments start after the linkage area, 1318 // although the first ones are often in registers. 1319 // 1320 // In the ELF 32 ABI, GPRs and stack are double word align: an argument 1321 // represented with two words (long long or double) must be copied to an 1322 // even GPR_idx value or to an even ArgOffset value. 1323 1324 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) { 1325 SDOperand ArgVal; 1326 bool needsLoad = false; 1327 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 1328 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8; 1329 unsigned ArgSize = ObjSize; 1330 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue(); 1331 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1332 // See if next argument requires stack alignment in ELF 1333 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) && 1334 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) && 1335 (!(Flags & AlignFlag))); 1336 1337 unsigned CurArgOffset = ArgOffset; 1338 switch (ObjectVT) { 1339 default: assert(0 && "Unhandled argument type!"); 1340 case MVT::i32: 1341 // Double word align in ELF 1342 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2); 1343 if (GPR_idx != Num_GPR_Regs) { 1344 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1345 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1346 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1347 ++GPR_idx; 1348 } else { 1349 needsLoad = true; 1350 ArgSize = PtrByteSize; 1351 } 1352 // Stack align in ELF 1353 if (needsLoad && Expand && isELF32_ABI) 1354 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1355 // All int arguments reserve stack space in Macho ABI. 1356 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize; 1357 break; 1358 1359 case MVT::i64: // PPC64 1360 if (GPR_idx != Num_GPR_Regs) { 1361 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1362 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1363 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64); 1364 ++GPR_idx; 1365 } else { 1366 needsLoad = true; 1367 } 1368 // All int arguments reserve stack space in Macho ABI. 1369 if (isMachoABI || needsLoad) ArgOffset += 8; 1370 break; 1371 1372 case MVT::f32: 1373 case MVT::f64: 1374 // Every 4 bytes of argument space consumes one of the GPRs available for 1375 // argument passing. 1376 if (GPR_idx != Num_GPR_Regs && isMachoABI) { 1377 ++GPR_idx; 1378 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1379 ++GPR_idx; 1380 } 1381 if (FPR_idx != Num_FPR_Regs) { 1382 unsigned VReg; 1383 if (ObjectVT == MVT::f32) 1384 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass); 1385 else 1386 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1387 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1388 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1389 ++FPR_idx; 1390 } else { 1391 needsLoad = true; 1392 } 1393 1394 // Stack align in ELF 1395 if (needsLoad && Expand && isELF32_ABI) 1396 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1397 // All FP arguments reserve stack space in Macho ABI. 1398 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize; 1399 break; 1400 case MVT::v4f32: 1401 case MVT::v4i32: 1402 case MVT::v8i16: 1403 case MVT::v16i8: 1404 // Note that vector arguments in registers don't reserve stack space. 1405 if (VR_idx != Num_VR_Regs) { 1406 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass); 1407 RegInfo.addLiveIn(VR[VR_idx], VReg); 1408 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT); 1409 ++VR_idx; 1410 } else { 1411 // This should be simple, but requires getting 16-byte aligned stack 1412 // values. 1413 assert(0 && "Loading VR argument not implemented yet!"); 1414 needsLoad = true; 1415 } 1416 break; 1417 } 1418 1419 // We need to load the argument to a virtual register if we determined above 1420 // that we ran out of physical registers of the appropriate type 1421 if (needsLoad) { 1422 // If the argument is actually used, emit a load from the right stack 1423 // slot. 1424 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 1425 int FI = MFI->CreateFixedObject(ObjSize, 1426 CurArgOffset + (ArgSize - ObjSize)); 1427 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT); 1428 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 1429 } else { 1430 // Don't emit a dead load. 1431 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT); 1432 } 1433 } 1434 1435 ArgValues.push_back(ArgVal); 1436 } 1437 1438 // If the function takes variable number of arguments, make a frame index for 1439 // the start of the first vararg value... for expansion of llvm.va_start. 1440 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1441 if (isVarArg) { 1442 1443 int depth; 1444 if (isELF32_ABI) { 1445 VarArgsNumGPR = GPR_idx; 1446 VarArgsNumFPR = FPR_idx; 1447 1448 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame 1449 // pointer. 1450 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 + 1451 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 + 1452 MVT::getSizeInBits(PtrVT)/8); 1453 1454 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1455 ArgOffset); 1456 1457 } 1458 else 1459 depth = ArgOffset; 1460 1461 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8, 1462 depth); 1463 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1464 1465 SmallVector<SDOperand, 8> MemOps; 1466 1467 // In ELF 32 ABI, the fixed integer arguments of a variadic function are 1468 // stored to the VarArgsFrameIndex on the stack. 1469 if (isELF32_ABI) { 1470 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) { 1471 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT); 1472 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1473 MemOps.push_back(Store); 1474 // Increment the address by four for the next argument to store 1475 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1476 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1477 } 1478 } 1479 1480 // If this function is vararg, store any remaining integer argument regs 1481 // to their spots on the stack so that they may be loaded by deferencing the 1482 // result of va_next. 1483 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 1484 unsigned VReg; 1485 if (isPPC64) 1486 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); 1487 else 1488 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); 1489 1490 RegInfo.addLiveIn(GPR[GPR_idx], VReg); 1491 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT); 1492 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1493 MemOps.push_back(Store); 1494 // Increment the address by four for the next argument to store 1495 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT); 1496 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1497 } 1498 1499 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex 1500 // on the stack. 1501 if (isELF32_ABI) { 1502 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) { 1503 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64); 1504 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0); 1505 MemOps.push_back(Store); 1506 // Increment the address by eight for the next argument to store 1507 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1508 PtrVT); 1509 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1510 } 1511 1512 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { 1513 unsigned VReg; 1514 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); 1515 1516 RegInfo.addLiveIn(FPR[FPR_idx], VReg); 1517 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64); 1518 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1519 MemOps.push_back(Store); 1520 // Increment the address by eight for the next argument to store 1521 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8, 1522 PtrVT); 1523 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff); 1524 } 1525 } 1526 1527 if (!MemOps.empty()) 1528 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size()); 1529 } 1530 1531 ArgValues.push_back(Root); 1532 1533 // Return the new list of results. 1534 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1535 Op.Val->value_end()); 1536 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1537} 1538 1539/// isCallCompatibleAddress - Return the immediate to use if the specified 1540/// 32-bit value is representable in the immediate field of a BxA instruction. 1541static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) { 1542 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 1543 if (!C) return 0; 1544 1545 int Addr = C->getValue(); 1546 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 1547 (Addr << 6 >> 6) != Addr) 1548 return 0; // Top 6 bits have to be sext of immediate. 1549 1550 return DAG.getConstant((int)C->getValue() >> 2, 1551 DAG.getTargetLoweringInfo().getPointerTy()).Val; 1552} 1553 1554 1555static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, 1556 const PPCSubtarget &Subtarget) { 1557 SDOperand Chain = Op.getOperand(0); 1558 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1559 SDOperand Callee = Op.getOperand(4); 1560 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 1561 1562 bool isMachoABI = Subtarget.isMachoABI(); 1563 bool isELF32_ABI = Subtarget.isELF32_ABI(); 1564 1565 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1566 bool isPPC64 = PtrVT == MVT::i64; 1567 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1568 1569 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1570 // SelectExpr to use to put the arguments in the appropriate registers. 1571 std::vector<SDOperand> args_to_use; 1572 1573 // Count how many bytes are to be pushed on the stack, including the linkage 1574 // area, and parameter passing area. We start with 24/48 bytes, which is 1575 // prereserved space for [SP][CR][LR][3 x unused]. 1576 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1577 1578 // Add up all the space actually used. 1579 for (unsigned i = 0; i != NumOps; ++i) { 1580 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8; 1581 ArgSize = std::max(ArgSize, PtrByteSize); 1582 NumBytes += ArgSize; 1583 } 1584 1585 // The prolog code of the callee may store up to 8 GPR argument registers to 1586 // the stack, allowing va_start to index over them in memory if its varargs. 1587 // Because we cannot tell if this is needed on the caller side, we have to 1588 // conservatively assume that it is needed. As such, make sure we have at 1589 // least enough stack space for the caller to store the 8 GPRs. 1590 NumBytes = std::max(NumBytes, 1591 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI)); 1592 1593 // Adjust the stack pointer for the new arguments... 1594 // These operations are automatically eliminated by the prolog/epilog pass 1595 Chain = DAG.getCALLSEQ_START(Chain, 1596 DAG.getConstant(NumBytes, PtrVT)); 1597 1598 // Set up a copy of the stack pointer for use loading and storing any 1599 // arguments that may not fit in the registers available for argument 1600 // passing. 1601 SDOperand StackPtr; 1602 if (isPPC64) 1603 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 1604 else 1605 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1606 1607 // Figure out which arguments are going to go in registers, and which in 1608 // memory. Also, if this is a vararg function, floating point operations 1609 // must be stored to our stack, and loaded into integer regs as well, if 1610 // any integer regs are available for argument passing. 1611 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI); 1612 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1613 1614 static const unsigned GPR_32[] = { // 32-bit registers. 1615 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1616 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1617 }; 1618 static const unsigned GPR_64[] = { // 64-bit registers. 1619 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1620 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1621 }; 1622 static const unsigned *FPR = GetFPR(Subtarget); 1623 1624 static const unsigned VR[] = { 1625 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1626 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1627 }; 1628 const unsigned NumGPRs = array_lengthof(GPR_32); 1629 const unsigned NumFPRs = isMachoABI ? 13 : 8; 1630 const unsigned NumVRs = array_lengthof( VR); 1631 1632 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1633 1634 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 1635 SmallVector<SDOperand, 8> MemOpChains; 1636 for (unsigned i = 0; i != NumOps; ++i) { 1637 bool inMem = false; 1638 SDOperand Arg = Op.getOperand(5+2*i); 1639 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue(); 1640 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs; 1641 // See if next argument requires stack alignment in ELF 1642 unsigned next = 5+2*(i+1)+1; 1643 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) && 1644 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) && 1645 (!(Flags & AlignFlag))); 1646 1647 // PtrOff will be used to store the current argument to the stack if a 1648 // register cannot be found for it. 1649 SDOperand PtrOff; 1650 1651 // Stack align in ELF 32 1652 if (isELF32_ABI && Expand) 1653 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize, 1654 StackPtr.getValueType()); 1655 else 1656 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 1657 1658 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff); 1659 1660 // On PPC64, promote integers to 64-bit values. 1661 if (isPPC64 && Arg.getValueType() == MVT::i32) { 1662 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 1663 1664 Arg = DAG.getNode(ExtOp, MVT::i64, Arg); 1665 } 1666 1667 switch (Arg.getValueType()) { 1668 default: assert(0 && "Unexpected ValueType for argument!"); 1669 case MVT::i32: 1670 case MVT::i64: 1671 // Double word align in ELF 1672 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2); 1673 if (GPR_idx != NumGPRs) { 1674 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 1675 } else { 1676 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1677 inMem = true; 1678 } 1679 if (inMem || isMachoABI) { 1680 // Stack align in ELF 1681 if (isELF32_ABI && Expand) 1682 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1683 1684 ArgOffset += PtrByteSize; 1685 } 1686 break; 1687 case MVT::f32: 1688 case MVT::f64: 1689 if (isVarArg) { 1690 // Float varargs need to be promoted to double. 1691 if (Arg.getValueType() == MVT::f32) 1692 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); 1693 } 1694 1695 if (FPR_idx != NumFPRs) { 1696 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 1697 1698 if (isVarArg) { 1699 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0); 1700 MemOpChains.push_back(Store); 1701 1702 // Float varargs are always shadowed in available integer registers 1703 if (GPR_idx != NumGPRs) { 1704 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1705 MemOpChains.push_back(Load.getValue(1)); 1706 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1707 Load)); 1708 } 1709 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 1710 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 1711 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); 1712 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); 1713 MemOpChains.push_back(Load.getValue(1)); 1714 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], 1715 Load)); 1716 } 1717 } else { 1718 // If we have any FPRs remaining, we may also have GPRs remaining. 1719 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1720 // GPRs. 1721 if (isMachoABI) { 1722 if (GPR_idx != NumGPRs) 1723 ++GPR_idx; 1724 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 1725 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 1726 ++GPR_idx; 1727 } 1728 } 1729 } else { 1730 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 1731 inMem = true; 1732 } 1733 if (inMem || isMachoABI) { 1734 // Stack align in ELF 1735 if (isELF32_ABI && Expand) 1736 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize; 1737 if (isPPC64) 1738 ArgOffset += 8; 1739 else 1740 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 1741 } 1742 break; 1743 case MVT::v4f32: 1744 case MVT::v4i32: 1745 case MVT::v8i16: 1746 case MVT::v16i8: 1747 assert(!isVarArg && "Don't support passing vectors to varargs yet!"); 1748 assert(VR_idx != NumVRs && 1749 "Don't support passing more than 12 vector args yet!"); 1750 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 1751 break; 1752 } 1753 } 1754 if (!MemOpChains.empty()) 1755 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 1756 &MemOpChains[0], MemOpChains.size()); 1757 1758 // Build a sequence of copy-to-reg nodes chained together with token chain 1759 // and flag operands which copy the outgoing args into the appropriate regs. 1760 SDOperand InFlag; 1761 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1762 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 1763 InFlag); 1764 InFlag = Chain.getValue(1); 1765 } 1766 1767 // With the ELF 32 ABI, set CR6 to true if this is a vararg call. 1768 if (isVarArg && isELF32_ABI) { 1769 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0); 1770 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag); 1771 InFlag = Chain.getValue(1); 1772 } 1773 1774 std::vector<MVT::ValueType> NodeTys; 1775 NodeTys.push_back(MVT::Other); // Returns a chain 1776 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 1777 1778 SmallVector<SDOperand, 8> Ops; 1779 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF; 1780 1781 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1782 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1783 // node so that legalize doesn't hack it. 1784 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1785 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 1786 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 1787 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 1788 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 1789 // If this is an absolute destination address, use the munged value. 1790 Callee = SDOperand(Dest, 0); 1791 else { 1792 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 1793 // to do the call, we can't use PPCISD::CALL. 1794 SDOperand MTCTROps[] = {Chain, Callee, InFlag}; 1795 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0)); 1796 InFlag = Chain.getValue(1); 1797 1798 // Copy the callee address into R12 on darwin. 1799 if (isMachoABI) { 1800 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag); 1801 InFlag = Chain.getValue(1); 1802 } 1803 1804 NodeTys.clear(); 1805 NodeTys.push_back(MVT::Other); 1806 NodeTys.push_back(MVT::Flag); 1807 Ops.push_back(Chain); 1808 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF; 1809 Callee.Val = 0; 1810 } 1811 1812 // If this is a direct call, pass the chain and the callee. 1813 if (Callee.Val) { 1814 Ops.push_back(Chain); 1815 Ops.push_back(Callee); 1816 } 1817 1818 // Add argument registers to the end of the list so that they are known live 1819 // into the call. 1820 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1821 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1822 RegsToPass[i].second.getValueType())); 1823 1824 if (InFlag.Val) 1825 Ops.push_back(InFlag); 1826 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 1827 InFlag = Chain.getValue(1); 1828 1829 Chain = DAG.getCALLSEQ_END(Chain, 1830 DAG.getConstant(NumBytes, PtrVT), 1831 DAG.getConstant(0, PtrVT), 1832 InFlag); 1833 if (Op.Val->getValueType(0) != MVT::Other) 1834 InFlag = Chain.getValue(1); 1835 1836 SDOperand ResultVals[3]; 1837 unsigned NumResults = 0; 1838 NodeTys.clear(); 1839 1840 // If the call has results, copy the values out of the ret val registers. 1841 switch (Op.Val->getValueType(0)) { 1842 default: assert(0 && "Unexpected ret value!"); 1843 case MVT::Other: break; 1844 case MVT::i32: 1845 if (Op.Val->getValueType(1) == MVT::i32) { 1846 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1847 ResultVals[0] = Chain.getValue(0); 1848 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, 1849 Chain.getValue(2)).getValue(1); 1850 ResultVals[1] = Chain.getValue(0); 1851 NumResults = 2; 1852 NodeTys.push_back(MVT::i32); 1853 } else { 1854 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1); 1855 ResultVals[0] = Chain.getValue(0); 1856 NumResults = 1; 1857 } 1858 NodeTys.push_back(MVT::i32); 1859 break; 1860 case MVT::i64: 1861 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1); 1862 ResultVals[0] = Chain.getValue(0); 1863 NumResults = 1; 1864 NodeTys.push_back(MVT::i64); 1865 break; 1866 case MVT::f64: 1867 if (Op.Val->getValueType(1) == MVT::f64) { 1868 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1); 1869 ResultVals[0] = Chain.getValue(0); 1870 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64, 1871 Chain.getValue(2)).getValue(1); 1872 ResultVals[1] = Chain.getValue(0); 1873 NumResults = 2; 1874 NodeTys.push_back(MVT::f64); 1875 NodeTys.push_back(MVT::f64); 1876 break; 1877 } 1878 // else fall through 1879 case MVT::f32: 1880 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), 1881 InFlag).getValue(1); 1882 ResultVals[0] = Chain.getValue(0); 1883 NumResults = 1; 1884 NodeTys.push_back(Op.Val->getValueType(0)); 1885 break; 1886 case MVT::v4f32: 1887 case MVT::v4i32: 1888 case MVT::v8i16: 1889 case MVT::v16i8: 1890 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0), 1891 InFlag).getValue(1); 1892 ResultVals[0] = Chain.getValue(0); 1893 NumResults = 1; 1894 NodeTys.push_back(Op.Val->getValueType(0)); 1895 break; 1896 } 1897 1898 NodeTys.push_back(MVT::Other); 1899 1900 // If the function returns void, just return the chain. 1901 if (NumResults == 0) 1902 return Chain; 1903 1904 // Otherwise, merge everything together with a MERGE_VALUES node. 1905 ResultVals[NumResults++] = Chain; 1906 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, 1907 ResultVals, NumResults); 1908 return Res.getValue(Op.ResNo); 1909} 1910 1911static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) { 1912 SmallVector<CCValAssign, 16> RVLocs; 1913 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 1914 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1915 CCState CCInfo(CC, isVarArg, TM, RVLocs); 1916 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC); 1917 1918 // If this is the first return lowered for this function, add the regs to the 1919 // liveout set for the function. 1920 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1921 for (unsigned i = 0; i != RVLocs.size(); ++i) 1922 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1923 } 1924 1925 SDOperand Chain = Op.getOperand(0); 1926 SDOperand Flag; 1927 1928 // Copy the result values into the output registers. 1929 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1930 CCValAssign &VA = RVLocs[i]; 1931 assert(VA.isRegLoc() && "Can only return in registers!"); 1932 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag); 1933 Flag = Chain.getValue(1); 1934 } 1935 1936 if (Flag.Val) 1937 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag); 1938 else 1939 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain); 1940} 1941 1942static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG, 1943 const PPCSubtarget &Subtarget) { 1944 // When we pop the dynamic allocation we need to restore the SP link. 1945 1946 // Get the corect type for pointers. 1947 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1948 1949 // Construct the stack pointer operand. 1950 bool IsPPC64 = Subtarget.isPPC64(); 1951 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1; 1952 SDOperand StackPtr = DAG.getRegister(SP, PtrVT); 1953 1954 // Get the operands for the STACKRESTORE. 1955 SDOperand Chain = Op.getOperand(0); 1956 SDOperand SaveSP = Op.getOperand(1); 1957 1958 // Load the old link SP. 1959 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0); 1960 1961 // Restore the stack pointer. 1962 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP); 1963 1964 // Store the old link SP. 1965 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0); 1966} 1967 1968static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG, 1969 const PPCSubtarget &Subtarget) { 1970 MachineFunction &MF = DAG.getMachineFunction(); 1971 bool IsPPC64 = Subtarget.isPPC64(); 1972 bool isMachoABI = Subtarget.isMachoABI(); 1973 1974 // Get current frame pointer save index. The users of this index will be 1975 // primarily DYNALLOC instructions. 1976 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1977 int FPSI = FI->getFramePointerSaveIndex(); 1978 1979 // If the frame pointer save index hasn't been defined yet. 1980 if (!FPSI) { 1981 // Find out what the fix offset of the frame pointer save area. 1982 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI); 1983 1984 // Allocate the frame index for frame pointer save area. 1985 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset); 1986 // Save the result. 1987 FI->setFramePointerSaveIndex(FPSI); 1988 } 1989 1990 // Get the inputs. 1991 SDOperand Chain = Op.getOperand(0); 1992 SDOperand Size = Op.getOperand(1); 1993 1994 // Get the corect type for pointers. 1995 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1996 // Negate the size. 1997 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT, 1998 DAG.getConstant(0, PtrVT), Size); 1999 // Construct a node for the frame pointer save index. 2000 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT); 2001 // Build a DYNALLOC node. 2002 SDOperand Ops[3] = { Chain, NegSize, FPSIdx }; 2003 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 2004 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3); 2005} 2006 2007 2008/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 2009/// possible. 2010static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) { 2011 // Not FP? Not a fsel. 2012 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 2013 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 2014 return SDOperand(); 2015 2016 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2017 2018 // Cannot handle SETEQ/SETNE. 2019 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand(); 2020 2021 MVT::ValueType ResVT = Op.getValueType(); 2022 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 2023 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 2024 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 2025 2026 // If the RHS of the comparison is a 0.0, we don't need to do the 2027 // subtraction at all. 2028 if (isFloatingPointZero(RHS)) 2029 switch (CC) { 2030 default: break; // SETUO etc aren't handled by fsel. 2031 case ISD::SETULT: 2032 case ISD::SETOLT: 2033 case ISD::SETLT: 2034 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2035 case ISD::SETUGE: 2036 case ISD::SETOGE: 2037 case ISD::SETGE: 2038 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2039 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2040 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 2041 case ISD::SETUGT: 2042 case ISD::SETOGT: 2043 case ISD::SETGT: 2044 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 2045 case ISD::SETULE: 2046 case ISD::SETOLE: 2047 case ISD::SETLE: 2048 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 2049 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 2050 return DAG.getNode(PPCISD::FSEL, ResVT, 2051 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 2052 } 2053 2054 SDOperand Cmp; 2055 switch (CC) { 2056 default: break; // SETUO etc aren't handled by fsel. 2057 case ISD::SETULT: 2058 case ISD::SETOLT: 2059 case ISD::SETLT: 2060 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2061 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2062 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2063 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2064 case ISD::SETUGE: 2065 case ISD::SETOGE: 2066 case ISD::SETGE: 2067 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 2068 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2069 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2070 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2071 case ISD::SETUGT: 2072 case ISD::SETOGT: 2073 case ISD::SETGT: 2074 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2075 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2076 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2077 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 2078 case ISD::SETULE: 2079 case ISD::SETOLE: 2080 case ISD::SETLE: 2081 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 2082 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 2083 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 2084 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 2085 } 2086 return SDOperand(); 2087} 2088 2089// FIXME: Split this code up when LegalizeDAGTypes lands. 2090static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) { 2091 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 2092 SDOperand Src = Op.getOperand(0); 2093 if (Src.getValueType() == MVT::f32) 2094 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 2095 2096 SDOperand Tmp; 2097 switch (Op.getValueType()) { 2098 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 2099 case MVT::i32: 2100 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 2101 break; 2102 case MVT::i64: 2103 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 2104 break; 2105 } 2106 2107 // Convert the FP value to an int value through memory. 2108 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64); 2109 2110 // Emit a store to the stack slot. 2111 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0); 2112 2113 // Result is a load from the stack slot. If loading 4 bytes, make sure to 2114 // add in a bias. 2115 if (Op.getValueType() == MVT::i32) 2116 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, 2117 DAG.getConstant(4, FIPtr.getValueType())); 2118 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0); 2119} 2120 2121static SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG) { 2122 assert(Op.getValueType() == MVT::ppcf128); 2123 SDNode *Node = Op.Val; 2124 assert(Node->getOperand(0).getValueType() == MVT::ppcf128); 2125 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR); 2126 SDOperand Lo = Node->getOperand(0).Val->getOperand(0); 2127 SDOperand Hi = Node->getOperand(0).Val->getOperand(1); 2128 2129 // This sequence changes FPSCR to do round-to-zero, adds the two halves 2130 // of the long double, and puts FPSCR back the way it was. We do not 2131 // actually model FPSCR. 2132 std::vector<MVT::ValueType> NodeTys; 2133 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg; 2134 2135 NodeTys.push_back(MVT::f64); // Return register 2136 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 2137 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); 2138 MFFSreg = Result.getValue(0); 2139 InFlag = Result.getValue(1); 2140 2141 NodeTys.clear(); 2142 NodeTys.push_back(MVT::Flag); // Returns a flag 2143 Ops[0] = DAG.getConstant(31, MVT::i32); 2144 Ops[1] = InFlag; 2145 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2); 2146 InFlag = Result.getValue(0); 2147 2148 NodeTys.clear(); 2149 NodeTys.push_back(MVT::Flag); // Returns a flag 2150 Ops[0] = DAG.getConstant(30, MVT::i32); 2151 Ops[1] = InFlag; 2152 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2); 2153 InFlag = Result.getValue(0); 2154 2155 NodeTys.clear(); 2156 NodeTys.push_back(MVT::f64); // result of add 2157 NodeTys.push_back(MVT::Flag); // Returns a flag 2158 Ops[0] = Lo; 2159 Ops[1] = Hi; 2160 Ops[2] = InFlag; 2161 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3); 2162 FPreg = Result.getValue(0); 2163 InFlag = Result.getValue(1); 2164 2165 NodeTys.clear(); 2166 NodeTys.push_back(MVT::f64); 2167 Ops[0] = DAG.getConstant(1, MVT::i32); 2168 Ops[1] = MFFSreg; 2169 Ops[2] = FPreg; 2170 Ops[3] = InFlag; 2171 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4); 2172 FPreg = Result.getValue(0); 2173 2174 // We know the low half is about to be thrown away, so just use something 2175 // convenient. 2176 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); 2177} 2178 2179static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 2180 if (Op.getOperand(0).getValueType() == MVT::i64) { 2181 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 2182 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 2183 if (Op.getValueType() == MVT::f32) 2184 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); 2185 return FP; 2186 } 2187 2188 assert(Op.getOperand(0).getValueType() == MVT::i32 && 2189 "Unhandled SINT_TO_FP type in custom expander!"); 2190 // Since we only generate this in 64-bit mode, we can take advantage of 2191 // 64-bit registers. In particular, sign extend the input value into the 2192 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 2193 // then lfd it and fcfid it. 2194 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2195 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 2196 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2197 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2198 2199 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 2200 Op.getOperand(0)); 2201 2202 // STD the extended value into the stack slot. 2203 MemOperand MO(&PseudoSourceValue::FPRel, 2204 MemOperand::MOStore, FrameIdx, 8, 8); 2205 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 2206 DAG.getEntryNode(), Ext64, FIdx, 2207 DAG.getMemOperand(MO)); 2208 // Load the value as a double. 2209 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0); 2210 2211 // FCFID it and return it. 2212 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 2213 if (Op.getValueType() == MVT::f32) 2214 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0)); 2215 return FP; 2216} 2217 2218static SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) { 2219 /* 2220 The rounding mode is in bits 30:31 of FPSR, and has the following 2221 settings: 2222 00 Round to nearest 2223 01 Round to 0 2224 10 Round to +inf 2225 11 Round to -inf 2226 2227 FLT_ROUNDS, on the other hand, expects the following: 2228 -1 Undefined 2229 0 Round to 0 2230 1 Round to nearest 2231 2 Round to +inf 2232 3 Round to -inf 2233 2234 To perform the conversion, we do: 2235 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 2236 */ 2237 2238 MachineFunction &MF = DAG.getMachineFunction(); 2239 MVT::ValueType VT = Op.getValueType(); 2240 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2241 std::vector<MVT::ValueType> NodeTys; 2242 SDOperand MFFSreg, InFlag; 2243 2244 // Save FP Control Word to register 2245 NodeTys.push_back(MVT::f64); // return register 2246 NodeTys.push_back(MVT::Flag); // unused in this context 2247 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0); 2248 2249 // Save FP register to stack slot 2250 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 2251 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 2252 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain, 2253 StackSlot, NULL, 0); 2254 2255 // Load FP Control Word from low 32 bits of stack slot. 2256 SDOperand Four = DAG.getConstant(4, PtrVT); 2257 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four); 2258 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0); 2259 2260 // Transform as necessary 2261 SDOperand CWD1 = 2262 DAG.getNode(ISD::AND, MVT::i32, 2263 CWD, DAG.getConstant(3, MVT::i32)); 2264 SDOperand CWD2 = 2265 DAG.getNode(ISD::SRL, MVT::i32, 2266 DAG.getNode(ISD::AND, MVT::i32, 2267 DAG.getNode(ISD::XOR, MVT::i32, 2268 CWD, DAG.getConstant(3, MVT::i32)), 2269 DAG.getConstant(3, MVT::i32)), 2270 DAG.getConstant(1, MVT::i8)); 2271 2272 SDOperand RetVal = 2273 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2); 2274 2275 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ? 2276 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); 2277} 2278 2279static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2280 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2281 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 2282 2283 // Expand into a bunch of logical ops. Note that these ops 2284 // depend on the PPC behavior for oversized shift amounts. 2285 SDOperand Lo = Op.getOperand(0); 2286 SDOperand Hi = Op.getOperand(1); 2287 SDOperand Amt = Op.getOperand(2); 2288 2289 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2290 DAG.getConstant(32, MVT::i32), Amt); 2291 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 2292 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 2293 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2294 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2295 DAG.getConstant(-32U, MVT::i32)); 2296 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 2297 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2298 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 2299 SDOperand OutOps[] = { OutLo, OutHi }; 2300 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2301 OutOps, 2); 2302} 2303 2304static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) { 2305 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2306 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!"); 2307 2308 // Otherwise, expand into a bunch of logical ops. Note that these ops 2309 // depend on the PPC behavior for oversized shift amounts. 2310 SDOperand Lo = Op.getOperand(0); 2311 SDOperand Hi = Op.getOperand(1); 2312 SDOperand Amt = Op.getOperand(2); 2313 2314 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2315 DAG.getConstant(32, MVT::i32), Amt); 2316 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2317 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2318 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2319 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2320 DAG.getConstant(-32U, MVT::i32)); 2321 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 2322 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 2323 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 2324 SDOperand OutOps[] = { OutLo, OutHi }; 2325 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2326 OutOps, 2); 2327} 2328 2329static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) { 2330 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 && 2331 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 2332 2333 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 2334 SDOperand Lo = Op.getOperand(0); 2335 SDOperand Hi = Op.getOperand(1); 2336 SDOperand Amt = Op.getOperand(2); 2337 2338 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 2339 DAG.getConstant(32, MVT::i32), Amt); 2340 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 2341 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 2342 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 2343 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 2344 DAG.getConstant(-32U, MVT::i32)); 2345 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 2346 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 2347 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 2348 Tmp4, Tmp6, ISD::SETLE); 2349 SDOperand OutOps[] = { OutLo, OutHi }; 2350 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32), 2351 OutOps, 2); 2352} 2353 2354//===----------------------------------------------------------------------===// 2355// Vector related lowering. 2356// 2357 2358// If this is a vector of constants or undefs, get the bits. A bit in 2359// UndefBits is set if the corresponding element of the vector is an 2360// ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2361// zero. Return true if this is not an array of constants, false if it is. 2362// 2363static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2], 2364 uint64_t UndefBits[2]) { 2365 // Start with zero'd results. 2366 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0; 2367 2368 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType()); 2369 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 2370 SDOperand OpVal = BV->getOperand(i); 2371 2372 unsigned PartNo = i >= e/2; // In the upper 128 bits? 2373 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t. 2374 2375 uint64_t EltBits = 0; 2376 if (OpVal.getOpcode() == ISD::UNDEF) { 2377 uint64_t EltUndefBits = ~0U >> (32-EltBitSize); 2378 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize); 2379 continue; 2380 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 2381 EltBits = CN->getValue() & (~0U >> (32-EltBitSize)); 2382 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 2383 assert(CN->getValueType(0) == MVT::f32 && 2384 "Only one legal FP vector type!"); 2385 EltBits = FloatToBits(CN->getValueAPF().convertToFloat()); 2386 } else { 2387 // Nonconstant element. 2388 return true; 2389 } 2390 2391 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize); 2392 } 2393 2394 //printf("%llx %llx %llx %llx\n", 2395 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]); 2396 return false; 2397} 2398 2399// If this is a splat (repetition) of a value across the whole vector, return 2400// the smallest size that splats it. For example, "0x01010101010101..." is a 2401// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2402// SplatSize = 1 byte. 2403static bool isConstantSplat(const uint64_t Bits128[2], 2404 const uint64_t Undef128[2], 2405 unsigned &SplatBits, unsigned &SplatUndef, 2406 unsigned &SplatSize) { 2407 2408 // Don't let undefs prevent splats from matching. See if the top 64-bits are 2409 // the same as the lower 64-bits, ignoring undefs. 2410 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0])) 2411 return false; // Can't be a splat if two pieces don't match. 2412 2413 uint64_t Bits64 = Bits128[0] | Bits128[1]; 2414 uint64_t Undef64 = Undef128[0] & Undef128[1]; 2415 2416 // Check that the top 32-bits are the same as the lower 32-bits, ignoring 2417 // undefs. 2418 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64)) 2419 return false; // Can't be a splat if two pieces don't match. 2420 2421 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32); 2422 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32); 2423 2424 // If the top 16-bits are different than the lower 16-bits, ignoring 2425 // undefs, we have an i32 splat. 2426 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) { 2427 SplatBits = Bits32; 2428 SplatUndef = Undef32; 2429 SplatSize = 4; 2430 return true; 2431 } 2432 2433 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16); 2434 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16); 2435 2436 // If the top 8-bits are different than the lower 8-bits, ignoring 2437 // undefs, we have an i16 splat. 2438 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) { 2439 SplatBits = Bits16; 2440 SplatUndef = Undef16; 2441 SplatSize = 2; 2442 return true; 2443 } 2444 2445 // Otherwise, we have an 8-bit splat. 2446 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8); 2447 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8); 2448 SplatSize = 1; 2449 return true; 2450} 2451 2452/// BuildSplatI - Build a canonical splati of Val with an element size of 2453/// SplatSize. Cast the result to VT. 2454static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT, 2455 SelectionDAG &DAG) { 2456 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 2457 2458 static const MVT::ValueType VTys[] = { // canonical VT to use for each size. 2459 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 2460 }; 2461 2462 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 2463 2464 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 2465 if (Val == -1) 2466 SplatSize = 1; 2467 2468 MVT::ValueType CanonicalVT = VTys[SplatSize-1]; 2469 2470 // Build a canonical splat for this value. 2471 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT)); 2472 SmallVector<SDOperand, 8> Ops; 2473 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt); 2474 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, 2475 &Ops[0], Ops.size()); 2476 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res); 2477} 2478 2479/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 2480/// specified intrinsic ID. 2481static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS, 2482 SelectionDAG &DAG, 2483 MVT::ValueType DestVT = MVT::Other) { 2484 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 2485 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2486 DAG.getConstant(IID, MVT::i32), LHS, RHS); 2487} 2488 2489/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 2490/// specified intrinsic ID. 2491static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1, 2492 SDOperand Op2, SelectionDAG &DAG, 2493 MVT::ValueType DestVT = MVT::Other) { 2494 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 2495 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT, 2496 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 2497} 2498 2499 2500/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 2501/// amount. The result has the specified value type. 2502static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt, 2503 MVT::ValueType VT, SelectionDAG &DAG) { 2504 // Force LHS/RHS to be the right type. 2505 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS); 2506 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS); 2507 2508 SDOperand Ops[16]; 2509 for (unsigned i = 0; i != 16; ++i) 2510 Ops[i] = DAG.getConstant(i+Amt, MVT::i32); 2511 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS, 2512 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16)); 2513 return DAG.getNode(ISD::BIT_CONVERT, VT, T); 2514} 2515 2516// If this is a case we can't handle, return null and let the default 2517// expansion code take care of it. If we CAN select this case, and if it 2518// selects to a single instruction, return Op. Otherwise, if we can codegen 2519// this case more efficiently than a constant pool load, lower it to the 2520// sequence of ops that should be used. 2521static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2522 // If this is a vector of constants or undefs, get the bits. A bit in 2523 // UndefBits is set if the corresponding element of the vector is an 2524 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are 2525 // zero. 2526 uint64_t VectorBits[2]; 2527 uint64_t UndefBits[2]; 2528 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)) 2529 return SDOperand(); // Not a constant vector. 2530 2531 // If this is a splat (repetition) of a value across the whole vector, return 2532 // the smallest size that splats it. For example, "0x01010101010101..." is a 2533 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and 2534 // SplatSize = 1 byte. 2535 unsigned SplatBits, SplatUndef, SplatSize; 2536 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){ 2537 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0; 2538 2539 // First, handle single instruction cases. 2540 2541 // All zeros? 2542 if (SplatBits == 0) { 2543 // Canonicalize all zero vectors to be v4i32. 2544 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 2545 SDOperand Z = DAG.getConstant(0, MVT::i32); 2546 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z); 2547 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z); 2548 } 2549 return Op; 2550 } 2551 2552 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 2553 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize); 2554 if (SextVal >= -16 && SextVal <= 15) 2555 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG); 2556 2557 2558 // Two instruction sequences. 2559 2560 // If this value is in the range [-32,30] and is even, use: 2561 // tmp = VSPLTI[bhw], result = add tmp, tmp 2562 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 2563 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG); 2564 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op); 2565 } 2566 2567 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 2568 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 2569 // for fneg/fabs. 2570 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 2571 // Make -1 and vspltisw -1: 2572 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG); 2573 2574 // Make the VSLW intrinsic, computing 0x8000_0000. 2575 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 2576 OnesV, DAG); 2577 2578 // xor by OnesV to invert it. 2579 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV); 2580 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2581 } 2582 2583 // Check to see if this is a wide variety of vsplti*, binop self cases. 2584 unsigned SplatBitSize = SplatSize*8; 2585 static const signed char SplatCsts[] = { 2586 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 2587 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 2588 }; 2589 2590 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 2591 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 2592 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 2593 int i = SplatCsts[idx]; 2594 2595 // Figure out what shift amount will be used by altivec if shifted by i in 2596 // this splat size. 2597 unsigned TypeShiftAmt = i & (SplatBitSize-1); 2598 2599 // vsplti + shl self. 2600 if (SextVal == (i << (int)TypeShiftAmt)) { 2601 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2602 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2603 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 2604 Intrinsic::ppc_altivec_vslw 2605 }; 2606 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2607 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2608 } 2609 2610 // vsplti + srl self. 2611 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2612 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2613 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2614 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 2615 Intrinsic::ppc_altivec_vsrw 2616 }; 2617 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2618 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2619 } 2620 2621 // vsplti + sra self. 2622 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 2623 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2624 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2625 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 2626 Intrinsic::ppc_altivec_vsraw 2627 }; 2628 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2629 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2630 } 2631 2632 // vsplti + rol self. 2633 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 2634 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 2635 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG); 2636 static const unsigned IIDs[] = { // Intrinsic to use for each size. 2637 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 2638 Intrinsic::ppc_altivec_vrlw 2639 }; 2640 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG); 2641 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res); 2642 } 2643 2644 // t = vsplti c, result = vsldoi t, t, 1 2645 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 2646 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2647 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG); 2648 } 2649 // t = vsplti c, result = vsldoi t, t, 2 2650 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 2651 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2652 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG); 2653 } 2654 // t = vsplti c, result = vsldoi t, t, 3 2655 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 2656 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG); 2657 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG); 2658 } 2659 } 2660 2661 // Three instruction sequences. 2662 2663 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 2664 if (SextVal >= 0 && SextVal <= 31) { 2665 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG); 2666 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2667 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS); 2668 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2669 } 2670 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 2671 if (SextVal >= -31 && SextVal <= 0) { 2672 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG); 2673 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG); 2674 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS); 2675 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS); 2676 } 2677 } 2678 2679 return SDOperand(); 2680} 2681 2682/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 2683/// the specified operations to build the shuffle. 2684static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, 2685 SDOperand RHS, SelectionDAG &DAG) { 2686 unsigned OpNum = (PFEntry >> 26) & 0x0F; 2687 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 2688 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 2689 2690 enum { 2691 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 2692 OP_VMRGHW, 2693 OP_VMRGLW, 2694 OP_VSPLTISW0, 2695 OP_VSPLTISW1, 2696 OP_VSPLTISW2, 2697 OP_VSPLTISW3, 2698 OP_VSLDOI4, 2699 OP_VSLDOI8, 2700 OP_VSLDOI12 2701 }; 2702 2703 if (OpNum == OP_COPY) { 2704 if (LHSID == (1*9+2)*9+3) return LHS; 2705 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 2706 return RHS; 2707 } 2708 2709 SDOperand OpLHS, OpRHS; 2710 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG); 2711 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG); 2712 2713 unsigned ShufIdxs[16]; 2714 switch (OpNum) { 2715 default: assert(0 && "Unknown i32 permute!"); 2716 case OP_VMRGHW: 2717 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 2718 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 2719 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 2720 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 2721 break; 2722 case OP_VMRGLW: 2723 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 2724 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 2725 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 2726 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 2727 break; 2728 case OP_VSPLTISW0: 2729 for (unsigned i = 0; i != 16; ++i) 2730 ShufIdxs[i] = (i&3)+0; 2731 break; 2732 case OP_VSPLTISW1: 2733 for (unsigned i = 0; i != 16; ++i) 2734 ShufIdxs[i] = (i&3)+4; 2735 break; 2736 case OP_VSPLTISW2: 2737 for (unsigned i = 0; i != 16; ++i) 2738 ShufIdxs[i] = (i&3)+8; 2739 break; 2740 case OP_VSPLTISW3: 2741 for (unsigned i = 0; i != 16; ++i) 2742 ShufIdxs[i] = (i&3)+12; 2743 break; 2744 case OP_VSLDOI4: 2745 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG); 2746 case OP_VSLDOI8: 2747 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG); 2748 case OP_VSLDOI12: 2749 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG); 2750 } 2751 SDOperand Ops[16]; 2752 for (unsigned i = 0; i != 16; ++i) 2753 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32); 2754 2755 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS, 2756 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 2757} 2758 2759/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 2760/// is a shuffle we can handle in a single instruction, return it. Otherwise, 2761/// return the code it can be lowered into. Worst case, it can always be 2762/// lowered into a vperm. 2763static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) { 2764 SDOperand V1 = Op.getOperand(0); 2765 SDOperand V2 = Op.getOperand(1); 2766 SDOperand PermMask = Op.getOperand(2); 2767 2768 // Cases that are handled by instructions that take permute immediates 2769 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 2770 // selected by the instruction selector. 2771 if (V2.getOpcode() == ISD::UNDEF) { 2772 if (PPC::isSplatShuffleMask(PermMask.Val, 1) || 2773 PPC::isSplatShuffleMask(PermMask.Val, 2) || 2774 PPC::isSplatShuffleMask(PermMask.Val, 4) || 2775 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) || 2776 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) || 2777 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 || 2778 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) || 2779 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) || 2780 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) || 2781 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) || 2782 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) || 2783 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) { 2784 return Op; 2785 } 2786 } 2787 2788 // Altivec has a variety of "shuffle immediates" that take two vector inputs 2789 // and produce a fixed permutation. If any of these match, do not lower to 2790 // VPERM. 2791 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) || 2792 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) || 2793 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 || 2794 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) || 2795 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) || 2796 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) || 2797 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) || 2798 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) || 2799 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false)) 2800 return Op; 2801 2802 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 2803 // perfect shuffle table to emit an optimal matching sequence. 2804 unsigned PFIndexes[4]; 2805 bool isFourElementShuffle = true; 2806 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 2807 unsigned EltNo = 8; // Start out undef. 2808 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 2809 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF) 2810 continue; // Undef, ignore it. 2811 2812 unsigned ByteSource = 2813 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue(); 2814 if ((ByteSource & 3) != j) { 2815 isFourElementShuffle = false; 2816 break; 2817 } 2818 2819 if (EltNo == 8) { 2820 EltNo = ByteSource/4; 2821 } else if (EltNo != ByteSource/4) { 2822 isFourElementShuffle = false; 2823 break; 2824 } 2825 } 2826 PFIndexes[i] = EltNo; 2827 } 2828 2829 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 2830 // perfect shuffle vector to determine if it is cost effective to do this as 2831 // discrete instructions, or whether we should use a vperm. 2832 if (isFourElementShuffle) { 2833 // Compute the index in the perfect shuffle table. 2834 unsigned PFTableIndex = 2835 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 2836 2837 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 2838 unsigned Cost = (PFEntry >> 30); 2839 2840 // Determining when to avoid vperm is tricky. Many things affect the cost 2841 // of vperm, particularly how many times the perm mask needs to be computed. 2842 // For example, if the perm mask can be hoisted out of a loop or is already 2843 // used (perhaps because there are multiple permutes with the same shuffle 2844 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 2845 // the loop requires an extra register. 2846 // 2847 // As a compromise, we only emit discrete instructions if the shuffle can be 2848 // generated in 3 or fewer operations. When we have loop information 2849 // available, if this block is within a loop, we should avoid using vperm 2850 // for 3-operation perms and use a constant pool load instead. 2851 if (Cost < 3) 2852 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG); 2853 } 2854 2855 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 2856 // vector that will get spilled to the constant pool. 2857 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 2858 2859 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 2860 // that it is in input element units, not in bytes. Convert now. 2861 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType()); 2862 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 2863 2864 SmallVector<SDOperand, 16> ResultMask; 2865 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 2866 unsigned SrcElt; 2867 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF) 2868 SrcElt = 0; 2869 else 2870 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 2871 2872 for (unsigned j = 0; j != BytesPerElement; ++j) 2873 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 2874 MVT::i8)); 2875 } 2876 2877 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, 2878 &ResultMask[0], ResultMask.size()); 2879 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 2880} 2881 2882/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 2883/// altivec comparison. If it is, return true and fill in Opc/isDot with 2884/// information about the intrinsic. 2885static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc, 2886 bool &isDot) { 2887 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue(); 2888 CompareOpc = -1; 2889 isDot = false; 2890 switch (IntrinsicID) { 2891 default: return false; 2892 // Comparison predicates. 2893 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 2894 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 2895 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 2896 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 2897 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 2898 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 2899 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 2900 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 2901 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 2902 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 2903 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 2904 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 2905 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 2906 2907 // Normal Comparisons. 2908 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 2909 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 2910 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 2911 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 2912 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 2913 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 2914 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 2915 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 2916 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 2917 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 2918 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 2919 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 2920 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 2921 } 2922 return true; 2923} 2924 2925/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 2926/// lower, do it, otherwise return null. 2927static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 2928 // If this is a lowered altivec predicate compare, CompareOpc is set to the 2929 // opcode number of the comparison. 2930 int CompareOpc; 2931 bool isDot; 2932 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 2933 return SDOperand(); // Don't custom lower most intrinsics. 2934 2935 // If this is a non-dot comparison, make the VCMP node and we are done. 2936 if (!isDot) { 2937 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 2938 Op.getOperand(1), Op.getOperand(2), 2939 DAG.getConstant(CompareOpc, MVT::i32)); 2940 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp); 2941 } 2942 2943 // Create the PPCISD altivec 'dot' comparison node. 2944 SDOperand Ops[] = { 2945 Op.getOperand(2), // LHS 2946 Op.getOperand(3), // RHS 2947 DAG.getConstant(CompareOpc, MVT::i32) 2948 }; 2949 std::vector<MVT::ValueType> VTs; 2950 VTs.push_back(Op.getOperand(2).getValueType()); 2951 VTs.push_back(MVT::Flag); 2952 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 2953 2954 // Now that we have the comparison, emit a copy from the CR to a GPR. 2955 // This is flagged to the above dot comparison. 2956 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 2957 DAG.getRegister(PPC::CR6, MVT::i32), 2958 CompNode.getValue(1)); 2959 2960 // Unpack the result based on how the target uses it. 2961 unsigned BitNo; // Bit # of CR6. 2962 bool InvertBit; // Invert result? 2963 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 2964 default: // Can't happen, don't crash on invalid number though. 2965 case 0: // Return the value of the EQ bit of CR6. 2966 BitNo = 0; InvertBit = false; 2967 break; 2968 case 1: // Return the inverted value of the EQ bit of CR6. 2969 BitNo = 0; InvertBit = true; 2970 break; 2971 case 2: // Return the value of the LT bit of CR6. 2972 BitNo = 2; InvertBit = false; 2973 break; 2974 case 3: // Return the inverted value of the LT bit of CR6. 2975 BitNo = 2; InvertBit = true; 2976 break; 2977 } 2978 2979 // Shift the bit into the low position. 2980 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 2981 DAG.getConstant(8-(3-BitNo), MVT::i32)); 2982 // Isolate the bit. 2983 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 2984 DAG.getConstant(1, MVT::i32)); 2985 2986 // If we are supposed to, toggle the bit. 2987 if (InvertBit) 2988 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 2989 DAG.getConstant(1, MVT::i32)); 2990 return Flags; 2991} 2992 2993static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) { 2994 // Create a stack slot that is 16-byte aligned. 2995 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2996 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 2997 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2998 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 2999 3000 // Store the input value into Value#0 of the stack slot. 3001 SDOperand Store = DAG.getStore(DAG.getEntryNode(), 3002 Op.getOperand(0), FIdx, NULL, 0); 3003 // Load it out. 3004 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0); 3005} 3006 3007static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 3008 if (Op.getValueType() == MVT::v4i32) { 3009 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3010 3011 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG); 3012 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt. 3013 3014 SDOperand RHSSwap = // = vrlw RHS, 16 3015 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG); 3016 3017 // Shrinkify inputs to v8i16. 3018 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS); 3019 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS); 3020 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap); 3021 3022 // Low parts multiplied together, generating 32-bit results (we ignore the 3023 // top parts). 3024 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 3025 LHS, RHS, DAG, MVT::v4i32); 3026 3027 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 3028 LHS, RHSSwap, Zero, DAG, MVT::v4i32); 3029 // Shift the high parts up 16 bits. 3030 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG); 3031 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd); 3032 } else if (Op.getValueType() == MVT::v8i16) { 3033 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3034 3035 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG); 3036 3037 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 3038 LHS, RHS, Zero, DAG); 3039 } else if (Op.getValueType() == MVT::v16i8) { 3040 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3041 3042 // Multiply the even 8-bit parts, producing 16-bit sums. 3043 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 3044 LHS, RHS, DAG, MVT::v8i16); 3045 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts); 3046 3047 // Multiply the odd 8-bit parts, producing 16-bit sums. 3048 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 3049 LHS, RHS, DAG, MVT::v8i16); 3050 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts); 3051 3052 // Merge the results together. 3053 SDOperand Ops[16]; 3054 for (unsigned i = 0; i != 8; ++i) { 3055 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8); 3056 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8); 3057 } 3058 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts, 3059 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16)); 3060 } else { 3061 assert(0 && "Unknown mul to lower!"); 3062 abort(); 3063 } 3064} 3065 3066/// LowerOperation - Provide custom lowering hooks for some operations. 3067/// 3068SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 3069 switch (Op.getOpcode()) { 3070 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3071 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 3072 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 3073 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 3074 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 3075 case ISD::SETCC: return LowerSETCC(Op, DAG); 3076 case ISD::VASTART: 3077 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3078 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3079 3080 case ISD::VAARG: 3081 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset, 3082 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget); 3083 3084 case ISD::FORMAL_ARGUMENTS: 3085 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex, 3086 VarArgsStackOffset, VarArgsNumGPR, 3087 VarArgsNumFPR, PPCSubTarget); 3088 3089 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget); 3090 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine()); 3091 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 3092 case ISD::DYNAMIC_STACKALLOC: 3093 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 3094 3095 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 3096 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 3097 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 3098 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG); 3099 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 3100 3101 // Lower 64-bit shifts. 3102 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 3103 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 3104 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 3105 3106 // Vector-related lowering. 3107 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 3108 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 3109 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 3110 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 3111 case ISD::MUL: return LowerMUL(Op, DAG); 3112 3113 // Frame & Return address. 3114 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 3115 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 3116 } 3117 return SDOperand(); 3118} 3119 3120SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) { 3121 switch (N->getOpcode()) { 3122 default: assert(0 && "Wasn't expecting to be able to lower this!"); 3123 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val; 3124 } 3125} 3126 3127 3128//===----------------------------------------------------------------------===// 3129// Other Lowering Code 3130//===----------------------------------------------------------------------===// 3131 3132MachineBasicBlock * 3133PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 3134 MachineBasicBlock *BB) { 3135 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 3136 assert((MI->getOpcode() == PPC::SELECT_CC_I4 || 3137 MI->getOpcode() == PPC::SELECT_CC_I8 || 3138 MI->getOpcode() == PPC::SELECT_CC_F4 || 3139 MI->getOpcode() == PPC::SELECT_CC_F8 || 3140 MI->getOpcode() == PPC::SELECT_CC_VRRC) && 3141 "Unexpected instr type to insert"); 3142 3143 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 3144 // control-flow pattern. The incoming instruction knows the destination vreg 3145 // to set, the condition code register to branch on, the true/false values to 3146 // select between, and a branch opcode to use. 3147 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 3148 ilist<MachineBasicBlock>::iterator It = BB; 3149 ++It; 3150 3151 // thisMBB: 3152 // ... 3153 // TrueVal = ... 3154 // cmpTY ccX, r1, r2 3155 // bCC copy1MBB 3156 // fallthrough --> copy0MBB 3157 MachineBasicBlock *thisMBB = BB; 3158 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 3159 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 3160 unsigned SelectPred = MI->getOperand(4).getImm(); 3161 BuildMI(BB, TII->get(PPC::BCC)) 3162 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 3163 MachineFunction *F = BB->getParent(); 3164 F->getBasicBlockList().insert(It, copy0MBB); 3165 F->getBasicBlockList().insert(It, sinkMBB); 3166 // Update machine-CFG edges by first adding all successors of the current 3167 // block to the new block which will contain the Phi node for the select. 3168 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 3169 e = BB->succ_end(); i != e; ++i) 3170 sinkMBB->addSuccessor(*i); 3171 // Next, remove all successors of the current block, and add the true 3172 // and fallthrough blocks as its successors. 3173 while(!BB->succ_empty()) 3174 BB->removeSuccessor(BB->succ_begin()); 3175 BB->addSuccessor(copy0MBB); 3176 BB->addSuccessor(sinkMBB); 3177 3178 // copy0MBB: 3179 // %FalseValue = ... 3180 // # fallthrough to sinkMBB 3181 BB = copy0MBB; 3182 3183 // Update machine-CFG edges 3184 BB->addSuccessor(sinkMBB); 3185 3186 // sinkMBB: 3187 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 3188 // ... 3189 BB = sinkMBB; 3190 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 3191 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 3192 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 3193 3194 delete MI; // The pseudo instruction is gone now. 3195 return BB; 3196} 3197 3198//===----------------------------------------------------------------------===// 3199// Target Optimization Hooks 3200//===----------------------------------------------------------------------===// 3201 3202SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 3203 DAGCombinerInfo &DCI) const { 3204 TargetMachine &TM = getTargetMachine(); 3205 SelectionDAG &DAG = DCI.DAG; 3206 switch (N->getOpcode()) { 3207 default: break; 3208 case PPCISD::SHL: 3209 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3210 if (C->getValue() == 0) // 0 << V -> 0. 3211 return N->getOperand(0); 3212 } 3213 break; 3214 case PPCISD::SRL: 3215 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3216 if (C->getValue() == 0) // 0 >>u V -> 0. 3217 return N->getOperand(0); 3218 } 3219 break; 3220 case PPCISD::SRA: 3221 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 3222 if (C->getValue() == 0 || // 0 >>s V -> 0. 3223 C->isAllOnesValue()) // -1 >>s V -> -1. 3224 return N->getOperand(0); 3225 } 3226 break; 3227 3228 case ISD::SINT_TO_FP: 3229 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 3230 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 3231 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 3232 // We allow the src/dst to be either f32/f64, but the intermediate 3233 // type must be i64. 3234 if (N->getOperand(0).getValueType() == MVT::i64 && 3235 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 3236 SDOperand Val = N->getOperand(0).getOperand(0); 3237 if (Val.getValueType() == MVT::f32) { 3238 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3239 DCI.AddToWorklist(Val.Val); 3240 } 3241 3242 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 3243 DCI.AddToWorklist(Val.Val); 3244 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 3245 DCI.AddToWorklist(Val.Val); 3246 if (N->getValueType(0) == MVT::f32) { 3247 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val, 3248 DAG.getIntPtrConstant(0)); 3249 DCI.AddToWorklist(Val.Val); 3250 } 3251 return Val; 3252 } else if (N->getOperand(0).getValueType() == MVT::i32) { 3253 // If the intermediate type is i32, we can avoid the load/store here 3254 // too. 3255 } 3256 } 3257 } 3258 break; 3259 case ISD::STORE: 3260 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 3261 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 3262 !cast<StoreSDNode>(N)->isTruncatingStore() && 3263 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 3264 N->getOperand(1).getValueType() == MVT::i32 && 3265 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 3266 SDOperand Val = N->getOperand(1).getOperand(0); 3267 if (Val.getValueType() == MVT::f32) { 3268 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 3269 DCI.AddToWorklist(Val.Val); 3270 } 3271 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 3272 DCI.AddToWorklist(Val.Val); 3273 3274 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 3275 N->getOperand(2), N->getOperand(3)); 3276 DCI.AddToWorklist(Val.Val); 3277 return Val; 3278 } 3279 3280 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 3281 if (N->getOperand(1).getOpcode() == ISD::BSWAP && 3282 N->getOperand(1).Val->hasOneUse() && 3283 (N->getOperand(1).getValueType() == MVT::i32 || 3284 N->getOperand(1).getValueType() == MVT::i16)) { 3285 SDOperand BSwapOp = N->getOperand(1).getOperand(0); 3286 // Do an any-extend to 32-bits if this is a half-word input. 3287 if (BSwapOp.getValueType() == MVT::i16) 3288 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp); 3289 3290 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp, 3291 N->getOperand(2), N->getOperand(3), 3292 DAG.getValueType(N->getOperand(1).getValueType())); 3293 } 3294 break; 3295 case ISD::BSWAP: 3296 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 3297 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) && 3298 N->getOperand(0).hasOneUse() && 3299 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 3300 SDOperand Load = N->getOperand(0); 3301 LoadSDNode *LD = cast<LoadSDNode>(Load); 3302 // Create the byte-swapping load. 3303 std::vector<MVT::ValueType> VTs; 3304 VTs.push_back(MVT::i32); 3305 VTs.push_back(MVT::Other); 3306 SDOperand MO = DAG.getMemOperand(LD->getMemOperand()); 3307 SDOperand Ops[] = { 3308 LD->getChain(), // Chain 3309 LD->getBasePtr(), // Ptr 3310 MO, // MemOperand 3311 DAG.getValueType(N->getValueType(0)) // VT 3312 }; 3313 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4); 3314 3315 // If this is an i16 load, insert the truncate. 3316 SDOperand ResVal = BSLoad; 3317 if (N->getValueType(0) == MVT::i16) 3318 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad); 3319 3320 // First, combine the bswap away. This makes the value produced by the 3321 // load dead. 3322 DCI.CombineTo(N, ResVal); 3323 3324 // Next, combine the load away, we give it a bogus result value but a real 3325 // chain result. The result value is dead because the bswap is dead. 3326 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1)); 3327 3328 // Return N so it doesn't get rechecked! 3329 return SDOperand(N, 0); 3330 } 3331 3332 break; 3333 case PPCISD::VCMP: { 3334 // If a VCMPo node already exists with exactly the same operands as this 3335 // node, use its result instead of this node (VCMPo computes both a CR6 and 3336 // a normal output). 3337 // 3338 if (!N->getOperand(0).hasOneUse() && 3339 !N->getOperand(1).hasOneUse() && 3340 !N->getOperand(2).hasOneUse()) { 3341 3342 // Scan all of the users of the LHS, looking for VCMPo's that match. 3343 SDNode *VCMPoNode = 0; 3344 3345 SDNode *LHSN = N->getOperand(0).Val; 3346 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 3347 UI != E; ++UI) 3348 if ((*UI)->getOpcode() == PPCISD::VCMPo && 3349 (*UI)->getOperand(1) == N->getOperand(1) && 3350 (*UI)->getOperand(2) == N->getOperand(2) && 3351 (*UI)->getOperand(0) == N->getOperand(0)) { 3352 VCMPoNode = *UI; 3353 break; 3354 } 3355 3356 // If there is no VCMPo node, or if the flag value has a single use, don't 3357 // transform this. 3358 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 3359 break; 3360 3361 // Look at the (necessarily single) use of the flag value. If it has a 3362 // chain, this transformation is more complex. Note that multiple things 3363 // could use the value result, which we should ignore. 3364 SDNode *FlagUser = 0; 3365 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 3366 FlagUser == 0; ++UI) { 3367 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 3368 SDNode *User = *UI; 3369 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 3370 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) { 3371 FlagUser = User; 3372 break; 3373 } 3374 } 3375 } 3376 3377 // If the user is a MFCR instruction, we know this is safe. Otherwise we 3378 // give up for right now. 3379 if (FlagUser->getOpcode() == PPCISD::MFCR) 3380 return SDOperand(VCMPoNode, 0); 3381 } 3382 break; 3383 } 3384 case ISD::BR_CC: { 3385 // If this is a branch on an altivec predicate comparison, lower this so 3386 // that we don't have to do a MFCR: instead, branch directly on CR6. This 3387 // lowering is done pre-legalize, because the legalizer lowers the predicate 3388 // compare down to code that is difficult to reassemble. 3389 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 3390 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3); 3391 int CompareOpc; 3392 bool isDot; 3393 3394 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 3395 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 3396 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 3397 assert(isDot && "Can't compare against a vector result!"); 3398 3399 // If this is a comparison against something other than 0/1, then we know 3400 // that the condition is never/always true. 3401 unsigned Val = cast<ConstantSDNode>(RHS)->getValue(); 3402 if (Val != 0 && Val != 1) { 3403 if (CC == ISD::SETEQ) // Cond never true, remove branch. 3404 return N->getOperand(0); 3405 // Always !=, turn it into an unconditional branch. 3406 return DAG.getNode(ISD::BR, MVT::Other, 3407 N->getOperand(0), N->getOperand(4)); 3408 } 3409 3410 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 3411 3412 // Create the PPCISD altivec 'dot' comparison node. 3413 std::vector<MVT::ValueType> VTs; 3414 SDOperand Ops[] = { 3415 LHS.getOperand(2), // LHS of compare 3416 LHS.getOperand(3), // RHS of compare 3417 DAG.getConstant(CompareOpc, MVT::i32) 3418 }; 3419 VTs.push_back(LHS.getOperand(2).getValueType()); 3420 VTs.push_back(MVT::Flag); 3421 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3); 3422 3423 // Unpack the result based on how the target uses it. 3424 PPC::Predicate CompOpc; 3425 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) { 3426 default: // Can't happen, don't crash on invalid number though. 3427 case 0: // Branch on the value of the EQ bit of CR6. 3428 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 3429 break; 3430 case 1: // Branch on the inverted value of the EQ bit of CR6. 3431 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 3432 break; 3433 case 2: // Branch on the value of the LT bit of CR6. 3434 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 3435 break; 3436 case 3: // Branch on the inverted value of the LT bit of CR6. 3437 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 3438 break; 3439 } 3440 3441 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0), 3442 DAG.getConstant(CompOpc, MVT::i32), 3443 DAG.getRegister(PPC::CR6, MVT::i32), 3444 N->getOperand(4), CompNode.getValue(1)); 3445 } 3446 break; 3447 } 3448 } 3449 3450 return SDOperand(); 3451} 3452 3453//===----------------------------------------------------------------------===// 3454// Inline Assembly Support 3455//===----------------------------------------------------------------------===// 3456 3457void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 3458 uint64_t Mask, 3459 uint64_t &KnownZero, 3460 uint64_t &KnownOne, 3461 const SelectionDAG &DAG, 3462 unsigned Depth) const { 3463 KnownZero = 0; 3464 KnownOne = 0; 3465 switch (Op.getOpcode()) { 3466 default: break; 3467 case PPCISD::LBRX: { 3468 // lhbrx is known to have the top bits cleared out. 3469 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) 3470 KnownZero = 0xFFFF0000; 3471 break; 3472 } 3473 case ISD::INTRINSIC_WO_CHAIN: { 3474 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) { 3475 default: break; 3476 case Intrinsic::ppc_altivec_vcmpbfp_p: 3477 case Intrinsic::ppc_altivec_vcmpeqfp_p: 3478 case Intrinsic::ppc_altivec_vcmpequb_p: 3479 case Intrinsic::ppc_altivec_vcmpequh_p: 3480 case Intrinsic::ppc_altivec_vcmpequw_p: 3481 case Intrinsic::ppc_altivec_vcmpgefp_p: 3482 case Intrinsic::ppc_altivec_vcmpgtfp_p: 3483 case Intrinsic::ppc_altivec_vcmpgtsb_p: 3484 case Intrinsic::ppc_altivec_vcmpgtsh_p: 3485 case Intrinsic::ppc_altivec_vcmpgtsw_p: 3486 case Intrinsic::ppc_altivec_vcmpgtub_p: 3487 case Intrinsic::ppc_altivec_vcmpgtuh_p: 3488 case Intrinsic::ppc_altivec_vcmpgtuw_p: 3489 KnownZero = ~1U; // All bits but the low one are known to be zero. 3490 break; 3491 } 3492 } 3493 } 3494} 3495 3496 3497/// getConstraintType - Given a constraint, return the type of 3498/// constraint it is for this target. 3499PPCTargetLowering::ConstraintType 3500PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 3501 if (Constraint.size() == 1) { 3502 switch (Constraint[0]) { 3503 default: break; 3504 case 'b': 3505 case 'r': 3506 case 'f': 3507 case 'v': 3508 case 'y': 3509 return C_RegisterClass; 3510 } 3511 } 3512 return TargetLowering::getConstraintType(Constraint); 3513} 3514 3515std::pair<unsigned, const TargetRegisterClass*> 3516PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3517 MVT::ValueType VT) const { 3518 if (Constraint.size() == 1) { 3519 // GCC RS6000 Constraint Letters 3520 switch (Constraint[0]) { 3521 case 'b': // R1-R31 3522 case 'r': // R0-R31 3523 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 3524 return std::make_pair(0U, PPC::G8RCRegisterClass); 3525 return std::make_pair(0U, PPC::GPRCRegisterClass); 3526 case 'f': 3527 if (VT == MVT::f32) 3528 return std::make_pair(0U, PPC::F4RCRegisterClass); 3529 else if (VT == MVT::f64) 3530 return std::make_pair(0U, PPC::F8RCRegisterClass); 3531 break; 3532 case 'v': 3533 return std::make_pair(0U, PPC::VRRCRegisterClass); 3534 case 'y': // crrc 3535 return std::make_pair(0U, PPC::CRRCRegisterClass); 3536 } 3537 } 3538 3539 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3540} 3541 3542 3543/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3544/// vector. If it is invalid, don't add anything to Ops. 3545void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter, 3546 std::vector<SDOperand>&Ops, 3547 SelectionDAG &DAG) { 3548 SDOperand Result(0,0); 3549 switch (Letter) { 3550 default: break; 3551 case 'I': 3552 case 'J': 3553 case 'K': 3554 case 'L': 3555 case 'M': 3556 case 'N': 3557 case 'O': 3558 case 'P': { 3559 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 3560 if (!CST) return; // Must be an immediate to match. 3561 unsigned Value = CST->getValue(); 3562 switch (Letter) { 3563 default: assert(0 && "Unknown constraint letter!"); 3564 case 'I': // "I" is a signed 16-bit constant. 3565 if ((short)Value == (int)Value) 3566 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3567 break; 3568 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 3569 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 3570 if ((short)Value == 0) 3571 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3572 break; 3573 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 3574 if ((Value >> 16) == 0) 3575 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3576 break; 3577 case 'M': // "M" is a constant that is greater than 31. 3578 if (Value > 31) 3579 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3580 break; 3581 case 'N': // "N" is a positive constant that is an exact power of two. 3582 if ((int)Value > 0 && isPowerOf2_32(Value)) 3583 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3584 break; 3585 case 'O': // "O" is the constant zero. 3586 if (Value == 0) 3587 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3588 break; 3589 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 3590 if ((short)-Value == (int)-Value) 3591 Result = DAG.getTargetConstant(Value, Op.getValueType()); 3592 break; 3593 } 3594 break; 3595 } 3596 } 3597 3598 if (Result.Val) { 3599 Ops.push_back(Result); 3600 return; 3601 } 3602 3603 // Handle standard constraint letters. 3604 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); 3605} 3606 3607// isLegalAddressingMode - Return true if the addressing mode represented 3608// by AM is legal for this target, for a load/store of the specified type. 3609bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3610 const Type *Ty) const { 3611 // FIXME: PPC does not allow r+i addressing modes for vectors! 3612 3613 // PPC allows a sign-extended 16-bit immediate field. 3614 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 3615 return false; 3616 3617 // No global is ever allowed as a base. 3618 if (AM.BaseGV) 3619 return false; 3620 3621 // PPC only support r+r, 3622 switch (AM.Scale) { 3623 case 0: // "r+i" or just "i", depending on HasBaseReg. 3624 break; 3625 case 1: 3626 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 3627 return false; 3628 // Otherwise we have r+r or r+i. 3629 break; 3630 case 2: 3631 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 3632 return false; 3633 // Allow 2*r as r+r. 3634 break; 3635 default: 3636 // No other scales are supported. 3637 return false; 3638 } 3639 3640 return true; 3641} 3642 3643/// isLegalAddressImmediate - Return true if the integer value can be used 3644/// as the offset of the target addressing mode for load / store of the 3645/// given type. 3646bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 3647 // PPC allows a sign-extended 16-bit immediate field. 3648 return (V > -(1 << 16) && V < (1 << 16)-1); 3649} 3650 3651bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 3652 return false; 3653} 3654 3655SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) { 3656 // Depths > 0 not supported yet! 3657 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3658 return SDOperand(); 3659 3660 MachineFunction &MF = DAG.getMachineFunction(); 3661 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 3662 int RAIdx = FuncInfo->getReturnAddrSaveIndex(); 3663 if (RAIdx == 0) { 3664 bool isPPC64 = PPCSubTarget.isPPC64(); 3665 int Offset = 3666 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI()); 3667 3668 // Set up a frame object for the return address. 3669 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset); 3670 3671 // Remember it for next time. 3672 FuncInfo->setReturnAddrSaveIndex(RAIdx); 3673 3674 // Make sure the function really does not optimize away the store of the RA 3675 // to the stack. 3676 FuncInfo->setLRStoreRequired(); 3677 } 3678 3679 // Just load the return address off the stack. 3680 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy()); 3681 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0); 3682} 3683 3684SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) { 3685 // Depths > 0 not supported yet! 3686 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0) 3687 return SDOperand(); 3688 3689 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3690 bool isPPC64 = PtrVT == MVT::i64; 3691 3692 MachineFunction &MF = DAG.getMachineFunction(); 3693 MachineFrameInfo *MFI = MF.getFrameInfo(); 3694 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects()) 3695 && MFI->getStackSize(); 3696 3697 if (isPPC64) 3698 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1, 3699 MVT::i64); 3700 else 3701 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1, 3702 MVT::i32); 3703} 3704