PPCISelLowering.cpp revision 258c58cc6257cf61c9bdbb9c4cea67ba2691adf0
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPerfectShuffle.h" 17#include "PPCPredicates.h" 18#include "PPCTargetMachine.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 29#include "llvm/CallingConv.h" 30#include "llvm/Constants.h" 31#include "llvm/Function.h" 32#include "llvm/Intrinsics.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/DerivedTypes.h" 39using namespace llvm; 40 41static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 42 CCValAssign::LocInfo &LocInfo, 43 ISD::ArgFlagsTy &ArgFlags, 44 CCState &State); 45static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, 46 EVT &LocVT, 47 CCValAssign::LocInfo &LocInfo, 48 ISD::ArgFlagsTy &ArgFlags, 49 CCState &State); 50static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, 51 EVT &LocVT, 52 CCValAssign::LocInfo &LocInfo, 53 ISD::ArgFlagsTy &ArgFlags, 54 CCState &State); 55 56static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 57cl::desc("enable preincrement load/store generation on PPC (experimental)"), 58 cl::Hidden); 59 60static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 61 if (TM.getSubtargetImpl()->isDarwin()) 62 return new TargetLoweringObjectFileMachO(); 63 64 return new TargetLoweringObjectFileELF(); 65} 66 67PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 69 70 setPow2DivIsCheap(); 71 72 // Use _setjmp/_longjmp instead of setjmp/longjmp. 73 setUseUnderscoreSetJmp(true); 74 setUseUnderscoreLongJmp(true); 75 76 // Set up the register classes. 77 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 78 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 79 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 80 81 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 83 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 84 85 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 86 87 // PowerPC has pre-inc load and store's. 88 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 89 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 90 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 91 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 92 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 98 99 // This is used in the ppcf128->int sequence. Note it has different semantics 100 // from FP_ROUND: that rounds to nearest, this rounds to zero. 101 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 102 103 // PowerPC has no SREM/UREM instructions 104 setOperationAction(ISD::SREM, MVT::i32, Expand); 105 setOperationAction(ISD::UREM, MVT::i32, Expand); 106 setOperationAction(ISD::SREM, MVT::i64, Expand); 107 setOperationAction(ISD::UREM, MVT::i64, Expand); 108 109 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 110 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 111 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 112 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 113 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 114 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 115 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 116 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 117 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 118 119 // We don't support sin/cos/sqrt/fmod/pow 120 setOperationAction(ISD::FSIN , MVT::f64, Expand); 121 setOperationAction(ISD::FCOS , MVT::f64, Expand); 122 setOperationAction(ISD::FREM , MVT::f64, Expand); 123 setOperationAction(ISD::FPOW , MVT::f64, Expand); 124 setOperationAction(ISD::FSIN , MVT::f32, Expand); 125 setOperationAction(ISD::FCOS , MVT::f32, Expand); 126 setOperationAction(ISD::FREM , MVT::f32, Expand); 127 setOperationAction(ISD::FPOW , MVT::f32, Expand); 128 129 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 130 131 // If we're enabling GP optimizations, use hardware square root 132 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 133 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 134 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 135 } 136 137 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 138 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 139 140 // PowerPC does not have BSWAP, CTPOP or CTTZ 141 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 142 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 143 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 144 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 145 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 146 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 147 148 // PowerPC does not have ROTR 149 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 150 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 151 152 // PowerPC does not have Select 153 setOperationAction(ISD::SELECT, MVT::i32, Expand); 154 setOperationAction(ISD::SELECT, MVT::i64, Expand); 155 setOperationAction(ISD::SELECT, MVT::f32, Expand); 156 setOperationAction(ISD::SELECT, MVT::f64, Expand); 157 158 // PowerPC wants to turn select_cc of FP into fsel when possible. 159 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 160 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 161 162 // PowerPC wants to optimize integer setcc a bit 163 setOperationAction(ISD::SETCC, MVT::i32, Custom); 164 165 // PowerPC does not have BRCOND which requires SetCC 166 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 167 168 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 169 170 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 171 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 172 173 // PowerPC does not have [U|S]INT_TO_FP 174 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 175 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 176 177 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 178 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 179 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 180 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 181 182 // We cannot sextinreg(i1). Expand to shifts. 183 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 184 185 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 186 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 187 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 188 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 189 190 191 // We want to legalize GlobalAddress and ConstantPool nodes into the 192 // appropriate instructions to materialize the address. 193 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 194 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 195 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 197 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 198 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 199 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 200 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 201 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 202 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 203 204 // TRAP is legal. 205 setOperationAction(ISD::TRAP, MVT::Other, Legal); 206 207 // TRAMPOLINE is custom lowered. 208 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 209 210 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 211 setOperationAction(ISD::VASTART , MVT::Other, Custom); 212 213 // VAARG is custom lowered with the 32-bit SVR4 ABI. 214 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 215 && !TM.getSubtarget<PPCSubtarget>().isPPC64()) 216 setOperationAction(ISD::VAARG, MVT::Other, Custom); 217 else 218 setOperationAction(ISD::VAARG, MVT::Other, Expand); 219 220 // Use the default implementation. 221 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 222 setOperationAction(ISD::VAEND , MVT::Other, Expand); 223 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 224 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 225 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 227 228 // We want to custom lower some of our intrinsics. 229 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 230 231 // Comparisons that require checking two conditions. 232 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 233 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 234 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 235 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 236 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 237 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 238 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 239 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 240 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 241 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 242 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 243 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 244 245 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 246 // They also have instructions for converting between i64 and fp. 247 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 248 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 249 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 250 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 251 // This is just the low 32 bits of a (signed) fp->i64 conversion. 252 // We cannot do this with Promote because i64 is not a legal type. 253 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 254 255 // FIXME: disable this lowered code. This generates 64-bit register values, 256 // and we don't model the fact that the top part is clobbered by calls. We 257 // need to flag these together so that the value isn't live across a call. 258 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 259 } else { 260 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 261 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 262 } 263 264 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 265 // 64-bit PowerPC implementations can support i64 types directly 266 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 267 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 268 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 269 // 64-bit PowerPC wants to expand i128 shifts itself. 270 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 271 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 272 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 273 } else { 274 // 32-bit PowerPC wants to expand i64 shifts itself. 275 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 276 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 277 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 278 } 279 280 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 281 // First set operation action for all vector types to expand. Then we 282 // will selectively turn on ones that can be effectively codegen'd. 283 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 284 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 285 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 286 287 // add/sub are legal for all supported vector VT's. 288 setOperationAction(ISD::ADD , VT, Legal); 289 setOperationAction(ISD::SUB , VT, Legal); 290 291 // We promote all shuffles to v16i8. 292 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 293 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 294 295 // We promote all non-typed operations to v4i32. 296 setOperationAction(ISD::AND , VT, Promote); 297 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 298 setOperationAction(ISD::OR , VT, Promote); 299 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 300 setOperationAction(ISD::XOR , VT, Promote); 301 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 302 setOperationAction(ISD::LOAD , VT, Promote); 303 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 304 setOperationAction(ISD::SELECT, VT, Promote); 305 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 306 setOperationAction(ISD::STORE, VT, Promote); 307 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 308 309 // No other operations are legal. 310 setOperationAction(ISD::MUL , VT, Expand); 311 setOperationAction(ISD::SDIV, VT, Expand); 312 setOperationAction(ISD::SREM, VT, Expand); 313 setOperationAction(ISD::UDIV, VT, Expand); 314 setOperationAction(ISD::UREM, VT, Expand); 315 setOperationAction(ISD::FDIV, VT, Expand); 316 setOperationAction(ISD::FNEG, VT, Expand); 317 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 318 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 319 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 320 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 321 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 322 setOperationAction(ISD::UDIVREM, VT, Expand); 323 setOperationAction(ISD::SDIVREM, VT, Expand); 324 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 325 setOperationAction(ISD::FPOW, VT, Expand); 326 setOperationAction(ISD::CTPOP, VT, Expand); 327 setOperationAction(ISD::CTLZ, VT, Expand); 328 setOperationAction(ISD::CTTZ, VT, Expand); 329 } 330 331 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 332 // with merges, splats, etc. 333 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 334 335 setOperationAction(ISD::AND , MVT::v4i32, Legal); 336 setOperationAction(ISD::OR , MVT::v4i32, Legal); 337 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 338 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 339 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 340 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 341 342 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 343 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 344 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 345 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 346 347 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 348 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 349 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 350 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 351 352 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 353 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 354 355 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 356 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 357 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 358 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 359 } 360 361 setShiftAmountType(MVT::i32); 362 setBooleanContents(ZeroOrOneBooleanContent); 363 364 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 365 setStackPointerRegisterToSaveRestore(PPC::X1); 366 setExceptionPointerRegister(PPC::X3); 367 setExceptionSelectorRegister(PPC::X4); 368 } else { 369 setStackPointerRegisterToSaveRestore(PPC::R1); 370 setExceptionPointerRegister(PPC::R3); 371 setExceptionSelectorRegister(PPC::R4); 372 } 373 374 // We have target-specific dag combine patterns for the following nodes: 375 setTargetDAGCombine(ISD::SINT_TO_FP); 376 setTargetDAGCombine(ISD::STORE); 377 setTargetDAGCombine(ISD::BR_CC); 378 setTargetDAGCombine(ISD::BSWAP); 379 380 // Darwin long double math library functions have $LDBL128 appended. 381 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 382 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 383 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 384 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 385 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 386 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 387 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 388 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 389 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 390 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 391 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 392 } 393 394 computeRegisterProperties(); 395} 396 397/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 398/// function arguments in the caller parameter area. 399unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { 400 const TargetMachine &TM = getTargetMachine(); 401 // Darwin passes everything on 4 byte boundary. 402 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 403 return 4; 404 // FIXME SVR4 TBD 405 return 4; 406} 407 408const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 409 switch (Opcode) { 410 default: return 0; 411 case PPCISD::FSEL: return "PPCISD::FSEL"; 412 case PPCISD::FCFID: return "PPCISD::FCFID"; 413 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 414 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 415 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 416 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 417 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 418 case PPCISD::VPERM: return "PPCISD::VPERM"; 419 case PPCISD::Hi: return "PPCISD::Hi"; 420 case PPCISD::Lo: return "PPCISD::Lo"; 421 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 422 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 423 case PPCISD::LOAD: return "PPCISD::LOAD"; 424 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 425 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 426 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 427 case PPCISD::SRL: return "PPCISD::SRL"; 428 case PPCISD::SRA: return "PPCISD::SRA"; 429 case PPCISD::SHL: return "PPCISD::SHL"; 430 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 431 case PPCISD::STD_32: return "PPCISD::STD_32"; 432 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 433 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 434 case PPCISD::NOP: return "PPCISD::NOP"; 435 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 436 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 437 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 438 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 439 case PPCISD::MFCR: return "PPCISD::MFCR"; 440 case PPCISD::VCMP: return "PPCISD::VCMP"; 441 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 442 case PPCISD::LBRX: return "PPCISD::LBRX"; 443 case PPCISD::STBRX: return "PPCISD::STBRX"; 444 case PPCISD::LARX: return "PPCISD::LARX"; 445 case PPCISD::STCX: return "PPCISD::STCX"; 446 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 447 case PPCISD::MFFS: return "PPCISD::MFFS"; 448 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 449 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 450 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 451 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 452 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 453 } 454} 455 456MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const { 457 return MVT::i32; 458} 459 460/// getFunctionAlignment - Return the Log2 alignment of this function. 461unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const { 462 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) 463 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4; 464 else 465 return 2; 466} 467 468//===----------------------------------------------------------------------===// 469// Node matching predicates, for use by the tblgen matching code. 470//===----------------------------------------------------------------------===// 471 472/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 473static bool isFloatingPointZero(SDValue Op) { 474 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 475 return CFP->getValueAPF().isZero(); 476 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 477 // Maybe this has already been legalized into the constant pool? 478 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 479 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 480 return CFP->getValueAPF().isZero(); 481 } 482 return false; 483} 484 485/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 486/// true if Op is undef or if it matches the specified value. 487static bool isConstantOrUndef(int Op, int Val) { 488 return Op < 0 || Op == Val; 489} 490 491/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 492/// VPKUHUM instruction. 493bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 494 if (!isUnary) { 495 for (unsigned i = 0; i != 16; ++i) 496 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 497 return false; 498 } else { 499 for (unsigned i = 0; i != 8; ++i) 500 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 501 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 502 return false; 503 } 504 return true; 505} 506 507/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 508/// VPKUWUM instruction. 509bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 510 if (!isUnary) { 511 for (unsigned i = 0; i != 16; i += 2) 512 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 513 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 514 return false; 515 } else { 516 for (unsigned i = 0; i != 8; i += 2) 517 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 518 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 519 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 520 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 521 return false; 522 } 523 return true; 524} 525 526/// isVMerge - Common function, used to match vmrg* shuffles. 527/// 528static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 529 unsigned LHSStart, unsigned RHSStart) { 530 assert(N->getValueType(0) == MVT::v16i8 && 531 "PPC only supports shuffles by bytes!"); 532 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 533 "Unsupported merge size!"); 534 535 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 536 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 537 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 538 LHSStart+j+i*UnitSize) || 539 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 540 RHSStart+j+i*UnitSize)) 541 return false; 542 } 543 return true; 544} 545 546/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 547/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 548bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 549 bool isUnary) { 550 if (!isUnary) 551 return isVMerge(N, UnitSize, 8, 24); 552 return isVMerge(N, UnitSize, 8, 8); 553} 554 555/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 556/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 557bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 558 bool isUnary) { 559 if (!isUnary) 560 return isVMerge(N, UnitSize, 0, 16); 561 return isVMerge(N, UnitSize, 0, 0); 562} 563 564 565/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 566/// amount, otherwise return -1. 567int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 568 assert(N->getValueType(0) == MVT::v16i8 && 569 "PPC only supports shuffles by bytes!"); 570 571 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 572 573 // Find the first non-undef value in the shuffle mask. 574 unsigned i; 575 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 576 /*search*/; 577 578 if (i == 16) return -1; // all undef. 579 580 // Otherwise, check to see if the rest of the elements are consecutively 581 // numbered from this value. 582 unsigned ShiftAmt = SVOp->getMaskElt(i); 583 if (ShiftAmt < i) return -1; 584 ShiftAmt -= i; 585 586 if (!isUnary) { 587 // Check the rest of the elements to see if they are consecutive. 588 for (++i; i != 16; ++i) 589 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 590 return -1; 591 } else { 592 // Check the rest of the elements to see if they are consecutive. 593 for (++i; i != 16; ++i) 594 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 595 return -1; 596 } 597 return ShiftAmt; 598} 599 600/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 601/// specifies a splat of a single element that is suitable for input to 602/// VSPLTB/VSPLTH/VSPLTW. 603bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 604 assert(N->getValueType(0) == MVT::v16i8 && 605 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 606 607 // This is a splat operation if each element of the permute is the same, and 608 // if the value doesn't reference the second vector. 609 unsigned ElementBase = N->getMaskElt(0); 610 611 // FIXME: Handle UNDEF elements too! 612 if (ElementBase >= 16) 613 return false; 614 615 // Check that the indices are consecutive, in the case of a multi-byte element 616 // splatted with a v16i8 mask. 617 for (unsigned i = 1; i != EltSize; ++i) 618 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 619 return false; 620 621 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 622 if (N->getMaskElt(i) < 0) continue; 623 for (unsigned j = 0; j != EltSize; ++j) 624 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 625 return false; 626 } 627 return true; 628} 629 630/// isAllNegativeZeroVector - Returns true if all elements of build_vector 631/// are -0.0. 632bool PPC::isAllNegativeZeroVector(SDNode *N) { 633 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 634 635 APInt APVal, APUndef; 636 unsigned BitSize; 637 bool HasAnyUndefs; 638 639 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 640 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 641 return CFP->getValueAPF().isNegZero(); 642 643 return false; 644} 645 646/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 647/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 648unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 649 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 650 assert(isSplatShuffleMask(SVOp, EltSize)); 651 return SVOp->getMaskElt(0) / EltSize; 652} 653 654/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 655/// by using a vspltis[bhw] instruction of the specified element size, return 656/// the constant being splatted. The ByteSize field indicates the number of 657/// bytes of each element [124] -> [bhw]. 658SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 659 SDValue OpVal(0, 0); 660 661 // If ByteSize of the splat is bigger than the element size of the 662 // build_vector, then we have a case where we are checking for a splat where 663 // multiple elements of the buildvector are folded together into a single 664 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 665 unsigned EltSize = 16/N->getNumOperands(); 666 if (EltSize < ByteSize) { 667 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 668 SDValue UniquedVals[4]; 669 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 670 671 // See if all of the elements in the buildvector agree across. 672 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 673 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 674 // If the element isn't a constant, bail fully out. 675 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 676 677 678 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 679 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 680 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 681 return SDValue(); // no match. 682 } 683 684 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 685 // either constant or undef values that are identical for each chunk. See 686 // if these chunks can form into a larger vspltis*. 687 688 // Check to see if all of the leading entries are either 0 or -1. If 689 // neither, then this won't fit into the immediate field. 690 bool LeadingZero = true; 691 bool LeadingOnes = true; 692 for (unsigned i = 0; i != Multiple-1; ++i) { 693 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 694 695 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 696 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 697 } 698 // Finally, check the least significant entry. 699 if (LeadingZero) { 700 if (UniquedVals[Multiple-1].getNode() == 0) 701 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 702 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 703 if (Val < 16) 704 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 705 } 706 if (LeadingOnes) { 707 if (UniquedVals[Multiple-1].getNode() == 0) 708 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 709 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 710 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 711 return DAG.getTargetConstant(Val, MVT::i32); 712 } 713 714 return SDValue(); 715 } 716 717 // Check to see if this buildvec has a single non-undef value in its elements. 718 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 719 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 720 if (OpVal.getNode() == 0) 721 OpVal = N->getOperand(i); 722 else if (OpVal != N->getOperand(i)) 723 return SDValue(); 724 } 725 726 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 727 728 unsigned ValSizeInBytes = EltSize; 729 uint64_t Value = 0; 730 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 731 Value = CN->getZExtValue(); 732 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 733 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 734 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 735 } 736 737 // If the splat value is larger than the element value, then we can never do 738 // this splat. The only case that we could fit the replicated bits into our 739 // immediate field for would be zero, and we prefer to use vxor for it. 740 if (ValSizeInBytes < ByteSize) return SDValue(); 741 742 // If the element value is larger than the splat value, cut it in half and 743 // check to see if the two halves are equal. Continue doing this until we 744 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 745 while (ValSizeInBytes > ByteSize) { 746 ValSizeInBytes >>= 1; 747 748 // If the top half equals the bottom half, we're still ok. 749 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 750 (Value & ((1 << (8*ValSizeInBytes))-1))) 751 return SDValue(); 752 } 753 754 // Properly sign extend the value. 755 int ShAmt = (4-ByteSize)*8; 756 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 757 758 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 759 if (MaskVal == 0) return SDValue(); 760 761 // Finally, if this value fits in a 5 bit sext field, return it 762 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 763 return DAG.getTargetConstant(MaskVal, MVT::i32); 764 return SDValue(); 765} 766 767//===----------------------------------------------------------------------===// 768// Addressing Mode Selection 769//===----------------------------------------------------------------------===// 770 771/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 772/// or 64-bit immediate, and if the value can be accurately represented as a 773/// sign extension from a 16-bit value. If so, this returns true and the 774/// immediate. 775static bool isIntS16Immediate(SDNode *N, short &Imm) { 776 if (N->getOpcode() != ISD::Constant) 777 return false; 778 779 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 780 if (N->getValueType(0) == MVT::i32) 781 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 782 else 783 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 784} 785static bool isIntS16Immediate(SDValue Op, short &Imm) { 786 return isIntS16Immediate(Op.getNode(), Imm); 787} 788 789 790/// SelectAddressRegReg - Given the specified addressed, check to see if it 791/// can be represented as an indexed [r+r] operation. Returns false if it 792/// can be more efficiently represented with [r+imm]. 793bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 794 SDValue &Index, 795 SelectionDAG &DAG) const { 796 short imm = 0; 797 if (N.getOpcode() == ISD::ADD) { 798 if (isIntS16Immediate(N.getOperand(1), imm)) 799 return false; // r+i 800 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 801 return false; // r+i 802 803 Base = N.getOperand(0); 804 Index = N.getOperand(1); 805 return true; 806 } else if (N.getOpcode() == ISD::OR) { 807 if (isIntS16Immediate(N.getOperand(1), imm)) 808 return false; // r+i can fold it if we can. 809 810 // If this is an or of disjoint bitfields, we can codegen this as an add 811 // (for better address arithmetic) if the LHS and RHS of the OR are provably 812 // disjoint. 813 APInt LHSKnownZero, LHSKnownOne; 814 APInt RHSKnownZero, RHSKnownOne; 815 DAG.ComputeMaskedBits(N.getOperand(0), 816 APInt::getAllOnesValue(N.getOperand(0) 817 .getValueSizeInBits()), 818 LHSKnownZero, LHSKnownOne); 819 820 if (LHSKnownZero.getBoolValue()) { 821 DAG.ComputeMaskedBits(N.getOperand(1), 822 APInt::getAllOnesValue(N.getOperand(1) 823 .getValueSizeInBits()), 824 RHSKnownZero, RHSKnownOne); 825 // If all of the bits are known zero on the LHS or RHS, the add won't 826 // carry. 827 if (~(LHSKnownZero | RHSKnownZero) == 0) { 828 Base = N.getOperand(0); 829 Index = N.getOperand(1); 830 return true; 831 } 832 } 833 } 834 835 return false; 836} 837 838/// Returns true if the address N can be represented by a base register plus 839/// a signed 16-bit displacement [r+imm], and if it is not better 840/// represented as reg+reg. 841bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 842 SDValue &Base, 843 SelectionDAG &DAG) const { 844 // FIXME dl should come from parent load or store, not from address 845 DebugLoc dl = N.getDebugLoc(); 846 // If this can be more profitably realized as r+r, fail. 847 if (SelectAddressRegReg(N, Disp, Base, DAG)) 848 return false; 849 850 if (N.getOpcode() == ISD::ADD) { 851 short imm = 0; 852 if (isIntS16Immediate(N.getOperand(1), imm)) { 853 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 854 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 855 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 856 } else { 857 Base = N.getOperand(0); 858 } 859 return true; // [r+i] 860 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 861 // Match LOAD (ADD (X, Lo(G))). 862 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 863 && "Cannot handle constant offsets yet!"); 864 Disp = N.getOperand(1).getOperand(0); // The global address. 865 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 866 Disp.getOpcode() == ISD::TargetConstantPool || 867 Disp.getOpcode() == ISD::TargetJumpTable); 868 Base = N.getOperand(0); 869 return true; // [&g+r] 870 } 871 } else if (N.getOpcode() == ISD::OR) { 872 short imm = 0; 873 if (isIntS16Immediate(N.getOperand(1), imm)) { 874 // If this is an or of disjoint bitfields, we can codegen this as an add 875 // (for better address arithmetic) if the LHS and RHS of the OR are 876 // provably disjoint. 877 APInt LHSKnownZero, LHSKnownOne; 878 DAG.ComputeMaskedBits(N.getOperand(0), 879 APInt::getAllOnesValue(N.getOperand(0) 880 .getValueSizeInBits()), 881 LHSKnownZero, LHSKnownOne); 882 883 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 884 // If all of the bits are known zero on the LHS or RHS, the add won't 885 // carry. 886 Base = N.getOperand(0); 887 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 888 return true; 889 } 890 } 891 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 892 // Loading from a constant address. 893 894 // If this address fits entirely in a 16-bit sext immediate field, codegen 895 // this as "d, 0" 896 short Imm; 897 if (isIntS16Immediate(CN, Imm)) { 898 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 899 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 900 return true; 901 } 902 903 // Handle 32-bit sext immediates with LIS + addr mode. 904 if (CN->getValueType(0) == MVT::i32 || 905 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 906 int Addr = (int)CN->getZExtValue(); 907 908 // Otherwise, break this down into an LIS + disp. 909 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 910 911 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 912 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 913 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 914 return true; 915 } 916 } 917 918 Disp = DAG.getTargetConstant(0, getPointerTy()); 919 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 920 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 921 else 922 Base = N; 923 return true; // [r+0] 924} 925 926/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 927/// represented as an indexed [r+r] operation. 928bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 929 SDValue &Index, 930 SelectionDAG &DAG) const { 931 // Check to see if we can easily represent this as an [r+r] address. This 932 // will fail if it thinks that the address is more profitably represented as 933 // reg+imm, e.g. where imm = 0. 934 if (SelectAddressRegReg(N, Base, Index, DAG)) 935 return true; 936 937 // If the operand is an addition, always emit this as [r+r], since this is 938 // better (for code size, and execution, as the memop does the add for free) 939 // than emitting an explicit add. 940 if (N.getOpcode() == ISD::ADD) { 941 Base = N.getOperand(0); 942 Index = N.getOperand(1); 943 return true; 944 } 945 946 // Otherwise, do it the hard way, using R0 as the base register. 947 Base = DAG.getRegister(PPC::R0, N.getValueType()); 948 Index = N; 949 return true; 950} 951 952/// SelectAddressRegImmShift - Returns true if the address N can be 953/// represented by a base register plus a signed 14-bit displacement 954/// [r+imm*4]. Suitable for use by STD and friends. 955bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 956 SDValue &Base, 957 SelectionDAG &DAG) const { 958 // FIXME dl should come from the parent load or store, not the address 959 DebugLoc dl = N.getDebugLoc(); 960 // If this can be more profitably realized as r+r, fail. 961 if (SelectAddressRegReg(N, Disp, Base, DAG)) 962 return false; 963 964 if (N.getOpcode() == ISD::ADD) { 965 short imm = 0; 966 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 967 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 968 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 969 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 970 } else { 971 Base = N.getOperand(0); 972 } 973 return true; // [r+i] 974 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 975 // Match LOAD (ADD (X, Lo(G))). 976 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 977 && "Cannot handle constant offsets yet!"); 978 Disp = N.getOperand(1).getOperand(0); // The global address. 979 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 980 Disp.getOpcode() == ISD::TargetConstantPool || 981 Disp.getOpcode() == ISD::TargetJumpTable); 982 Base = N.getOperand(0); 983 return true; // [&g+r] 984 } 985 } else if (N.getOpcode() == ISD::OR) { 986 short imm = 0; 987 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 988 // If this is an or of disjoint bitfields, we can codegen this as an add 989 // (for better address arithmetic) if the LHS and RHS of the OR are 990 // provably disjoint. 991 APInt LHSKnownZero, LHSKnownOne; 992 DAG.ComputeMaskedBits(N.getOperand(0), 993 APInt::getAllOnesValue(N.getOperand(0) 994 .getValueSizeInBits()), 995 LHSKnownZero, LHSKnownOne); 996 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 997 // If all of the bits are known zero on the LHS or RHS, the add won't 998 // carry. 999 Base = N.getOperand(0); 1000 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1001 return true; 1002 } 1003 } 1004 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1005 // Loading from a constant address. Verify low two bits are clear. 1006 if ((CN->getZExtValue() & 3) == 0) { 1007 // If this address fits entirely in a 14-bit sext immediate field, codegen 1008 // this as "d, 0" 1009 short Imm; 1010 if (isIntS16Immediate(CN, Imm)) { 1011 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1012 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 1013 return true; 1014 } 1015 1016 // Fold the low-part of 32-bit absolute addresses into addr mode. 1017 if (CN->getValueType(0) == MVT::i32 || 1018 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1019 int Addr = (int)CN->getZExtValue(); 1020 1021 // Otherwise, break this down into an LIS + disp. 1022 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1023 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1024 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1025 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1026 return true; 1027 } 1028 } 1029 } 1030 1031 Disp = DAG.getTargetConstant(0, getPointerTy()); 1032 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1033 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1034 else 1035 Base = N; 1036 return true; // [r+0] 1037} 1038 1039 1040/// getPreIndexedAddressParts - returns true by value, base pointer and 1041/// offset pointer and addressing mode by reference if the node's address 1042/// can be legally represented as pre-indexed load / store address. 1043bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1044 SDValue &Offset, 1045 ISD::MemIndexedMode &AM, 1046 SelectionDAG &DAG) const { 1047 // Disabled by default for now. 1048 if (!EnablePPCPreinc) return false; 1049 1050 SDValue Ptr; 1051 EVT VT; 1052 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1053 Ptr = LD->getBasePtr(); 1054 VT = LD->getMemoryVT(); 1055 1056 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1057 ST = ST; 1058 Ptr = ST->getBasePtr(); 1059 VT = ST->getMemoryVT(); 1060 } else 1061 return false; 1062 1063 // PowerPC doesn't have preinc load/store instructions for vectors. 1064 if (VT.isVector()) 1065 return false; 1066 1067 // TODO: Check reg+reg first. 1068 1069 // LDU/STU use reg+imm*4, others use reg+imm. 1070 if (VT != MVT::i64) { 1071 // reg + imm 1072 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1073 return false; 1074 } else { 1075 // reg + imm * 4. 1076 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1077 return false; 1078 } 1079 1080 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1081 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1082 // sext i32 to i64 when addr mode is r+i. 1083 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1084 LD->getExtensionType() == ISD::SEXTLOAD && 1085 isa<ConstantSDNode>(Offset)) 1086 return false; 1087 } 1088 1089 AM = ISD::PRE_INC; 1090 return true; 1091} 1092 1093//===----------------------------------------------------------------------===// 1094// LowerOperation implementation 1095//===----------------------------------------------------------------------===// 1096 1097SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1098 SelectionDAG &DAG) const { 1099 EVT PtrVT = Op.getValueType(); 1100 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1101 const Constant *C = CP->getConstVal(); 1102 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1103 SDValue Zero = DAG.getConstant(0, PtrVT); 1104 // FIXME there isn't really any debug info here 1105 DebugLoc dl = Op.getDebugLoc(); 1106 1107 const TargetMachine &TM = DAG.getTarget(); 1108 1109 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero); 1110 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero); 1111 1112 // If this is a non-darwin platform, we don't support non-static relo models 1113 // yet. 1114 if (TM.getRelocationModel() == Reloc::Static || 1115 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1116 // Generate non-pic code that has direct accesses to the constant pool. 1117 // The address of the global is just (hi(&g)+lo(&g)). 1118 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1119 } 1120 1121 if (TM.getRelocationModel() == Reloc::PIC_) { 1122 // With PIC, the first instruction is actually "GR+hi(&G)". 1123 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1124 DAG.getNode(PPCISD::GlobalBaseReg, 1125 DebugLoc(), PtrVT), Hi); 1126 } 1127 1128 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1129 return Lo; 1130} 1131 1132SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1133 EVT PtrVT = Op.getValueType(); 1134 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1135 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1136 SDValue Zero = DAG.getConstant(0, PtrVT); 1137 // FIXME there isn't really any debug loc here 1138 DebugLoc dl = Op.getDebugLoc(); 1139 1140 const TargetMachine &TM = DAG.getTarget(); 1141 1142 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero); 1143 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero); 1144 1145 // If this is a non-darwin platform, we don't support non-static relo models 1146 // yet. 1147 if (TM.getRelocationModel() == Reloc::Static || 1148 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1149 // Generate non-pic code that has direct accesses to the constant pool. 1150 // The address of the global is just (hi(&g)+lo(&g)). 1151 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1152 } 1153 1154 if (TM.getRelocationModel() == Reloc::PIC_) { 1155 // With PIC, the first instruction is actually "GR+hi(&G)". 1156 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1157 DAG.getNode(PPCISD::GlobalBaseReg, 1158 DebugLoc(), PtrVT), Hi); 1159 } 1160 1161 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1162 return Lo; 1163} 1164 1165SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1166 SelectionDAG &DAG) const { 1167 llvm_unreachable("TLS not implemented for PPC."); 1168 return SDValue(); // Not reached 1169} 1170 1171SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1172 SelectionDAG &DAG) const { 1173 EVT PtrVT = Op.getValueType(); 1174 DebugLoc DL = Op.getDebugLoc(); 1175 1176 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1177 SDValue TgtBA = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true); 1178 SDValue Zero = DAG.getConstant(0, PtrVT); 1179 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero); 1180 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero); 1181 1182 // If this is a non-darwin platform, we don't support non-static relo models 1183 // yet. 1184 const TargetMachine &TM = DAG.getTarget(); 1185 if (TM.getRelocationModel() == Reloc::Static || 1186 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1187 // Generate non-pic code that has direct accesses to globals. 1188 // The address of the global is just (hi(&g)+lo(&g)). 1189 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1190 } 1191 1192 if (TM.getRelocationModel() == Reloc::PIC_) { 1193 // With PIC, the first instruction is actually "GR+hi(&G)". 1194 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1195 DAG.getNode(PPCISD::GlobalBaseReg, 1196 DebugLoc(), PtrVT), Hi); 1197 } 1198 1199 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1200} 1201 1202SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1203 SelectionDAG &DAG) const { 1204 EVT PtrVT = Op.getValueType(); 1205 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1206 const GlobalValue *GV = GSDN->getGlobal(); 1207 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); 1208 SDValue Zero = DAG.getConstant(0, PtrVT); 1209 // FIXME there isn't really any debug info here 1210 DebugLoc dl = GSDN->getDebugLoc(); 1211 1212 const TargetMachine &TM = DAG.getTarget(); 1213 1214 // 64-bit SVR4 ABI code is always position-independent. 1215 // The actual address of the GlobalValue is stored in the TOC. 1216 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1217 return DAG.getNode(PPCISD::TOC_ENTRY, dl, MVT::i64, GA, 1218 DAG.getRegister(PPC::X2, MVT::i64)); 1219 } 1220 1221 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero); 1222 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero); 1223 1224 // If this is a non-darwin platform, we don't support non-static relo models 1225 // yet. 1226 if (TM.getRelocationModel() == Reloc::Static || 1227 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1228 // Generate non-pic code that has direct accesses to globals. 1229 // The address of the global is just (hi(&g)+lo(&g)). 1230 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1231 } 1232 1233 if (TM.getRelocationModel() == Reloc::PIC_) { 1234 // With PIC, the first instruction is actually "GR+hi(&G)". 1235 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1236 DAG.getNode(PPCISD::GlobalBaseReg, 1237 DebugLoc(), PtrVT), Hi); 1238 } 1239 1240 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1241 1242 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) 1243 return Lo; 1244 1245 // If the global is weak or external, we have to go through the lazy 1246 // resolution stub. 1247 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0, 1248 false, false, 0); 1249} 1250 1251SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1252 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1253 DebugLoc dl = Op.getDebugLoc(); 1254 1255 // If we're comparing for equality to zero, expose the fact that this is 1256 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1257 // fold the new nodes. 1258 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1259 if (C->isNullValue() && CC == ISD::SETEQ) { 1260 EVT VT = Op.getOperand(0).getValueType(); 1261 SDValue Zext = Op.getOperand(0); 1262 if (VT.bitsLT(MVT::i32)) { 1263 VT = MVT::i32; 1264 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1265 } 1266 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1267 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1268 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1269 DAG.getConstant(Log2b, MVT::i32)); 1270 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1271 } 1272 // Leave comparisons against 0 and -1 alone for now, since they're usually 1273 // optimized. FIXME: revisit this when we can custom lower all setcc 1274 // optimizations. 1275 if (C->isAllOnesValue() || C->isNullValue()) 1276 return SDValue(); 1277 } 1278 1279 // If we have an integer seteq/setne, turn it into a compare against zero 1280 // by xor'ing the rhs with the lhs, which is faster than setting a 1281 // condition register, reading it back out, and masking the correct bit. The 1282 // normal approach here uses sub to do this instead of xor. Using xor exposes 1283 // the result to other bit-twiddling opportunities. 1284 EVT LHSVT = Op.getOperand(0).getValueType(); 1285 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1286 EVT VT = Op.getValueType(); 1287 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1288 Op.getOperand(1)); 1289 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1290 } 1291 return SDValue(); 1292} 1293 1294SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1295 const PPCSubtarget &Subtarget) const { 1296 1297 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!"); 1298 return SDValue(); // Not reached 1299} 1300 1301SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, 1302 SelectionDAG &DAG) const { 1303 SDValue Chain = Op.getOperand(0); 1304 SDValue Trmp = Op.getOperand(1); // trampoline 1305 SDValue FPtr = Op.getOperand(2); // nested function 1306 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1307 DebugLoc dl = Op.getDebugLoc(); 1308 1309 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1310 bool isPPC64 = (PtrVT == MVT::i64); 1311 const Type *IntPtrTy = 1312 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType( 1313 *DAG.getContext()); 1314 1315 TargetLowering::ArgListTy Args; 1316 TargetLowering::ArgListEntry Entry; 1317 1318 Entry.Ty = IntPtrTy; 1319 Entry.Node = Trmp; Args.push_back(Entry); 1320 1321 // TrampSize == (isPPC64 ? 48 : 40); 1322 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1323 isPPC64 ? MVT::i64 : MVT::i32); 1324 Args.push_back(Entry); 1325 1326 Entry.Node = FPtr; Args.push_back(Entry); 1327 Entry.Node = Nest; Args.push_back(Entry); 1328 1329 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1330 std::pair<SDValue, SDValue> CallResult = 1331 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()), 1332 false, false, false, false, 0, CallingConv::C, false, 1333 /*isReturnValueUsed=*/true, 1334 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1335 Args, DAG, dl); 1336 1337 SDValue Ops[] = 1338 { CallResult.first, CallResult.second }; 1339 1340 return DAG.getMergeValues(Ops, 2, dl); 1341} 1342 1343SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1344 const PPCSubtarget &Subtarget) const { 1345 MachineFunction &MF = DAG.getMachineFunction(); 1346 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1347 1348 DebugLoc dl = Op.getDebugLoc(); 1349 1350 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1351 // vastart just stores the address of the VarArgsFrameIndex slot into the 1352 // memory location argument. 1353 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1354 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1355 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1356 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0, 1357 false, false, 0); 1358 } 1359 1360 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1361 // We suppose the given va_list is already allocated. 1362 // 1363 // typedef struct { 1364 // char gpr; /* index into the array of 8 GPRs 1365 // * stored in the register save area 1366 // * gpr=0 corresponds to r3, 1367 // * gpr=1 to r4, etc. 1368 // */ 1369 // char fpr; /* index into the array of 8 FPRs 1370 // * stored in the register save area 1371 // * fpr=0 corresponds to f1, 1372 // * fpr=1 to f2, etc. 1373 // */ 1374 // char *overflow_arg_area; 1375 // /* location on stack that holds 1376 // * the next overflow argument 1377 // */ 1378 // char *reg_save_area; 1379 // /* where r3:r10 and f1:f8 (if saved) 1380 // * are stored 1381 // */ 1382 // } va_list[1]; 1383 1384 1385 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1386 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1387 1388 1389 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1390 1391 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1392 PtrVT); 1393 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1394 PtrVT); 1395 1396 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1397 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1398 1399 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1400 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1401 1402 uint64_t FPROffset = 1; 1403 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1404 1405 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1406 1407 // Store first byte : number of int regs 1408 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1409 Op.getOperand(1), SV, 0, MVT::i8, 1410 false, false, 0); 1411 uint64_t nextOffset = FPROffset; 1412 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1413 ConstFPROffset); 1414 1415 // Store second byte : number of float regs 1416 SDValue secondStore = 1417 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8, 1418 false, false, 0); 1419 nextOffset += StackOffset; 1420 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1421 1422 // Store second word : arguments given on stack 1423 SDValue thirdStore = 1424 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset, 1425 false, false, 0); 1426 nextOffset += FrameOffset; 1427 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1428 1429 // Store third word : arguments given in registers 1430 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset, 1431 false, false, 0); 1432 1433} 1434 1435#include "PPCGenCallingConv.inc" 1436 1437static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 1438 CCValAssign::LocInfo &LocInfo, 1439 ISD::ArgFlagsTy &ArgFlags, 1440 CCState &State) { 1441 return true; 1442} 1443 1444static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, 1445 EVT &LocVT, 1446 CCValAssign::LocInfo &LocInfo, 1447 ISD::ArgFlagsTy &ArgFlags, 1448 CCState &State) { 1449 static const unsigned ArgRegs[] = { 1450 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1451 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1452 }; 1453 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1454 1455 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1456 1457 // Skip one register if the first unallocated register has an even register 1458 // number and there are still argument registers available which have not been 1459 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1460 // need to skip a register if RegNum is odd. 1461 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1462 State.AllocateReg(ArgRegs[RegNum]); 1463 } 1464 1465 // Always return false here, as this function only makes sure that the first 1466 // unallocated register has an odd register number and does not actually 1467 // allocate a register for the current argument. 1468 return false; 1469} 1470 1471static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, 1472 EVT &LocVT, 1473 CCValAssign::LocInfo &LocInfo, 1474 ISD::ArgFlagsTy &ArgFlags, 1475 CCState &State) { 1476 static const unsigned ArgRegs[] = { 1477 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1478 PPC::F8 1479 }; 1480 1481 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1482 1483 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1484 1485 // If there is only one Floating-point register left we need to put both f64 1486 // values of a split ppc_fp128 value on the stack. 1487 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1488 State.AllocateReg(ArgRegs[RegNum]); 1489 } 1490 1491 // Always return false here, as this function only makes sure that the two f64 1492 // values a ppc_fp128 value is split into are both passed in registers or both 1493 // passed on the stack and does not actually allocate a register for the 1494 // current argument. 1495 return false; 1496} 1497 1498/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1499/// on Darwin. 1500static const unsigned *GetFPR() { 1501 static const unsigned FPR[] = { 1502 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1503 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1504 }; 1505 1506 return FPR; 1507} 1508 1509/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1510/// the stack. 1511static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1512 unsigned PtrByteSize) { 1513 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1514 if (Flags.isByVal()) 1515 ArgSize = Flags.getByValSize(); 1516 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1517 1518 return ArgSize; 1519} 1520 1521SDValue 1522PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1523 CallingConv::ID CallConv, bool isVarArg, 1524 const SmallVectorImpl<ISD::InputArg> 1525 &Ins, 1526 DebugLoc dl, SelectionDAG &DAG, 1527 SmallVectorImpl<SDValue> &InVals) 1528 const { 1529 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 1530 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins, 1531 dl, DAG, InVals); 1532 } else { 1533 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1534 dl, DAG, InVals); 1535 } 1536} 1537 1538SDValue 1539PPCTargetLowering::LowerFormalArguments_SVR4( 1540 SDValue Chain, 1541 CallingConv::ID CallConv, bool isVarArg, 1542 const SmallVectorImpl<ISD::InputArg> 1543 &Ins, 1544 DebugLoc dl, SelectionDAG &DAG, 1545 SmallVectorImpl<SDValue> &InVals) const { 1546 1547 // 32-bit SVR4 ABI Stack Frame Layout: 1548 // +-----------------------------------+ 1549 // +--> | Back chain | 1550 // | +-----------------------------------+ 1551 // | | Floating-point register save area | 1552 // | +-----------------------------------+ 1553 // | | General register save area | 1554 // | +-----------------------------------+ 1555 // | | CR save word | 1556 // | +-----------------------------------+ 1557 // | | VRSAVE save word | 1558 // | +-----------------------------------+ 1559 // | | Alignment padding | 1560 // | +-----------------------------------+ 1561 // | | Vector register save area | 1562 // | +-----------------------------------+ 1563 // | | Local variable space | 1564 // | +-----------------------------------+ 1565 // | | Parameter list area | 1566 // | +-----------------------------------+ 1567 // | | LR save word | 1568 // | +-----------------------------------+ 1569 // SP--> +--- | Back chain | 1570 // +-----------------------------------+ 1571 // 1572 // Specifications: 1573 // System V Application Binary Interface PowerPC Processor Supplement 1574 // AltiVec Technology Programming Interface Manual 1575 1576 MachineFunction &MF = DAG.getMachineFunction(); 1577 MachineFrameInfo *MFI = MF.getFrameInfo(); 1578 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1579 1580 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1581 // Potential tail calls could cause overwriting of argument stack slots. 1582 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1583 unsigned PtrByteSize = 4; 1584 1585 // Assign locations to all of the incoming arguments. 1586 SmallVector<CCValAssign, 16> ArgLocs; 1587 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1588 *DAG.getContext()); 1589 1590 // Reserve space for the linkage area on the stack. 1591 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); 1592 1593 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); 1594 1595 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1596 CCValAssign &VA = ArgLocs[i]; 1597 1598 // Arguments stored in registers. 1599 if (VA.isRegLoc()) { 1600 TargetRegisterClass *RC; 1601 EVT ValVT = VA.getValVT(); 1602 1603 switch (ValVT.getSimpleVT().SimpleTy) { 1604 default: 1605 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1606 case MVT::i32: 1607 RC = PPC::GPRCRegisterClass; 1608 break; 1609 case MVT::f32: 1610 RC = PPC::F4RCRegisterClass; 1611 break; 1612 case MVT::f64: 1613 RC = PPC::F8RCRegisterClass; 1614 break; 1615 case MVT::v16i8: 1616 case MVT::v8i16: 1617 case MVT::v4i32: 1618 case MVT::v4f32: 1619 RC = PPC::VRRCRegisterClass; 1620 break; 1621 } 1622 1623 // Transform the arguments stored in physical registers into virtual ones. 1624 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1625 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1626 1627 InVals.push_back(ArgValue); 1628 } else { 1629 // Argument stored in memory. 1630 assert(VA.isMemLoc()); 1631 1632 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1633 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1634 isImmutable); 1635 1636 // Create load nodes to retrieve arguments from the stack. 1637 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1638 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0, 1639 false, false, 0)); 1640 } 1641 } 1642 1643 // Assign locations to all of the incoming aggregate by value arguments. 1644 // Aggregates passed by value are stored in the local variable space of the 1645 // caller's stack frame, right above the parameter list area. 1646 SmallVector<CCValAssign, 16> ByValArgLocs; 1647 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), 1648 ByValArgLocs, *DAG.getContext()); 1649 1650 // Reserve stack space for the allocations in CCInfo. 1651 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1652 1653 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal); 1654 1655 // Area that is at least reserved in the caller of this function. 1656 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1657 1658 // Set the size that is at least reserved in caller of this function. Tail 1659 // call optimized function's reserved stack space needs to be aligned so that 1660 // taking the difference between two stack areas will result in an aligned 1661 // stack. 1662 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1663 1664 MinReservedArea = 1665 std::max(MinReservedArea, 1666 PPCFrameInfo::getMinCallFrameSize(false, false)); 1667 1668 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 1669 getStackAlignment(); 1670 unsigned AlignMask = TargetAlign-1; 1671 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1672 1673 FI->setMinReservedArea(MinReservedArea); 1674 1675 SmallVector<SDValue, 8> MemOps; 1676 1677 // If the function takes variable number of arguments, make a frame index for 1678 // the start of the first vararg value... for expansion of llvm.va_start. 1679 if (isVarArg) { 1680 static const unsigned GPArgRegs[] = { 1681 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1682 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1683 }; 1684 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 1685 1686 static const unsigned FPArgRegs[] = { 1687 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1688 PPC::F8 1689 }; 1690 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 1691 1692 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 1693 NumGPArgRegs)); 1694 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 1695 NumFPArgRegs)); 1696 1697 // Make room for NumGPArgRegs and NumFPArgRegs. 1698 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 1699 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 1700 1701 FuncInfo->setVarArgsStackOffset( 1702 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1703 CCInfo.getNextStackOffset(), true)); 1704 1705 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 1706 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1707 1708 // The fixed integer arguments of a variadic function are 1709 // stored to the VarArgsFrameIndex on the stack. 1710 unsigned GPRIndex = 0; 1711 for (; GPRIndex != FuncInfo->getVarArgsNumGPR(); ++GPRIndex) { 1712 SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT); 1713 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0, 1714 false, false, 0); 1715 MemOps.push_back(Store); 1716 // Increment the address by four for the next argument to store 1717 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1718 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1719 } 1720 1721 // If this function is vararg, store any remaining integer argument regs 1722 // to their spots on the stack so that they may be loaded by deferencing the 1723 // result of va_next. 1724 for (; GPRIndex != NumGPArgRegs; ++GPRIndex) { 1725 unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 1726 1727 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1728 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0, 1729 false, false, 0); 1730 MemOps.push_back(Store); 1731 // Increment the address by four for the next argument to store 1732 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1733 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1734 } 1735 1736 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 1737 // is set. 1738 1739 // The double arguments are stored to the VarArgsFrameIndex 1740 // on the stack. 1741 unsigned FPRIndex = 0; 1742 for (FPRIndex = 0; FPRIndex != FuncInfo->getVarArgsNumFPR(); ++FPRIndex) { 1743 SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64); 1744 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0, 1745 false, false, 0); 1746 MemOps.push_back(Store); 1747 // Increment the address by eight for the next argument to store 1748 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1749 PtrVT); 1750 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1751 } 1752 1753 for (; FPRIndex != NumFPArgRegs; ++FPRIndex) { 1754 unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 1755 1756 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 1757 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0, 1758 false, false, 0); 1759 MemOps.push_back(Store); 1760 // Increment the address by eight for the next argument to store 1761 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1762 PtrVT); 1763 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1764 } 1765 } 1766 1767 if (!MemOps.empty()) 1768 Chain = DAG.getNode(ISD::TokenFactor, dl, 1769 MVT::Other, &MemOps[0], MemOps.size()); 1770 1771 return Chain; 1772} 1773 1774SDValue 1775PPCTargetLowering::LowerFormalArguments_Darwin( 1776 SDValue Chain, 1777 CallingConv::ID CallConv, bool isVarArg, 1778 const SmallVectorImpl<ISD::InputArg> 1779 &Ins, 1780 DebugLoc dl, SelectionDAG &DAG, 1781 SmallVectorImpl<SDValue> &InVals) const { 1782 // TODO: add description of PPC stack frame format, or at least some docs. 1783 // 1784 MachineFunction &MF = DAG.getMachineFunction(); 1785 MachineFrameInfo *MFI = MF.getFrameInfo(); 1786 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1787 1788 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1789 bool isPPC64 = PtrVT == MVT::i64; 1790 // Potential tail calls could cause overwriting of argument stack slots. 1791 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1792 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1793 1794 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); 1795 // Area that is at least reserved in caller of this function. 1796 unsigned MinReservedArea = ArgOffset; 1797 1798 static const unsigned GPR_32[] = { // 32-bit registers. 1799 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1800 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1801 }; 1802 static const unsigned GPR_64[] = { // 64-bit registers. 1803 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1804 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1805 }; 1806 1807 static const unsigned *FPR = GetFPR(); 1808 1809 static const unsigned VR[] = { 1810 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1811 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1812 }; 1813 1814 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1815 const unsigned Num_FPR_Regs = 13; 1816 const unsigned Num_VR_Regs = array_lengthof( VR); 1817 1818 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1819 1820 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1821 1822 // In 32-bit non-varargs functions, the stack space for vectors is after the 1823 // stack space for non-vectors. We do not use this space unless we have 1824 // too many vectors to fit in registers, something that only occurs in 1825 // constructed examples:), but we have to walk the arglist to figure 1826 // that out...for the pathological case, compute VecArgOffset as the 1827 // start of the vector parameter area. Computing VecArgOffset is the 1828 // entire point of the following loop. 1829 unsigned VecArgOffset = ArgOffset; 1830 if (!isVarArg && !isPPC64) { 1831 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 1832 ++ArgNo) { 1833 EVT ObjectVT = Ins[ArgNo].VT; 1834 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1835 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1836 1837 if (Flags.isByVal()) { 1838 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 1839 ObjSize = Flags.getByValSize(); 1840 unsigned ArgSize = 1841 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1842 VecArgOffset += ArgSize; 1843 continue; 1844 } 1845 1846 switch(ObjectVT.getSimpleVT().SimpleTy) { 1847 default: llvm_unreachable("Unhandled argument type!"); 1848 case MVT::i32: 1849 case MVT::f32: 1850 VecArgOffset += isPPC64 ? 8 : 4; 1851 break; 1852 case MVT::i64: // PPC64 1853 case MVT::f64: 1854 VecArgOffset += 8; 1855 break; 1856 case MVT::v4f32: 1857 case MVT::v4i32: 1858 case MVT::v8i16: 1859 case MVT::v16i8: 1860 // Nothing to do, we're only looking at Nonvector args here. 1861 break; 1862 } 1863 } 1864 } 1865 // We've found where the vector parameter area in memory is. Skip the 1866 // first 12 parameters; these don't use that memory. 1867 VecArgOffset = ((VecArgOffset+15)/16)*16; 1868 VecArgOffset += 12*16; 1869 1870 // Add DAG nodes to load the arguments or copy them out of registers. On 1871 // entry to a function on PPC, the arguments start after the linkage area, 1872 // although the first ones are often in registers. 1873 1874 SmallVector<SDValue, 8> MemOps; 1875 unsigned nAltivecParamsAtEnd = 0; 1876 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 1877 SDValue ArgVal; 1878 bool needsLoad = false; 1879 EVT ObjectVT = Ins[ArgNo].VT; 1880 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1881 unsigned ArgSize = ObjSize; 1882 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1883 1884 unsigned CurArgOffset = ArgOffset; 1885 1886 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 1887 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 1888 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 1889 if (isVarArg || isPPC64) { 1890 MinReservedArea = ((MinReservedArea+15)/16)*16; 1891 MinReservedArea += CalculateStackSlotSize(ObjectVT, 1892 Flags, 1893 PtrByteSize); 1894 } else nAltivecParamsAtEnd++; 1895 } else 1896 // Calculate min reserved area. 1897 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 1898 Flags, 1899 PtrByteSize); 1900 1901 // FIXME the codegen can be much improved in some cases. 1902 // We do not have to keep everything in memory. 1903 if (Flags.isByVal()) { 1904 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1905 ObjSize = Flags.getByValSize(); 1906 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1907 // Objects of size 1 and 2 are right justified, everything else is 1908 // left justified. This means the memory address is adjusted forwards. 1909 if (ObjSize==1 || ObjSize==2) { 1910 CurArgOffset = CurArgOffset + (4 - ObjSize); 1911 } 1912 // The value of the object is its address. 1913 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 1914 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1915 InVals.push_back(FIN); 1916 if (ObjSize==1 || ObjSize==2) { 1917 if (GPR_idx != Num_GPR_Regs) { 1918 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1919 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1920 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 1921 NULL, 0, 1922 ObjSize==1 ? MVT::i8 : MVT::i16, 1923 false, false, 0); 1924 MemOps.push_back(Store); 1925 ++GPR_idx; 1926 } 1927 1928 ArgOffset += PtrByteSize; 1929 1930 continue; 1931 } 1932 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 1933 // Store whatever pieces of the object are in registers 1934 // to memory. ArgVal will be address of the beginning of 1935 // the object. 1936 if (GPR_idx != Num_GPR_Regs) { 1937 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1938 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 1939 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1940 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1941 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0, 1942 false, false, 0); 1943 MemOps.push_back(Store); 1944 ++GPR_idx; 1945 ArgOffset += PtrByteSize; 1946 } else { 1947 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 1948 break; 1949 } 1950 } 1951 continue; 1952 } 1953 1954 switch (ObjectVT.getSimpleVT().SimpleTy) { 1955 default: llvm_unreachable("Unhandled argument type!"); 1956 case MVT::i32: 1957 if (!isPPC64) { 1958 if (GPR_idx != Num_GPR_Regs) { 1959 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1960 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 1961 ++GPR_idx; 1962 } else { 1963 needsLoad = true; 1964 ArgSize = PtrByteSize; 1965 } 1966 // All int arguments reserve stack space in the Darwin ABI. 1967 ArgOffset += PtrByteSize; 1968 break; 1969 } 1970 // FALLTHROUGH 1971 case MVT::i64: // PPC64 1972 if (GPR_idx != Num_GPR_Regs) { 1973 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 1974 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1975 1976 if (ObjectVT == MVT::i32) { 1977 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 1978 // value to MVT::i64 and then truncate to the correct register size. 1979 if (Flags.isSExt()) 1980 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 1981 DAG.getValueType(ObjectVT)); 1982 else if (Flags.isZExt()) 1983 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 1984 DAG.getValueType(ObjectVT)); 1985 1986 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 1987 } 1988 1989 ++GPR_idx; 1990 } else { 1991 needsLoad = true; 1992 ArgSize = PtrByteSize; 1993 } 1994 // All int arguments reserve stack space in the Darwin ABI. 1995 ArgOffset += 8; 1996 break; 1997 1998 case MVT::f32: 1999 case MVT::f64: 2000 // Every 4 bytes of argument space consumes one of the GPRs available for 2001 // argument passing. 2002 if (GPR_idx != Num_GPR_Regs) { 2003 ++GPR_idx; 2004 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 2005 ++GPR_idx; 2006 } 2007 if (FPR_idx != Num_FPR_Regs) { 2008 unsigned VReg; 2009 2010 if (ObjectVT == MVT::f32) 2011 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2012 else 2013 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2014 2015 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2016 ++FPR_idx; 2017 } else { 2018 needsLoad = true; 2019 } 2020 2021 // All FP arguments reserve stack space in the Darwin ABI. 2022 ArgOffset += isPPC64 ? 8 : ObjSize; 2023 break; 2024 case MVT::v4f32: 2025 case MVT::v4i32: 2026 case MVT::v8i16: 2027 case MVT::v16i8: 2028 // Note that vector arguments in registers don't reserve stack space, 2029 // except in varargs functions. 2030 if (VR_idx != Num_VR_Regs) { 2031 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2032 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2033 if (isVarArg) { 2034 while ((ArgOffset % 16) != 0) { 2035 ArgOffset += PtrByteSize; 2036 if (GPR_idx != Num_GPR_Regs) 2037 GPR_idx++; 2038 } 2039 ArgOffset += 16; 2040 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2041 } 2042 ++VR_idx; 2043 } else { 2044 if (!isVarArg && !isPPC64) { 2045 // Vectors go after all the nonvectors. 2046 CurArgOffset = VecArgOffset; 2047 VecArgOffset += 16; 2048 } else { 2049 // Vectors are aligned. 2050 ArgOffset = ((ArgOffset+15)/16)*16; 2051 CurArgOffset = ArgOffset; 2052 ArgOffset += 16; 2053 } 2054 needsLoad = true; 2055 } 2056 break; 2057 } 2058 2059 // We need to load the argument to a virtual register if we determined above 2060 // that we ran out of physical registers of the appropriate type. 2061 if (needsLoad) { 2062 int FI = MFI->CreateFixedObject(ObjSize, 2063 CurArgOffset + (ArgSize - ObjSize), 2064 isImmutable); 2065 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2066 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0, 2067 false, false, 0); 2068 } 2069 2070 InVals.push_back(ArgVal); 2071 } 2072 2073 // Set the size that is at least reserved in caller of this function. Tail 2074 // call optimized function's reserved stack space needs to be aligned so that 2075 // taking the difference between two stack areas will result in an aligned 2076 // stack. 2077 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2078 // Add the Altivec parameters at the end, if needed. 2079 if (nAltivecParamsAtEnd) { 2080 MinReservedArea = ((MinReservedArea+15)/16)*16; 2081 MinReservedArea += 16*nAltivecParamsAtEnd; 2082 } 2083 MinReservedArea = 2084 std::max(MinReservedArea, 2085 PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); 2086 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 2087 getStackAlignment(); 2088 unsigned AlignMask = TargetAlign-1; 2089 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2090 FI->setMinReservedArea(MinReservedArea); 2091 2092 // If the function takes variable number of arguments, make a frame index for 2093 // the start of the first vararg value... for expansion of llvm.va_start. 2094 if (isVarArg) { 2095 int Depth = ArgOffset; 2096 2097 FuncInfo->setVarArgsFrameIndex( 2098 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2099 Depth, true)); 2100 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2101 2102 // If this function is vararg, store any remaining integer argument regs 2103 // to their spots on the stack so that they may be loaded by deferencing the 2104 // result of va_next. 2105 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2106 unsigned VReg; 2107 2108 if (isPPC64) 2109 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2110 else 2111 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2112 2113 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2114 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0, 2115 false, false, 0); 2116 MemOps.push_back(Store); 2117 // Increment the address by four for the next argument to store 2118 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2119 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2120 } 2121 } 2122 2123 if (!MemOps.empty()) 2124 Chain = DAG.getNode(ISD::TokenFactor, dl, 2125 MVT::Other, &MemOps[0], MemOps.size()); 2126 2127 return Chain; 2128} 2129 2130/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus 2131/// linkage area for the Darwin ABI. 2132static unsigned 2133CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2134 bool isPPC64, 2135 bool isVarArg, 2136 unsigned CC, 2137 const SmallVectorImpl<ISD::OutputArg> 2138 &Outs, 2139 unsigned &nAltivecParamsAtEnd) { 2140 // Count how many bytes are to be pushed on the stack, including the linkage 2141 // area, and parameter passing area. We start with 24/48 bytes, which is 2142 // prereserved space for [SP][CR][LR][3 x unused]. 2143 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true); 2144 unsigned NumOps = Outs.size(); 2145 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2146 2147 // Add up all the space actually used. 2148 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2149 // they all go in registers, but we must reserve stack space for them for 2150 // possible use by the caller. In varargs or 64-bit calls, parameters are 2151 // assigned stack space in order, with padding so Altivec parameters are 2152 // 16-byte aligned. 2153 nAltivecParamsAtEnd = 0; 2154 for (unsigned i = 0; i != NumOps; ++i) { 2155 SDValue Arg = Outs[i].Val; 2156 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2157 EVT ArgVT = Arg.getValueType(); 2158 // Varargs Altivec parameters are padded to a 16 byte boundary. 2159 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2160 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2161 if (!isVarArg && !isPPC64) { 2162 // Non-varargs Altivec parameters go after all the non-Altivec 2163 // parameters; handle those later so we know how much padding we need. 2164 nAltivecParamsAtEnd++; 2165 continue; 2166 } 2167 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2168 NumBytes = ((NumBytes+15)/16)*16; 2169 } 2170 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2171 } 2172 2173 // Allow for Altivec parameters at the end, if needed. 2174 if (nAltivecParamsAtEnd) { 2175 NumBytes = ((NumBytes+15)/16)*16; 2176 NumBytes += 16*nAltivecParamsAtEnd; 2177 } 2178 2179 // The prolog code of the callee may store up to 8 GPR argument registers to 2180 // the stack, allowing va_start to index over them in memory if its varargs. 2181 // Because we cannot tell if this is needed on the caller side, we have to 2182 // conservatively assume that it is needed. As such, make sure we have at 2183 // least enough stack space for the caller to store the 8 GPRs. 2184 NumBytes = std::max(NumBytes, 2185 PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); 2186 2187 // Tail call needs the stack to be aligned. 2188 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) { 2189 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 2190 getStackAlignment(); 2191 unsigned AlignMask = TargetAlign-1; 2192 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2193 } 2194 2195 return NumBytes; 2196} 2197 2198/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2199/// adjusted to accomodate the arguments for the tailcall. 2200static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2201 unsigned ParamSize) { 2202 2203 if (!isTailCall) return 0; 2204 2205 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2206 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2207 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2208 // Remember only if the new adjustement is bigger. 2209 if (SPDiff < FI->getTailCallSPDelta()) 2210 FI->setTailCallSPDelta(SPDiff); 2211 2212 return SPDiff; 2213} 2214 2215/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2216/// for tail call optimization. Targets which want to do tail call 2217/// optimization should implement this function. 2218bool 2219PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2220 CallingConv::ID CalleeCC, 2221 bool isVarArg, 2222 const SmallVectorImpl<ISD::InputArg> &Ins, 2223 SelectionDAG& DAG) const { 2224 if (!GuaranteedTailCallOpt) 2225 return false; 2226 2227 // Variable argument functions are not supported. 2228 if (isVarArg) 2229 return false; 2230 2231 MachineFunction &MF = DAG.getMachineFunction(); 2232 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2233 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2234 // Functions containing by val parameters are not supported. 2235 for (unsigned i = 0; i != Ins.size(); i++) { 2236 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2237 if (Flags.isByVal()) return false; 2238 } 2239 2240 // Non PIC/GOT tail calls are supported. 2241 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2242 return true; 2243 2244 // At the moment we can only do local tail calls (in same module, hidden 2245 // or protected) if we are generating PIC. 2246 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2247 return G->getGlobal()->hasHiddenVisibility() 2248 || G->getGlobal()->hasProtectedVisibility(); 2249 } 2250 2251 return false; 2252} 2253 2254/// isCallCompatibleAddress - Return the immediate to use if the specified 2255/// 32-bit value is representable in the immediate field of a BxA instruction. 2256static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2257 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2258 if (!C) return 0; 2259 2260 int Addr = C->getZExtValue(); 2261 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2262 (Addr << 6 >> 6) != Addr) 2263 return 0; // Top 6 bits have to be sext of immediate. 2264 2265 return DAG.getConstant((int)C->getZExtValue() >> 2, 2266 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2267} 2268 2269namespace { 2270 2271struct TailCallArgumentInfo { 2272 SDValue Arg; 2273 SDValue FrameIdxOp; 2274 int FrameIdx; 2275 2276 TailCallArgumentInfo() : FrameIdx(0) {} 2277}; 2278 2279} 2280 2281/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2282static void 2283StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2284 SDValue Chain, 2285 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2286 SmallVector<SDValue, 8> &MemOpChains, 2287 DebugLoc dl) { 2288 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2289 SDValue Arg = TailCallArgs[i].Arg; 2290 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2291 int FI = TailCallArgs[i].FrameIdx; 2292 // Store relative to framepointer. 2293 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2294 PseudoSourceValue::getFixedStack(FI), 2295 0, false, false, 0)); 2296 } 2297} 2298 2299/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2300/// the appropriate stack slot for the tail call optimized function call. 2301static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2302 MachineFunction &MF, 2303 SDValue Chain, 2304 SDValue OldRetAddr, 2305 SDValue OldFP, 2306 int SPDiff, 2307 bool isPPC64, 2308 bool isDarwinABI, 2309 DebugLoc dl) { 2310 if (SPDiff) { 2311 // Calculate the new stack slot for the return address. 2312 int SlotSize = isPPC64 ? 8 : 4; 2313 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64, 2314 isDarwinABI); 2315 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2316 NewRetAddrLoc, true); 2317 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2318 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2319 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2320 PseudoSourceValue::getFixedStack(NewRetAddr), 0, 2321 false, false, 0); 2322 2323 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2324 // slot as the FP is never overwritten. 2325 if (isDarwinABI) { 2326 int NewFPLoc = 2327 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2328 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2329 true); 2330 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2331 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2332 PseudoSourceValue::getFixedStack(NewFPIdx), 0, 2333 false, false, 0); 2334 } 2335 } 2336 return Chain; 2337} 2338 2339/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2340/// the position of the argument. 2341static void 2342CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2343 SDValue Arg, int SPDiff, unsigned ArgOffset, 2344 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2345 int Offset = ArgOffset + SPDiff; 2346 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2347 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2348 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2349 SDValue FIN = DAG.getFrameIndex(FI, VT); 2350 TailCallArgumentInfo Info; 2351 Info.Arg = Arg; 2352 Info.FrameIdxOp = FIN; 2353 Info.FrameIdx = FI; 2354 TailCallArguments.push_back(Info); 2355} 2356 2357/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2358/// stack slot. Returns the chain as result and the loaded frame pointers in 2359/// LROpOut/FPOpout. Used when tail calling. 2360SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2361 int SPDiff, 2362 SDValue Chain, 2363 SDValue &LROpOut, 2364 SDValue &FPOpOut, 2365 bool isDarwinABI, 2366 DebugLoc dl) const { 2367 if (SPDiff) { 2368 // Load the LR and FP stack slot for later adjusting. 2369 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2370 LROpOut = getReturnAddrFrameIndex(DAG); 2371 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0, 2372 false, false, 0); 2373 Chain = SDValue(LROpOut.getNode(), 1); 2374 2375 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2376 // slot as the FP is never overwritten. 2377 if (isDarwinABI) { 2378 FPOpOut = getFramePointerFrameIndex(DAG); 2379 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0, 2380 false, false, 0); 2381 Chain = SDValue(FPOpOut.getNode(), 1); 2382 } 2383 } 2384 return Chain; 2385} 2386 2387/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2388/// by "Src" to address "Dst" of size "Size". Alignment information is 2389/// specified by the specific parameter attribute. The copy will be passed as 2390/// a byval function parameter. 2391/// Sometimes what we are copying is the end of a larger object, the part that 2392/// does not fit in registers. 2393static SDValue 2394CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2395 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2396 DebugLoc dl) { 2397 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 2398 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 2399 false, false, NULL, 0, NULL, 0); 2400} 2401 2402/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2403/// tail calls. 2404static void 2405LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2406 SDValue Arg, SDValue PtrOff, int SPDiff, 2407 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2408 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2409 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments, 2410 DebugLoc dl) { 2411 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2412 if (!isTailCall) { 2413 if (isVector) { 2414 SDValue StackPtr; 2415 if (isPPC64) 2416 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2417 else 2418 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2419 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 2420 DAG.getConstant(ArgOffset, PtrVT)); 2421 } 2422 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0, 2423 false, false, 0)); 2424 // Calculate and remember argument location. 2425 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2426 TailCallArguments); 2427} 2428 2429static 2430void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 2431 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 2432 SDValue LROp, SDValue FPOp, bool isDarwinABI, 2433 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 2434 MachineFunction &MF = DAG.getMachineFunction(); 2435 2436 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2437 // might overwrite each other in case of tail call optimization. 2438 SmallVector<SDValue, 8> MemOpChains2; 2439 // Do not flag preceeding copytoreg stuff together with the following stuff. 2440 InFlag = SDValue(); 2441 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2442 MemOpChains2, dl); 2443 if (!MemOpChains2.empty()) 2444 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2445 &MemOpChains2[0], MemOpChains2.size()); 2446 2447 // Store the return address to the appropriate stack slot. 2448 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2449 isPPC64, isDarwinABI, dl); 2450 2451 // Emit callseq_end just before tailcall node. 2452 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2453 DAG.getIntPtrConstant(0, true), InFlag); 2454 InFlag = Chain.getValue(1); 2455} 2456 2457static 2458unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 2459 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 2460 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 2461 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 2462 bool isPPC64, bool isSVR4ABI) { 2463 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2464 NodeTys.push_back(MVT::Other); // Returns a chain 2465 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 2466 2467 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 2468 2469 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2470 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2471 // node so that legalize doesn't hack it. 2472 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2473 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType()); 2474 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) 2475 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); 2476 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) 2477 // If this is an absolute destination address, use the munged value. 2478 Callee = SDValue(Dest, 0); 2479 else { 2480 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2481 // to do the call, we can't use PPCISD::CALL. 2482 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2483 2484 if (isSVR4ABI && isPPC64) { 2485 // Function pointers in the 64-bit SVR4 ABI do not point to the function 2486 // entry point, but to the function descriptor (the function entry point 2487 // address is part of the function descriptor though). 2488 // The function descriptor is a three doubleword structure with the 2489 // following fields: function entry point, TOC base address and 2490 // environment pointer. 2491 // Thus for a call through a function pointer, the following actions need 2492 // to be performed: 2493 // 1. Save the TOC of the caller in the TOC save area of its stack 2494 // frame (this is done in LowerCall_Darwin()). 2495 // 2. Load the address of the function entry point from the function 2496 // descriptor. 2497 // 3. Load the TOC of the callee from the function descriptor into r2. 2498 // 4. Load the environment pointer from the function descriptor into 2499 // r11. 2500 // 5. Branch to the function entry point address. 2501 // 6. On return of the callee, the TOC of the caller needs to be 2502 // restored (this is done in FinishCall()). 2503 // 2504 // All those operations are flagged together to ensure that no other 2505 // operations can be scheduled in between. E.g. without flagging the 2506 // operations together, a TOC access in the caller could be scheduled 2507 // between the load of the callee TOC and the branch to the callee, which 2508 // results in the TOC access going through the TOC of the callee instead 2509 // of going through the TOC of the caller, which leads to incorrect code. 2510 2511 // Load the address of the function entry point from the function 2512 // descriptor. 2513 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Flag); 2514 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 2515 InFlag.getNode() ? 3 : 2); 2516 Chain = LoadFuncPtr.getValue(1); 2517 InFlag = LoadFuncPtr.getValue(2); 2518 2519 // Load environment pointer into r11. 2520 // Offset of the environment pointer within the function descriptor. 2521 SDValue PtrOff = DAG.getIntPtrConstant(16); 2522 2523 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 2524 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 2525 InFlag); 2526 Chain = LoadEnvPtr.getValue(1); 2527 InFlag = LoadEnvPtr.getValue(2); 2528 2529 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 2530 InFlag); 2531 Chain = EnvVal.getValue(0); 2532 InFlag = EnvVal.getValue(1); 2533 2534 // Load TOC of the callee into r2. We are using a target-specific load 2535 // with r2 hard coded, because the result of a target-independent load 2536 // would never go directly into r2, since r2 is a reserved register (which 2537 // prevents the register allocator from allocating it), resulting in an 2538 // additional register being allocated and an unnecessary move instruction 2539 // being generated. 2540 VTs = DAG.getVTList(MVT::Other, MVT::Flag); 2541 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 2542 Callee, InFlag); 2543 Chain = LoadTOCPtr.getValue(0); 2544 InFlag = LoadTOCPtr.getValue(1); 2545 2546 MTCTROps[0] = Chain; 2547 MTCTROps[1] = LoadFuncPtr; 2548 MTCTROps[2] = InFlag; 2549 } 2550 2551 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 2552 2 + (InFlag.getNode() != 0)); 2553 InFlag = Chain.getValue(1); 2554 2555 NodeTys.clear(); 2556 NodeTys.push_back(MVT::Other); 2557 NodeTys.push_back(MVT::Flag); 2558 Ops.push_back(Chain); 2559 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 2560 Callee.setNode(0); 2561 // Add CTR register as callee so a bctr can be emitted later. 2562 if (isTailCall) 2563 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT)); 2564 } 2565 2566 // If this is a direct call, pass the chain and the callee. 2567 if (Callee.getNode()) { 2568 Ops.push_back(Chain); 2569 Ops.push_back(Callee); 2570 } 2571 // If this is a tail call add stack pointer delta. 2572 if (isTailCall) 2573 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2574 2575 // Add argument registers to the end of the list so that they are known live 2576 // into the call. 2577 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2578 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2579 RegsToPass[i].second.getValueType())); 2580 2581 return CallOpc; 2582} 2583 2584SDValue 2585PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2586 CallingConv::ID CallConv, bool isVarArg, 2587 const SmallVectorImpl<ISD::InputArg> &Ins, 2588 DebugLoc dl, SelectionDAG &DAG, 2589 SmallVectorImpl<SDValue> &InVals) const { 2590 2591 SmallVector<CCValAssign, 16> RVLocs; 2592 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(), 2593 RVLocs, *DAG.getContext()); 2594 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2595 2596 // Copy all of the result registers out of their specified physreg. 2597 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2598 CCValAssign &VA = RVLocs[i]; 2599 EVT VT = VA.getValVT(); 2600 assert(VA.isRegLoc() && "Can only return in registers!"); 2601 Chain = DAG.getCopyFromReg(Chain, dl, 2602 VA.getLocReg(), VT, InFlag).getValue(1); 2603 InVals.push_back(Chain.getValue(0)); 2604 InFlag = Chain.getValue(2); 2605 } 2606 2607 return Chain; 2608} 2609 2610SDValue 2611PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 2612 bool isTailCall, bool isVarArg, 2613 SelectionDAG &DAG, 2614 SmallVector<std::pair<unsigned, SDValue>, 8> 2615 &RegsToPass, 2616 SDValue InFlag, SDValue Chain, 2617 SDValue &Callee, 2618 int SPDiff, unsigned NumBytes, 2619 const SmallVectorImpl<ISD::InputArg> &Ins, 2620 SmallVectorImpl<SDValue> &InVals) const { 2621 std::vector<EVT> NodeTys; 2622 SmallVector<SDValue, 8> Ops; 2623 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 2624 isTailCall, RegsToPass, Ops, NodeTys, 2625 PPCSubTarget.isPPC64(), 2626 PPCSubTarget.isSVR4ABI()); 2627 2628 // When performing tail call optimization the callee pops its arguments off 2629 // the stack. Account for this here so these bytes can be pushed back on in 2630 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2631 int BytesCalleePops = 2632 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0; 2633 2634 if (InFlag.getNode()) 2635 Ops.push_back(InFlag); 2636 2637 // Emit tail call. 2638 if (isTailCall) { 2639 // If this is the first return lowered for this function, add the regs 2640 // to the liveout set for the function. 2641 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2642 SmallVector<CCValAssign, 16> RVLocs; 2643 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2644 *DAG.getContext()); 2645 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2646 for (unsigned i = 0; i != RVLocs.size(); ++i) 2647 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2648 } 2649 2650 assert(((Callee.getOpcode() == ISD::Register && 2651 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 2652 Callee.getOpcode() == ISD::TargetExternalSymbol || 2653 Callee.getOpcode() == ISD::TargetGlobalAddress || 2654 isa<ConstantSDNode>(Callee)) && 2655 "Expecting an global address, external symbol, absolute value or register"); 2656 2657 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 2658 } 2659 2660 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 2661 InFlag = Chain.getValue(1); 2662 2663 // Add a NOP immediately after the branch instruction when using the 64-bit 2664 // SVR4 ABI. At link time, if caller and callee are in a different module and 2665 // thus have a different TOC, the call will be replaced with a call to a stub 2666 // function which saves the current TOC, loads the TOC of the callee and 2667 // branches to the callee. The NOP will be replaced with a load instruction 2668 // which restores the TOC of the caller from the TOC save slot of the current 2669 // stack frame. If caller and callee belong to the same module (and have the 2670 // same TOC), the NOP will remain unchanged. 2671 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 2672 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag); 2673 if (CallOpc == PPCISD::BCTRL_SVR4) { 2674 // This is a call through a function pointer. 2675 // Restore the caller TOC from the save area into R2. 2676 // See PrepareCall() for more information about calls through function 2677 // pointers in the 64-bit SVR4 ABI. 2678 // We are using a target-specific load with r2 hard coded, because the 2679 // result of a target-independent load would never go directly into r2, 2680 // since r2 is a reserved register (which prevents the register allocator 2681 // from allocating it), resulting in an additional register being 2682 // allocated and an unnecessary move instruction being generated. 2683 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 2684 InFlag = Chain.getValue(1); 2685 } else { 2686 // Otherwise insert NOP. 2687 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag); 2688 } 2689 } 2690 2691 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2692 DAG.getIntPtrConstant(BytesCalleePops, true), 2693 InFlag); 2694 if (!Ins.empty()) 2695 InFlag = Chain.getValue(1); 2696 2697 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2698 Ins, dl, DAG, InVals); 2699} 2700 2701SDValue 2702PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2703 CallingConv::ID CallConv, bool isVarArg, 2704 bool &isTailCall, 2705 const SmallVectorImpl<ISD::OutputArg> &Outs, 2706 const SmallVectorImpl<ISD::InputArg> &Ins, 2707 DebugLoc dl, SelectionDAG &DAG, 2708 SmallVectorImpl<SDValue> &InVals) const { 2709 if (isTailCall) 2710 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 2711 Ins, DAG); 2712 2713 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 2714 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg, 2715 isTailCall, Outs, Ins, 2716 dl, DAG, InVals); 2717 } else { 2718 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 2719 isTailCall, Outs, Ins, 2720 dl, DAG, InVals); 2721 } 2722} 2723 2724SDValue 2725PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, 2726 CallingConv::ID CallConv, bool isVarArg, 2727 bool isTailCall, 2728 const SmallVectorImpl<ISD::OutputArg> &Outs, 2729 const SmallVectorImpl<ISD::InputArg> &Ins, 2730 DebugLoc dl, SelectionDAG &DAG, 2731 SmallVectorImpl<SDValue> &InVals) const { 2732 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description 2733 // of the 32-bit SVR4 ABI stack frame layout. 2734 2735 assert((CallConv == CallingConv::C || 2736 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 2737 2738 unsigned PtrByteSize = 4; 2739 2740 MachineFunction &MF = DAG.getMachineFunction(); 2741 2742 // Mark this function as potentially containing a function that contains a 2743 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2744 // and restoring the callers stack pointer in this functions epilog. This is 2745 // done because by tail calling the called function might overwrite the value 2746 // in this function's (MF) stack pointer stack slot 0(SP). 2747 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2748 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2749 2750 // Count how many bytes are to be pushed on the stack, including the linkage 2751 // area, parameter list area and the part of the local variable space which 2752 // contains copies of aggregates which are passed by value. 2753 2754 // Assign locations to all of the outgoing arguments. 2755 SmallVector<CCValAssign, 16> ArgLocs; 2756 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 2757 ArgLocs, *DAG.getContext()); 2758 2759 // Reserve space for the linkage area on the stack. 2760 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); 2761 2762 if (isVarArg) { 2763 // Handle fixed and variable vector arguments differently. 2764 // Fixed vector arguments go into registers as long as registers are 2765 // available. Variable vector arguments always go into memory. 2766 unsigned NumArgs = Outs.size(); 2767 2768 for (unsigned i = 0; i != NumArgs; ++i) { 2769 EVT ArgVT = Outs[i].Val.getValueType(); 2770 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2771 bool Result; 2772 2773 if (Outs[i].IsFixed) { 2774 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 2775 CCInfo); 2776 } else { 2777 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 2778 ArgFlags, CCInfo); 2779 } 2780 2781 if (Result) { 2782#ifndef NDEBUG 2783 errs() << "Call operand #" << i << " has unhandled type " 2784 << ArgVT.getEVTString() << "\n"; 2785#endif 2786 llvm_unreachable(0); 2787 } 2788 } 2789 } else { 2790 // All arguments are treated the same. 2791 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4); 2792 } 2793 2794 // Assign locations to all of the outgoing aggregate by value arguments. 2795 SmallVector<CCValAssign, 16> ByValArgLocs; 2796 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs, 2797 *DAG.getContext()); 2798 2799 // Reserve stack space for the allocations in CCInfo. 2800 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 2801 2802 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal); 2803 2804 // Size of the linkage area, parameter list area and the part of the local 2805 // space variable where copies of aggregates which are passed by value are 2806 // stored. 2807 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 2808 2809 // Calculate by how many bytes the stack has to be adjusted in case of tail 2810 // call optimization. 2811 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2812 2813 // Adjust the stack pointer for the new arguments... 2814 // These operations are automatically eliminated by the prolog/epilog pass 2815 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2816 SDValue CallSeqStart = Chain; 2817 2818 // Load the return address and frame pointer so it can be moved somewhere else 2819 // later. 2820 SDValue LROp, FPOp; 2821 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 2822 dl); 2823 2824 // Set up a copy of the stack pointer for use loading and storing any 2825 // arguments that may not fit in the registers available for argument 2826 // passing. 2827 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2828 2829 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2830 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2831 SmallVector<SDValue, 8> MemOpChains; 2832 2833 // Walk the register/memloc assignments, inserting copies/loads. 2834 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 2835 i != e; 2836 ++i) { 2837 CCValAssign &VA = ArgLocs[i]; 2838 SDValue Arg = Outs[i].Val; 2839 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2840 2841 if (Flags.isByVal()) { 2842 // Argument is an aggregate which is passed by value, thus we need to 2843 // create a copy of it in the local variable space of the current stack 2844 // frame (which is the stack frame of the caller) and pass the address of 2845 // this copy to the callee. 2846 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 2847 CCValAssign &ByValVA = ByValArgLocs[j++]; 2848 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 2849 2850 // Memory reserved in the local variable space of the callers stack frame. 2851 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 2852 2853 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2854 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2855 2856 // Create a copy of the argument in the local area of the current 2857 // stack frame. 2858 SDValue MemcpyCall = 2859 CreateCopyOfByValArgument(Arg, PtrOff, 2860 CallSeqStart.getNode()->getOperand(0), 2861 Flags, DAG, dl); 2862 2863 // This must go outside the CALLSEQ_START..END. 2864 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2865 CallSeqStart.getNode()->getOperand(1)); 2866 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 2867 NewCallSeqStart.getNode()); 2868 Chain = CallSeqStart = NewCallSeqStart; 2869 2870 // Pass the address of the aggregate copy on the stack either in a 2871 // physical register or in the parameter list area of the current stack 2872 // frame to the callee. 2873 Arg = PtrOff; 2874 } 2875 2876 if (VA.isRegLoc()) { 2877 // Put argument in a physical register. 2878 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2879 } else { 2880 // Put argument in the parameter list area of the current stack frame. 2881 assert(VA.isMemLoc()); 2882 unsigned LocMemOffset = VA.getLocMemOffset(); 2883 2884 if (!isTailCall) { 2885 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2886 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2887 2888 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2889 PseudoSourceValue::getStack(), LocMemOffset, 2890 false, false, 0)); 2891 } else { 2892 // Calculate and remember argument location. 2893 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 2894 TailCallArguments); 2895 } 2896 } 2897 } 2898 2899 if (!MemOpChains.empty()) 2900 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2901 &MemOpChains[0], MemOpChains.size()); 2902 2903 // Build a sequence of copy-to-reg nodes chained together with token chain 2904 // and flag operands which copy the outgoing args into the appropriate regs. 2905 SDValue InFlag; 2906 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2907 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2908 RegsToPass[i].second, InFlag); 2909 InFlag = Chain.getValue(1); 2910 } 2911 2912 // Set CR6 to true if this is a vararg call. 2913 if (isVarArg) { 2914 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0); 2915 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag); 2916 InFlag = Chain.getValue(1); 2917 } 2918 2919 if (isTailCall) { 2920 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 2921 false, TailCallArguments); 2922 } 2923 2924 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 2925 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 2926 Ins, InVals); 2927} 2928 2929SDValue 2930PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 2931 CallingConv::ID CallConv, bool isVarArg, 2932 bool isTailCall, 2933 const SmallVectorImpl<ISD::OutputArg> &Outs, 2934 const SmallVectorImpl<ISD::InputArg> &Ins, 2935 DebugLoc dl, SelectionDAG &DAG, 2936 SmallVectorImpl<SDValue> &InVals) const { 2937 2938 unsigned NumOps = Outs.size(); 2939 2940 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2941 bool isPPC64 = PtrVT == MVT::i64; 2942 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2943 2944 MachineFunction &MF = DAG.getMachineFunction(); 2945 2946 // Mark this function as potentially containing a function that contains a 2947 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2948 // and restoring the callers stack pointer in this functions epilog. This is 2949 // done because by tail calling the called function might overwrite the value 2950 // in this function's (MF) stack pointer stack slot 0(SP). 2951 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2952 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2953 2954 unsigned nAltivecParamsAtEnd = 0; 2955 2956 // Count how many bytes are to be pushed on the stack, including the linkage 2957 // area, and parameter passing area. We start with 24/48 bytes, which is 2958 // prereserved space for [SP][CR][LR][3 x unused]. 2959 unsigned NumBytes = 2960 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 2961 Outs, 2962 nAltivecParamsAtEnd); 2963 2964 // Calculate by how many bytes the stack has to be adjusted in case of tail 2965 // call optimization. 2966 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2967 2968 // To protect arguments on the stack from being clobbered in a tail call, 2969 // force all the loads to happen before doing any other lowering. 2970 if (isTailCall) 2971 Chain = DAG.getStackArgumentTokenFactor(Chain); 2972 2973 // Adjust the stack pointer for the new arguments... 2974 // These operations are automatically eliminated by the prolog/epilog pass 2975 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2976 SDValue CallSeqStart = Chain; 2977 2978 // Load the return address and frame pointer so it can be move somewhere else 2979 // later. 2980 SDValue LROp, FPOp; 2981 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 2982 dl); 2983 2984 // Set up a copy of the stack pointer for use loading and storing any 2985 // arguments that may not fit in the registers available for argument 2986 // passing. 2987 SDValue StackPtr; 2988 if (isPPC64) 2989 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2990 else 2991 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2992 2993 // Figure out which arguments are going to go in registers, and which in 2994 // memory. Also, if this is a vararg function, floating point operations 2995 // must be stored to our stack, and loaded into integer regs as well, if 2996 // any integer regs are available for argument passing. 2997 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); 2998 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 2999 3000 static const unsigned GPR_32[] = { // 32-bit registers. 3001 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 3002 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 3003 }; 3004 static const unsigned GPR_64[] = { // 64-bit registers. 3005 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3006 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3007 }; 3008 static const unsigned *FPR = GetFPR(); 3009 3010 static const unsigned VR[] = { 3011 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3012 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3013 }; 3014 const unsigned NumGPRs = array_lengthof(GPR_32); 3015 const unsigned NumFPRs = 13; 3016 const unsigned NumVRs = array_lengthof(VR); 3017 3018 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 3019 3020 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3021 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3022 3023 SmallVector<SDValue, 8> MemOpChains; 3024 for (unsigned i = 0; i != NumOps; ++i) { 3025 SDValue Arg = Outs[i].Val; 3026 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3027 3028 // PtrOff will be used to store the current argument to the stack if a 3029 // register cannot be found for it. 3030 SDValue PtrOff; 3031 3032 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3033 3034 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3035 3036 // On PPC64, promote integers to 64-bit values. 3037 if (isPPC64 && Arg.getValueType() == MVT::i32) { 3038 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3039 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3040 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3041 } 3042 3043 // FIXME memcpy is used way more than necessary. Correctness first. 3044 if (Flags.isByVal()) { 3045 unsigned Size = Flags.getByValSize(); 3046 if (Size==1 || Size==2) { 3047 // Very small objects are passed right-justified. 3048 // Everything else is passed left-justified. 3049 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 3050 if (GPR_idx != NumGPRs) { 3051 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3052 NULL, 0, VT, false, false, 0); 3053 MemOpChains.push_back(Load.getValue(1)); 3054 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3055 3056 ArgOffset += PtrByteSize; 3057 } else { 3058 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 3059 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3060 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 3061 CallSeqStart.getNode()->getOperand(0), 3062 Flags, DAG, dl); 3063 // This must go outside the CALLSEQ_START..END. 3064 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3065 CallSeqStart.getNode()->getOperand(1)); 3066 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3067 NewCallSeqStart.getNode()); 3068 Chain = CallSeqStart = NewCallSeqStart; 3069 ArgOffset += PtrByteSize; 3070 } 3071 continue; 3072 } 3073 // Copy entire object into memory. There are cases where gcc-generated 3074 // code assumes it is there, even if it could be put entirely into 3075 // registers. (This is not what the doc says.) 3076 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3077 CallSeqStart.getNode()->getOperand(0), 3078 Flags, DAG, dl); 3079 // This must go outside the CALLSEQ_START..END. 3080 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3081 CallSeqStart.getNode()->getOperand(1)); 3082 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); 3083 Chain = CallSeqStart = NewCallSeqStart; 3084 // And copy the pieces of it that fit into registers. 3085 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3086 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3087 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3088 if (GPR_idx != NumGPRs) { 3089 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0, 3090 false, false, 0); 3091 MemOpChains.push_back(Load.getValue(1)); 3092 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3093 ArgOffset += PtrByteSize; 3094 } else { 3095 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3096 break; 3097 } 3098 } 3099 continue; 3100 } 3101 3102 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3103 default: llvm_unreachable("Unexpected ValueType for argument!"); 3104 case MVT::i32: 3105 case MVT::i64: 3106 if (GPR_idx != NumGPRs) { 3107 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3108 } else { 3109 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3110 isPPC64, isTailCall, false, MemOpChains, 3111 TailCallArguments, dl); 3112 } 3113 ArgOffset += PtrByteSize; 3114 break; 3115 case MVT::f32: 3116 case MVT::f64: 3117 if (FPR_idx != NumFPRs) { 3118 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3119 3120 if (isVarArg) { 3121 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0, 3122 false, false, 0); 3123 MemOpChains.push_back(Store); 3124 3125 // Float varargs are always shadowed in available integer registers 3126 if (GPR_idx != NumGPRs) { 3127 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0, 3128 false, false, 0); 3129 MemOpChains.push_back(Load.getValue(1)); 3130 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3131 } 3132 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 3133 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3134 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3135 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0, 3136 false, false, 0); 3137 MemOpChains.push_back(Load.getValue(1)); 3138 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3139 } 3140 } else { 3141 // If we have any FPRs remaining, we may also have GPRs remaining. 3142 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 3143 // GPRs. 3144 if (GPR_idx != NumGPRs) 3145 ++GPR_idx; 3146 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 3147 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 3148 ++GPR_idx; 3149 } 3150 } else { 3151 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3152 isPPC64, isTailCall, false, MemOpChains, 3153 TailCallArguments, dl); 3154 } 3155 if (isPPC64) 3156 ArgOffset += 8; 3157 else 3158 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 3159 break; 3160 case MVT::v4f32: 3161 case MVT::v4i32: 3162 case MVT::v8i16: 3163 case MVT::v16i8: 3164 if (isVarArg) { 3165 // These go aligned on the stack, or in the corresponding R registers 3166 // when within range. The Darwin PPC ABI doc claims they also go in 3167 // V registers; in fact gcc does this only for arguments that are 3168 // prototyped, not for those that match the ... We do it for all 3169 // arguments, seems to work. 3170 while (ArgOffset % 16 !=0) { 3171 ArgOffset += PtrByteSize; 3172 if (GPR_idx != NumGPRs) 3173 GPR_idx++; 3174 } 3175 // We could elide this store in the case where the object fits 3176 // entirely in R registers. Maybe later. 3177 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3178 DAG.getConstant(ArgOffset, PtrVT)); 3179 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0, 3180 false, false, 0); 3181 MemOpChains.push_back(Store); 3182 if (VR_idx != NumVRs) { 3183 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0, 3184 false, false, 0); 3185 MemOpChains.push_back(Load.getValue(1)); 3186 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3187 } 3188 ArgOffset += 16; 3189 for (unsigned i=0; i<16; i+=PtrByteSize) { 3190 if (GPR_idx == NumGPRs) 3191 break; 3192 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3193 DAG.getConstant(i, PtrVT)); 3194 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0, 3195 false, false, 0); 3196 MemOpChains.push_back(Load.getValue(1)); 3197 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3198 } 3199 break; 3200 } 3201 3202 // Non-varargs Altivec params generally go in registers, but have 3203 // stack space allocated at the end. 3204 if (VR_idx != NumVRs) { 3205 // Doesn't have GPR space allocated. 3206 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3207 } else if (nAltivecParamsAtEnd==0) { 3208 // We are emitting Altivec params in order. 3209 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3210 isPPC64, isTailCall, true, MemOpChains, 3211 TailCallArguments, dl); 3212 ArgOffset += 16; 3213 } 3214 break; 3215 } 3216 } 3217 // If all Altivec parameters fit in registers, as they usually do, 3218 // they get stack space following the non-Altivec parameters. We 3219 // don't track this here because nobody below needs it. 3220 // If there are more Altivec parameters than fit in registers emit 3221 // the stores here. 3222 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 3223 unsigned j = 0; 3224 // Offset is aligned; skip 1st 12 params which go in V registers. 3225 ArgOffset = ((ArgOffset+15)/16)*16; 3226 ArgOffset += 12*16; 3227 for (unsigned i = 0; i != NumOps; ++i) { 3228 SDValue Arg = Outs[i].Val; 3229 EVT ArgType = Arg.getValueType(); 3230 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 3231 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 3232 if (++j > NumVRs) { 3233 SDValue PtrOff; 3234 // We are emitting Altivec params in order. 3235 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3236 isPPC64, isTailCall, true, MemOpChains, 3237 TailCallArguments, dl); 3238 ArgOffset += 16; 3239 } 3240 } 3241 } 3242 } 3243 3244 if (!MemOpChains.empty()) 3245 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3246 &MemOpChains[0], MemOpChains.size()); 3247 3248 // Check if this is an indirect call (MTCTR/BCTRL). 3249 // See PrepareCall() for more information about calls through function 3250 // pointers in the 64-bit SVR4 ABI. 3251 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() && 3252 !dyn_cast<GlobalAddressSDNode>(Callee) && 3253 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3254 !isBLACompatibleAddress(Callee, DAG)) { 3255 // Load r2 into a virtual register and store it to the TOC save area. 3256 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 3257 // TOC save area offset. 3258 SDValue PtrOff = DAG.getIntPtrConstant(40); 3259 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3260 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, NULL, 0, 3261 false, false, 0); 3262 } 3263 3264 // On Darwin, R12 must contain the address of an indirect callee. This does 3265 // not mean the MTCTR instruction must use R12; it's easier to model this as 3266 // an extra parameter, so do that. 3267 if (!isTailCall && 3268 !dyn_cast<GlobalAddressSDNode>(Callee) && 3269 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3270 !isBLACompatibleAddress(Callee, DAG)) 3271 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 3272 PPC::R12), Callee)); 3273 3274 // Build a sequence of copy-to-reg nodes chained together with token chain 3275 // and flag operands which copy the outgoing args into the appropriate regs. 3276 SDValue InFlag; 3277 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3278 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3279 RegsToPass[i].second, InFlag); 3280 InFlag = Chain.getValue(1); 3281 } 3282 3283 if (isTailCall) { 3284 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 3285 FPOp, true, TailCallArguments); 3286 } 3287 3288 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3289 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3290 Ins, InVals); 3291} 3292 3293SDValue 3294PPCTargetLowering::LowerReturn(SDValue Chain, 3295 CallingConv::ID CallConv, bool isVarArg, 3296 const SmallVectorImpl<ISD::OutputArg> &Outs, 3297 DebugLoc dl, SelectionDAG &DAG) const { 3298 3299 SmallVector<CCValAssign, 16> RVLocs; 3300 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 3301 RVLocs, *DAG.getContext()); 3302 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 3303 3304 // If this is the first return lowered for this function, add the regs to the 3305 // liveout set for the function. 3306 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3307 for (unsigned i = 0; i != RVLocs.size(); ++i) 3308 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3309 } 3310 3311 SDValue Flag; 3312 3313 // Copy the result values into the output registers. 3314 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3315 CCValAssign &VA = RVLocs[i]; 3316 assert(VA.isRegLoc() && "Can only return in registers!"); 3317 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 3318 Outs[i].Val, Flag); 3319 Flag = Chain.getValue(1); 3320 } 3321 3322 if (Flag.getNode()) 3323 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 3324 else 3325 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 3326} 3327 3328SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 3329 const PPCSubtarget &Subtarget) const { 3330 // When we pop the dynamic allocation we need to restore the SP link. 3331 DebugLoc dl = Op.getDebugLoc(); 3332 3333 // Get the corect type for pointers. 3334 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3335 3336 // Construct the stack pointer operand. 3337 bool isPPC64 = Subtarget.isPPC64(); 3338 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 3339 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 3340 3341 // Get the operands for the STACKRESTORE. 3342 SDValue Chain = Op.getOperand(0); 3343 SDValue SaveSP = Op.getOperand(1); 3344 3345 // Load the old link SP. 3346 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0, 3347 false, false, 0); 3348 3349 // Restore the stack pointer. 3350 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 3351 3352 // Store the old link SP. 3353 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0, 3354 false, false, 0); 3355} 3356 3357 3358 3359SDValue 3360PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 3361 MachineFunction &MF = DAG.getMachineFunction(); 3362 bool isPPC64 = PPCSubTarget.isPPC64(); 3363 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3364 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3365 3366 // Get current frame pointer save index. The users of this index will be 3367 // primarily DYNALLOC instructions. 3368 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3369 int RASI = FI->getReturnAddrSaveIndex(); 3370 3371 // If the frame pointer save index hasn't been defined yet. 3372 if (!RASI) { 3373 // Find out what the fix offset of the frame pointer save area. 3374 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 3375 // Allocate the frame index for frame pointer save area. 3376 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 3377 // Save the result. 3378 FI->setReturnAddrSaveIndex(RASI); 3379 } 3380 return DAG.getFrameIndex(RASI, PtrVT); 3381} 3382 3383SDValue 3384PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 3385 MachineFunction &MF = DAG.getMachineFunction(); 3386 bool isPPC64 = PPCSubTarget.isPPC64(); 3387 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3388 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3389 3390 // Get current frame pointer save index. The users of this index will be 3391 // primarily DYNALLOC instructions. 3392 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3393 int FPSI = FI->getFramePointerSaveIndex(); 3394 3395 // If the frame pointer save index hasn't been defined yet. 3396 if (!FPSI) { 3397 // Find out what the fix offset of the frame pointer save area. 3398 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 3399 isDarwinABI); 3400 3401 // Allocate the frame index for frame pointer save area. 3402 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 3403 // Save the result. 3404 FI->setFramePointerSaveIndex(FPSI); 3405 } 3406 return DAG.getFrameIndex(FPSI, PtrVT); 3407} 3408 3409SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 3410 SelectionDAG &DAG, 3411 const PPCSubtarget &Subtarget) const { 3412 // Get the inputs. 3413 SDValue Chain = Op.getOperand(0); 3414 SDValue Size = Op.getOperand(1); 3415 DebugLoc dl = Op.getDebugLoc(); 3416 3417 // Get the corect type for pointers. 3418 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3419 // Negate the size. 3420 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 3421 DAG.getConstant(0, PtrVT), Size); 3422 // Construct a node for the frame pointer save index. 3423 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 3424 // Build a DYNALLOC node. 3425 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 3426 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 3427 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 3428} 3429 3430/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 3431/// possible. 3432SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 3433 // Not FP? Not a fsel. 3434 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 3435 !Op.getOperand(2).getValueType().isFloatingPoint()) 3436 return Op; 3437 3438 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 3439 3440 // Cannot handle SETEQ/SETNE. 3441 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 3442 3443 EVT ResVT = Op.getValueType(); 3444 EVT CmpVT = Op.getOperand(0).getValueType(); 3445 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3446 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 3447 DebugLoc dl = Op.getDebugLoc(); 3448 3449 // If the RHS of the comparison is a 0.0, we don't need to do the 3450 // subtraction at all. 3451 if (isFloatingPointZero(RHS)) 3452 switch (CC) { 3453 default: break; // SETUO etc aren't handled by fsel. 3454 case ISD::SETULT: 3455 case ISD::SETLT: 3456 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3457 case ISD::SETOGE: 3458 case ISD::SETGE: 3459 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3460 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3461 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 3462 case ISD::SETUGT: 3463 case ISD::SETGT: 3464 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3465 case ISD::SETOLE: 3466 case ISD::SETLE: 3467 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3468 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3469 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 3470 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 3471 } 3472 3473 SDValue Cmp; 3474 switch (CC) { 3475 default: break; // SETUO etc aren't handled by fsel. 3476 case ISD::SETULT: 3477 case ISD::SETLT: 3478 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3479 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3480 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3481 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3482 case ISD::SETOGE: 3483 case ISD::SETGE: 3484 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3485 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3486 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3487 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3488 case ISD::SETUGT: 3489 case ISD::SETGT: 3490 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3491 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3492 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3493 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3494 case ISD::SETOLE: 3495 case ISD::SETLE: 3496 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3497 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3498 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3499 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3500 } 3501 return Op; 3502} 3503 3504// FIXME: Split this code up when LegalizeDAGTypes lands. 3505SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 3506 DebugLoc dl) const { 3507 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 3508 SDValue Src = Op.getOperand(0); 3509 if (Src.getValueType() == MVT::f32) 3510 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 3511 3512 SDValue Tmp; 3513 switch (Op.getValueType().getSimpleVT().SimpleTy) { 3514 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 3515 case MVT::i32: 3516 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 3517 PPCISD::FCTIDZ, 3518 dl, MVT::f64, Src); 3519 break; 3520 case MVT::i64: 3521 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 3522 break; 3523 } 3524 3525 // Convert the FP value to an int value through memory. 3526 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 3527 3528 // Emit a store to the stack slot. 3529 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0, 3530 false, false, 0); 3531 3532 // Result is a load from the stack slot. If loading 4 bytes, make sure to 3533 // add in a bias. 3534 if (Op.getValueType() == MVT::i32) 3535 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 3536 DAG.getConstant(4, FIPtr.getValueType())); 3537 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0, 3538 false, false, 0); 3539} 3540 3541SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, 3542 SelectionDAG &DAG) const { 3543 DebugLoc dl = Op.getDebugLoc(); 3544 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 3545 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 3546 return SDValue(); 3547 3548 if (Op.getOperand(0).getValueType() == MVT::i64) { 3549 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl, 3550 MVT::f64, Op.getOperand(0)); 3551 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 3552 if (Op.getValueType() == MVT::f32) 3553 FP = DAG.getNode(ISD::FP_ROUND, dl, 3554 MVT::f32, FP, DAG.getIntPtrConstant(0)); 3555 return FP; 3556 } 3557 3558 assert(Op.getOperand(0).getValueType() == MVT::i32 && 3559 "Unhandled SINT_TO_FP type in custom expander!"); 3560 // Since we only generate this in 64-bit mode, we can take advantage of 3561 // 64-bit registers. In particular, sign extend the input value into the 3562 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 3563 // then lfd it and fcfid it. 3564 MachineFunction &MF = DAG.getMachineFunction(); 3565 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 3566 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 3567 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3568 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3569 3570 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 3571 Op.getOperand(0)); 3572 3573 // STD the extended value into the stack slot. 3574 MachineMemOperand *MMO = 3575 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx), 3576 MachineMemOperand::MOStore, 0, 8, 8); 3577 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 3578 SDValue Store = 3579 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 3580 Ops, 4, MVT::i64, MMO); 3581 // Load the value as a double. 3582 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0, false, false, 0); 3583 3584 // FCFID it and return it. 3585 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 3586 if (Op.getValueType() == MVT::f32) 3587 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 3588 return FP; 3589} 3590 3591SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3592 SelectionDAG &DAG) const { 3593 DebugLoc dl = Op.getDebugLoc(); 3594 /* 3595 The rounding mode is in bits 30:31 of FPSR, and has the following 3596 settings: 3597 00 Round to nearest 3598 01 Round to 0 3599 10 Round to +inf 3600 11 Round to -inf 3601 3602 FLT_ROUNDS, on the other hand, expects the following: 3603 -1 Undefined 3604 0 Round to 0 3605 1 Round to nearest 3606 2 Round to +inf 3607 3 Round to -inf 3608 3609 To perform the conversion, we do: 3610 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 3611 */ 3612 3613 MachineFunction &MF = DAG.getMachineFunction(); 3614 EVT VT = Op.getValueType(); 3615 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3616 std::vector<EVT> NodeTys; 3617 SDValue MFFSreg, InFlag; 3618 3619 // Save FP Control Word to register 3620 NodeTys.push_back(MVT::f64); // return register 3621 NodeTys.push_back(MVT::Flag); // unused in this context 3622 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 3623 3624 // Save FP register to stack slot 3625 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 3626 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 3627 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 3628 StackSlot, NULL, 0, false, false, 0); 3629 3630 // Load FP Control Word from low 32 bits of stack slot. 3631 SDValue Four = DAG.getConstant(4, PtrVT); 3632 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 3633 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0, 3634 false, false, 0); 3635 3636 // Transform as necessary 3637 SDValue CWD1 = 3638 DAG.getNode(ISD::AND, dl, MVT::i32, 3639 CWD, DAG.getConstant(3, MVT::i32)); 3640 SDValue CWD2 = 3641 DAG.getNode(ISD::SRL, dl, MVT::i32, 3642 DAG.getNode(ISD::AND, dl, MVT::i32, 3643 DAG.getNode(ISD::XOR, dl, MVT::i32, 3644 CWD, DAG.getConstant(3, MVT::i32)), 3645 DAG.getConstant(3, MVT::i32)), 3646 DAG.getConstant(1, MVT::i32)); 3647 3648 SDValue RetVal = 3649 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 3650 3651 return DAG.getNode((VT.getSizeInBits() < 16 ? 3652 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 3653} 3654 3655SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3656 EVT VT = Op.getValueType(); 3657 unsigned BitWidth = VT.getSizeInBits(); 3658 DebugLoc dl = Op.getDebugLoc(); 3659 assert(Op.getNumOperands() == 3 && 3660 VT == Op.getOperand(1).getValueType() && 3661 "Unexpected SHL!"); 3662 3663 // Expand into a bunch of logical ops. Note that these ops 3664 // depend on the PPC behavior for oversized shift amounts. 3665 SDValue Lo = Op.getOperand(0); 3666 SDValue Hi = Op.getOperand(1); 3667 SDValue Amt = Op.getOperand(2); 3668 EVT AmtVT = Amt.getValueType(); 3669 3670 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3671 DAG.getConstant(BitWidth, AmtVT), Amt); 3672 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 3673 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 3674 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 3675 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3676 DAG.getConstant(-BitWidth, AmtVT)); 3677 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 3678 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3679 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 3680 SDValue OutOps[] = { OutLo, OutHi }; 3681 return DAG.getMergeValues(OutOps, 2, dl); 3682} 3683 3684SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3685 EVT VT = Op.getValueType(); 3686 DebugLoc dl = Op.getDebugLoc(); 3687 unsigned BitWidth = VT.getSizeInBits(); 3688 assert(Op.getNumOperands() == 3 && 3689 VT == Op.getOperand(1).getValueType() && 3690 "Unexpected SRL!"); 3691 3692 // Expand into a bunch of logical ops. Note that these ops 3693 // depend on the PPC behavior for oversized shift amounts. 3694 SDValue Lo = Op.getOperand(0); 3695 SDValue Hi = Op.getOperand(1); 3696 SDValue Amt = Op.getOperand(2); 3697 EVT AmtVT = Amt.getValueType(); 3698 3699 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3700 DAG.getConstant(BitWidth, AmtVT), Amt); 3701 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3702 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3703 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3704 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3705 DAG.getConstant(-BitWidth, AmtVT)); 3706 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 3707 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3708 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 3709 SDValue OutOps[] = { OutLo, OutHi }; 3710 return DAG.getMergeValues(OutOps, 2, dl); 3711} 3712 3713SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 3714 DebugLoc dl = Op.getDebugLoc(); 3715 EVT VT = Op.getValueType(); 3716 unsigned BitWidth = VT.getSizeInBits(); 3717 assert(Op.getNumOperands() == 3 && 3718 VT == Op.getOperand(1).getValueType() && 3719 "Unexpected SRA!"); 3720 3721 // Expand into a bunch of logical ops, followed by a select_cc. 3722 SDValue Lo = Op.getOperand(0); 3723 SDValue Hi = Op.getOperand(1); 3724 SDValue Amt = Op.getOperand(2); 3725 EVT AmtVT = Amt.getValueType(); 3726 3727 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3728 DAG.getConstant(BitWidth, AmtVT), Amt); 3729 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3730 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3731 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3732 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3733 DAG.getConstant(-BitWidth, AmtVT)); 3734 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 3735 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 3736 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 3737 Tmp4, Tmp6, ISD::SETLE); 3738 SDValue OutOps[] = { OutLo, OutHi }; 3739 return DAG.getMergeValues(OutOps, 2, dl); 3740} 3741 3742//===----------------------------------------------------------------------===// 3743// Vector related lowering. 3744// 3745 3746/// BuildSplatI - Build a canonical splati of Val with an element size of 3747/// SplatSize. Cast the result to VT. 3748static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 3749 SelectionDAG &DAG, DebugLoc dl) { 3750 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 3751 3752 static const EVT VTys[] = { // canonical VT to use for each size. 3753 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 3754 }; 3755 3756 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 3757 3758 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 3759 if (Val == -1) 3760 SplatSize = 1; 3761 3762 EVT CanonicalVT = VTys[SplatSize-1]; 3763 3764 // Build a canonical splat for this value. 3765 SDValue Elt = DAG.getConstant(Val, MVT::i32); 3766 SmallVector<SDValue, 8> Ops; 3767 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 3768 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 3769 &Ops[0], Ops.size()); 3770 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res); 3771} 3772 3773/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 3774/// specified intrinsic ID. 3775static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 3776 SelectionDAG &DAG, DebugLoc dl, 3777 EVT DestVT = MVT::Other) { 3778 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 3779 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3780 DAG.getConstant(IID, MVT::i32), LHS, RHS); 3781} 3782 3783/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 3784/// specified intrinsic ID. 3785static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 3786 SDValue Op2, SelectionDAG &DAG, 3787 DebugLoc dl, EVT DestVT = MVT::Other) { 3788 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 3789 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3790 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 3791} 3792 3793 3794/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 3795/// amount. The result has the specified value type. 3796static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 3797 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3798 // Force LHS/RHS to be the right type. 3799 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS); 3800 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS); 3801 3802 int Ops[16]; 3803 for (unsigned i = 0; i != 16; ++i) 3804 Ops[i] = i + Amt; 3805 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 3806 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); 3807} 3808 3809// If this is a case we can't handle, return null and let the default 3810// expansion code take care of it. If we CAN select this case, and if it 3811// selects to a single instruction, return Op. Otherwise, if we can codegen 3812// this case more efficiently than a constant pool load, lower it to the 3813// sequence of ops that should be used. 3814SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 3815 SelectionDAG &DAG) const { 3816 DebugLoc dl = Op.getDebugLoc(); 3817 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 3818 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 3819 3820 // Check if this is a splat of a constant value. 3821 APInt APSplatBits, APSplatUndef; 3822 unsigned SplatBitSize; 3823 bool HasAnyUndefs; 3824 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 3825 HasAnyUndefs, 0, true) || SplatBitSize > 32) 3826 return SDValue(); 3827 3828 unsigned SplatBits = APSplatBits.getZExtValue(); 3829 unsigned SplatUndef = APSplatUndef.getZExtValue(); 3830 unsigned SplatSize = SplatBitSize / 8; 3831 3832 // First, handle single instruction cases. 3833 3834 // All zeros? 3835 if (SplatBits == 0) { 3836 // Canonicalize all zero vectors to be v4i32. 3837 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 3838 SDValue Z = DAG.getConstant(0, MVT::i32); 3839 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 3840 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z); 3841 } 3842 return Op; 3843 } 3844 3845 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 3846 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 3847 (32-SplatBitSize)); 3848 if (SextVal >= -16 && SextVal <= 15) 3849 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 3850 3851 3852 // Two instruction sequences. 3853 3854 // If this value is in the range [-32,30] and is even, use: 3855 // tmp = VSPLTI[bhw], result = add tmp, tmp 3856 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 3857 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 3858 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 3859 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3860 } 3861 3862 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 3863 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 3864 // for fneg/fabs. 3865 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 3866 // Make -1 and vspltisw -1: 3867 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 3868 3869 // Make the VSLW intrinsic, computing 0x8000_0000. 3870 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 3871 OnesV, DAG, dl); 3872 3873 // xor by OnesV to invert it. 3874 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 3875 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3876 } 3877 3878 // Check to see if this is a wide variety of vsplti*, binop self cases. 3879 static const signed char SplatCsts[] = { 3880 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 3881 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 3882 }; 3883 3884 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 3885 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 3886 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 3887 int i = SplatCsts[idx]; 3888 3889 // Figure out what shift amount will be used by altivec if shifted by i in 3890 // this splat size. 3891 unsigned TypeShiftAmt = i & (SplatBitSize-1); 3892 3893 // vsplti + shl self. 3894 if (SextVal == (i << (int)TypeShiftAmt)) { 3895 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3896 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3897 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 3898 Intrinsic::ppc_altivec_vslw 3899 }; 3900 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3901 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3902 } 3903 3904 // vsplti + srl self. 3905 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3906 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3907 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3908 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 3909 Intrinsic::ppc_altivec_vsrw 3910 }; 3911 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3912 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3913 } 3914 3915 // vsplti + sra self. 3916 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3917 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3918 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3919 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 3920 Intrinsic::ppc_altivec_vsraw 3921 }; 3922 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3923 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3924 } 3925 3926 // vsplti + rol self. 3927 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 3928 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 3929 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3930 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3931 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 3932 Intrinsic::ppc_altivec_vrlw 3933 }; 3934 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3935 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3936 } 3937 3938 // t = vsplti c, result = vsldoi t, t, 1 3939 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { 3940 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3941 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 3942 } 3943 // t = vsplti c, result = vsldoi t, t, 2 3944 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { 3945 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3946 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 3947 } 3948 // t = vsplti c, result = vsldoi t, t, 3 3949 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { 3950 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3951 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 3952 } 3953 } 3954 3955 // Three instruction sequences. 3956 3957 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 3958 if (SextVal >= 0 && SextVal <= 31) { 3959 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 3960 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3961 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 3962 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3963 } 3964 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 3965 if (SextVal >= -31 && SextVal <= 0) { 3966 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 3967 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3968 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 3969 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3970 } 3971 3972 return SDValue(); 3973} 3974 3975/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3976/// the specified operations to build the shuffle. 3977static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3978 SDValue RHS, SelectionDAG &DAG, 3979 DebugLoc dl) { 3980 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3981 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3982 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 3983 3984 enum { 3985 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 3986 OP_VMRGHW, 3987 OP_VMRGLW, 3988 OP_VSPLTISW0, 3989 OP_VSPLTISW1, 3990 OP_VSPLTISW2, 3991 OP_VSPLTISW3, 3992 OP_VSLDOI4, 3993 OP_VSLDOI8, 3994 OP_VSLDOI12 3995 }; 3996 3997 if (OpNum == OP_COPY) { 3998 if (LHSID == (1*9+2)*9+3) return LHS; 3999 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4000 return RHS; 4001 } 4002 4003 SDValue OpLHS, OpRHS; 4004 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4005 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4006 4007 int ShufIdxs[16]; 4008 switch (OpNum) { 4009 default: llvm_unreachable("Unknown i32 permute!"); 4010 case OP_VMRGHW: 4011 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 4012 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 4013 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 4014 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 4015 break; 4016 case OP_VMRGLW: 4017 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 4018 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 4019 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 4020 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 4021 break; 4022 case OP_VSPLTISW0: 4023 for (unsigned i = 0; i != 16; ++i) 4024 ShufIdxs[i] = (i&3)+0; 4025 break; 4026 case OP_VSPLTISW1: 4027 for (unsigned i = 0; i != 16; ++i) 4028 ShufIdxs[i] = (i&3)+4; 4029 break; 4030 case OP_VSPLTISW2: 4031 for (unsigned i = 0; i != 16; ++i) 4032 ShufIdxs[i] = (i&3)+8; 4033 break; 4034 case OP_VSPLTISW3: 4035 for (unsigned i = 0; i != 16; ++i) 4036 ShufIdxs[i] = (i&3)+12; 4037 break; 4038 case OP_VSLDOI4: 4039 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 4040 case OP_VSLDOI8: 4041 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 4042 case OP_VSLDOI12: 4043 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 4044 } 4045 EVT VT = OpLHS.getValueType(); 4046 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS); 4047 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS); 4048 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 4049 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); 4050} 4051 4052/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 4053/// is a shuffle we can handle in a single instruction, return it. Otherwise, 4054/// return the code it can be lowered into. Worst case, it can always be 4055/// lowered into a vperm. 4056SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4057 SelectionDAG &DAG) const { 4058 DebugLoc dl = Op.getDebugLoc(); 4059 SDValue V1 = Op.getOperand(0); 4060 SDValue V2 = Op.getOperand(1); 4061 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4062 EVT VT = Op.getValueType(); 4063 4064 // Cases that are handled by instructions that take permute immediates 4065 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 4066 // selected by the instruction selector. 4067 if (V2.getOpcode() == ISD::UNDEF) { 4068 if (PPC::isSplatShuffleMask(SVOp, 1) || 4069 PPC::isSplatShuffleMask(SVOp, 2) || 4070 PPC::isSplatShuffleMask(SVOp, 4) || 4071 PPC::isVPKUWUMShuffleMask(SVOp, true) || 4072 PPC::isVPKUHUMShuffleMask(SVOp, true) || 4073 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 4074 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 4075 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 4076 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 4077 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 4078 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 4079 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 4080 return Op; 4081 } 4082 } 4083 4084 // Altivec has a variety of "shuffle immediates" that take two vector inputs 4085 // and produce a fixed permutation. If any of these match, do not lower to 4086 // VPERM. 4087 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 4088 PPC::isVPKUHUMShuffleMask(SVOp, false) || 4089 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 4090 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 4091 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 4092 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 4093 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 4094 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 4095 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 4096 return Op; 4097 4098 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 4099 // perfect shuffle table to emit an optimal matching sequence. 4100 SmallVector<int, 16> PermMask; 4101 SVOp->getMask(PermMask); 4102 4103 unsigned PFIndexes[4]; 4104 bool isFourElementShuffle = true; 4105 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 4106 unsigned EltNo = 8; // Start out undef. 4107 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 4108 if (PermMask[i*4+j] < 0) 4109 continue; // Undef, ignore it. 4110 4111 unsigned ByteSource = PermMask[i*4+j]; 4112 if ((ByteSource & 3) != j) { 4113 isFourElementShuffle = false; 4114 break; 4115 } 4116 4117 if (EltNo == 8) { 4118 EltNo = ByteSource/4; 4119 } else if (EltNo != ByteSource/4) { 4120 isFourElementShuffle = false; 4121 break; 4122 } 4123 } 4124 PFIndexes[i] = EltNo; 4125 } 4126 4127 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 4128 // perfect shuffle vector to determine if it is cost effective to do this as 4129 // discrete instructions, or whether we should use a vperm. 4130 if (isFourElementShuffle) { 4131 // Compute the index in the perfect shuffle table. 4132 unsigned PFTableIndex = 4133 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4134 4135 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4136 unsigned Cost = (PFEntry >> 30); 4137 4138 // Determining when to avoid vperm is tricky. Many things affect the cost 4139 // of vperm, particularly how many times the perm mask needs to be computed. 4140 // For example, if the perm mask can be hoisted out of a loop or is already 4141 // used (perhaps because there are multiple permutes with the same shuffle 4142 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 4143 // the loop requires an extra register. 4144 // 4145 // As a compromise, we only emit discrete instructions if the shuffle can be 4146 // generated in 3 or fewer operations. When we have loop information 4147 // available, if this block is within a loop, we should avoid using vperm 4148 // for 3-operation perms and use a constant pool load instead. 4149 if (Cost < 3) 4150 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4151 } 4152 4153 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 4154 // vector that will get spilled to the constant pool. 4155 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 4156 4157 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 4158 // that it is in input element units, not in bytes. Convert now. 4159 EVT EltVT = V1.getValueType().getVectorElementType(); 4160 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 4161 4162 SmallVector<SDValue, 16> ResultMask; 4163 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4164 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 4165 4166 for (unsigned j = 0; j != BytesPerElement; ++j) 4167 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 4168 MVT::i32)); 4169 } 4170 4171 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 4172 &ResultMask[0], ResultMask.size()); 4173 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 4174} 4175 4176/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 4177/// altivec comparison. If it is, return true and fill in Opc/isDot with 4178/// information about the intrinsic. 4179static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 4180 bool &isDot) { 4181 unsigned IntrinsicID = 4182 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 4183 CompareOpc = -1; 4184 isDot = false; 4185 switch (IntrinsicID) { 4186 default: return false; 4187 // Comparison predicates. 4188 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 4189 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 4190 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 4191 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 4192 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 4193 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 4194 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 4195 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 4196 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 4197 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 4198 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 4199 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 4200 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 4201 4202 // Normal Comparisons. 4203 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 4204 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 4205 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 4206 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 4207 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 4208 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 4209 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 4210 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 4211 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 4212 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 4213 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 4214 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 4215 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 4216 } 4217 return true; 4218} 4219 4220/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 4221/// lower, do it, otherwise return null. 4222SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 4223 SelectionDAG &DAG) const { 4224 // If this is a lowered altivec predicate compare, CompareOpc is set to the 4225 // opcode number of the comparison. 4226 DebugLoc dl = Op.getDebugLoc(); 4227 int CompareOpc; 4228 bool isDot; 4229 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 4230 return SDValue(); // Don't custom lower most intrinsics. 4231 4232 // If this is a non-dot comparison, make the VCMP node and we are done. 4233 if (!isDot) { 4234 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 4235 Op.getOperand(1), Op.getOperand(2), 4236 DAG.getConstant(CompareOpc, MVT::i32)); 4237 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp); 4238 } 4239 4240 // Create the PPCISD altivec 'dot' comparison node. 4241 SDValue Ops[] = { 4242 Op.getOperand(2), // LHS 4243 Op.getOperand(3), // RHS 4244 DAG.getConstant(CompareOpc, MVT::i32) 4245 }; 4246 std::vector<EVT> VTs; 4247 VTs.push_back(Op.getOperand(2).getValueType()); 4248 VTs.push_back(MVT::Flag); 4249 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 4250 4251 // Now that we have the comparison, emit a copy from the CR to a GPR. 4252 // This is flagged to the above dot comparison. 4253 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 4254 DAG.getRegister(PPC::CR6, MVT::i32), 4255 CompNode.getValue(1)); 4256 4257 // Unpack the result based on how the target uses it. 4258 unsigned BitNo; // Bit # of CR6. 4259 bool InvertBit; // Invert result? 4260 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 4261 default: // Can't happen, don't crash on invalid number though. 4262 case 0: // Return the value of the EQ bit of CR6. 4263 BitNo = 0; InvertBit = false; 4264 break; 4265 case 1: // Return the inverted value of the EQ bit of CR6. 4266 BitNo = 0; InvertBit = true; 4267 break; 4268 case 2: // Return the value of the LT bit of CR6. 4269 BitNo = 2; InvertBit = false; 4270 break; 4271 case 3: // Return the inverted value of the LT bit of CR6. 4272 BitNo = 2; InvertBit = true; 4273 break; 4274 } 4275 4276 // Shift the bit into the low position. 4277 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 4278 DAG.getConstant(8-(3-BitNo), MVT::i32)); 4279 // Isolate the bit. 4280 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 4281 DAG.getConstant(1, MVT::i32)); 4282 4283 // If we are supposed to, toggle the bit. 4284 if (InvertBit) 4285 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 4286 DAG.getConstant(1, MVT::i32)); 4287 return Flags; 4288} 4289 4290SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 4291 SelectionDAG &DAG) const { 4292 DebugLoc dl = Op.getDebugLoc(); 4293 // Create a stack slot that is 16-byte aligned. 4294 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4295 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 4296 EVT PtrVT = getPointerTy(); 4297 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4298 4299 // Store the input value into Value#0 of the stack slot. 4300 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 4301 Op.getOperand(0), FIdx, NULL, 0, 4302 false, false, 0); 4303 // Load it out. 4304 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0, 4305 false, false, 0); 4306} 4307 4308SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 4309 DebugLoc dl = Op.getDebugLoc(); 4310 if (Op.getValueType() == MVT::v4i32) { 4311 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4312 4313 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 4314 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 4315 4316 SDValue RHSSwap = // = vrlw RHS, 16 4317 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 4318 4319 // Shrinkify inputs to v8i16. 4320 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS); 4321 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS); 4322 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap); 4323 4324 // Low parts multiplied together, generating 32-bit results (we ignore the 4325 // top parts). 4326 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 4327 LHS, RHS, DAG, dl, MVT::v4i32); 4328 4329 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 4330 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 4331 // Shift the high parts up 16 bits. 4332 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 4333 Neg16, DAG, dl); 4334 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 4335 } else if (Op.getValueType() == MVT::v8i16) { 4336 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4337 4338 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 4339 4340 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 4341 LHS, RHS, Zero, DAG, dl); 4342 } else if (Op.getValueType() == MVT::v16i8) { 4343 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4344 4345 // Multiply the even 8-bit parts, producing 16-bit sums. 4346 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 4347 LHS, RHS, DAG, dl, MVT::v8i16); 4348 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts); 4349 4350 // Multiply the odd 8-bit parts, producing 16-bit sums. 4351 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 4352 LHS, RHS, DAG, dl, MVT::v8i16); 4353 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts); 4354 4355 // Merge the results together. 4356 int Ops[16]; 4357 for (unsigned i = 0; i != 8; ++i) { 4358 Ops[i*2 ] = 2*i+1; 4359 Ops[i*2+1] = 2*i+1+16; 4360 } 4361 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 4362 } else { 4363 llvm_unreachable("Unknown mul to lower!"); 4364 } 4365} 4366 4367/// LowerOperation - Provide custom lowering hooks for some operations. 4368/// 4369SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4370 switch (Op.getOpcode()) { 4371 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 4372 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4373 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4374 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 4375 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 4376 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 4377 case ISD::SETCC: return LowerSETCC(Op, DAG); 4378 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 4379 case ISD::VASTART: 4380 return LowerVASTART(Op, DAG, PPCSubTarget); 4381 4382 case ISD::VAARG: 4383 return LowerVAARG(Op, DAG, PPCSubTarget); 4384 4385 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 4386 case ISD::DYNAMIC_STACKALLOC: 4387 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 4388 4389 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4390 case ISD::FP_TO_UINT: 4391 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 4392 Op.getDebugLoc()); 4393 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 4394 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4395 4396 // Lower 64-bit shifts. 4397 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 4398 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 4399 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 4400 4401 // Vector-related lowering. 4402 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 4403 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4404 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 4405 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 4406 case ISD::MUL: return LowerMUL(Op, DAG); 4407 4408 // Frame & Return address. 4409 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4410 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4411 } 4412 return SDValue(); 4413} 4414 4415void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 4416 SmallVectorImpl<SDValue>&Results, 4417 SelectionDAG &DAG) const { 4418 DebugLoc dl = N->getDebugLoc(); 4419 switch (N->getOpcode()) { 4420 default: 4421 assert(false && "Do not know how to custom type legalize this operation!"); 4422 return; 4423 case ISD::FP_ROUND_INREG: { 4424 assert(N->getValueType(0) == MVT::ppcf128); 4425 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 4426 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4427 MVT::f64, N->getOperand(0), 4428 DAG.getIntPtrConstant(0)); 4429 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4430 MVT::f64, N->getOperand(0), 4431 DAG.getIntPtrConstant(1)); 4432 4433 // This sequence changes FPSCR to do round-to-zero, adds the two halves 4434 // of the long double, and puts FPSCR back the way it was. We do not 4435 // actually model FPSCR. 4436 std::vector<EVT> NodeTys; 4437 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 4438 4439 NodeTys.push_back(MVT::f64); // Return register 4440 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 4441 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4442 MFFSreg = Result.getValue(0); 4443 InFlag = Result.getValue(1); 4444 4445 NodeTys.clear(); 4446 NodeTys.push_back(MVT::Flag); // Returns a flag 4447 Ops[0] = DAG.getConstant(31, MVT::i32); 4448 Ops[1] = InFlag; 4449 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 4450 InFlag = Result.getValue(0); 4451 4452 NodeTys.clear(); 4453 NodeTys.push_back(MVT::Flag); // Returns a flag 4454 Ops[0] = DAG.getConstant(30, MVT::i32); 4455 Ops[1] = InFlag; 4456 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 4457 InFlag = Result.getValue(0); 4458 4459 NodeTys.clear(); 4460 NodeTys.push_back(MVT::f64); // result of add 4461 NodeTys.push_back(MVT::Flag); // Returns a flag 4462 Ops[0] = Lo; 4463 Ops[1] = Hi; 4464 Ops[2] = InFlag; 4465 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 4466 FPreg = Result.getValue(0); 4467 InFlag = Result.getValue(1); 4468 4469 NodeTys.clear(); 4470 NodeTys.push_back(MVT::f64); 4471 Ops[0] = DAG.getConstant(1, MVT::i32); 4472 Ops[1] = MFFSreg; 4473 Ops[2] = FPreg; 4474 Ops[3] = InFlag; 4475 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 4476 FPreg = Result.getValue(0); 4477 4478 // We know the low half is about to be thrown away, so just use something 4479 // convenient. 4480 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 4481 FPreg, FPreg)); 4482 return; 4483 } 4484 case ISD::FP_TO_SINT: 4485 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 4486 return; 4487 } 4488} 4489 4490 4491//===----------------------------------------------------------------------===// 4492// Other Lowering Code 4493//===----------------------------------------------------------------------===// 4494 4495MachineBasicBlock * 4496PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 4497 bool is64bit, unsigned BinOpcode) const { 4498 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4499 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4500 4501 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4502 MachineFunction *F = BB->getParent(); 4503 MachineFunction::iterator It = BB; 4504 ++It; 4505 4506 unsigned dest = MI->getOperand(0).getReg(); 4507 unsigned ptrA = MI->getOperand(1).getReg(); 4508 unsigned ptrB = MI->getOperand(2).getReg(); 4509 unsigned incr = MI->getOperand(3).getReg(); 4510 DebugLoc dl = MI->getDebugLoc(); 4511 4512 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4513 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4514 F->insert(It, loopMBB); 4515 F->insert(It, exitMBB); 4516 exitMBB->transferSuccessors(BB); 4517 4518 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4519 unsigned TmpReg = (!BinOpcode) ? incr : 4520 RegInfo.createVirtualRegister( 4521 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4522 (const TargetRegisterClass *) &PPC::GPRCRegClass); 4523 4524 // thisMBB: 4525 // ... 4526 // fallthrough --> loopMBB 4527 BB->addSuccessor(loopMBB); 4528 4529 // loopMBB: 4530 // l[wd]arx dest, ptr 4531 // add r0, dest, incr 4532 // st[wd]cx. r0, ptr 4533 // bne- loopMBB 4534 // fallthrough --> exitMBB 4535 BB = loopMBB; 4536 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4537 .addReg(ptrA).addReg(ptrB); 4538 if (BinOpcode) 4539 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 4540 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4541 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 4542 BuildMI(BB, dl, TII->get(PPC::BCC)) 4543 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4544 BB->addSuccessor(loopMBB); 4545 BB->addSuccessor(exitMBB); 4546 4547 // exitMBB: 4548 // ... 4549 BB = exitMBB; 4550 return BB; 4551} 4552 4553MachineBasicBlock * 4554PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 4555 MachineBasicBlock *BB, 4556 bool is8bit, // operation 4557 unsigned BinOpcode) const { 4558 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4559 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4560 // In 64 bit mode we have to use 64 bits for addresses, even though the 4561 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 4562 // registers without caring whether they're 32 or 64, but here we're 4563 // doing actual arithmetic on the addresses. 4564 bool is64bit = PPCSubTarget.isPPC64(); 4565 4566 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4567 MachineFunction *F = BB->getParent(); 4568 MachineFunction::iterator It = BB; 4569 ++It; 4570 4571 unsigned dest = MI->getOperand(0).getReg(); 4572 unsigned ptrA = MI->getOperand(1).getReg(); 4573 unsigned ptrB = MI->getOperand(2).getReg(); 4574 unsigned incr = MI->getOperand(3).getReg(); 4575 DebugLoc dl = MI->getDebugLoc(); 4576 4577 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4578 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4579 F->insert(It, loopMBB); 4580 F->insert(It, exitMBB); 4581 exitMBB->transferSuccessors(BB); 4582 4583 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4584 const TargetRegisterClass *RC = 4585 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4586 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4587 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4588 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4589 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4590 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 4591 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4592 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4593 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4594 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4595 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 4596 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4597 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4598 unsigned Ptr1Reg; 4599 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 4600 4601 // thisMBB: 4602 // ... 4603 // fallthrough --> loopMBB 4604 BB->addSuccessor(loopMBB); 4605 4606 // The 4-byte load must be aligned, while a char or short may be 4607 // anywhere in the word. Hence all this nasty bookkeeping code. 4608 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4609 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4610 // xori shift, shift1, 24 [16] 4611 // rlwinm ptr, ptr1, 0, 0, 29 4612 // slw incr2, incr, shift 4613 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4614 // slw mask, mask2, shift 4615 // loopMBB: 4616 // lwarx tmpDest, ptr 4617 // add tmp, tmpDest, incr2 4618 // andc tmp2, tmpDest, mask 4619 // and tmp3, tmp, mask 4620 // or tmp4, tmp3, tmp2 4621 // stwcx. tmp4, ptr 4622 // bne- loopMBB 4623 // fallthrough --> exitMBB 4624 // srw dest, tmpDest, shift 4625 4626 if (ptrA!=PPC::R0) { 4627 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4628 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4629 .addReg(ptrA).addReg(ptrB); 4630 } else { 4631 Ptr1Reg = ptrB; 4632 } 4633 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4634 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4635 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4636 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4637 if (is64bit) 4638 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4639 .addReg(Ptr1Reg).addImm(0).addImm(61); 4640 else 4641 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4642 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4643 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 4644 .addReg(incr).addReg(ShiftReg); 4645 if (is8bit) 4646 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4647 else { 4648 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4649 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 4650 } 4651 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 4652 .addReg(Mask2Reg).addReg(ShiftReg); 4653 4654 BB = loopMBB; 4655 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 4656 .addReg(PPC::R0).addReg(PtrReg); 4657 if (BinOpcode) 4658 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 4659 .addReg(Incr2Reg).addReg(TmpDestReg); 4660 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 4661 .addReg(TmpDestReg).addReg(MaskReg); 4662 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 4663 .addReg(TmpReg).addReg(MaskReg); 4664 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 4665 .addReg(Tmp3Reg).addReg(Tmp2Reg); 4666 BuildMI(BB, dl, TII->get(PPC::STWCX)) 4667 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg); 4668 BuildMI(BB, dl, TII->get(PPC::BCC)) 4669 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4670 BB->addSuccessor(loopMBB); 4671 BB->addSuccessor(exitMBB); 4672 4673 // exitMBB: 4674 // ... 4675 BB = exitMBB; 4676 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg); 4677 return BB; 4678} 4679 4680MachineBasicBlock * 4681PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4682 MachineBasicBlock *BB) const { 4683 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4684 4685 // To "insert" these instructions we actually have to insert their 4686 // control-flow patterns. 4687 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4688 MachineFunction::iterator It = BB; 4689 ++It; 4690 4691 MachineFunction *F = BB->getParent(); 4692 4693 if (MI->getOpcode() == PPC::SELECT_CC_I4 || 4694 MI->getOpcode() == PPC::SELECT_CC_I8 || 4695 MI->getOpcode() == PPC::SELECT_CC_F4 || 4696 MI->getOpcode() == PPC::SELECT_CC_F8 || 4697 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 4698 4699 // The incoming instruction knows the destination vreg to set, the 4700 // condition code register to branch on, the true/false values to 4701 // select between, and a branch opcode to use. 4702 4703 // thisMBB: 4704 // ... 4705 // TrueVal = ... 4706 // cmpTY ccX, r1, r2 4707 // bCC copy1MBB 4708 // fallthrough --> copy0MBB 4709 MachineBasicBlock *thisMBB = BB; 4710 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4711 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4712 unsigned SelectPred = MI->getOperand(4).getImm(); 4713 DebugLoc dl = MI->getDebugLoc(); 4714 BuildMI(BB, dl, TII->get(PPC::BCC)) 4715 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 4716 F->insert(It, copy0MBB); 4717 F->insert(It, sinkMBB); 4718 // Update machine-CFG edges by first adding all successors of the current 4719 // block to the new block which will contain the Phi node for the select. 4720 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), 4721 E = BB->succ_end(); I != E; ++I) 4722 sinkMBB->addSuccessor(*I); 4723 // Next, remove all successors of the current block, and add the true 4724 // and fallthrough blocks as its successors. 4725 while (!BB->succ_empty()) 4726 BB->removeSuccessor(BB->succ_begin()); 4727 // Next, add the true and fallthrough blocks as its successors. 4728 BB->addSuccessor(copy0MBB); 4729 BB->addSuccessor(sinkMBB); 4730 4731 // copy0MBB: 4732 // %FalseValue = ... 4733 // # fallthrough to sinkMBB 4734 BB = copy0MBB; 4735 4736 // Update machine-CFG edges 4737 BB->addSuccessor(sinkMBB); 4738 4739 // sinkMBB: 4740 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4741 // ... 4742 BB = sinkMBB; 4743 BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg()) 4744 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 4745 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4746 } 4747 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 4748 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 4749 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 4750 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 4751 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 4752 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 4753 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 4754 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 4755 4756 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 4757 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 4758 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 4759 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 4760 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 4761 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 4762 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 4763 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 4764 4765 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 4766 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 4767 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 4768 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 4769 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 4770 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 4771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 4772 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 4773 4774 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 4775 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 4776 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 4777 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 4778 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 4779 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 4780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 4781 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 4782 4783 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 4784 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 4785 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 4786 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 4787 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 4788 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 4789 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 4790 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 4791 4792 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 4793 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 4794 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 4795 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 4796 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 4797 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 4798 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 4799 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 4800 4801 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 4802 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 4803 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 4804 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 4805 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 4806 BB = EmitAtomicBinary(MI, BB, false, 0); 4807 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 4808 BB = EmitAtomicBinary(MI, BB, true, 0); 4809 4810 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 4811 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 4812 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 4813 4814 unsigned dest = MI->getOperand(0).getReg(); 4815 unsigned ptrA = MI->getOperand(1).getReg(); 4816 unsigned ptrB = MI->getOperand(2).getReg(); 4817 unsigned oldval = MI->getOperand(3).getReg(); 4818 unsigned newval = MI->getOperand(4).getReg(); 4819 DebugLoc dl = MI->getDebugLoc(); 4820 4821 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4822 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4823 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4824 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4825 F->insert(It, loop1MBB); 4826 F->insert(It, loop2MBB); 4827 F->insert(It, midMBB); 4828 F->insert(It, exitMBB); 4829 exitMBB->transferSuccessors(BB); 4830 4831 // thisMBB: 4832 // ... 4833 // fallthrough --> loopMBB 4834 BB->addSuccessor(loop1MBB); 4835 4836 // loop1MBB: 4837 // l[wd]arx dest, ptr 4838 // cmp[wd] dest, oldval 4839 // bne- midMBB 4840 // loop2MBB: 4841 // st[wd]cx. newval, ptr 4842 // bne- loopMBB 4843 // b exitBB 4844 // midMBB: 4845 // st[wd]cx. dest, ptr 4846 // exitBB: 4847 BB = loop1MBB; 4848 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4849 .addReg(ptrA).addReg(ptrB); 4850 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 4851 .addReg(oldval).addReg(dest); 4852 BuildMI(BB, dl, TII->get(PPC::BCC)) 4853 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4854 BB->addSuccessor(loop2MBB); 4855 BB->addSuccessor(midMBB); 4856 4857 BB = loop2MBB; 4858 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4859 .addReg(newval).addReg(ptrA).addReg(ptrB); 4860 BuildMI(BB, dl, TII->get(PPC::BCC)) 4861 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 4862 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 4863 BB->addSuccessor(loop1MBB); 4864 BB->addSuccessor(exitMBB); 4865 4866 BB = midMBB; 4867 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4868 .addReg(dest).addReg(ptrA).addReg(ptrB); 4869 BB->addSuccessor(exitMBB); 4870 4871 // exitMBB: 4872 // ... 4873 BB = exitMBB; 4874 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 4875 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 4876 // We must use 64-bit registers for addresses when targeting 64-bit, 4877 // since we're actually doing arithmetic on them. Other registers 4878 // can be 32-bit. 4879 bool is64bit = PPCSubTarget.isPPC64(); 4880 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 4881 4882 unsigned dest = MI->getOperand(0).getReg(); 4883 unsigned ptrA = MI->getOperand(1).getReg(); 4884 unsigned ptrB = MI->getOperand(2).getReg(); 4885 unsigned oldval = MI->getOperand(3).getReg(); 4886 unsigned newval = MI->getOperand(4).getReg(); 4887 DebugLoc dl = MI->getDebugLoc(); 4888 4889 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4890 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4891 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4892 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4893 F->insert(It, loop1MBB); 4894 F->insert(It, loop2MBB); 4895 F->insert(It, midMBB); 4896 F->insert(It, exitMBB); 4897 exitMBB->transferSuccessors(BB); 4898 4899 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4900 const TargetRegisterClass *RC = 4901 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4902 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4903 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4904 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4905 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4906 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 4907 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 4908 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 4909 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 4910 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4911 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4912 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4913 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4914 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4915 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4916 unsigned Ptr1Reg; 4917 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 4918 // thisMBB: 4919 // ... 4920 // fallthrough --> loopMBB 4921 BB->addSuccessor(loop1MBB); 4922 4923 // The 4-byte load must be aligned, while a char or short may be 4924 // anywhere in the word. Hence all this nasty bookkeeping code. 4925 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4926 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4927 // xori shift, shift1, 24 [16] 4928 // rlwinm ptr, ptr1, 0, 0, 29 4929 // slw newval2, newval, shift 4930 // slw oldval2, oldval,shift 4931 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4932 // slw mask, mask2, shift 4933 // and newval3, newval2, mask 4934 // and oldval3, oldval2, mask 4935 // loop1MBB: 4936 // lwarx tmpDest, ptr 4937 // and tmp, tmpDest, mask 4938 // cmpw tmp, oldval3 4939 // bne- midMBB 4940 // loop2MBB: 4941 // andc tmp2, tmpDest, mask 4942 // or tmp4, tmp2, newval3 4943 // stwcx. tmp4, ptr 4944 // bne- loop1MBB 4945 // b exitBB 4946 // midMBB: 4947 // stwcx. tmpDest, ptr 4948 // exitBB: 4949 // srw dest, tmpDest, shift 4950 if (ptrA!=PPC::R0) { 4951 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4952 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4953 .addReg(ptrA).addReg(ptrB); 4954 } else { 4955 Ptr1Reg = ptrB; 4956 } 4957 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4958 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4959 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4960 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4961 if (is64bit) 4962 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4963 .addReg(Ptr1Reg).addImm(0).addImm(61); 4964 else 4965 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4966 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4967 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 4968 .addReg(newval).addReg(ShiftReg); 4969 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 4970 .addReg(oldval).addReg(ShiftReg); 4971 if (is8bit) 4972 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4973 else { 4974 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4975 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 4976 .addReg(Mask3Reg).addImm(65535); 4977 } 4978 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 4979 .addReg(Mask2Reg).addReg(ShiftReg); 4980 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 4981 .addReg(NewVal2Reg).addReg(MaskReg); 4982 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 4983 .addReg(OldVal2Reg).addReg(MaskReg); 4984 4985 BB = loop1MBB; 4986 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 4987 .addReg(PPC::R0).addReg(PtrReg); 4988 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 4989 .addReg(TmpDestReg).addReg(MaskReg); 4990 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 4991 .addReg(TmpReg).addReg(OldVal3Reg); 4992 BuildMI(BB, dl, TII->get(PPC::BCC)) 4993 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4994 BB->addSuccessor(loop2MBB); 4995 BB->addSuccessor(midMBB); 4996 4997 BB = loop2MBB; 4998 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 4999 .addReg(TmpDestReg).addReg(MaskReg); 5000 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 5001 .addReg(Tmp2Reg).addReg(NewVal3Reg); 5002 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 5003 .addReg(PPC::R0).addReg(PtrReg); 5004 BuildMI(BB, dl, TII->get(PPC::BCC)) 5005 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5006 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5007 BB->addSuccessor(loop1MBB); 5008 BB->addSuccessor(exitMBB); 5009 5010 BB = midMBB; 5011 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 5012 .addReg(PPC::R0).addReg(PtrReg); 5013 BB->addSuccessor(exitMBB); 5014 5015 // exitMBB: 5016 // ... 5017 BB = exitMBB; 5018 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); 5019 } else { 5020 llvm_unreachable("Unexpected instr type to insert"); 5021 } 5022 5023 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 5024 return BB; 5025} 5026 5027//===----------------------------------------------------------------------===// 5028// Target Optimization Hooks 5029//===----------------------------------------------------------------------===// 5030 5031SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 5032 DAGCombinerInfo &DCI) const { 5033 const TargetMachine &TM = getTargetMachine(); 5034 SelectionDAG &DAG = DCI.DAG; 5035 DebugLoc dl = N->getDebugLoc(); 5036 switch (N->getOpcode()) { 5037 default: break; 5038 case PPCISD::SHL: 5039 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5040 if (C->isNullValue()) // 0 << V -> 0. 5041 return N->getOperand(0); 5042 } 5043 break; 5044 case PPCISD::SRL: 5045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5046 if (C->isNullValue()) // 0 >>u V -> 0. 5047 return N->getOperand(0); 5048 } 5049 break; 5050 case PPCISD::SRA: 5051 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5052 if (C->isNullValue() || // 0 >>s V -> 0. 5053 C->isAllOnesValue()) // -1 >>s V -> -1. 5054 return N->getOperand(0); 5055 } 5056 break; 5057 5058 case ISD::SINT_TO_FP: 5059 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 5060 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 5061 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 5062 // We allow the src/dst to be either f32/f64, but the intermediate 5063 // type must be i64. 5064 if (N->getOperand(0).getValueType() == MVT::i64 && 5065 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 5066 SDValue Val = N->getOperand(0).getOperand(0); 5067 if (Val.getValueType() == MVT::f32) { 5068 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5069 DCI.AddToWorklist(Val.getNode()); 5070 } 5071 5072 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 5073 DCI.AddToWorklist(Val.getNode()); 5074 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 5075 DCI.AddToWorklist(Val.getNode()); 5076 if (N->getValueType(0) == MVT::f32) { 5077 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 5078 DAG.getIntPtrConstant(0)); 5079 DCI.AddToWorklist(Val.getNode()); 5080 } 5081 return Val; 5082 } else if (N->getOperand(0).getValueType() == MVT::i32) { 5083 // If the intermediate type is i32, we can avoid the load/store here 5084 // too. 5085 } 5086 } 5087 } 5088 break; 5089 case ISD::STORE: 5090 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 5091 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 5092 !cast<StoreSDNode>(N)->isTruncatingStore() && 5093 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 5094 N->getOperand(1).getValueType() == MVT::i32 && 5095 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 5096 SDValue Val = N->getOperand(1).getOperand(0); 5097 if (Val.getValueType() == MVT::f32) { 5098 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5099 DCI.AddToWorklist(Val.getNode()); 5100 } 5101 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 5102 DCI.AddToWorklist(Val.getNode()); 5103 5104 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 5105 N->getOperand(2), N->getOperand(3)); 5106 DCI.AddToWorklist(Val.getNode()); 5107 return Val; 5108 } 5109 5110 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 5111 if (cast<StoreSDNode>(N)->isUnindexed() && 5112 N->getOperand(1).getOpcode() == ISD::BSWAP && 5113 N->getOperand(1).getNode()->hasOneUse() && 5114 (N->getOperand(1).getValueType() == MVT::i32 || 5115 N->getOperand(1).getValueType() == MVT::i16)) { 5116 SDValue BSwapOp = N->getOperand(1).getOperand(0); 5117 // Do an any-extend to 32-bits if this is a half-word input. 5118 if (BSwapOp.getValueType() == MVT::i16) 5119 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 5120 5121 SDValue Ops[] = { 5122 N->getOperand(0), BSwapOp, N->getOperand(2), 5123 DAG.getValueType(N->getOperand(1).getValueType()) 5124 }; 5125 return 5126 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 5127 Ops, array_lengthof(Ops), 5128 cast<StoreSDNode>(N)->getMemoryVT(), 5129 cast<StoreSDNode>(N)->getMemOperand()); 5130 } 5131 break; 5132 case ISD::BSWAP: 5133 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 5134 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 5135 N->getOperand(0).hasOneUse() && 5136 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 5137 SDValue Load = N->getOperand(0); 5138 LoadSDNode *LD = cast<LoadSDNode>(Load); 5139 // Create the byte-swapping load. 5140 SDValue Ops[] = { 5141 LD->getChain(), // Chain 5142 LD->getBasePtr(), // Ptr 5143 DAG.getValueType(N->getValueType(0)) // VT 5144 }; 5145 SDValue BSLoad = 5146 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 5147 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 5148 LD->getMemoryVT(), LD->getMemOperand()); 5149 5150 // If this is an i16 load, insert the truncate. 5151 SDValue ResVal = BSLoad; 5152 if (N->getValueType(0) == MVT::i16) 5153 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 5154 5155 // First, combine the bswap away. This makes the value produced by the 5156 // load dead. 5157 DCI.CombineTo(N, ResVal); 5158 5159 // Next, combine the load away, we give it a bogus result value but a real 5160 // chain result. The result value is dead because the bswap is dead. 5161 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 5162 5163 // Return N so it doesn't get rechecked! 5164 return SDValue(N, 0); 5165 } 5166 5167 break; 5168 case PPCISD::VCMP: { 5169 // If a VCMPo node already exists with exactly the same operands as this 5170 // node, use its result instead of this node (VCMPo computes both a CR6 and 5171 // a normal output). 5172 // 5173 if (!N->getOperand(0).hasOneUse() && 5174 !N->getOperand(1).hasOneUse() && 5175 !N->getOperand(2).hasOneUse()) { 5176 5177 // Scan all of the users of the LHS, looking for VCMPo's that match. 5178 SDNode *VCMPoNode = 0; 5179 5180 SDNode *LHSN = N->getOperand(0).getNode(); 5181 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 5182 UI != E; ++UI) 5183 if (UI->getOpcode() == PPCISD::VCMPo && 5184 UI->getOperand(1) == N->getOperand(1) && 5185 UI->getOperand(2) == N->getOperand(2) && 5186 UI->getOperand(0) == N->getOperand(0)) { 5187 VCMPoNode = *UI; 5188 break; 5189 } 5190 5191 // If there is no VCMPo node, or if the flag value has a single use, don't 5192 // transform this. 5193 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 5194 break; 5195 5196 // Look at the (necessarily single) use of the flag value. If it has a 5197 // chain, this transformation is more complex. Note that multiple things 5198 // could use the value result, which we should ignore. 5199 SDNode *FlagUser = 0; 5200 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 5201 FlagUser == 0; ++UI) { 5202 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 5203 SDNode *User = *UI; 5204 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 5205 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 5206 FlagUser = User; 5207 break; 5208 } 5209 } 5210 } 5211 5212 // If the user is a MFCR instruction, we know this is safe. Otherwise we 5213 // give up for right now. 5214 if (FlagUser->getOpcode() == PPCISD::MFCR) 5215 return SDValue(VCMPoNode, 0); 5216 } 5217 break; 5218 } 5219 case ISD::BR_CC: { 5220 // If this is a branch on an altivec predicate comparison, lower this so 5221 // that we don't have to do a MFCR: instead, branch directly on CR6. This 5222 // lowering is done pre-legalize, because the legalizer lowers the predicate 5223 // compare down to code that is difficult to reassemble. 5224 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 5225 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 5226 int CompareOpc; 5227 bool isDot; 5228 5229 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 5230 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 5231 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 5232 assert(isDot && "Can't compare against a vector result!"); 5233 5234 // If this is a comparison against something other than 0/1, then we know 5235 // that the condition is never/always true. 5236 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 5237 if (Val != 0 && Val != 1) { 5238 if (CC == ISD::SETEQ) // Cond never true, remove branch. 5239 return N->getOperand(0); 5240 // Always !=, turn it into an unconditional branch. 5241 return DAG.getNode(ISD::BR, dl, MVT::Other, 5242 N->getOperand(0), N->getOperand(4)); 5243 } 5244 5245 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 5246 5247 // Create the PPCISD altivec 'dot' comparison node. 5248 std::vector<EVT> VTs; 5249 SDValue Ops[] = { 5250 LHS.getOperand(2), // LHS of compare 5251 LHS.getOperand(3), // RHS of compare 5252 DAG.getConstant(CompareOpc, MVT::i32) 5253 }; 5254 VTs.push_back(LHS.getOperand(2).getValueType()); 5255 VTs.push_back(MVT::Flag); 5256 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5257 5258 // Unpack the result based on how the target uses it. 5259 PPC::Predicate CompOpc; 5260 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 5261 default: // Can't happen, don't crash on invalid number though. 5262 case 0: // Branch on the value of the EQ bit of CR6. 5263 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 5264 break; 5265 case 1: // Branch on the inverted value of the EQ bit of CR6. 5266 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 5267 break; 5268 case 2: // Branch on the value of the LT bit of CR6. 5269 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 5270 break; 5271 case 3: // Branch on the inverted value of the LT bit of CR6. 5272 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 5273 break; 5274 } 5275 5276 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 5277 DAG.getConstant(CompOpc, MVT::i32), 5278 DAG.getRegister(PPC::CR6, MVT::i32), 5279 N->getOperand(4), CompNode.getValue(1)); 5280 } 5281 break; 5282 } 5283 } 5284 5285 return SDValue(); 5286} 5287 5288//===----------------------------------------------------------------------===// 5289// Inline Assembly Support 5290//===----------------------------------------------------------------------===// 5291 5292void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 5293 const APInt &Mask, 5294 APInt &KnownZero, 5295 APInt &KnownOne, 5296 const SelectionDAG &DAG, 5297 unsigned Depth) const { 5298 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 5299 switch (Op.getOpcode()) { 5300 default: break; 5301 case PPCISD::LBRX: { 5302 // lhbrx is known to have the top bits cleared out. 5303 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 5304 KnownZero = 0xFFFF0000; 5305 break; 5306 } 5307 case ISD::INTRINSIC_WO_CHAIN: { 5308 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 5309 default: break; 5310 case Intrinsic::ppc_altivec_vcmpbfp_p: 5311 case Intrinsic::ppc_altivec_vcmpeqfp_p: 5312 case Intrinsic::ppc_altivec_vcmpequb_p: 5313 case Intrinsic::ppc_altivec_vcmpequh_p: 5314 case Intrinsic::ppc_altivec_vcmpequw_p: 5315 case Intrinsic::ppc_altivec_vcmpgefp_p: 5316 case Intrinsic::ppc_altivec_vcmpgtfp_p: 5317 case Intrinsic::ppc_altivec_vcmpgtsb_p: 5318 case Intrinsic::ppc_altivec_vcmpgtsh_p: 5319 case Intrinsic::ppc_altivec_vcmpgtsw_p: 5320 case Intrinsic::ppc_altivec_vcmpgtub_p: 5321 case Intrinsic::ppc_altivec_vcmpgtuh_p: 5322 case Intrinsic::ppc_altivec_vcmpgtuw_p: 5323 KnownZero = ~1U; // All bits but the low one are known to be zero. 5324 break; 5325 } 5326 } 5327 } 5328} 5329 5330 5331/// getConstraintType - Given a constraint, return the type of 5332/// constraint it is for this target. 5333PPCTargetLowering::ConstraintType 5334PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 5335 if (Constraint.size() == 1) { 5336 switch (Constraint[0]) { 5337 default: break; 5338 case 'b': 5339 case 'r': 5340 case 'f': 5341 case 'v': 5342 case 'y': 5343 return C_RegisterClass; 5344 } 5345 } 5346 return TargetLowering::getConstraintType(Constraint); 5347} 5348 5349std::pair<unsigned, const TargetRegisterClass*> 5350PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5351 EVT VT) const { 5352 if (Constraint.size() == 1) { 5353 // GCC RS6000 Constraint Letters 5354 switch (Constraint[0]) { 5355 case 'b': // R1-R31 5356 case 'r': // R0-R31 5357 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 5358 return std::make_pair(0U, PPC::G8RCRegisterClass); 5359 return std::make_pair(0U, PPC::GPRCRegisterClass); 5360 case 'f': 5361 if (VT == MVT::f32) 5362 return std::make_pair(0U, PPC::F4RCRegisterClass); 5363 else if (VT == MVT::f64) 5364 return std::make_pair(0U, PPC::F8RCRegisterClass); 5365 break; 5366 case 'v': 5367 return std::make_pair(0U, PPC::VRRCRegisterClass); 5368 case 'y': // crrc 5369 return std::make_pair(0U, PPC::CRRCRegisterClass); 5370 } 5371 } 5372 5373 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5374} 5375 5376 5377/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5378/// vector. If it is invalid, don't add anything to Ops. 5379void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, 5380 std::vector<SDValue>&Ops, 5381 SelectionDAG &DAG) const { 5382 SDValue Result(0,0); 5383 switch (Letter) { 5384 default: break; 5385 case 'I': 5386 case 'J': 5387 case 'K': 5388 case 'L': 5389 case 'M': 5390 case 'N': 5391 case 'O': 5392 case 'P': { 5393 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 5394 if (!CST) return; // Must be an immediate to match. 5395 unsigned Value = CST->getZExtValue(); 5396 switch (Letter) { 5397 default: llvm_unreachable("Unknown constraint letter!"); 5398 case 'I': // "I" is a signed 16-bit constant. 5399 if ((short)Value == (int)Value) 5400 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5401 break; 5402 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 5403 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 5404 if ((short)Value == 0) 5405 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5406 break; 5407 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 5408 if ((Value >> 16) == 0) 5409 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5410 break; 5411 case 'M': // "M" is a constant that is greater than 31. 5412 if (Value > 31) 5413 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5414 break; 5415 case 'N': // "N" is a positive constant that is an exact power of two. 5416 if ((int)Value > 0 && isPowerOf2_32(Value)) 5417 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5418 break; 5419 case 'O': // "O" is the constant zero. 5420 if (Value == 0) 5421 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5422 break; 5423 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 5424 if ((short)-Value == (int)-Value) 5425 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5426 break; 5427 } 5428 break; 5429 } 5430 } 5431 5432 if (Result.getNode()) { 5433 Ops.push_back(Result); 5434 return; 5435 } 5436 5437 // Handle standard constraint letters. 5438 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); 5439} 5440 5441// isLegalAddressingMode - Return true if the addressing mode represented 5442// by AM is legal for this target, for a load/store of the specified type. 5443bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 5444 const Type *Ty) const { 5445 // FIXME: PPC does not allow r+i addressing modes for vectors! 5446 5447 // PPC allows a sign-extended 16-bit immediate field. 5448 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 5449 return false; 5450 5451 // No global is ever allowed as a base. 5452 if (AM.BaseGV) 5453 return false; 5454 5455 // PPC only support r+r, 5456 switch (AM.Scale) { 5457 case 0: // "r+i" or just "i", depending on HasBaseReg. 5458 break; 5459 case 1: 5460 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 5461 return false; 5462 // Otherwise we have r+r or r+i. 5463 break; 5464 case 2: 5465 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 5466 return false; 5467 // Allow 2*r as r+r. 5468 break; 5469 default: 5470 // No other scales are supported. 5471 return false; 5472 } 5473 5474 return true; 5475} 5476 5477/// isLegalAddressImmediate - Return true if the integer value can be used 5478/// as the offset of the target addressing mode for load / store of the 5479/// given type. 5480bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 5481 // PPC allows a sign-extended 16-bit immediate field. 5482 return (V > -(1 << 16) && V < (1 << 16)-1); 5483} 5484 5485bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 5486 return false; 5487} 5488 5489SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 5490 SelectionDAG &DAG) const { 5491 MachineFunction &MF = DAG.getMachineFunction(); 5492 MachineFrameInfo *MFI = MF.getFrameInfo(); 5493 MFI->setReturnAddressIsTaken(true); 5494 5495 DebugLoc dl = Op.getDebugLoc(); 5496 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5497 5498 // Make sure the function does not optimize away the store of the RA to 5499 // the stack. 5500 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 5501 FuncInfo->setLRStoreRequired(); 5502 bool isPPC64 = PPCSubTarget.isPPC64(); 5503 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 5504 5505 if (Depth > 0) { 5506 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 5507 SDValue Offset = 5508 5509 DAG.getConstant(PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI), 5510 isPPC64? MVT::i64 : MVT::i32); 5511 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5512 DAG.getNode(ISD::ADD, dl, getPointerTy(), 5513 FrameAddr, Offset), 5514 NULL, 0, false, false, 0); 5515 } 5516 5517 // Just load the return address off the stack. 5518 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 5519 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5520 RetAddrFI, NULL, 0, false, false, 0); 5521} 5522 5523SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 5524 SelectionDAG &DAG) const { 5525 DebugLoc dl = Op.getDebugLoc(); 5526 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5527 5528 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 5529 bool isPPC64 = PtrVT == MVT::i64; 5530 5531 MachineFunction &MF = DAG.getMachineFunction(); 5532 MachineFrameInfo *MFI = MF.getFrameInfo(); 5533 MFI->setFrameAddressIsTaken(true); 5534 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) && 5535 MFI->getStackSize() && 5536 !MF.getFunction()->hasFnAttr(Attribute::Naked); 5537 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) : 5538 (is31 ? PPC::R31 : PPC::R1); 5539 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 5540 PtrVT); 5541 while (Depth--) 5542 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 5543 FrameAddr, NULL, 0, false, false, 0); 5544 return FrameAddr; 5545} 5546 5547bool 5548PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 5549 // The PowerPC target isn't yet aware of offsets. 5550 return false; 5551} 5552 5553/// getOptimalMemOpType - Returns the target specific optimal type for load 5554/// and store operations as a result of memset, memcpy, and memmove 5555/// lowering. If DstAlign is zero that means it's safe to destination 5556/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 5557/// means there isn't a need to check it against alignment requirement, 5558/// probably because the source does not need to be loaded. If 5559/// 'NonScalarIntSafe' is true, that means it's safe to return a 5560/// non-scalar-integer type, e.g. empty string source, constant, or loaded 5561/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 5562/// constant so it does not need to be loaded. 5563/// It returns EVT::Other if the type should be determined using generic 5564/// target-independent logic. 5565EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 5566 unsigned DstAlign, unsigned SrcAlign, 5567 bool NonScalarIntSafe, 5568 bool MemcpyStrSrc, 5569 MachineFunction &MF) const { 5570 if (this->PPCSubTarget.isPPC64()) { 5571 return MVT::i64; 5572 } else { 5573 return MVT::i32; 5574 } 5575} 5576