PPCISelLowering.cpp revision 28a6b02626c29b1fe9bb16c14c193549fab4cab8
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCTargetMachine.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "llvm/CodeGen/SSARegMap.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23using namespace llvm; 24 25PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) 26 : TargetLowering(TM) { 27 28 // Fold away setcc operations if possible. 29 setSetCCIsExpensive(); 30 setPow2DivIsCheap(); 31 32 // Use _setjmp/_longjmp instead of setjmp/longjmp. 33 setUseUnderscoreSetJmpLongJmp(true); 34 35 // Set up the register classes. 36 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 37 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 38 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 39 40 // PowerPC has no intrinsics for these particular operations 41 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 42 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 43 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 44 45 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 46 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); 47 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); 48 49 // PowerPC has no SREM/UREM instructions 50 setOperationAction(ISD::SREM, MVT::i32, Expand); 51 setOperationAction(ISD::UREM, MVT::i32, Expand); 52 53 // We don't support sin/cos/sqrt/fmod 54 setOperationAction(ISD::FSIN , MVT::f64, Expand); 55 setOperationAction(ISD::FCOS , MVT::f64, Expand); 56 setOperationAction(ISD::FREM , MVT::f64, Expand); 57 setOperationAction(ISD::FSIN , MVT::f32, Expand); 58 setOperationAction(ISD::FCOS , MVT::f32, Expand); 59 setOperationAction(ISD::FREM , MVT::f32, Expand); 60 61 // If we're enabling GP optimizations, use hardware square root 62 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 63 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 64 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 65 } 66 67 // PowerPC does not have CTPOP or CTTZ 68 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 69 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 70 71 // PowerPC does not have Select 72 setOperationAction(ISD::SELECT, MVT::i32, Expand); 73 setOperationAction(ISD::SELECT, MVT::f32, Expand); 74 setOperationAction(ISD::SELECT, MVT::f64, Expand); 75 76 // PowerPC wants to turn select_cc of FP into fsel when possible. 77 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 78 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 79 80 // PowerPC does not have BRCOND* which requires SetCC 81 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 82 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 83 84 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 85 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 86 87 // PowerPC does not have [U|S]INT_TO_FP 88 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 89 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 90 91 // PowerPC does not have truncstore for i1. 92 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); 93 94 // PowerPC doesn't have line number support yet. 95 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 96 97 // We want to legalize GlobalAddress and ConstantPool nodes into the 98 // appropriate instructions to materialize the address. 99 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 100 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 101 102 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 103 // They also have instructions for converting between i64 and fp. 104 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 105 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 106 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 107 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 108 } else { 109 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 110 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 111 } 112 113 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) { 114 // 64 bit PowerPC implementations can support i64 types directly 115 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 116 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 117 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 118 } else { 119 // 32 bit PowerPC wants to expand i64 shifts itself. 120 setOperationAction(ISD::SHL, MVT::i64, Custom); 121 setOperationAction(ISD::SRL, MVT::i64, Custom); 122 setOperationAction(ISD::SRA, MVT::i64, Custom); 123 } 124 125 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 126 // FIXME: AltiVec supports a wide variety of packed types. For now, we're 127 // bringing up support with just v4f32. 128 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 129 } 130 131 setSetCCResultContents(ZeroOrOneSetCCResult); 132 133 computeRegisterProperties(); 134} 135 136/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 137static bool isFloatingPointZero(SDOperand Op) { 138 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 139 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 140 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { 141 // Maybe this has already been legalized into the constant pool? 142 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 143 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get())) 144 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 145 } 146 return false; 147} 148 149/// LowerOperation - Provide custom lowering hooks for some operations. 150/// 151SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 152 switch (Op.getOpcode()) { 153 default: assert(0 && "Wasn't expecting to be able to lower this!"); 154 case ISD::FP_TO_SINT: { 155 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 156 SDOperand Src = Op.getOperand(0); 157 if (Src.getValueType() == MVT::f32) 158 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 159 160 switch (Op.getValueType()) { 161 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 162 case MVT::i32: 163 Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 164 break; 165 case MVT::i64: 166 Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 167 break; 168 } 169 170 int FrameIdx = 171 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); 172 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 173 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 174 Op, FI, DAG.getSrcValue(0)); 175 if (Op.getOpcode() == PPCISD::FCTIDZ) { 176 Op = DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0)); 177 } else { 178 FI = DAG.getNode(ISD::ADD, MVT::i32, FI, DAG.getConstant(4, MVT::i32)); 179 Op = DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0)); 180 } 181 return Op; 182 } 183 case ISD::SINT_TO_FP: { 184 assert(MVT::i64 == Op.getOperand(0).getValueType() && 185 "Unhandled SINT_TO_FP type in custom expander!"); 186 int FrameIdx = 187 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); 188 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 189 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 190 Op.getOperand(0), FI, DAG.getSrcValue(0)); 191 SDOperand LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0)); 192 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, LD); 193 if (MVT::f32 == Op.getValueType()) 194 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 195 return FP; 196 } 197 case ISD::SELECT_CC: { 198 // Turn FP only select_cc's into fsel instructions. 199 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 200 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 201 break; 202 203 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 204 205 // Cannot handle SETEQ/SETNE. 206 if (CC == ISD::SETEQ || CC == ISD::SETNE) break; 207 208 MVT::ValueType ResVT = Op.getValueType(); 209 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 210 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 211 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 212 213 // If the RHS of the comparison is a 0.0, we don't need to do the 214 // subtraction at all. 215 if (isFloatingPointZero(RHS)) 216 switch (CC) { 217 default: assert(0 && "Invalid FSEL condition"); abort(); 218 case ISD::SETULT: 219 case ISD::SETLT: 220 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 221 case ISD::SETUGE: 222 case ISD::SETGE: 223 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 224 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 225 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 226 case ISD::SETUGT: 227 case ISD::SETGT: 228 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 229 case ISD::SETULE: 230 case ISD::SETLE: 231 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 232 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 233 return DAG.getNode(PPCISD::FSEL, ResVT, 234 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 235 } 236 237 SDOperand Cmp; 238 switch (CC) { 239 default: assert(0 && "Invalid FSEL condition"); abort(); 240 case ISD::SETULT: 241 case ISD::SETLT: 242 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 243 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 244 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 245 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 246 case ISD::SETUGE: 247 case ISD::SETGE: 248 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 249 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 250 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 251 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 252 case ISD::SETUGT: 253 case ISD::SETGT: 254 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 255 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 256 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 257 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 258 case ISD::SETULE: 259 case ISD::SETLE: 260 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 261 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 262 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 263 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 264 } 265 break; 266 } 267 case ISD::SHL: { 268 assert(Op.getValueType() == MVT::i64 && 269 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 270 // The generic code does a fine job expanding shift by a constant. 271 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 272 273 // Otherwise, expand into a bunch of logical ops. Note that these ops 274 // depend on the PPC behavior for oversized shift amounts. 275 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 276 DAG.getConstant(0, MVT::i32)); 277 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 278 DAG.getConstant(1, MVT::i32)); 279 SDOperand Amt = Op.getOperand(1); 280 281 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 282 DAG.getConstant(32, MVT::i32), Amt); 283 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 284 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 285 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 286 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 287 DAG.getConstant(-32U, MVT::i32)); 288 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 289 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 290 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 291 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 292 } 293 case ISD::SRL: { 294 assert(Op.getValueType() == MVT::i64 && 295 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 296 // The generic code does a fine job expanding shift by a constant. 297 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 298 299 // Otherwise, expand into a bunch of logical ops. Note that these ops 300 // depend on the PPC behavior for oversized shift amounts. 301 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 302 DAG.getConstant(0, MVT::i32)); 303 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 304 DAG.getConstant(1, MVT::i32)); 305 SDOperand Amt = Op.getOperand(1); 306 307 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 308 DAG.getConstant(32, MVT::i32), Amt); 309 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 310 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 311 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 312 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 313 DAG.getConstant(-32U, MVT::i32)); 314 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 315 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 316 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 317 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 318 } 319 case ISD::SRA: { 320 assert(Op.getValueType() == MVT::i64 && 321 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 322 // The generic code does a fine job expanding shift by a constant. 323 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 324 325 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 326 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 327 DAG.getConstant(0, MVT::i32)); 328 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 329 DAG.getConstant(1, MVT::i32)); 330 SDOperand Amt = Op.getOperand(1); 331 332 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 333 DAG.getConstant(32, MVT::i32), Amt); 334 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 335 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 336 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 337 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 338 DAG.getConstant(-32U, MVT::i32)); 339 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 340 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 341 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 342 Tmp4, Tmp6, ISD::SETLE); 343 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 344 } 345 case ISD::ConstantPool: { 346 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 347 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32); 348 SDOperand Zero = DAG.getConstant(0, MVT::i32); 349 350 if (PPCGenerateStaticCode) { 351 // Generate non-pic code that has direct accesses to the constant pool. 352 // The address of the global is just (hi(&g)+lo(&g)). 353 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 354 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 355 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 356 } 357 358 // Only lower ConstantPool on Darwin. 359 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 360 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 361 if (PICEnabled) { 362 // With PIC, the first instruction is actually "GR+hi(&G)". 363 Hi = DAG.getNode(ISD::ADD, MVT::i32, 364 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 365 } 366 367 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 368 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 369 return Lo; 370 } 371 case ISD::GlobalAddress: { 372 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 373 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 374 SDOperand Zero = DAG.getConstant(0, MVT::i32); 375 376 if (PPCGenerateStaticCode) { 377 // Generate non-pic code that has direct accesses to globals. 378 // The address of the global is just (hi(&g)+lo(&g)). 379 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 380 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 381 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 382 } 383 384 // Only lower GlobalAddress on Darwin. 385 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 386 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 387 if (PICEnabled) { 388 // With PIC, the first instruction is actually "GR+hi(&G)". 389 Hi = DAG.getNode(ISD::ADD, MVT::i32, 390 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 391 } 392 393 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 394 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 395 396 if (!GV->hasWeakLinkage() && !GV->isExternal()) 397 return Lo; 398 399 // If the global is weak or external, we have to go through the lazy 400 // resolution stub. 401 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); 402 } 403 } 404 return SDOperand(); 405} 406 407std::vector<SDOperand> 408PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 409 // 410 // add beautiful description of PPC stack frame format, or at least some docs 411 // 412 MachineFunction &MF = DAG.getMachineFunction(); 413 MachineFrameInfo *MFI = MF.getFrameInfo(); 414 MachineBasicBlock& BB = MF.front(); 415 SSARegMap *RegMap = MF.getSSARegMap(); 416 std::vector<SDOperand> ArgValues; 417 418 unsigned ArgOffset = 24; 419 unsigned GPR_remaining = 8; 420 unsigned FPR_remaining = 13; 421 unsigned GPR_idx = 0, FPR_idx = 0; 422 static const unsigned GPR[] = { 423 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 424 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 425 }; 426 static const unsigned FPR[] = { 427 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 428 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 429 }; 430 431 // Add DAG nodes to load the arguments... On entry to a function on PPC, 432 // the arguments start at offset 24, although they are likely to be passed 433 // in registers. 434 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 435 SDOperand newroot, argt; 436 unsigned ObjSize; 437 bool needsLoad = false; 438 bool ArgLive = !I->use_empty(); 439 MVT::ValueType ObjectVT = getValueType(I->getType()); 440 441 switch (ObjectVT) { 442 default: assert(0 && "Unhandled argument type!"); 443 case MVT::i1: 444 case MVT::i8: 445 case MVT::i16: 446 case MVT::i32: 447 ObjSize = 4; 448 if (!ArgLive) break; 449 if (GPR_remaining > 0) { 450 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 451 MF.addLiveIn(GPR[GPR_idx], VReg); 452 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 453 if (ObjectVT != MVT::i32) { 454 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 455 : ISD::AssertZext; 456 argt = DAG.getNode(AssertOp, MVT::i32, argt, 457 DAG.getValueType(ObjectVT)); 458 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt); 459 } 460 } else { 461 needsLoad = true; 462 } 463 break; 464 case MVT::i64: 465 ObjSize = 8; 466 if (!ArgLive) break; 467 if (GPR_remaining > 0) { 468 SDOperand argHi, argLo; 469 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 470 MF.addLiveIn(GPR[GPR_idx], VReg); 471 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 472 // If we have two or more remaining argument registers, then both halves 473 // of the i64 can be sourced from there. Otherwise, the lower half will 474 // have to come off the stack. This can happen when an i64 is preceded 475 // by 28 bytes of arguments. 476 if (GPR_remaining > 1) { 477 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 478 MF.addLiveIn(GPR[GPR_idx+1], VReg); 479 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32); 480 } else { 481 int FI = MFI->CreateFixedObject(4, ArgOffset+4); 482 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 483 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 484 DAG.getSrcValue(NULL)); 485 } 486 // Build the outgoing arg thingy 487 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi); 488 newroot = argLo; 489 } else { 490 needsLoad = true; 491 } 492 break; 493 case MVT::f32: 494 case MVT::f64: 495 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4; 496 if (!ArgLive) break; 497 if (FPR_remaining > 0) { 498 unsigned VReg; 499 if (ObjectVT == MVT::f32) 500 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 501 else 502 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 503 MF.addLiveIn(FPR[FPR_idx], VReg); 504 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT); 505 --FPR_remaining; 506 ++FPR_idx; 507 } else { 508 needsLoad = true; 509 } 510 break; 511 } 512 513 // We need to load the argument to a virtual register if we determined above 514 // that we ran out of physical registers of the appropriate type 515 if (needsLoad) { 516 unsigned SubregOffset = 0; 517 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3; 518 if (ObjectVT == MVT::i16) SubregOffset = 2; 519 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 520 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 521 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, 522 DAG.getConstant(SubregOffset, MVT::i32)); 523 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 524 DAG.getSrcValue(NULL)); 525 } 526 527 // Every 4 bytes of argument space consumes one of the GPRs available for 528 // argument passing. 529 if (GPR_remaining > 0) { 530 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; 531 GPR_remaining -= delta; 532 GPR_idx += delta; 533 } 534 ArgOffset += ObjSize; 535 if (newroot.Val) 536 DAG.setRoot(newroot.getValue(1)); 537 538 ArgValues.push_back(argt); 539 } 540 541 // If the function takes variable number of arguments, make a frame index for 542 // the start of the first vararg value... for expansion of llvm.va_start. 543 if (F.isVarArg()) { 544 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 545 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 546 // If this function is vararg, store any remaining integer argument regs 547 // to their spots on the stack so that they may be loaded by deferencing the 548 // result of va_next. 549 std::vector<SDOperand> MemOps; 550 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { 551 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 552 MF.addLiveIn(GPR[GPR_idx], VReg); 553 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 554 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 555 Val, FIN, DAG.getSrcValue(NULL)); 556 MemOps.push_back(Store); 557 // Increment the address by four for the next argument to store 558 SDOperand PtrOff = DAG.getConstant(4, getPointerTy()); 559 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff); 560 } 561 if (!MemOps.empty()) { 562 MemOps.push_back(DAG.getRoot()); 563 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps)); 564 } 565 } 566 567 // Finally, inform the code generator which regs we return values in. 568 switch (getValueType(F.getReturnType())) { 569 default: assert(0 && "Unknown type!"); 570 case MVT::isVoid: break; 571 case MVT::i1: 572 case MVT::i8: 573 case MVT::i16: 574 case MVT::i32: 575 MF.addLiveOut(PPC::R3); 576 break; 577 case MVT::i64: 578 MF.addLiveOut(PPC::R3); 579 MF.addLiveOut(PPC::R4); 580 break; 581 case MVT::f32: 582 case MVT::f64: 583 MF.addLiveOut(PPC::F1); 584 break; 585 } 586 587 return ArgValues; 588} 589 590std::pair<SDOperand, SDOperand> 591PPCTargetLowering::LowerCallTo(SDOperand Chain, 592 const Type *RetTy, bool isVarArg, 593 unsigned CallingConv, bool isTailCall, 594 SDOperand Callee, ArgListTy &Args, 595 SelectionDAG &DAG) { 596 // args_to_use will accumulate outgoing args for the ISD::CALL case in 597 // SelectExpr to use to put the arguments in the appropriate registers. 598 std::vector<SDOperand> args_to_use; 599 600 // Count how many bytes are to be pushed on the stack, including the linkage 601 // area, and parameter passing area. 602 unsigned NumBytes = 24; 603 604 if (Args.empty()) { 605 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 606 DAG.getConstant(NumBytes, getPointerTy())); 607 } else { 608 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 609 switch (getValueType(Args[i].second)) { 610 default: assert(0 && "Unknown value type!"); 611 case MVT::i1: 612 case MVT::i8: 613 case MVT::i16: 614 case MVT::i32: 615 case MVT::f32: 616 NumBytes += 4; 617 break; 618 case MVT::i64: 619 case MVT::f64: 620 NumBytes += 8; 621 break; 622 } 623 } 624 625 // Just to be safe, we'll always reserve the full 24 bytes of linkage area 626 // plus 32 bytes of argument space in case any called code gets funky on us. 627 // (Required by ABI to support var arg) 628 if (NumBytes < 56) NumBytes = 56; 629 630 // Adjust the stack pointer for the new arguments... 631 // These operations are automatically eliminated by the prolog/epilog pass 632 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 633 DAG.getConstant(NumBytes, getPointerTy())); 634 635 // Set up a copy of the stack pointer for use loading and storing any 636 // arguments that may not fit in the registers available for argument 637 // passing. 638 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), 639 PPC::R1, MVT::i32); 640 641 // Figure out which arguments are going to go in registers, and which in 642 // memory. Also, if this is a vararg function, floating point operations 643 // must be stored to our stack, and loaded into integer regs as well, if 644 // any integer regs are available for argument passing. 645 unsigned ArgOffset = 24; 646 unsigned GPR_remaining = 8; 647 unsigned FPR_remaining = 13; 648 649 std::vector<SDOperand> MemOps; 650 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 651 // PtrOff will be used to store the current argument to the stack if a 652 // register cannot be found for it. 653 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 654 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 655 MVT::ValueType ArgVT = getValueType(Args[i].second); 656 657 switch (ArgVT) { 658 default: assert(0 && "Unexpected ValueType for argument!"); 659 case MVT::i1: 660 case MVT::i8: 661 case MVT::i16: 662 // Promote the integer to 32 bits. If the input type is signed use a 663 // sign extend, otherwise use a zero extend. 664 if (Args[i].second->isSigned()) 665 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 666 else 667 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 668 // FALL THROUGH 669 case MVT::i32: 670 if (GPR_remaining > 0) { 671 args_to_use.push_back(Args[i].first); 672 --GPR_remaining; 673 } else { 674 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 675 Args[i].first, PtrOff, 676 DAG.getSrcValue(NULL))); 677 } 678 ArgOffset += 4; 679 break; 680 case MVT::i64: 681 // If we have one free GPR left, we can place the upper half of the i64 682 // in it, and store the other half to the stack. If we have two or more 683 // free GPRs, then we can pass both halves of the i64 in registers. 684 if (GPR_remaining > 0) { 685 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 686 Args[i].first, DAG.getConstant(1, MVT::i32)); 687 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 688 Args[i].first, DAG.getConstant(0, MVT::i32)); 689 args_to_use.push_back(Hi); 690 --GPR_remaining; 691 if (GPR_remaining > 0) { 692 args_to_use.push_back(Lo); 693 --GPR_remaining; 694 } else { 695 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 696 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 697 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 698 Lo, PtrOff, DAG.getSrcValue(NULL))); 699 } 700 } else { 701 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 702 Args[i].first, PtrOff, 703 DAG.getSrcValue(NULL))); 704 } 705 ArgOffset += 8; 706 break; 707 case MVT::f32: 708 case MVT::f64: 709 if (FPR_remaining > 0) { 710 args_to_use.push_back(Args[i].first); 711 --FPR_remaining; 712 if (isVarArg) { 713 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 714 Args[i].first, PtrOff, 715 DAG.getSrcValue(NULL)); 716 MemOps.push_back(Store); 717 // Float varargs are always shadowed in available integer registers 718 if (GPR_remaining > 0) { 719 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 720 DAG.getSrcValue(NULL)); 721 MemOps.push_back(Load.getValue(1)); 722 args_to_use.push_back(Load); 723 --GPR_remaining; 724 } 725 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 726 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 727 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 728 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 729 DAG.getSrcValue(NULL)); 730 MemOps.push_back(Load.getValue(1)); 731 args_to_use.push_back(Load); 732 --GPR_remaining; 733 } 734 } else { 735 // If we have any FPRs remaining, we may also have GPRs remaining. 736 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 737 // GPRs. 738 if (GPR_remaining > 0) { 739 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 740 --GPR_remaining; 741 } 742 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 743 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 744 --GPR_remaining; 745 } 746 } 747 } else { 748 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 749 Args[i].first, PtrOff, 750 DAG.getSrcValue(NULL))); 751 } 752 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8; 753 break; 754 } 755 } 756 if (!MemOps.empty()) 757 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); 758 } 759 760 std::vector<MVT::ValueType> RetVals; 761 MVT::ValueType RetTyVT = getValueType(RetTy); 762 MVT::ValueType ActualRetTyVT = RetTyVT; 763 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 764 ActualRetTyVT = MVT::i32; // Promote result to i32. 765 766 if (RetTyVT != MVT::isVoid) 767 RetVals.push_back(ActualRetTyVT); 768 RetVals.push_back(MVT::Other); 769 770 // If the callee is a GlobalAddress node (quite common, every direct call is) 771 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 772 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 773 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 774 775 SDOperand TheCall = SDOperand(DAG.getCall(RetVals, 776 Chain, Callee, args_to_use), 0); 777 Chain = TheCall.getValue(RetTyVT != MVT::isVoid); 778 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 779 DAG.getConstant(NumBytes, getPointerTy())); 780 SDOperand RetVal = TheCall; 781 782 // If the result is a small value, add a note so that we keep track of the 783 // information about whether it is sign or zero extended. 784 if (RetTyVT != ActualRetTyVT) { 785 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext, 786 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 787 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 788 } 789 790 return std::make_pair(RetVal, Chain); 791} 792 793SDOperand PPCTargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 794 SelectionDAG &DAG) { 795 if (Op.getValueType() == MVT::i64) { 796 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 797 DAG.getConstant(1, MVT::i32)); 798 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 799 DAG.getConstant(0, MVT::i32)); 800 return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi); 801 } else { 802 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op); 803 } 804} 805 806SDOperand PPCTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP, 807 Value *VAListV, SelectionDAG &DAG) { 808 // vastart just stores the address of the VarArgsFrameIndex slot into the 809 // memory location argument. 810 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 811 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, 812 DAG.getSrcValue(VAListV)); 813} 814 815std::pair<SDOperand,SDOperand> 816PPCTargetLowering::LowerVAArg(SDOperand Chain, 817 SDOperand VAListP, Value *VAListV, 818 const Type *ArgTy, SelectionDAG &DAG) { 819 MVT::ValueType ArgVT = getValueType(ArgTy); 820 821 SDOperand VAList = 822 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV)); 823 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL)); 824 unsigned Amt; 825 if (ArgVT == MVT::i32 || ArgVT == MVT::f32) 826 Amt = 4; 827 else { 828 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) && 829 "Other types should have been promoted for varargs!"); 830 Amt = 8; 831 } 832 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList, 833 DAG.getConstant(Amt, VAList.getValueType())); 834 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, 835 VAList, VAListP, DAG.getSrcValue(VAListV)); 836 return std::make_pair(Result, Chain); 837} 838 839 840std::pair<SDOperand, SDOperand> PPCTargetLowering:: 841LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, 842 SelectionDAG &DAG) { 843 assert(0 && "LowerFrameReturnAddress unimplemented"); 844 abort(); 845} 846 847MachineBasicBlock * 848PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 849 MachineBasicBlock *BB) { 850 assert((MI->getOpcode() == PPC::SELECT_CC_Int || 851 MI->getOpcode() == PPC::SELECT_CC_F4 || 852 MI->getOpcode() == PPC::SELECT_CC_F8) && 853 "Unexpected instr type to insert"); 854 855 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 856 // control-flow pattern. The incoming instruction knows the destination vreg 857 // to set, the condition code register to branch on, the true/false values to 858 // select between, and a branch opcode to use. 859 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 860 ilist<MachineBasicBlock>::iterator It = BB; 861 ++It; 862 863 // thisMBB: 864 // ... 865 // TrueVal = ... 866 // cmpTY ccX, r1, r2 867 // bCC copy1MBB 868 // fallthrough --> copy0MBB 869 MachineBasicBlock *thisMBB = BB; 870 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 871 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 872 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2) 873 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 874 MachineFunction *F = BB->getParent(); 875 F->getBasicBlockList().insert(It, copy0MBB); 876 F->getBasicBlockList().insert(It, sinkMBB); 877 // Update machine-CFG edges 878 BB->addSuccessor(copy0MBB); 879 BB->addSuccessor(sinkMBB); 880 881 // copy0MBB: 882 // %FalseValue = ... 883 // # fallthrough to sinkMBB 884 BB = copy0MBB; 885 886 // Update machine-CFG edges 887 BB->addSuccessor(sinkMBB); 888 889 // sinkMBB: 890 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 891 // ... 892 BB = sinkMBB; 893 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg()) 894 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 895 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 896 897 delete MI; // The pseudo instruction is gone now. 898 return BB; 899} 900 901