PPCISelLowering.cpp revision 35ef913ec21de0f4f1b39c811b4335438717a9b8 
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the PPCISelLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCISelLowering.h"
15#include "PPCTargetMachine.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/CodeGen/SSARegMap.h"
21#include "llvm/Constants.h"
22#include "llvm/Function.h"
23using namespace llvm;
24
25PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
26  : TargetLowering(TM) {
27
28  // Fold away setcc operations if possible.
29  setSetCCIsExpensive();
30  setPow2DivIsCheap();
31
32  // Use _setjmp/_longjmp instead of setjmp/longjmp.
33  setUseUnderscoreSetJmpLongJmp(true);
34
35  // Set up the register classes.
36  addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
37  addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
38  addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
39
40  // PowerPC has no intrinsics for these particular operations
41  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
42  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
43  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
44
45  // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
46  setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
47  setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
48
49  // PowerPC has no SREM/UREM instructions
50  setOperationAction(ISD::SREM, MVT::i32, Expand);
51  setOperationAction(ISD::UREM, MVT::i32, Expand);
52
53  // We don't support sin/cos/sqrt/fmod
54  setOperationAction(ISD::FSIN , MVT::f64, Expand);
55  setOperationAction(ISD::FCOS , MVT::f64, Expand);
56  setOperationAction(ISD::FREM , MVT::f64, Expand);
57  setOperationAction(ISD::FSIN , MVT::f32, Expand);
58  setOperationAction(ISD::FCOS , MVT::f32, Expand);
59  setOperationAction(ISD::FREM , MVT::f32, Expand);
60
61  // If we're enabling GP optimizations, use hardware square root
62  if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
63    setOperationAction(ISD::FSQRT, MVT::f64, Expand);
64    setOperationAction(ISD::FSQRT, MVT::f32, Expand);
65  }
66
67  // PowerPC does not have CTPOP or CTTZ
68  setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
69  setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
70
71  // PowerPC does not have ROTR
72  setOperationAction(ISD::ROTR, MVT::i32   , Expand);
73
74  // PowerPC does not have Select
75  setOperationAction(ISD::SELECT, MVT::i32, Expand);
76  setOperationAction(ISD::SELECT, MVT::f32, Expand);
77  setOperationAction(ISD::SELECT, MVT::f64, Expand);
78
79  // PowerPC wants to turn select_cc of FP into fsel when possible.
80  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
81  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
82
83  // PowerPC does not have BRCOND* which requires SetCC
84  setOperationAction(ISD::BRCOND,       MVT::Other, Expand);
85  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
86
87  // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
88  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
89
90  // PowerPC does not have [U|S]INT_TO_FP
91  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
92  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
93
94  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
95  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
96
97  // PowerPC does not have truncstore for i1.
98  setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
99
100  // Support label based line numbers.
101  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
102  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
103  // FIXME - use subtarget debug flags
104  if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
105    setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
106
107  // We want to legalize GlobalAddress and ConstantPool nodes into the
108  // appropriate instructions to materialize the address.
109  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
110  setOperationAction(ISD::ConstantPool,  MVT::i32, Custom);
111
112  if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
113    // They also have instructions for converting between i64 and fp.
114    setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
115    setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
116    // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
117    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
118  } else {
119    // PowerPC does not have FP_TO_UINT on 32-bit implementations.
120    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
121  }
122
123  if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
124    // 64 bit PowerPC implementations can support i64 types directly
125    addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
126    // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
127    setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
128  } else {
129    // 32 bit PowerPC wants to expand i64 shifts itself.
130    setOperationAction(ISD::SHL, MVT::i64, Custom);
131    setOperationAction(ISD::SRL, MVT::i64, Custom);
132    setOperationAction(ISD::SRA, MVT::i64, Custom);
133  }
134
135  if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
136    addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
137    addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
138  }
139
140  setSetCCResultContents(ZeroOrOneSetCCResult);
141
142  computeRegisterProperties();
143}
144
145const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
146  switch (Opcode) {
147  default: return 0;
148  case PPCISD::FSEL:          return "PPCISD::FSEL";
149  case PPCISD::FCFID:         return "PPCISD::FCFID";
150  case PPCISD::FCTIDZ:        return "PPCISD::FCTIDZ";
151  case PPCISD::FCTIWZ:        return "PPCISD::FCTIWZ";
152  case PPCISD::VMADDFP:       return "PPCISD::VMADDFP";
153  case PPCISD::VNMSUBFP:      return "PPCISD::VNMSUBFP";
154  case PPCISD::Hi:            return "PPCISD::Hi";
155  case PPCISD::Lo:            return "PPCISD::Lo";
156  case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
157  case PPCISD::SRL:           return "PPCISD::SRL";
158  case PPCISD::SRA:           return "PPCISD::SRA";
159  case PPCISD::SHL:           return "PPCISD::SHL";
160  case PPCISD::RET_FLAG:      return "PPCISD::RET_FLAG";
161  }
162}
163
164/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
165static bool isFloatingPointZero(SDOperand Op) {
166  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
167    return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
168  else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
169    // Maybe this has already been legalized into the constant pool?
170    if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
171      if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
172        return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
173  }
174  return false;
175}
176
177/// LowerOperation - Provide custom lowering hooks for some operations.
178///
179SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
180  switch (Op.getOpcode()) {
181  default: assert(0 && "Wasn't expecting to be able to lower this!");
182  case ISD::FP_TO_SINT: {
183    assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
184    SDOperand Src = Op.getOperand(0);
185    if (Src.getValueType() == MVT::f32)
186      Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
187
188    SDOperand Tmp;
189    switch (Op.getValueType()) {
190    default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
191    case MVT::i32:
192      Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
193      break;
194    case MVT::i64:
195      Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
196      break;
197    }
198
199    // Convert the FP value to an int value through memory.
200    SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
201    if (Op.getValueType() == MVT::i32)
202      Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
203    return Bits;
204  }
205  case ISD::SINT_TO_FP: {
206    assert(MVT::i64 == Op.getOperand(0).getValueType() &&
207           "Unhandled SINT_TO_FP type in custom expander!");
208    SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
209    SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
210    if (MVT::f32 == Op.getValueType())
211      FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
212    return FP;
213  }
214  case ISD::SELECT_CC: {
215    // Turn FP only select_cc's into fsel instructions.
216    if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
217        !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
218      break;
219
220    ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
221
222    // Cannot handle SETEQ/SETNE.
223    if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
224
225    MVT::ValueType ResVT = Op.getValueType();
226    MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
227    SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
228    SDOperand TV  = Op.getOperand(2), FV  = Op.getOperand(3);
229
230    // If the RHS of the comparison is a 0.0, we don't need to do the
231    // subtraction at all.
232    if (isFloatingPointZero(RHS))
233      switch (CC) {
234      default: assert(0 && "Invalid FSEL condition"); abort();
235      case ISD::SETULT:
236      case ISD::SETLT:
237        std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
238      case ISD::SETUGE:
239      case ISD::SETGE:
240        if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
241          LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
242        return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
243      case ISD::SETUGT:
244      case ISD::SETGT:
245        std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
246      case ISD::SETULE:
247      case ISD::SETLE:
248        if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
249          LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
250        return DAG.getNode(PPCISD::FSEL, ResVT,
251                           DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
252      }
253
254    SDOperand Cmp;
255    switch (CC) {
256    default: assert(0 && "Invalid FSEL condition"); abort();
257    case ISD::SETULT:
258    case ISD::SETLT:
259      Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
260      if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
261        Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
262      return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
263    case ISD::SETUGE:
264    case ISD::SETGE:
265      Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
266      if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
267        Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
268      return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
269    case ISD::SETUGT:
270    case ISD::SETGT:
271      Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
272      if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
273        Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
274      return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
275    case ISD::SETULE:
276    case ISD::SETLE:
277      Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
278      if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
279        Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
280      return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
281    }
282    break;
283  }
284  case ISD::SHL: {
285    assert(Op.getValueType() == MVT::i64 &&
286           Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
287    // The generic code does a fine job expanding shift by a constant.
288    if (isa<ConstantSDNode>(Op.getOperand(1))) break;
289
290    // Otherwise, expand into a bunch of logical ops.  Note that these ops
291    // depend on the PPC behavior for oversized shift amounts.
292    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
293                               DAG.getConstant(0, MVT::i32));
294    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
295                               DAG.getConstant(1, MVT::i32));
296    SDOperand Amt = Op.getOperand(1);
297
298    SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
299                                 DAG.getConstant(32, MVT::i32), Amt);
300    SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
301    SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
302    SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
303    SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
304                                 DAG.getConstant(-32U, MVT::i32));
305    SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
306    SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
307    SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
308    return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
309  }
310  case ISD::SRL: {
311    assert(Op.getValueType() == MVT::i64 &&
312           Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
313    // The generic code does a fine job expanding shift by a constant.
314    if (isa<ConstantSDNode>(Op.getOperand(1))) break;
315
316    // Otherwise, expand into a bunch of logical ops.  Note that these ops
317    // depend on the PPC behavior for oversized shift amounts.
318    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
319                               DAG.getConstant(0, MVT::i32));
320    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
321                               DAG.getConstant(1, MVT::i32));
322    SDOperand Amt = Op.getOperand(1);
323
324    SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
325                                 DAG.getConstant(32, MVT::i32), Amt);
326    SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
327    SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
328    SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
329    SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
330                                 DAG.getConstant(-32U, MVT::i32));
331    SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
332    SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
333    SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
334    return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
335  }
336  case ISD::SRA: {
337    assert(Op.getValueType() == MVT::i64 &&
338           Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
339    // The generic code does a fine job expanding shift by a constant.
340    if (isa<ConstantSDNode>(Op.getOperand(1))) break;
341
342    // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
343    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
344                               DAG.getConstant(0, MVT::i32));
345    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
346                               DAG.getConstant(1, MVT::i32));
347    SDOperand Amt = Op.getOperand(1);
348
349    SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
350                                 DAG.getConstant(32, MVT::i32), Amt);
351    SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
352    SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
353    SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
354    SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
355                                 DAG.getConstant(-32U, MVT::i32));
356    SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
357    SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
358    SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
359                                      Tmp4, Tmp6, ISD::SETLE);
360    return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
361  }
362  case ISD::ConstantPool: {
363    Constant *C = cast<ConstantPoolSDNode>(Op)->get();
364    SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32);
365    SDOperand Zero = DAG.getConstant(0, MVT::i32);
366
367    if (PPCGenerateStaticCode) {
368      // Generate non-pic code that has direct accesses to the constant pool.
369      // The address of the global is just (hi(&g)+lo(&g)).
370      SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
371      SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
372      return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
373    }
374
375    // Only lower ConstantPool on Darwin.
376    if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break;
377    SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
378    if (PICEnabled) {
379      // With PIC, the first instruction is actually "GR+hi(&G)".
380      Hi = DAG.getNode(ISD::ADD, MVT::i32,
381                       DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
382    }
383
384    SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
385    Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
386    return Lo;
387  }
388  case ISD::GlobalAddress: {
389    GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
390    GlobalValue *GV = GSDN->getGlobal();
391    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset());
392    SDOperand Zero = DAG.getConstant(0, MVT::i32);
393
394    if (PPCGenerateStaticCode) {
395      // Generate non-pic code that has direct accesses to globals.
396      // The address of the global is just (hi(&g)+lo(&g)).
397      SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
398      SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
399      return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
400    }
401
402    // Only lower GlobalAddress on Darwin.
403    if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break;
404
405    SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
406    if (PICEnabled) {
407      // With PIC, the first instruction is actually "GR+hi(&G)".
408      Hi = DAG.getNode(ISD::ADD, MVT::i32,
409                       DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
410    }
411
412    SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
413    Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
414
415    if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && !GV->isExternal())
416      return Lo;
417
418    // If the global is weak or external, we have to go through the lazy
419    // resolution stub.
420    return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
421  }
422  }
423  return SDOperand();
424}
425
426std::vector<SDOperand>
427PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
428  //
429  // add beautiful description of PPC stack frame format, or at least some docs
430  //
431  MachineFunction &MF = DAG.getMachineFunction();
432  MachineFrameInfo *MFI = MF.getFrameInfo();
433  MachineBasicBlock& BB = MF.front();
434  SSARegMap *RegMap = MF.getSSARegMap();
435  std::vector<SDOperand> ArgValues;
436
437  unsigned ArgOffset = 24;
438  unsigned GPR_remaining = 8;
439  unsigned FPR_remaining = 13;
440  unsigned GPR_idx = 0, FPR_idx = 0;
441  static const unsigned GPR[] = {
442    PPC::R3, PPC::R4, PPC::R5, PPC::R6,
443    PPC::R7, PPC::R8, PPC::R9, PPC::R10,
444  };
445  static const unsigned FPR[] = {
446    PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
447    PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
448  };
449
450  // Add DAG nodes to load the arguments...  On entry to a function on PPC,
451  // the arguments start at offset 24, although they are likely to be passed
452  // in registers.
453  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
454    SDOperand newroot, argt;
455    unsigned ObjSize;
456    bool needsLoad = false;
457    bool ArgLive = !I->use_empty();
458    MVT::ValueType ObjectVT = getValueType(I->getType());
459
460    switch (ObjectVT) {
461    default: assert(0 && "Unhandled argument type!");
462    case MVT::i1:
463    case MVT::i8:
464    case MVT::i16:
465    case MVT::i32:
466      ObjSize = 4;
467      if (!ArgLive) break;
468      if (GPR_remaining > 0) {
469        unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
470        MF.addLiveIn(GPR[GPR_idx], VReg);
471        argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
472        if (ObjectVT != MVT::i32) {
473          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
474                                                       : ISD::AssertZext;
475          argt = DAG.getNode(AssertOp, MVT::i32, argt,
476                             DAG.getValueType(ObjectVT));
477          argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
478        }
479      } else {
480        needsLoad = true;
481      }
482      break;
483    case MVT::i64:
484      ObjSize = 8;
485      if (!ArgLive) break;
486      if (GPR_remaining > 0) {
487        SDOperand argHi, argLo;
488        unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
489        MF.addLiveIn(GPR[GPR_idx], VReg);
490        argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
491        // If we have two or more remaining argument registers, then both halves
492        // of the i64 can be sourced from there.  Otherwise, the lower half will
493        // have to come off the stack.  This can happen when an i64 is preceded
494        // by 28 bytes of arguments.
495        if (GPR_remaining > 1) {
496          unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
497          MF.addLiveIn(GPR[GPR_idx+1], VReg);
498          argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
499        } else {
500          int FI = MFI->CreateFixedObject(4, ArgOffset+4);
501          SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
502          argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
503                              DAG.getSrcValue(NULL));
504        }
505        // Build the outgoing arg thingy
506        argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
507        newroot = argLo;
508      } else {
509        needsLoad = true;
510      }
511      break;
512    case MVT::f32:
513    case MVT::f64:
514      ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
515      if (!ArgLive) {
516        if (FPR_remaining > 0) {
517          --FPR_remaining;
518          ++FPR_idx;
519        }
520        break;
521      }
522      if (FPR_remaining > 0) {
523        unsigned VReg;
524        if (ObjectVT == MVT::f32)
525          VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
526        else
527          VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
528        MF.addLiveIn(FPR[FPR_idx], VReg);
529        argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
530        --FPR_remaining;
531        ++FPR_idx;
532      } else {
533        needsLoad = true;
534      }
535      break;
536    }
537
538    // We need to load the argument to a virtual register if we determined above
539    // that we ran out of physical registers of the appropriate type
540    if (needsLoad) {
541      unsigned SubregOffset = 0;
542      if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
543      if (ObjectVT == MVT::i16) SubregOffset = 2;
544      int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
545      SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
546      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
547                        DAG.getConstant(SubregOffset, MVT::i32));
548      argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
549                                   DAG.getSrcValue(NULL));
550    }
551
552    // Every 4 bytes of argument space consumes one of the GPRs available for
553    // argument passing.
554    if (GPR_remaining > 0) {
555      unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
556      GPR_remaining -= delta;
557      GPR_idx += delta;
558    }
559    ArgOffset += ObjSize;
560    if (newroot.Val)
561      DAG.setRoot(newroot.getValue(1));
562
563    ArgValues.push_back(argt);
564  }
565
566  // If the function takes variable number of arguments, make a frame index for
567  // the start of the first vararg value... for expansion of llvm.va_start.
568  if (F.isVarArg()) {
569    VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
570    SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
571    // If this function is vararg, store any remaining integer argument regs
572    // to their spots on the stack so that they may be loaded by deferencing the
573    // result of va_next.
574    std::vector<SDOperand> MemOps;
575    for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
576      unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
577      MF.addLiveIn(GPR[GPR_idx], VReg);
578      SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
579      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
580                                    Val, FIN, DAG.getSrcValue(NULL));
581      MemOps.push_back(Store);
582      // Increment the address by four for the next argument to store
583      SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
584      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
585    }
586    if (!MemOps.empty()) {
587      MemOps.push_back(DAG.getRoot());
588      DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
589    }
590  }
591
592  // Finally, inform the code generator which regs we return values in.
593  switch (getValueType(F.getReturnType())) {
594    default: assert(0 && "Unknown type!");
595    case MVT::isVoid: break;
596    case MVT::i1:
597    case MVT::i8:
598    case MVT::i16:
599    case MVT::i32:
600      MF.addLiveOut(PPC::R3);
601      break;
602    case MVT::i64:
603      MF.addLiveOut(PPC::R3);
604      MF.addLiveOut(PPC::R4);
605      break;
606    case MVT::f32:
607    case MVT::f64:
608      MF.addLiveOut(PPC::F1);
609      break;
610  }
611
612  return ArgValues;
613}
614
615std::pair<SDOperand, SDOperand>
616PPCTargetLowering::LowerCallTo(SDOperand Chain,
617                               const Type *RetTy, bool isVarArg,
618                               unsigned CallingConv, bool isTailCall,
619                               SDOperand Callee, ArgListTy &Args,
620                               SelectionDAG &DAG) {
621  // args_to_use will accumulate outgoing args for the ISD::CALL case in
622  // SelectExpr to use to put the arguments in the appropriate registers.
623  std::vector<SDOperand> args_to_use;
624
625  // Count how many bytes are to be pushed on the stack, including the linkage
626  // area, and parameter passing area.
627  unsigned NumBytes = 24;
628
629  if (Args.empty()) {
630    Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
631                        DAG.getConstant(NumBytes, getPointerTy()));
632  } else {
633    for (unsigned i = 0, e = Args.size(); i != e; ++i) {
634      switch (getValueType(Args[i].second)) {
635      default: assert(0 && "Unknown value type!");
636      case MVT::i1:
637      case MVT::i8:
638      case MVT::i16:
639      case MVT::i32:
640      case MVT::f32:
641        NumBytes += 4;
642        break;
643      case MVT::i64:
644      case MVT::f64:
645        NumBytes += 8;
646        break;
647      }
648    }
649
650    // Just to be safe, we'll always reserve the full 24 bytes of linkage area
651    // plus 32 bytes of argument space in case any called code gets funky on us.
652    // (Required by ABI to support var arg)
653    if (NumBytes < 56) NumBytes = 56;
654
655    // Adjust the stack pointer for the new arguments...
656    // These operations are automatically eliminated by the prolog/epilog pass
657    Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
658                        DAG.getConstant(NumBytes, getPointerTy()));
659
660    // Set up a copy of the stack pointer for use loading and storing any
661    // arguments that may not fit in the registers available for argument
662    // passing.
663    SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
664
665    // Figure out which arguments are going to go in registers, and which in
666    // memory.  Also, if this is a vararg function, floating point operations
667    // must be stored to our stack, and loaded into integer regs as well, if
668    // any integer regs are available for argument passing.
669    unsigned ArgOffset = 24;
670    unsigned GPR_remaining = 8;
671    unsigned FPR_remaining = 13;
672
673    std::vector<SDOperand> MemOps;
674    for (unsigned i = 0, e = Args.size(); i != e; ++i) {
675      // PtrOff will be used to store the current argument to the stack if a
676      // register cannot be found for it.
677      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
678      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
679      MVT::ValueType ArgVT = getValueType(Args[i].second);
680
681      switch (ArgVT) {
682      default: assert(0 && "Unexpected ValueType for argument!");
683      case MVT::i1:
684      case MVT::i8:
685      case MVT::i16:
686        // Promote the integer to 32 bits.  If the input type is signed use a
687        // sign extend, otherwise use a zero extend.
688        if (Args[i].second->isSigned())
689          Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
690        else
691          Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
692        // FALL THROUGH
693      case MVT::i32:
694        if (GPR_remaining > 0) {
695          args_to_use.push_back(Args[i].first);
696          --GPR_remaining;
697        } else {
698          MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
699                                       Args[i].first, PtrOff,
700                                       DAG.getSrcValue(NULL)));
701        }
702        ArgOffset += 4;
703        break;
704      case MVT::i64:
705        // If we have one free GPR left, we can place the upper half of the i64
706        // in it, and store the other half to the stack.  If we have two or more
707        // free GPRs, then we can pass both halves of the i64 in registers.
708        if (GPR_remaining > 0) {
709          SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
710                                     Args[i].first, DAG.getConstant(1, MVT::i32));
711          SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
712                                     Args[i].first, DAG.getConstant(0, MVT::i32));
713          args_to_use.push_back(Hi);
714          --GPR_remaining;
715          if (GPR_remaining > 0) {
716            args_to_use.push_back(Lo);
717            --GPR_remaining;
718          } else {
719            SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
720            PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
721            MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
722                                         Lo, PtrOff, DAG.getSrcValue(NULL)));
723          }
724        } else {
725          MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
726                                       Args[i].first, PtrOff,
727                                       DAG.getSrcValue(NULL)));
728        }
729        ArgOffset += 8;
730        break;
731      case MVT::f32:
732      case MVT::f64:
733        if (FPR_remaining > 0) {
734          args_to_use.push_back(Args[i].first);
735          --FPR_remaining;
736          if (isVarArg) {
737            SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
738                                          Args[i].first, PtrOff,
739                                          DAG.getSrcValue(NULL));
740            MemOps.push_back(Store);
741            // Float varargs are always shadowed in available integer registers
742            if (GPR_remaining > 0) {
743              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
744                                           DAG.getSrcValue(NULL));
745              MemOps.push_back(Load.getValue(1));
746              args_to_use.push_back(Load);
747              --GPR_remaining;
748            }
749            if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
750              SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
751              PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
752              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
753                                           DAG.getSrcValue(NULL));
754              MemOps.push_back(Load.getValue(1));
755              args_to_use.push_back(Load);
756              --GPR_remaining;
757            }
758          } else {
759            // If we have any FPRs remaining, we may also have GPRs remaining.
760            // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
761            // GPRs.
762            if (GPR_remaining > 0) {
763              args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
764              --GPR_remaining;
765            }
766            if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
767              args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
768              --GPR_remaining;
769            }
770          }
771        } else {
772          MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
773                                       Args[i].first, PtrOff,
774                                       DAG.getSrcValue(NULL)));
775        }
776        ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
777        break;
778      }
779    }
780    if (!MemOps.empty())
781      Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
782  }
783
784  std::vector<MVT::ValueType> RetVals;
785  MVT::ValueType RetTyVT = getValueType(RetTy);
786  MVT::ValueType ActualRetTyVT = RetTyVT;
787  if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
788    ActualRetTyVT = MVT::i32;   // Promote result to i32.
789
790  if (RetTyVT != MVT::isVoid)
791    RetVals.push_back(ActualRetTyVT);
792  RetVals.push_back(MVT::Other);
793
794  // If the callee is a GlobalAddress node (quite common, every direct call is)
795  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
796  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
797    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
798
799  SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
800                                            Chain, Callee, args_to_use), 0);
801  Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
802  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
803                      DAG.getConstant(NumBytes, getPointerTy()));
804  SDOperand RetVal = TheCall;
805
806  // If the result is a small value, add a note so that we keep track of the
807  // information about whether it is sign or zero extended.
808  if (RetTyVT != ActualRetTyVT) {
809    RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
810                         MVT::i32, RetVal, DAG.getValueType(RetTyVT));
811    RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
812  }
813
814  return std::make_pair(RetVal, Chain);
815}
816
817SDOperand PPCTargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
818                                           SelectionDAG &DAG) {
819  SDOperand Copy;
820  switch (Op.getValueType()) {
821    default: assert(0 && "Unknown type to return!");
822    case MVT::i32:
823      Copy = DAG.getCopyToReg(Chain, PPC::R3, Op, SDOperand());
824      break;
825    case MVT::f32:
826    case MVT::f64:
827      Copy = DAG.getCopyToReg(Chain, PPC::F1, Op, SDOperand());
828      break;
829    case MVT::i64:
830      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
831                                 DAG.getConstant(1, MVT::i32));
832      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
833                                 DAG.getConstant(0, MVT::i32));
834      Copy = DAG.getCopyToReg(Chain, PPC::R3, Hi, SDOperand());
835      Copy = DAG.getCopyToReg(Copy, PPC::R4, Lo, Copy.getValue(1));
836      break;
837  }
838  return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
839}
840
841SDOperand PPCTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
842                                          Value *VAListV, SelectionDAG &DAG) {
843  // vastart just stores the address of the VarArgsFrameIndex slot into the
844  // memory location argument.
845  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
846  return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
847                     DAG.getSrcValue(VAListV));
848}
849
850std::pair<SDOperand,SDOperand>
851PPCTargetLowering::LowerVAArg(SDOperand Chain,
852                              SDOperand VAListP, Value *VAListV,
853                              const Type *ArgTy, SelectionDAG &DAG) {
854  MVT::ValueType ArgVT = getValueType(ArgTy);
855
856  SDOperand VAList =
857    DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
858  SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
859  unsigned Amt;
860  if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
861    Amt = 4;
862  else {
863    assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
864           "Other types should have been promoted for varargs!");
865    Amt = 8;
866  }
867  VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
868                       DAG.getConstant(Amt, VAList.getValueType()));
869  Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
870                      VAList, VAListP, DAG.getSrcValue(VAListV));
871  return std::make_pair(Result, Chain);
872}
873
874
875std::pair<SDOperand, SDOperand> PPCTargetLowering::
876LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
877                        SelectionDAG &DAG) {
878  assert(0 && "LowerFrameReturnAddress unimplemented");
879  abort();
880}
881
882MachineBasicBlock *
883PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
884                                           MachineBasicBlock *BB) {
885  assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
886          MI->getOpcode() == PPC::SELECT_CC_F4 ||
887          MI->getOpcode() == PPC::SELECT_CC_F8) &&
888         "Unexpected instr type to insert");
889
890  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
891  // control-flow pattern.  The incoming instruction knows the destination vreg
892  // to set, the condition code register to branch on, the true/false values to
893  // select between, and a branch opcode to use.
894  const BasicBlock *LLVM_BB = BB->getBasicBlock();
895  ilist<MachineBasicBlock>::iterator It = BB;
896  ++It;
897
898  //  thisMBB:
899  //  ...
900  //   TrueVal = ...
901  //   cmpTY ccX, r1, r2
902  //   bCC copy1MBB
903  //   fallthrough --> copy0MBB
904  MachineBasicBlock *thisMBB = BB;
905  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
906  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
907  BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
908    .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
909  MachineFunction *F = BB->getParent();
910  F->getBasicBlockList().insert(It, copy0MBB);
911  F->getBasicBlockList().insert(It, sinkMBB);
912  // Update machine-CFG edges
913  BB->addSuccessor(copy0MBB);
914  BB->addSuccessor(sinkMBB);
915
916  //  copy0MBB:
917  //   %FalseValue = ...
918  //   # fallthrough to sinkMBB
919  BB = copy0MBB;
920
921  // Update machine-CFG edges
922  BB->addSuccessor(sinkMBB);
923
924  //  sinkMBB:
925  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
926  //  ...
927  BB = sinkMBB;
928  BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
929    .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
930    .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
931
932  delete MI;   // The pseudo instruction is gone now.
933  return BB;
934}
935
936