PPCISelLowering.cpp revision 4468c224586ba0f75e17ed7520a39a30e8caf636
1551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 263b3afa98460ce38a1c48d3c44ef6edfdaf37b77Misha Brukman// 3b2109ce97881269a610fa4afbcbca350e975174dJohn Criswell// The LLVM Compiler Infrastructure 4b2109ce97881269a610fa4afbcbca350e975174dJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file was developed by Chris Lattner and is distributed under 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// the University of Illinois Open Source License. See LICENSE.TXT for details. 763b3afa98460ce38a1c48d3c44ef6edfdaf37b77Misha Brukman// 8b2109ce97881269a610fa4afbcbca350e975174dJohn Criswell//===----------------------------------------------------------------------===// 9589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner// 10589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner// This file implements the PPCISelLowering class. 11589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner// 12589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner//===----------------------------------------------------------------------===// 13589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner 14589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner#include "PPCISelLowering.h" 15551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "PPCTargetMachine.h" 16551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/ADT/VectorExtras.h" 17589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner#include "llvm/Analysis/ScalarEvolutionExpressions.h" 188b8fa7b2f403ae2f342413239c4151e075022c97Sean Silva#include "llvm/CodeGen/MachineFrameInfo.h" 19c7365a9ec96ff434d93d0d8052812283b33e537dReid Spencer#include "llvm/CodeGen/MachineFunction.h" 20c7365a9ec96ff434d93d0d8052812283b33e537dReid Spencer#include "llvm/CodeGen/MachineInstrBuilder.h" 21d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke#include "llvm/CodeGen/SelectionDAG.h" 22d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke#include "llvm/CodeGen/SSARegMap.h" 23589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner#include "llvm/Constants.h" 247e70829632f82de15db187845666aaca6e04b792Chris Lattner#include "llvm/Function.h" 25589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner#include "llvm/Intrinsics.h" 26589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner#include "llvm/Support/MathExtras.h" 277e70829632f82de15db187845666aaca6e04b792Chris Lattner#include "llvm/Target/TargetOptions.h" 287e70829632f82de15db187845666aaca6e04b792Chris Lattnerusing namespace llvm; 297e70829632f82de15db187845666aaca6e04b792Chris Lattner 307e70829632f82de15db187845666aaca6e04b792Chris LattnerPPCTargetLowering::PPCTargetLowering(TargetMachine &TM) 317e70829632f82de15db187845666aaca6e04b792Chris Lattner : TargetLowering(TM) { 327e70829632f82de15db187845666aaca6e04b792Chris Lattner 337e70829632f82de15db187845666aaca6e04b792Chris Lattner // Fold away setcc operations if possible. 347e70829632f82de15db187845666aaca6e04b792Chris Lattner setSetCCIsExpensive(); 357e70829632f82de15db187845666aaca6e04b792Chris Lattner setPow2DivIsCheap(); 367e70829632f82de15db187845666aaca6e04b792Chris Lattner 377e70829632f82de15db187845666aaca6e04b792Chris Lattner // Use _setjmp/_longjmp instead of setjmp/longjmp. 387e70829632f82de15db187845666aaca6e04b792Chris Lattner setUseUnderscoreSetJmpLongJmp(true); 397fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola 407fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola // Set up the register classes. 417fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 427fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 437fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 447fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola 457fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 467e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 477e70829632f82de15db187845666aaca6e04b792Chris Lattner 487e70829632f82de15db187845666aaca6e04b792Chris Lattner // PowerPC has no intrinsics for these particular operations 4921c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 5021c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::MEMSET, MVT::Other, Expand); 5121c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 528b8fa7b2f403ae2f342413239c4151e075022c97Sean Silva 530179e977234fef45b1877eb93a3c7565cdd1862dDouglas Gregor // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 540179e977234fef45b1877eb93a3c7565cdd1862dDouglas Gregor setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); 550179e977234fef45b1877eb93a3c7565cdd1862dDouglas Gregor setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); 560179e977234fef45b1877eb93a3c7565cdd1862dDouglas Gregor 570179e977234fef45b1877eb93a3c7565cdd1862dDouglas Gregor // PowerPC has no SREM/UREM instructions 587e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::SREM, MVT::i32, Expand); 598b8fa7b2f403ae2f342413239c4151e075022c97Sean Silva setOperationAction(ISD::UREM, MVT::i32, Expand); 608b8fa7b2f403ae2f342413239c4151e075022c97Sean Silva 618b8fa7b2f403ae2f342413239c4151e075022c97Sean Silva // We don't support sin/cos/sqrt/fmod 620711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie setOperationAction(ISD::FSIN , MVT::f64, Expand); 630711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie setOperationAction(ISD::FCOS , MVT::f64, Expand); 648b8fa7b2f403ae2f342413239c4151e075022c97Sean Silva setOperationAction(ISD::FREM , MVT::f64, Expand); 658b8fa7b2f403ae2f342413239c4151e075022c97Sean Silva setOperationAction(ISD::FSIN , MVT::f32, Expand); 668b8fa7b2f403ae2f342413239c4151e075022c97Sean Silva setOperationAction(ISD::FCOS , MVT::f32, Expand); 678b8fa7b2f403ae2f342413239c4151e075022c97Sean Silva setOperationAction(ISD::FREM , MVT::f32, Expand); 688b8fa7b2f403ae2f342413239c4151e075022c97Sean Silva 6921c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman // If we're enabling GP optimizations, use hardware square root 7021c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 7121c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::FSQRT, MVT::f64, Expand); 727e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::FSQRT, MVT::f32, Expand); 737e70829632f82de15db187845666aaca6e04b792Chris Lattner } 747e70829632f82de15db187845666aaca6e04b792Chris Lattner 7521c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 7621c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 7721c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman 787e70829632f82de15db187845666aaca6e04b792Chris Lattner // PowerPC does not have BSWAP, CTPOP or CTTZ 797e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 807e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 8121c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 8221c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman 83f5091b476c46333ecfcf095cd2e422e9748e9546Jordan Rose // PowerPC does not have ROTR 8421c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::ROTR, MVT::i32 , Expand); 857e70829632f82de15db187845666aaca6e04b792Chris Lattner 867e70829632f82de15db187845666aaca6e04b792Chris Lattner // PowerPC does not have Select 877e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::SELECT, MVT::i32, Expand); 887fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola setOperationAction(ISD::SELECT, MVT::f32, Expand); 897fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola setOperationAction(ISD::SELECT, MVT::f64, Expand); 907fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola 917fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola // PowerPC wants to turn select_cc of FP into fsel when possible. 927fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 937fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 947fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola 9521c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman // PowerPC wants to optimize integer setcc a bit 9621c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::SETCC, MVT::i32, Custom); 97f5091b476c46333ecfcf095cd2e422e9748e9546Jordan Rose 9821c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman // PowerPC does not have BRCOND which requires SetCC 997e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::BRCOND, MVT::Other, Expand); 1007e70829632f82de15db187845666aaca6e04b792Chris Lattner 1017e70829632f82de15db187845666aaca6e04b792Chris Lattner // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 10221c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 10321c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman 104f5091b476c46333ecfcf095cd2e422e9748e9546Jordan Rose // PowerPC does not have [U|S]INT_TO_FP 10521c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 1067e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 1077e70829632f82de15db187845666aaca6e04b792Chris Lattner 1087e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 10921c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 11021c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman 11121c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman // PowerPC does not have truncstore for i1. 11221c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); 11321c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman 11421c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman // Support label based line numbers. 11521c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::LOCATION, MVT::Other, Expand); 1167fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 1177e70829632f82de15db187845666aaca6e04b792Chris Lattner // FIXME - use subtarget debug flags 1187e70829632f82de15db187845666aaca6e04b792Chris Lattner if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) 1197e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 12021c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman 12121c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman // We want to legalize GlobalAddress and ConstantPool nodes into the 12221c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman // appropriate instructions to materialize the address. 12321c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 12421c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 12521c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman 12621c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman // RET must be custom lowered, to meet ABI requirements 12721c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::RET , MVT::Other, Custom); 12821c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman 12921c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman // VASTART needs to be custom lowered to use the VarArgsFrameIndex 13021c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman setOperationAction(ISD::VASTART , MVT::Other, Custom); 13121c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman 13221c60904ce6b937cb0c8744375e9c1a95fe0e495Eli Friedman // Use the default implementation. 133589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner setOperationAction(ISD::VAARG , MVT::Other, Expand); 1347e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::VACOPY , MVT::Other, Expand); 1357fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola setOperationAction(ISD::VAEND , MVT::Other, Expand); 1367fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 137589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 138589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 1397e70829632f82de15db187845666aaca6e04b792Chris Lattner 1407e70829632f82de15db187845666aaca6e04b792Chris Lattner // We want to custom lower some of our intrinsics. 1417e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1427e70829632f82de15db187845666aaca6e04b792Chris Lattner 1437e70829632f82de15db187845666aaca6e04b792Chris Lattner if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 1447e70829632f82de15db187845666aaca6e04b792Chris Lattner // They also have instructions for converting between i64 and fp. 1457e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 1467e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 1477e70829632f82de15db187845666aaca6e04b792Chris Lattner 1487e70829632f82de15db187845666aaca6e04b792Chris Lattner // FIXME: disable this lowered code. This generates 64-bit register values, 1497e70829632f82de15db187845666aaca6e04b792Chris Lattner // and we don't model the fact that the top part is clobbered by calls. We 1507e70829632f82de15db187845666aaca6e04b792Chris Lattner // need to flag these together so that the value isn't live across a call. 1517e70829632f82de15db187845666aaca6e04b792Chris Lattner //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 1527e70829632f82de15db187845666aaca6e04b792Chris Lattner 1537e70829632f82de15db187845666aaca6e04b792Chris Lattner // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 1547e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 1557e70829632f82de15db187845666aaca6e04b792Chris Lattner } else { 1567e70829632f82de15db187845666aaca6e04b792Chris Lattner // PowerPC does not have FP_TO_UINT on 32-bit implementations. 1577e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 1587e70829632f82de15db187845666aaca6e04b792Chris Lattner } 1597e70829632f82de15db187845666aaca6e04b792Chris Lattner 1607e70829632f82de15db187845666aaca6e04b792Chris Lattner if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) { 1617e70829632f82de15db187845666aaca6e04b792Chris Lattner // 64 bit PowerPC implementations can support i64 types directly 1627e70829632f82de15db187845666aaca6e04b792Chris Lattner addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 1637e70829632f82de15db187845666aaca6e04b792Chris Lattner // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 1647e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 1657e70829632f82de15db187845666aaca6e04b792Chris Lattner } else { 1667e70829632f82de15db187845666aaca6e04b792Chris Lattner // 32 bit PowerPC wants to expand i64 shifts itself. 1677e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::SHL, MVT::i64, Custom); 1687e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::SRL, MVT::i64, Custom); 1697e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::SRA, MVT::i64, Custom); 1707e70829632f82de15db187845666aaca6e04b792Chris Lattner } 1717e70829632f82de15db187845666aaca6e04b792Chris Lattner 1727e70829632f82de15db187845666aaca6e04b792Chris Lattner // First set operation action for all vector types to expand. Then we 1737e70829632f82de15db187845666aaca6e04b792Chris Lattner // will selectively turn on ones that can be effectively codegen'd. 1747e70829632f82de15db187845666aaca6e04b792Chris Lattner for (unsigned VT = (unsigned)MVT::Vector + 1; 1757e70829632f82de15db187845666aaca6e04b792Chris Lattner VT != (unsigned)MVT::LAST_VALUETYPE; VT++) { 1767e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); 1777e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); 1787e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); 1797e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); 1807e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 1817e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); 1827e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); 1837e70829632f82de15db187845666aaca6e04b792Chris Lattner } 18463b3afa98460ce38a1c48d3c44ef6edfdaf37b77Misha Brukman 1855a6d63ae29512d654c8c697f42f32f97b9dc010bChris Lattner if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 1867e70829632f82de15db187845666aaca6e04b792Chris Lattner addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 1877e70829632f82de15db187845666aaca6e04b792Chris Lattner addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 1887e70829632f82de15db187845666aaca6e04b792Chris Lattner addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 1897e70829632f82de15db187845666aaca6e04b792Chris Lattner addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 1907e70829632f82de15db187845666aaca6e04b792Chris Lattner 1917e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::ADD , MVT::v4f32, Legal); 1927e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::SUB , MVT::v4f32, Legal); 1937fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola setOperationAction(ISD::MUL , MVT::v4f32, Legal); 1947e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::ADD , MVT::v4i32, Legal); 1955a6d63ae29512d654c8c697f42f32f97b9dc010bChris Lattner 1967e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom); 1977e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 1987e70829632f82de15db187845666aaca6e04b792Chris Lattner 1997e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 2007e70829632f82de15db187845666aaca6e04b792Chris Lattner setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 2017e70829632f82de15db187845666aaca6e04b792Chris Lattner 2025a6d63ae29512d654c8c697f42f32f97b9dc010bChris Lattner setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 2033a3134ab12f3aa65f9791f702a73f6d0b2af423fChris Lattner setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 2043a3134ab12f3aa65f9791f702a73f6d0b2af423fChris Lattner } 2053a3134ab12f3aa65f9791f702a73f6d0b2af423fChris Lattner 2067e70829632f82de15db187845666aaca6e04b792Chris Lattner setSetCCResultContents(ZeroOrOneSetCCResult); 2077e70829632f82de15db187845666aaca6e04b792Chris Lattner setStackPointerRegisterToSaveRestore(PPC::R1); 2087e70829632f82de15db187845666aaca6e04b792Chris Lattner 20960f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola // We have target-specific dag combine patterns for the following nodes: 21060f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola setTargetDAGCombine(ISD::SINT_TO_FP); 21160f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola setTargetDAGCombine(ISD::STORE); 21260f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola 213589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner computeRegisterProperties(); 214589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner} 215589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner 2165fc25cccff3cdbfd34d08b9c1233f9af1879018cChris Lattnerconst char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 2175fc25cccff3cdbfd34d08b9c1233f9af1879018cChris Lattner switch (Opcode) { 218589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner default: return 0; 2197e70829632f82de15db187845666aaca6e04b792Chris Lattner case PPCISD::FSEL: return "PPCISD::FSEL"; 220589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner case PPCISD::FCFID: return "PPCISD::FCFID"; 221589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 22260f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 22360f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola case PPCISD::STFIWX: return "PPCISD::STFIWX"; 22460f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 22588d942d8983aadecae477fee523c23312d194515Misha Brukman case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 22660f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola case PPCISD::VPERM: return "PPCISD::VPERM"; 22760f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola case PPCISD::Hi: return "PPCISD::Hi"; 228589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner case PPCISD::Lo: return "PPCISD::Lo"; 229589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 2300711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie case PPCISD::SRL: return "PPCISD::SRL"; 2317fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola case PPCISD::SRA: return "PPCISD::SRA"; 2320711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie case PPCISD::SHL: return "PPCISD::SHL"; 2330711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 2340711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie case PPCISD::STD_32: return "PPCISD::STD_32"; 2350711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie case PPCISD::CALL: return "PPCISD::CALL"; 2360711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 2370711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie case PPCISD::MFCR: return "PPCISD::MFCR"; 23860f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola case PPCISD::VCMP: return "PPCISD::VCMP"; 2390711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie case PPCISD::VCMPo: return "PPCISD::VCMPo"; 2400711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie } 2410711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie} 2420711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie 2430711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 244589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattnerstatic bool isFloatingPointZero(SDOperand Op) { 245589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 246589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 247589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { 2489a0b165cb58cb5cf49cb3a143c302029f389acb2Argyrios Kyrtzidis // Maybe this has already been legalized into the constant pool? 2499a0b165cb58cb5cf49cb3a143c302029f389acb2Argyrios Kyrtzidis if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 25088d942d8983aadecae477fee523c23312d194515Misha Brukman if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get())) 2517e70829632f82de15db187845666aaca6e04b792Chris Lattner return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 252589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner } 253589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner return false; 254589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner} 255589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner 256589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner 257589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 258589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner/// specifies a splat of a single element that is suitable for input to 259589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner/// VSPLTB/VSPLTH/VSPLTW. 2601ff1da7ac9bff43ba24445ff30ba2fd79bd95cd7Chris Lattnerbool PPC::isSplatShuffleMask(SDNode *N) { 261589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner assert(N->getOpcode() == ISD::BUILD_VECTOR); 262589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner 263589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner // We can only splat 8-bit, 16-bit, and 32-bit quantities. 26460f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola if (N->getNumOperands() != 4 && N->getNumOperands() != 8 && 26560f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola N->getNumOperands() != 16) 26660f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola return false; 2670711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie 2680711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie // This is a splat operation if each element of the permute is the same, and 2690711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie // if the value doesn't reference the second vector. 2700711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie SDOperand Elt = N->getOperand(0); 2717fe65d691dcce550d53ec9310913aab67ab6d654Rafael Espindola assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!"); 2720711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) { 2730711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie assert(isa<ConstantSDNode>(N->getOperand(i)) && 2740711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie "Invalid VECTOR_SHUFFLE mask!"); 2750711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie if (N->getOperand(i) != Elt) return false; 27660f18ad8a5fa7d5b008a1fecf9a79b68883ca192Rafael Espindola } 2770711d46a72580a943d60a770776a22aeb494e66cDavid Blaikie 278589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner // Make sure it is a splat of the first vector operand. 279589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner return cast<ConstantSDNode>(Elt)->getValue() < N->getNumOperands(); 280589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner} 281589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner 282589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 283589df88ba03a81b2b3dc9d084c191a3a74724ecdChris Lattner/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 2843fde69c0f1d2ccfcc0847cebffb3b9805bef8a06Gabor Greifunsigned PPC::getVSPLTImmediate(SDNode *N) { 2853fde69c0f1d2ccfcc0847cebffb3b9805bef8a06Gabor Greif assert(isSplatShuffleMask(N)); 2867e70829632f82de15db187845666aaca6e04b792Chris Lattner return cast<ConstantSDNode>(N->getOperand(0))->getValue(); 2877e70829632f82de15db187845666aaca6e04b792Chris Lattner} 288d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 289d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke/// isVecSplatImm - Return true if this is a build_vector of constants which 2907e70829632f82de15db187845666aaca6e04b792Chris Lattner/// can be formed by using a vspltis[bhw] instruction. The ByteSize field 291/// indicates the number of bytes of each element [124] -> [bhw]. 292bool PPC::isVecSplatImm(SDNode *N, unsigned ByteSize, char *Val) { 293 SDOperand OpVal(0, 0); 294 // Check to see if this buildvec has a single non-undef value in its elements. 295 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 296 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 297 if (OpVal.Val == 0) 298 OpVal = N->getOperand(i); 299 else if (OpVal != N->getOperand(i)) 300 return false; 301 } 302 303 if (OpVal.Val == 0) return false; // All UNDEF: use implicit def. 304 305 unsigned ValSizeInBytes = 0; 306 uint64_t Value = 0; 307 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 308 Value = CN->getValue(); 309 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8; 310 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 311 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 312 Value = FloatToBits(CN->getValue()); 313 ValSizeInBytes = 4; 314 } 315 316 // If the splat value is larger than the element value, then we can never do 317 // this splat. The only case that we could fit the replicated bits into our 318 // immediate field for would be zero, and we prefer to use vxor for it. 319 if (ValSizeInBytes < ByteSize) return false; 320 321 // If the element value is larger than the splat value, cut it in half and 322 // check to see if the two halves are equal. Continue doing this until we 323 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 324 while (ValSizeInBytes > ByteSize) { 325 ValSizeInBytes >>= 1; 326 327 // If the top half equals the bottom half, we're still ok. 328 if (((Value >> (ValSizeInBytes*8)) & ((8 << ValSizeInBytes)-1)) != 329 (Value & ((8 << ValSizeInBytes)-1))) 330 return false; 331 } 332 333 // Properly sign extend the value. 334 int ShAmt = (4-ByteSize)*8; 335 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 336 337 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 338 if (MaskVal == 0) return false; 339 340 if (Val) *Val = MaskVal; 341 342 // Finally, if this value fits in a 5 bit sext field, return true. 343 return ((MaskVal << (32-5)) >> (32-5)) == MaskVal; 344} 345 346 347/// LowerOperation - Provide custom lowering hooks for some operations. 348/// 349SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 350 switch (Op.getOpcode()) { 351 default: assert(0 && "Wasn't expecting to be able to lower this!"); 352 case ISD::FP_TO_SINT: { 353 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 354 SDOperand Src = Op.getOperand(0); 355 if (Src.getValueType() == MVT::f32) 356 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 357 358 SDOperand Tmp; 359 switch (Op.getValueType()) { 360 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 361 case MVT::i32: 362 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 363 break; 364 case MVT::i64: 365 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 366 break; 367 } 368 369 // Convert the FP value to an int value through memory. 370 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 371 if (Op.getValueType() == MVT::i32) 372 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 373 return Bits; 374 } 375 case ISD::SINT_TO_FP: 376 if (Op.getOperand(0).getValueType() == MVT::i64) { 377 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 378 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 379 if (Op.getValueType() == MVT::f32) 380 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 381 return FP; 382 } else { 383 assert(Op.getOperand(0).getValueType() == MVT::i32 && 384 "Unhandled SINT_TO_FP type in custom expander!"); 385 // Since we only generate this in 64-bit mode, we can take advantage of 386 // 64-bit registers. In particular, sign extend the input value into the 387 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 388 // then lfd it and fcfid it. 389 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 390 int FrameIdx = FrameInfo->CreateStackObject(8, 8); 391 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); 392 393 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32, 394 Op.getOperand(0)); 395 396 // STD the extended value into the stack slot. 397 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other, 398 DAG.getEntryNode(), Ext64, FIdx, 399 DAG.getSrcValue(NULL)); 400 // Load the value as a double. 401 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL)); 402 403 // FCFID it and return it. 404 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld); 405 if (Op.getValueType() == MVT::f32) 406 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 407 return FP; 408 } 409 break; 410 411 case ISD::SELECT_CC: { 412 // Turn FP only select_cc's into fsel instructions. 413 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 414 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 415 break; 416 417 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 418 419 // Cannot handle SETEQ/SETNE. 420 if (CC == ISD::SETEQ || CC == ISD::SETNE) break; 421 422 MVT::ValueType ResVT = Op.getValueType(); 423 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 424 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 425 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 426 427 // If the RHS of the comparison is a 0.0, we don't need to do the 428 // subtraction at all. 429 if (isFloatingPointZero(RHS)) 430 switch (CC) { 431 default: break; // SETUO etc aren't handled by fsel. 432 case ISD::SETULT: 433 case ISD::SETLT: 434 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 435 case ISD::SETUGE: 436 case ISD::SETGE: 437 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 438 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 439 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 440 case ISD::SETUGT: 441 case ISD::SETGT: 442 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 443 case ISD::SETULE: 444 case ISD::SETLE: 445 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 446 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 447 return DAG.getNode(PPCISD::FSEL, ResVT, 448 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 449 } 450 451 SDOperand Cmp; 452 switch (CC) { 453 default: break; // SETUO etc aren't handled by fsel. 454 case ISD::SETULT: 455 case ISD::SETLT: 456 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 457 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 458 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 459 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 460 case ISD::SETUGE: 461 case ISD::SETGE: 462 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 463 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 464 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 465 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 466 case ISD::SETUGT: 467 case ISD::SETGT: 468 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 469 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 470 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 471 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 472 case ISD::SETULE: 473 case ISD::SETLE: 474 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 475 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 476 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 477 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 478 } 479 break; 480 } 481 case ISD::SHL: { 482 assert(Op.getValueType() == MVT::i64 && 483 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 484 // The generic code does a fine job expanding shift by a constant. 485 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 486 487 // Otherwise, expand into a bunch of logical ops. Note that these ops 488 // depend on the PPC behavior for oversized shift amounts. 489 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 490 DAG.getConstant(0, MVT::i32)); 491 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 492 DAG.getConstant(1, MVT::i32)); 493 SDOperand Amt = Op.getOperand(1); 494 495 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 496 DAG.getConstant(32, MVT::i32), Amt); 497 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 498 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 499 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 500 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 501 DAG.getConstant(-32U, MVT::i32)); 502 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 503 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 504 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 505 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 506 } 507 case ISD::SRL: { 508 assert(Op.getValueType() == MVT::i64 && 509 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 510 // The generic code does a fine job expanding shift by a constant. 511 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 512 513 // Otherwise, expand into a bunch of logical ops. Note that these ops 514 // depend on the PPC behavior for oversized shift amounts. 515 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 516 DAG.getConstant(0, MVT::i32)); 517 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 518 DAG.getConstant(1, MVT::i32)); 519 SDOperand Amt = Op.getOperand(1); 520 521 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 522 DAG.getConstant(32, MVT::i32), Amt); 523 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 524 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 525 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 526 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 527 DAG.getConstant(-32U, MVT::i32)); 528 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 529 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 530 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 531 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 532 } 533 case ISD::SRA: { 534 assert(Op.getValueType() == MVT::i64 && 535 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 536 // The generic code does a fine job expanding shift by a constant. 537 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 538 539 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 540 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 541 DAG.getConstant(0, MVT::i32)); 542 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 543 DAG.getConstant(1, MVT::i32)); 544 SDOperand Amt = Op.getOperand(1); 545 546 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 547 DAG.getConstant(32, MVT::i32), Amt); 548 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 549 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 550 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 551 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 552 DAG.getConstant(-32U, MVT::i32)); 553 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 554 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 555 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 556 Tmp4, Tmp6, ISD::SETLE); 557 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 558 } 559 case ISD::ConstantPool: { 560 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 561 Constant *C = CP->get(); 562 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment()); 563 SDOperand Zero = DAG.getConstant(0, MVT::i32); 564 565 if (getTargetMachine().getRelocationModel() == Reloc::Static) { 566 // Generate non-pic code that has direct accesses to the constant pool. 567 // The address of the global is just (hi(&g)+lo(&g)). 568 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 569 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 570 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 571 } 572 573 // Only lower ConstantPool on Darwin. 574 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 575 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 576 if (getTargetMachine().getRelocationModel() == Reloc::PIC) { 577 // With PIC, the first instruction is actually "GR+hi(&G)". 578 Hi = DAG.getNode(ISD::ADD, MVT::i32, 579 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 580 } 581 582 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 583 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 584 return Lo; 585 } 586 case ISD::GlobalAddress: { 587 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 588 GlobalValue *GV = GSDN->getGlobal(); 589 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset()); 590 SDOperand Zero = DAG.getConstant(0, MVT::i32); 591 592 if (getTargetMachine().getRelocationModel() == Reloc::Static) { 593 // Generate non-pic code that has direct accesses to globals. 594 // The address of the global is just (hi(&g)+lo(&g)). 595 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 596 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 597 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 598 } 599 600 // Only lower GlobalAddress on Darwin. 601 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 602 603 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 604 if (getTargetMachine().getRelocationModel() == Reloc::PIC) { 605 // With PIC, the first instruction is actually "GR+hi(&G)". 606 Hi = DAG.getNode(ISD::ADD, MVT::i32, 607 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 608 } 609 610 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 611 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 612 613 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && 614 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode())) 615 return Lo; 616 617 // If the global is weak or external, we have to go through the lazy 618 // resolution stub. 619 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); 620 } 621 case ISD::SETCC: { 622 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 623 624 // If we're comparing for equality to zero, expose the fact that this is 625 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 626 // fold the new nodes. 627 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 628 if (C->isNullValue() && CC == ISD::SETEQ) { 629 MVT::ValueType VT = Op.getOperand(0).getValueType(); 630 SDOperand Zext = Op.getOperand(0); 631 if (VT < MVT::i32) { 632 VT = MVT::i32; 633 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); 634 } 635 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT)); 636 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext); 637 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz, 638 DAG.getConstant(Log2b, getShiftAmountTy())); 639 return DAG.getNode(ISD::TRUNCATE, getSetCCResultTy(), Scc); 640 } 641 // Leave comparisons against 0 and -1 alone for now, since they're usually 642 // optimized. FIXME: revisit this when we can custom lower all setcc 643 // optimizations. 644 if (C->isAllOnesValue() || C->isNullValue()) 645 break; 646 } 647 648 // If we have an integer seteq/setne, turn it into a compare against zero 649 // by subtracting the rhs from the lhs, which is faster than setting a 650 // condition register, reading it back out, and masking the correct bit. 651 MVT::ValueType LHSVT = Op.getOperand(0).getValueType(); 652 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 653 MVT::ValueType VT = Op.getValueType(); 654 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0), 655 Op.getOperand(1)); 656 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); 657 } 658 break; 659 } 660 case ISD::VASTART: { 661 // vastart just stores the address of the VarArgsFrameIndex slot into the 662 // memory location argument. 663 // FIXME: Replace MVT::i32 with PointerTy 664 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 665 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR, 666 Op.getOperand(1), Op.getOperand(2)); 667 } 668 case ISD::RET: { 669 SDOperand Copy; 670 671 switch(Op.getNumOperands()) { 672 default: 673 assert(0 && "Do not know how to return this many arguments!"); 674 abort(); 675 case 1: 676 return SDOperand(); // ret void is legal 677 case 2: { 678 MVT::ValueType ArgVT = Op.getOperand(1).getValueType(); 679 unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1; 680 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 681 SDOperand()); 682 break; 683 } 684 case 3: 685 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2), 686 SDOperand()); 687 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1)); 688 break; 689 } 690 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 691 } 692 case ISD::SCALAR_TO_VECTOR: { 693 // Create a stack slot that is 16-byte aligned. 694 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 695 int FrameIdx = FrameInfo->CreateStackObject(16, 16); 696 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32); 697 698 // Store the input value into Value#0 of the stack slot. 699 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 700 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL)); 701 // Load it out. 702 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL)); 703 } 704 case ISD::BUILD_VECTOR: 705 // If this is a case we can't handle, return null and let the default 706 // expansion code take care of it. If we CAN select this case, return Op. 707 708 // See if this is all zeros. 709 // FIXME: We should handle splat(-0.0), and other cases here. 710 if (ISD::isBuildVectorAllZeros(Op.Val)) 711 return Op; 712 713 if (PPC::isVecSplatImm(Op.Val, 1) || // vspltisb 714 PPC::isVecSplatImm(Op.Val, 2) || // vspltish 715 PPC::isVecSplatImm(Op.Val, 4)) // vspltisw 716 return Op; 717 718 return SDOperand(); 719 720 case ISD::VECTOR_SHUFFLE: { 721 SDOperand V1 = Op.getOperand(0); 722 SDOperand V2 = Op.getOperand(1); 723 SDOperand PermMask = Op.getOperand(2); 724 725 // Cases that are handled by instructions that take permute immediates 726 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 727 // selected by the instruction selector. 728 if (PPC::isSplatShuffleMask(PermMask.Val) && V2.getOpcode() == ISD::UNDEF) 729 break; 730 731 // TODO: Handle more cases, and also handle cases that are cheaper to do as 732 // multiple such instructions than as a constant pool load/vperm pair. 733 734 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 735 // vector that will get spilled to the constant pool. 736 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 737 738 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 739 // that it is in input element units, not in bytes. Convert now. 740 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType()); 741 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8; 742 743 std::vector<SDOperand> ResultMask; 744 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) { 745 unsigned SrcElt =cast<ConstantSDNode>(PermMask.getOperand(i))->getValue(); 746 747 for (unsigned j = 0; j != BytesPerElement; ++j) 748 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 749 MVT::i8)); 750 } 751 752 SDOperand VPermMask =DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask); 753 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask); 754 } 755 case ISD::INTRINSIC_WO_CHAIN: { 756 unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(0))->getValue(); 757 758 // If this is a lowered altivec predicate compare, CompareOpc is set to the 759 // opcode number of the comparison. 760 int CompareOpc = -1; 761 bool isDot = false; 762 switch (IntNo) { 763 default: return SDOperand(); // Don't custom lower most intrinsics. 764 // Comparison predicates. 765 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 766 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 767 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 768 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 769 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 770 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 771 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 772 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 773 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 774 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 775 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 776 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 777 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 778 779 // Normal Comparisons. 780 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 781 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 782 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 783 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 784 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 785 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 786 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 787 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 788 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 789 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 790 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 791 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 792 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 793 } 794 795 assert(CompareOpc>0 && "We only lower altivec predicate compares so far!"); 796 797 // If this is a non-dot comparison, make the VCMP node. 798 if (!isDot) 799 return DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(), 800 Op.getOperand(1), Op.getOperand(2), 801 DAG.getConstant(CompareOpc, MVT::i32)); 802 803 // Create the PPCISD altivec 'dot' comparison node. 804 std::vector<SDOperand> Ops; 805 std::vector<MVT::ValueType> VTs; 806 Ops.push_back(Op.getOperand(2)); // LHS 807 Ops.push_back(Op.getOperand(3)); // RHS 808 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32)); 809 VTs.push_back(Op.getOperand(2).getValueType()); 810 VTs.push_back(MVT::Flag); 811 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops); 812 813 // Now that we have the comparison, emit a copy from the CR to a GPR. 814 // This is flagged to the above dot comparison. 815 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32, 816 DAG.getRegister(PPC::CR6, MVT::i32), 817 CompNode.getValue(1)); 818 819 // Unpack the result based on how the target uses it. 820 unsigned BitNo; // Bit # of CR6. 821 bool InvertBit; // Invert result? 822 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) { 823 default: // Can't happen, don't crash on invalid number though. 824 case 0: // Return the value of the EQ bit of CR6. 825 BitNo = 0; InvertBit = false; 826 break; 827 case 1: // Return the inverted value of the EQ bit of CR6. 828 BitNo = 0; InvertBit = true; 829 break; 830 case 2: // Return the value of the LT bit of CR6. 831 BitNo = 2; InvertBit = false; 832 break; 833 case 3: // Return the inverted value of the LT bit of CR6. 834 BitNo = 2; InvertBit = true; 835 break; 836 } 837 838 // Shift the bit into the low position. 839 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags, 840 DAG.getConstant(8-(3-BitNo), MVT::i32)); 841 // Isolate the bit. 842 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags, 843 DAG.getConstant(1, MVT::i32)); 844 845 // If we are supposed to, toggle the bit. 846 if (InvertBit) 847 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags, 848 DAG.getConstant(1, MVT::i32)); 849 return Flags; 850 } 851 } 852 return SDOperand(); 853} 854 855std::vector<SDOperand> 856PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 857 // 858 // add beautiful description of PPC stack frame format, or at least some docs 859 // 860 MachineFunction &MF = DAG.getMachineFunction(); 861 MachineFrameInfo *MFI = MF.getFrameInfo(); 862 MachineBasicBlock& BB = MF.front(); 863 SSARegMap *RegMap = MF.getSSARegMap(); 864 std::vector<SDOperand> ArgValues; 865 866 unsigned ArgOffset = 24; 867 unsigned GPR_remaining = 8; 868 unsigned FPR_remaining = 13; 869 unsigned GPR_idx = 0, FPR_idx = 0; 870 static const unsigned GPR[] = { 871 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 872 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 873 }; 874 static const unsigned FPR[] = { 875 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 876 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 877 }; 878 879 // Add DAG nodes to load the arguments... On entry to a function on PPC, 880 // the arguments start at offset 24, although they are likely to be passed 881 // in registers. 882 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 883 SDOperand newroot, argt; 884 unsigned ObjSize; 885 bool needsLoad = false; 886 bool ArgLive = !I->use_empty(); 887 MVT::ValueType ObjectVT = getValueType(I->getType()); 888 889 switch (ObjectVT) { 890 default: assert(0 && "Unhandled argument type!"); 891 case MVT::i1: 892 case MVT::i8: 893 case MVT::i16: 894 case MVT::i32: 895 ObjSize = 4; 896 if (!ArgLive) break; 897 if (GPR_remaining > 0) { 898 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 899 MF.addLiveIn(GPR[GPR_idx], VReg); 900 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 901 if (ObjectVT != MVT::i32) { 902 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 903 : ISD::AssertZext; 904 argt = DAG.getNode(AssertOp, MVT::i32, argt, 905 DAG.getValueType(ObjectVT)); 906 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt); 907 } 908 } else { 909 needsLoad = true; 910 } 911 break; 912 case MVT::i64: 913 ObjSize = 8; 914 if (!ArgLive) break; 915 if (GPR_remaining > 0) { 916 SDOperand argHi, argLo; 917 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 918 MF.addLiveIn(GPR[GPR_idx], VReg); 919 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 920 // If we have two or more remaining argument registers, then both halves 921 // of the i64 can be sourced from there. Otherwise, the lower half will 922 // have to come off the stack. This can happen when an i64 is preceded 923 // by 28 bytes of arguments. 924 if (GPR_remaining > 1) { 925 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 926 MF.addLiveIn(GPR[GPR_idx+1], VReg); 927 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32); 928 } else { 929 int FI = MFI->CreateFixedObject(4, ArgOffset+4); 930 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 931 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 932 DAG.getSrcValue(NULL)); 933 } 934 // Build the outgoing arg thingy 935 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi); 936 newroot = argLo; 937 } else { 938 needsLoad = true; 939 } 940 break; 941 case MVT::f32: 942 case MVT::f64: 943 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4; 944 if (!ArgLive) { 945 if (FPR_remaining > 0) { 946 --FPR_remaining; 947 ++FPR_idx; 948 } 949 break; 950 } 951 if (FPR_remaining > 0) { 952 unsigned VReg; 953 if (ObjectVT == MVT::f32) 954 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 955 else 956 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 957 MF.addLiveIn(FPR[FPR_idx], VReg); 958 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT); 959 --FPR_remaining; 960 ++FPR_idx; 961 } else { 962 needsLoad = true; 963 } 964 break; 965 } 966 967 // We need to load the argument to a virtual register if we determined above 968 // that we ran out of physical registers of the appropriate type 969 if (needsLoad) { 970 unsigned SubregOffset = 0; 971 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3; 972 if (ObjectVT == MVT::i16) SubregOffset = 2; 973 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 974 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 975 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, 976 DAG.getConstant(SubregOffset, MVT::i32)); 977 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 978 DAG.getSrcValue(NULL)); 979 } 980 981 // Every 4 bytes of argument space consumes one of the GPRs available for 982 // argument passing. 983 if (GPR_remaining > 0) { 984 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; 985 GPR_remaining -= delta; 986 GPR_idx += delta; 987 } 988 ArgOffset += ObjSize; 989 if (newroot.Val) 990 DAG.setRoot(newroot.getValue(1)); 991 992 ArgValues.push_back(argt); 993 } 994 995 // If the function takes variable number of arguments, make a frame index for 996 // the start of the first vararg value... for expansion of llvm.va_start. 997 if (F.isVarArg()) { 998 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 999 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 1000 // If this function is vararg, store any remaining integer argument regs 1001 // to their spots on the stack so that they may be loaded by deferencing the 1002 // result of va_next. 1003 std::vector<SDOperand> MemOps; 1004 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { 1005 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 1006 MF.addLiveIn(GPR[GPR_idx], VReg); 1007 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 1008 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 1009 Val, FIN, DAG.getSrcValue(NULL)); 1010 MemOps.push_back(Store); 1011 // Increment the address by four for the next argument to store 1012 SDOperand PtrOff = DAG.getConstant(4, getPointerTy()); 1013 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff); 1014 } 1015 if (!MemOps.empty()) { 1016 MemOps.push_back(DAG.getRoot()); 1017 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps)); 1018 } 1019 } 1020 1021 // Finally, inform the code generator which regs we return values in. 1022 switch (getValueType(F.getReturnType())) { 1023 default: assert(0 && "Unknown type!"); 1024 case MVT::isVoid: break; 1025 case MVT::i1: 1026 case MVT::i8: 1027 case MVT::i16: 1028 case MVT::i32: 1029 MF.addLiveOut(PPC::R3); 1030 break; 1031 case MVT::i64: 1032 MF.addLiveOut(PPC::R3); 1033 MF.addLiveOut(PPC::R4); 1034 break; 1035 case MVT::f32: 1036 case MVT::f64: 1037 MF.addLiveOut(PPC::F1); 1038 break; 1039 } 1040 1041 return ArgValues; 1042} 1043 1044std::pair<SDOperand, SDOperand> 1045PPCTargetLowering::LowerCallTo(SDOperand Chain, 1046 const Type *RetTy, bool isVarArg, 1047 unsigned CallingConv, bool isTailCall, 1048 SDOperand Callee, ArgListTy &Args, 1049 SelectionDAG &DAG) { 1050 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in 1051 // SelectExpr to use to put the arguments in the appropriate registers. 1052 std::vector<SDOperand> args_to_use; 1053 1054 // Count how many bytes are to be pushed on the stack, including the linkage 1055 // area, and parameter passing area. 1056 unsigned NumBytes = 24; 1057 1058 if (Args.empty()) { 1059 Chain = DAG.getCALLSEQ_START(Chain, 1060 DAG.getConstant(NumBytes, getPointerTy())); 1061 } else { 1062 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 1063 switch (getValueType(Args[i].second)) { 1064 default: assert(0 && "Unknown value type!"); 1065 case MVT::i1: 1066 case MVT::i8: 1067 case MVT::i16: 1068 case MVT::i32: 1069 case MVT::f32: 1070 NumBytes += 4; 1071 break; 1072 case MVT::i64: 1073 case MVT::f64: 1074 NumBytes += 8; 1075 break; 1076 } 1077 } 1078 1079 // Just to be safe, we'll always reserve the full 24 bytes of linkage area 1080 // plus 32 bytes of argument space in case any called code gets funky on us. 1081 // (Required by ABI to support var arg) 1082 if (NumBytes < 56) NumBytes = 56; 1083 1084 // Adjust the stack pointer for the new arguments... 1085 // These operations are automatically eliminated by the prolog/epilog pass 1086 Chain = DAG.getCALLSEQ_START(Chain, 1087 DAG.getConstant(NumBytes, getPointerTy())); 1088 1089 // Set up a copy of the stack pointer for use loading and storing any 1090 // arguments that may not fit in the registers available for argument 1091 // passing. 1092 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 1093 1094 // Figure out which arguments are going to go in registers, and which in 1095 // memory. Also, if this is a vararg function, floating point operations 1096 // must be stored to our stack, and loaded into integer regs as well, if 1097 // any integer regs are available for argument passing. 1098 unsigned ArgOffset = 24; 1099 unsigned GPR_remaining = 8; 1100 unsigned FPR_remaining = 13; 1101 1102 std::vector<SDOperand> MemOps; 1103 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 1104 // PtrOff will be used to store the current argument to the stack if a 1105 // register cannot be found for it. 1106 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 1107 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 1108 MVT::ValueType ArgVT = getValueType(Args[i].second); 1109 1110 switch (ArgVT) { 1111 default: assert(0 && "Unexpected ValueType for argument!"); 1112 case MVT::i1: 1113 case MVT::i8: 1114 case MVT::i16: 1115 // Promote the integer to 32 bits. If the input type is signed use a 1116 // sign extend, otherwise use a zero extend. 1117 if (Args[i].second->isSigned()) 1118 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 1119 else 1120 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 1121 // FALL THROUGH 1122 case MVT::i32: 1123 if (GPR_remaining > 0) { 1124 args_to_use.push_back(Args[i].first); 1125 --GPR_remaining; 1126 } else { 1127 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1128 Args[i].first, PtrOff, 1129 DAG.getSrcValue(NULL))); 1130 } 1131 ArgOffset += 4; 1132 break; 1133 case MVT::i64: 1134 // If we have one free GPR left, we can place the upper half of the i64 1135 // in it, and store the other half to the stack. If we have two or more 1136 // free GPRs, then we can pass both halves of the i64 in registers. 1137 if (GPR_remaining > 0) { 1138 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 1139 Args[i].first, DAG.getConstant(1, MVT::i32)); 1140 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 1141 Args[i].first, DAG.getConstant(0, MVT::i32)); 1142 args_to_use.push_back(Hi); 1143 --GPR_remaining; 1144 if (GPR_remaining > 0) { 1145 args_to_use.push_back(Lo); 1146 --GPR_remaining; 1147 } else { 1148 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 1149 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 1150 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1151 Lo, PtrOff, DAG.getSrcValue(NULL))); 1152 } 1153 } else { 1154 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1155 Args[i].first, PtrOff, 1156 DAG.getSrcValue(NULL))); 1157 } 1158 ArgOffset += 8; 1159 break; 1160 case MVT::f32: 1161 case MVT::f64: 1162 if (FPR_remaining > 0) { 1163 args_to_use.push_back(Args[i].first); 1164 --FPR_remaining; 1165 if (isVarArg) { 1166 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 1167 Args[i].first, PtrOff, 1168 DAG.getSrcValue(NULL)); 1169 MemOps.push_back(Store); 1170 // Float varargs are always shadowed in available integer registers 1171 if (GPR_remaining > 0) { 1172 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 1173 DAG.getSrcValue(NULL)); 1174 MemOps.push_back(Load.getValue(1)); 1175 args_to_use.push_back(Load); 1176 --GPR_remaining; 1177 } 1178 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 1179 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 1180 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 1181 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 1182 DAG.getSrcValue(NULL)); 1183 MemOps.push_back(Load.getValue(1)); 1184 args_to_use.push_back(Load); 1185 --GPR_remaining; 1186 } 1187 } else { 1188 // If we have any FPRs remaining, we may also have GPRs remaining. 1189 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 1190 // GPRs. 1191 if (GPR_remaining > 0) { 1192 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 1193 --GPR_remaining; 1194 } 1195 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 1196 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 1197 --GPR_remaining; 1198 } 1199 } 1200 } else { 1201 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 1202 Args[i].first, PtrOff, 1203 DAG.getSrcValue(NULL))); 1204 } 1205 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8; 1206 break; 1207 } 1208 } 1209 if (!MemOps.empty()) 1210 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); 1211 } 1212 1213 std::vector<MVT::ValueType> RetVals; 1214 MVT::ValueType RetTyVT = getValueType(RetTy); 1215 MVT::ValueType ActualRetTyVT = RetTyVT; 1216 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 1217 ActualRetTyVT = MVT::i32; // Promote result to i32. 1218 1219 if (RetTyVT == MVT::i64) { 1220 RetVals.push_back(MVT::i32); 1221 RetVals.push_back(MVT::i32); 1222 } else if (RetTyVT != MVT::isVoid) { 1223 RetVals.push_back(ActualRetTyVT); 1224 } 1225 RetVals.push_back(MVT::Other); 1226 1227 // If the callee is a GlobalAddress node (quite common, every direct call is) 1228 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1229 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1230 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 1231 1232 std::vector<SDOperand> Ops; 1233 Ops.push_back(Chain); 1234 Ops.push_back(Callee); 1235 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end()); 1236 SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops); 1237 Chain = TheCall.getValue(TheCall.Val->getNumValues()-1); 1238 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 1239 DAG.getConstant(NumBytes, getPointerTy())); 1240 SDOperand RetVal = TheCall; 1241 1242 // If the result is a small value, add a note so that we keep track of the 1243 // information about whether it is sign or zero extended. 1244 if (RetTyVT != ActualRetTyVT) { 1245 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext, 1246 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 1247 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 1248 } else if (RetTyVT == MVT::i64) { 1249 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, RetVal, RetVal.getValue(1)); 1250 } 1251 1252 return std::make_pair(RetVal, Chain); 1253} 1254 1255MachineBasicBlock * 1256PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 1257 MachineBasicBlock *BB) { 1258 assert((MI->getOpcode() == PPC::SELECT_CC_Int || 1259 MI->getOpcode() == PPC::SELECT_CC_F4 || 1260 MI->getOpcode() == PPC::SELECT_CC_F8) && 1261 "Unexpected instr type to insert"); 1262 1263 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1264 // control-flow pattern. The incoming instruction knows the destination vreg 1265 // to set, the condition code register to branch on, the true/false values to 1266 // select between, and a branch opcode to use. 1267 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1268 ilist<MachineBasicBlock>::iterator It = BB; 1269 ++It; 1270 1271 // thisMBB: 1272 // ... 1273 // TrueVal = ... 1274 // cmpTY ccX, r1, r2 1275 // bCC copy1MBB 1276 // fallthrough --> copy0MBB 1277 MachineBasicBlock *thisMBB = BB; 1278 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 1279 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 1280 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2) 1281 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 1282 MachineFunction *F = BB->getParent(); 1283 F->getBasicBlockList().insert(It, copy0MBB); 1284 F->getBasicBlockList().insert(It, sinkMBB); 1285 // Update machine-CFG edges by first adding all successors of the current 1286 // block to the new block which will contain the Phi node for the select. 1287 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 1288 e = BB->succ_end(); i != e; ++i) 1289 sinkMBB->addSuccessor(*i); 1290 // Next, remove all successors of the current block, and add the true 1291 // and fallthrough blocks as its successors. 1292 while(!BB->succ_empty()) 1293 BB->removeSuccessor(BB->succ_begin()); 1294 BB->addSuccessor(copy0MBB); 1295 BB->addSuccessor(sinkMBB); 1296 1297 // copy0MBB: 1298 // %FalseValue = ... 1299 // # fallthrough to sinkMBB 1300 BB = copy0MBB; 1301 1302 // Update machine-CFG edges 1303 BB->addSuccessor(sinkMBB); 1304 1305 // sinkMBB: 1306 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1307 // ... 1308 BB = sinkMBB; 1309 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg()) 1310 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 1311 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1312 1313 delete MI; // The pseudo instruction is gone now. 1314 return BB; 1315} 1316 1317SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N, 1318 DAGCombinerInfo &DCI) const { 1319 TargetMachine &TM = getTargetMachine(); 1320 SelectionDAG &DAG = DCI.DAG; 1321 switch (N->getOpcode()) { 1322 default: break; 1323 case ISD::SINT_TO_FP: 1324 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 1325 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 1326 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 1327 // We allow the src/dst to be either f32/f64, but the intermediate 1328 // type must be i64. 1329 if (N->getOperand(0).getValueType() == MVT::i64) { 1330 SDOperand Val = N->getOperand(0).getOperand(0); 1331 if (Val.getValueType() == MVT::f32) { 1332 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 1333 DCI.AddToWorklist(Val.Val); 1334 } 1335 1336 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val); 1337 DCI.AddToWorklist(Val.Val); 1338 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val); 1339 DCI.AddToWorklist(Val.Val); 1340 if (N->getValueType(0) == MVT::f32) { 1341 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val); 1342 DCI.AddToWorklist(Val.Val); 1343 } 1344 return Val; 1345 } else if (N->getOperand(0).getValueType() == MVT::i32) { 1346 // If the intermediate type is i32, we can avoid the load/store here 1347 // too. 1348 } 1349 } 1350 } 1351 break; 1352 case ISD::STORE: 1353 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 1354 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 1355 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 1356 N->getOperand(1).getValueType() == MVT::i32) { 1357 SDOperand Val = N->getOperand(1).getOperand(0); 1358 if (Val.getValueType() == MVT::f32) { 1359 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val); 1360 DCI.AddToWorklist(Val.Val); 1361 } 1362 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val); 1363 DCI.AddToWorklist(Val.Val); 1364 1365 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val, 1366 N->getOperand(2), N->getOperand(3)); 1367 DCI.AddToWorklist(Val.Val); 1368 return Val; 1369 } 1370 break; 1371 case PPCISD::VCMP: { 1372 // If a VCMPo node already exists with exactly the same operands as this 1373 // node, use its result instead of this node (VCMPo computes both a CR6 and 1374 // a normal output). 1375 // 1376 if (!N->getOperand(0).hasOneUse() && 1377 !N->getOperand(1).hasOneUse() && 1378 !N->getOperand(2).hasOneUse()) { 1379 1380 // Scan all of the users of the LHS, looking for VCMPo's that match. 1381 SDNode *VCMPoNode = 0; 1382 1383 SDNode *LHSN = N->getOperand(0).Val; 1384 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 1385 UI != E; ++UI) 1386 if ((*UI)->getOpcode() == PPCISD::VCMPo && 1387 (*UI)->getOperand(1) == N->getOperand(1) && 1388 (*UI)->getOperand(2) == N->getOperand(2) && 1389 (*UI)->getOperand(0) == N->getOperand(0)) { 1390 VCMPoNode = *UI; 1391 break; 1392 } 1393 1394 // If there are non-zero uses of the flag value, use the VCMPo node! 1395 if (!VCMPoNode->hasNUsesOfValue(0, 1)) 1396 return SDOperand(VCMPoNode, 0); 1397 } 1398 break; 1399 } 1400 } 1401 1402 return SDOperand(); 1403} 1404 1405/// getConstraintType - Given a constraint letter, return the type of 1406/// constraint it is for this target. 1407PPCTargetLowering::ConstraintType 1408PPCTargetLowering::getConstraintType(char ConstraintLetter) const { 1409 switch (ConstraintLetter) { 1410 default: break; 1411 case 'b': 1412 case 'r': 1413 case 'f': 1414 case 'v': 1415 case 'y': 1416 return C_RegisterClass; 1417 } 1418 return TargetLowering::getConstraintType(ConstraintLetter); 1419} 1420 1421 1422std::vector<unsigned> PPCTargetLowering:: 1423getRegClassForInlineAsmConstraint(const std::string &Constraint, 1424 MVT::ValueType VT) const { 1425 if (Constraint.size() == 1) { 1426 switch (Constraint[0]) { // GCC RS6000 Constraint Letters 1427 default: break; // Unknown constriant letter 1428 case 'b': 1429 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 , 1430 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , 1431 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 1432 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 1433 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 1434 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 1435 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 1436 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 1437 0); 1438 case 'r': 1439 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 , 1440 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 , 1441 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11, 1442 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 1443 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 1444 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 1445 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 1446 PPC::R28, PPC::R29, PPC::R30, PPC::R31, 1447 0); 1448 case 'f': 1449 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 , 1450 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 , 1451 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11, 1452 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 1453 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 1454 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 1455 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 1456 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 1457 0); 1458 case 'v': 1459 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , 1460 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 1461 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, 1462 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 1463 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 1464 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 1465 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 1466 PPC::V28, PPC::V29, PPC::V30, PPC::V31, 1467 0); 1468 case 'y': 1469 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 1470 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 1471 0); 1472 } 1473 } 1474 1475 return std::vector<unsigned>(); 1476} 1477 1478// isOperandValidForConstraint 1479bool PPCTargetLowering:: 1480isOperandValidForConstraint(SDOperand Op, char Letter) { 1481 switch (Letter) { 1482 default: break; 1483 case 'I': 1484 case 'J': 1485 case 'K': 1486 case 'L': 1487 case 'M': 1488 case 'N': 1489 case 'O': 1490 case 'P': { 1491 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate. 1492 unsigned Value = cast<ConstantSDNode>(Op)->getValue(); 1493 switch (Letter) { 1494 default: assert(0 && "Unknown constraint letter!"); 1495 case 'I': // "I" is a signed 16-bit constant. 1496 return (short)Value == (int)Value; 1497 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 1498 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 1499 return (short)Value == 0; 1500 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 1501 return (Value >> 16) == 0; 1502 case 'M': // "M" is a constant that is greater than 31. 1503 return Value > 31; 1504 case 'N': // "N" is a positive constant that is an exact power of two. 1505 return (int)Value > 0 && isPowerOf2_32(Value); 1506 case 'O': // "O" is the constant zero. 1507 return Value == 0; 1508 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 1509 return (short)-Value == (int)-Value; 1510 } 1511 break; 1512 } 1513 } 1514 1515 // Handle standard constraint letters. 1516 return TargetLowering::isOperandValidForConstraint(Op, Letter); 1517} 1518 1519/// isLegalAddressImmediate - Return true if the integer value can be used 1520/// as the offset of the target addressing mode. 1521bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const { 1522 // PPC allows a sign-extended 16-bit immediate field. 1523 return (V > -(1 << 16) && V < (1 << 16)-1); 1524} 1525