PPCISelLowering.cpp revision 44ab89eb376af838d1123293a79975aede501464
15821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// License. See LICENSE.TXT for details. 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file implements the PPCISelLowering class. 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "PPCISelLowering.h" 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "PPCMachineFunctionInfo.h" 165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "PPCPerfectShuffle.h" 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "PPCPredicates.h" 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "PPCTargetMachine.h" 195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/ADT/STLExtras.h" 205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/ADT/VectorExtras.h" 215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/CodeGen/CallingConvLower.h" 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/CodeGen/MachineFrameInfo.h" 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/CodeGen/MachineFunction.h" 245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/CodeGen/MachineInstrBuilder.h" 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/CodeGen/MachineRegisterInfo.h" 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/CodeGen/PseudoSourceValue.h" 275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/CodeGen/SelectionDAG.h" 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/CallingConv.h" 305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Constants.h" 315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Function.h" 325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Intrinsics.h" 335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Support/MathExtras.h" 345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Target/TargetOptions.h" 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Support/CommandLine.h" 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Support/ErrorHandling.h" 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Support/raw_ostream.h" 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/DerivedTypes.h" 395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)using namespace llvm; 405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) CCValAssign::LocInfo &LocInfo, 435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) ISD::ArgFlagsTy &ArgFlags, 445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) CCState &State); 455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, 465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) EVT &LocVT, 475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) CCValAssign::LocInfo &LocInfo, 485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) ISD::ArgFlagsTy &ArgFlags, 495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) CCState &State); 505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, 515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) EVT &LocVT, 525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) CCValAssign::LocInfo &LocInfo, 535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) ISD::ArgFlagsTy &ArgFlags, 545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) CCState &State); 555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)cl::desc("enable preincrement load/store generation on PPC (experimental)"), 585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) cl::Hidden); 595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (TM.getSubtargetImpl()->isDarwin()) 625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return new TargetLoweringObjectFileMachO(); 635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return new TargetLoweringObjectFileELF(); 655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) setPow2DivIsCheap(); 715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Use _setjmp/_longjmp instead of setjmp/longjmp. 735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) setUseUnderscoreSetJmp(true); 745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) setUseUnderscoreLongJmp(true); 755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all 775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // arguments are at least 4/8 bytes aligned. 785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4); 795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Set up the register classes. 815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 83 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 84 85 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 86 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 87 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 88 89 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 90 91 // PowerPC has pre-inc load and store's. 92 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 93 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 94 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 95 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 97 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 98 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 99 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 100 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 102 103 // This is used in the ppcf128->int sequence. Note it has different semantics 104 // from FP_ROUND: that rounds to nearest, this rounds to zero. 105 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 106 107 // PowerPC has no SREM/UREM instructions 108 setOperationAction(ISD::SREM, MVT::i32, Expand); 109 setOperationAction(ISD::UREM, MVT::i32, Expand); 110 setOperationAction(ISD::SREM, MVT::i64, Expand); 111 setOperationAction(ISD::UREM, MVT::i64, Expand); 112 113 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 114 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 116 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 117 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 118 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 119 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 120 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 121 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 122 123 // We don't support sin/cos/sqrt/fmod/pow 124 setOperationAction(ISD::FSIN , MVT::f64, Expand); 125 setOperationAction(ISD::FCOS , MVT::f64, Expand); 126 setOperationAction(ISD::FREM , MVT::f64, Expand); 127 setOperationAction(ISD::FPOW , MVT::f64, Expand); 128 setOperationAction(ISD::FSIN , MVT::f32, Expand); 129 setOperationAction(ISD::FCOS , MVT::f32, Expand); 130 setOperationAction(ISD::FREM , MVT::f32, Expand); 131 setOperationAction(ISD::FPOW , MVT::f32, Expand); 132 133 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 134 135 // If we're enabling GP optimizations, use hardware square root 136 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 137 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 138 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 139 } 140 141 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 142 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 143 144 // PowerPC does not have BSWAP, CTPOP or CTTZ 145 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 146 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 147 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 148 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 149 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 150 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 151 152 // PowerPC does not have ROTR 153 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 154 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 155 156 // PowerPC does not have Select 157 setOperationAction(ISD::SELECT, MVT::i32, Expand); 158 setOperationAction(ISD::SELECT, MVT::i64, Expand); 159 setOperationAction(ISD::SELECT, MVT::f32, Expand); 160 setOperationAction(ISD::SELECT, MVT::f64, Expand); 161 162 // PowerPC wants to turn select_cc of FP into fsel when possible. 163 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 164 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 165 166 // PowerPC wants to optimize integer setcc a bit 167 setOperationAction(ISD::SETCC, MVT::i32, Custom); 168 169 // PowerPC does not have BRCOND which requires SetCC 170 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 171 172 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 173 174 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 175 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 176 177 // PowerPC does not have [U|S]INT_TO_FP 178 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 179 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 180 181 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 182 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 183 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 184 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 185 186 // We cannot sextinreg(i1). Expand to shifts. 187 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 188 189 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 190 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 191 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 192 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 193 194 195 // We want to legalize GlobalAddress and ConstantPool nodes into the 196 // appropriate instructions to materialize the address. 197 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 199 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 200 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 201 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 202 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 203 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 204 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 206 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 207 208 // TRAP is legal. 209 setOperationAction(ISD::TRAP, MVT::Other, Legal); 210 211 // TRAMPOLINE is custom lowered. 212 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 213 214 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 215 setOperationAction(ISD::VASTART , MVT::Other, Custom); 216 217 // VAARG is custom lowered with the 32-bit SVR4 ABI. 218 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 219 && !TM.getSubtarget<PPCSubtarget>().isPPC64()) 220 setOperationAction(ISD::VAARG, MVT::Other, Custom); 221 else 222 setOperationAction(ISD::VAARG, MVT::Other, Expand); 223 224 // Use the default implementation. 225 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 226 setOperationAction(ISD::VAEND , MVT::Other, Expand); 227 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 228 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 229 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 230 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 231 232 // We want to custom lower some of our intrinsics. 233 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 234 235 // Comparisons that require checking two conditions. 236 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 237 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 238 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 239 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 240 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 241 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 242 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 243 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 244 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 245 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 246 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 247 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 248 249 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 250 // They also have instructions for converting between i64 and fp. 251 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 252 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 253 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 254 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 255 // This is just the low 32 bits of a (signed) fp->i64 conversion. 256 // We cannot do this with Promote because i64 is not a legal type. 257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 258 259 // FIXME: disable this lowered code. This generates 64-bit register values, 260 // and we don't model the fact that the top part is clobbered by calls. We 261 // need to flag these together so that the value isn't live across a call. 262 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 263 } else { 264 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 265 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 266 } 267 268 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 269 // 64-bit PowerPC implementations can support i64 types directly 270 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 271 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 272 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 273 // 64-bit PowerPC wants to expand i128 shifts itself. 274 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 275 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 276 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 277 } else { 278 // 32-bit PowerPC wants to expand i64 shifts itself. 279 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 280 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 281 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 282 } 283 284 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 285 // First set operation action for all vector types to expand. Then we 286 // will selectively turn on ones that can be effectively codegen'd. 287 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 288 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 289 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 290 291 // add/sub are legal for all supported vector VT's. 292 setOperationAction(ISD::ADD , VT, Legal); 293 setOperationAction(ISD::SUB , VT, Legal); 294 295 // We promote all shuffles to v16i8. 296 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 297 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 298 299 // We promote all non-typed operations to v4i32. 300 setOperationAction(ISD::AND , VT, Promote); 301 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 302 setOperationAction(ISD::OR , VT, Promote); 303 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 304 setOperationAction(ISD::XOR , VT, Promote); 305 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 306 setOperationAction(ISD::LOAD , VT, Promote); 307 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 308 setOperationAction(ISD::SELECT, VT, Promote); 309 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 310 setOperationAction(ISD::STORE, VT, Promote); 311 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 312 313 // No other operations are legal. 314 setOperationAction(ISD::MUL , VT, Expand); 315 setOperationAction(ISD::SDIV, VT, Expand); 316 setOperationAction(ISD::SREM, VT, Expand); 317 setOperationAction(ISD::UDIV, VT, Expand); 318 setOperationAction(ISD::UREM, VT, Expand); 319 setOperationAction(ISD::FDIV, VT, Expand); 320 setOperationAction(ISD::FNEG, VT, Expand); 321 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 323 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 324 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 325 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 326 setOperationAction(ISD::UDIVREM, VT, Expand); 327 setOperationAction(ISD::SDIVREM, VT, Expand); 328 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 329 setOperationAction(ISD::FPOW, VT, Expand); 330 setOperationAction(ISD::CTPOP, VT, Expand); 331 setOperationAction(ISD::CTLZ, VT, Expand); 332 setOperationAction(ISD::CTTZ, VT, Expand); 333 } 334 335 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 336 // with merges, splats, etc. 337 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 338 339 setOperationAction(ISD::AND , MVT::v4i32, Legal); 340 setOperationAction(ISD::OR , MVT::v4i32, Legal); 341 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 342 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 343 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 344 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 345 346 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 347 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 348 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 349 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 350 351 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 352 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 353 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 354 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 355 356 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 357 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 358 359 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 360 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 361 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 362 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 363 } 364 365 setShiftAmountType(MVT::i32); 366 setBooleanContents(ZeroOrOneBooleanContent); 367 368 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 369 setStackPointerRegisterToSaveRestore(PPC::X1); 370 setExceptionPointerRegister(PPC::X3); 371 setExceptionSelectorRegister(PPC::X4); 372 } else { 373 setStackPointerRegisterToSaveRestore(PPC::R1); 374 setExceptionPointerRegister(PPC::R3); 375 setExceptionSelectorRegister(PPC::R4); 376 } 377 378 // We have target-specific dag combine patterns for the following nodes: 379 setTargetDAGCombine(ISD::SINT_TO_FP); 380 setTargetDAGCombine(ISD::STORE); 381 setTargetDAGCombine(ISD::BR_CC); 382 setTargetDAGCombine(ISD::BSWAP); 383 384 // Darwin long double math library functions have $LDBL128 appended. 385 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 386 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 387 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 388 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 389 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 390 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 391 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 392 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 393 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 394 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 395 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 396 } 397 398 computeRegisterProperties(); 399} 400 401/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 402/// function arguments in the caller parameter area. 403unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { 404 const TargetMachine &TM = getTargetMachine(); 405 // Darwin passes everything on 4 byte boundary. 406 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 407 return 4; 408 // FIXME SVR4 TBD 409 return 4; 410} 411 412const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 413 switch (Opcode) { 414 default: return 0; 415 case PPCISD::FSEL: return "PPCISD::FSEL"; 416 case PPCISD::FCFID: return "PPCISD::FCFID"; 417 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 418 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 419 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 420 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 421 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 422 case PPCISD::VPERM: return "PPCISD::VPERM"; 423 case PPCISD::Hi: return "PPCISD::Hi"; 424 case PPCISD::Lo: return "PPCISD::Lo"; 425 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 426 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 427 case PPCISD::LOAD: return "PPCISD::LOAD"; 428 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 429 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 430 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 431 case PPCISD::SRL: return "PPCISD::SRL"; 432 case PPCISD::SRA: return "PPCISD::SRA"; 433 case PPCISD::SHL: return "PPCISD::SHL"; 434 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 435 case PPCISD::STD_32: return "PPCISD::STD_32"; 436 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 437 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 438 case PPCISD::NOP: return "PPCISD::NOP"; 439 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 440 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 441 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 442 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 443 case PPCISD::MFCR: return "PPCISD::MFCR"; 444 case PPCISD::VCMP: return "PPCISD::VCMP"; 445 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 446 case PPCISD::LBRX: return "PPCISD::LBRX"; 447 case PPCISD::STBRX: return "PPCISD::STBRX"; 448 case PPCISD::LARX: return "PPCISD::LARX"; 449 case PPCISD::STCX: return "PPCISD::STCX"; 450 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 451 case PPCISD::MFFS: return "PPCISD::MFFS"; 452 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 453 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 454 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 455 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 456 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 457 } 458} 459 460MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const { 461 return MVT::i32; 462} 463 464/// getFunctionAlignment - Return the Log2 alignment of this function. 465unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const { 466 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) 467 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4; 468 else 469 return 2; 470} 471 472//===----------------------------------------------------------------------===// 473// Node matching predicates, for use by the tblgen matching code. 474//===----------------------------------------------------------------------===// 475 476/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 477static bool isFloatingPointZero(SDValue Op) { 478 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 479 return CFP->getValueAPF().isZero(); 480 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 481 // Maybe this has already been legalized into the constant pool? 482 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 483 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 484 return CFP->getValueAPF().isZero(); 485 } 486 return false; 487} 488 489/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 490/// true if Op is undef or if it matches the specified value. 491static bool isConstantOrUndef(int Op, int Val) { 492 return Op < 0 || Op == Val; 493} 494 495/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 496/// VPKUHUM instruction. 497bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 498 if (!isUnary) { 499 for (unsigned i = 0; i != 16; ++i) 500 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 501 return false; 502 } else { 503 for (unsigned i = 0; i != 8; ++i) 504 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 505 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 506 return false; 507 } 508 return true; 509} 510 511/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 512/// VPKUWUM instruction. 513bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 514 if (!isUnary) { 515 for (unsigned i = 0; i != 16; i += 2) 516 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 517 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 518 return false; 519 } else { 520 for (unsigned i = 0; i != 8; i += 2) 521 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 522 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 523 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 524 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 525 return false; 526 } 527 return true; 528} 529 530/// isVMerge - Common function, used to match vmrg* shuffles. 531/// 532static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 533 unsigned LHSStart, unsigned RHSStart) { 534 assert(N->getValueType(0) == MVT::v16i8 && 535 "PPC only supports shuffles by bytes!"); 536 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 537 "Unsupported merge size!"); 538 539 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 540 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 541 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 542 LHSStart+j+i*UnitSize) || 543 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 544 RHSStart+j+i*UnitSize)) 545 return false; 546 } 547 return true; 548} 549 550/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 551/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 552bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 553 bool isUnary) { 554 if (!isUnary) 555 return isVMerge(N, UnitSize, 8, 24); 556 return isVMerge(N, UnitSize, 8, 8); 557} 558 559/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 560/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 561bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 562 bool isUnary) { 563 if (!isUnary) 564 return isVMerge(N, UnitSize, 0, 16); 565 return isVMerge(N, UnitSize, 0, 0); 566} 567 568 569/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 570/// amount, otherwise return -1. 571int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 572 assert(N->getValueType(0) == MVT::v16i8 && 573 "PPC only supports shuffles by bytes!"); 574 575 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 576 577 // Find the first non-undef value in the shuffle mask. 578 unsigned i; 579 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 580 /*search*/; 581 582 if (i == 16) return -1; // all undef. 583 584 // Otherwise, check to see if the rest of the elements are consecutively 585 // numbered from this value. 586 unsigned ShiftAmt = SVOp->getMaskElt(i); 587 if (ShiftAmt < i) return -1; 588 ShiftAmt -= i; 589 590 if (!isUnary) { 591 // Check the rest of the elements to see if they are consecutive. 592 for (++i; i != 16; ++i) 593 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 594 return -1; 595 } else { 596 // Check the rest of the elements to see if they are consecutive. 597 for (++i; i != 16; ++i) 598 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 599 return -1; 600 } 601 return ShiftAmt; 602} 603 604/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 605/// specifies a splat of a single element that is suitable for input to 606/// VSPLTB/VSPLTH/VSPLTW. 607bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 608 assert(N->getValueType(0) == MVT::v16i8 && 609 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 610 611 // This is a splat operation if each element of the permute is the same, and 612 // if the value doesn't reference the second vector. 613 unsigned ElementBase = N->getMaskElt(0); 614 615 // FIXME: Handle UNDEF elements too! 616 if (ElementBase >= 16) 617 return false; 618 619 // Check that the indices are consecutive, in the case of a multi-byte element 620 // splatted with a v16i8 mask. 621 for (unsigned i = 1; i != EltSize; ++i) 622 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 623 return false; 624 625 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 626 if (N->getMaskElt(i) < 0) continue; 627 for (unsigned j = 0; j != EltSize; ++j) 628 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 629 return false; 630 } 631 return true; 632} 633 634/// isAllNegativeZeroVector - Returns true if all elements of build_vector 635/// are -0.0. 636bool PPC::isAllNegativeZeroVector(SDNode *N) { 637 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 638 639 APInt APVal, APUndef; 640 unsigned BitSize; 641 bool HasAnyUndefs; 642 643 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 644 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 645 return CFP->getValueAPF().isNegZero(); 646 647 return false; 648} 649 650/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 651/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 652unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 653 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 654 assert(isSplatShuffleMask(SVOp, EltSize)); 655 return SVOp->getMaskElt(0) / EltSize; 656} 657 658/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 659/// by using a vspltis[bhw] instruction of the specified element size, return 660/// the constant being splatted. The ByteSize field indicates the number of 661/// bytes of each element [124] -> [bhw]. 662SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 663 SDValue OpVal(0, 0); 664 665 // If ByteSize of the splat is bigger than the element size of the 666 // build_vector, then we have a case where we are checking for a splat where 667 // multiple elements of the buildvector are folded together into a single 668 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 669 unsigned EltSize = 16/N->getNumOperands(); 670 if (EltSize < ByteSize) { 671 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 672 SDValue UniquedVals[4]; 673 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 674 675 // See if all of the elements in the buildvector agree across. 676 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 677 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 678 // If the element isn't a constant, bail fully out. 679 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 680 681 682 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 683 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 684 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 685 return SDValue(); // no match. 686 } 687 688 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 689 // either constant or undef values that are identical for each chunk. See 690 // if these chunks can form into a larger vspltis*. 691 692 // Check to see if all of the leading entries are either 0 or -1. If 693 // neither, then this won't fit into the immediate field. 694 bool LeadingZero = true; 695 bool LeadingOnes = true; 696 for (unsigned i = 0; i != Multiple-1; ++i) { 697 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 698 699 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 700 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 701 } 702 // Finally, check the least significant entry. 703 if (LeadingZero) { 704 if (UniquedVals[Multiple-1].getNode() == 0) 705 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 706 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 707 if (Val < 16) 708 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 709 } 710 if (LeadingOnes) { 711 if (UniquedVals[Multiple-1].getNode() == 0) 712 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 713 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 714 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 715 return DAG.getTargetConstant(Val, MVT::i32); 716 } 717 718 return SDValue(); 719 } 720 721 // Check to see if this buildvec has a single non-undef value in its elements. 722 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 723 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 724 if (OpVal.getNode() == 0) 725 OpVal = N->getOperand(i); 726 else if (OpVal != N->getOperand(i)) 727 return SDValue(); 728 } 729 730 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 731 732 unsigned ValSizeInBytes = EltSize; 733 uint64_t Value = 0; 734 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 735 Value = CN->getZExtValue(); 736 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 737 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 738 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 739 } 740 741 // If the splat value is larger than the element value, then we can never do 742 // this splat. The only case that we could fit the replicated bits into our 743 // immediate field for would be zero, and we prefer to use vxor for it. 744 if (ValSizeInBytes < ByteSize) return SDValue(); 745 746 // If the element value is larger than the splat value, cut it in half and 747 // check to see if the two halves are equal. Continue doing this until we 748 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 749 while (ValSizeInBytes > ByteSize) { 750 ValSizeInBytes >>= 1; 751 752 // If the top half equals the bottom half, we're still ok. 753 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 754 (Value & ((1 << (8*ValSizeInBytes))-1))) 755 return SDValue(); 756 } 757 758 // Properly sign extend the value. 759 int ShAmt = (4-ByteSize)*8; 760 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 761 762 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 763 if (MaskVal == 0) return SDValue(); 764 765 // Finally, if this value fits in a 5 bit sext field, return it 766 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 767 return DAG.getTargetConstant(MaskVal, MVT::i32); 768 return SDValue(); 769} 770 771//===----------------------------------------------------------------------===// 772// Addressing Mode Selection 773//===----------------------------------------------------------------------===// 774 775/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 776/// or 64-bit immediate, and if the value can be accurately represented as a 777/// sign extension from a 16-bit value. If so, this returns true and the 778/// immediate. 779static bool isIntS16Immediate(SDNode *N, short &Imm) { 780 if (N->getOpcode() != ISD::Constant) 781 return false; 782 783 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 784 if (N->getValueType(0) == MVT::i32) 785 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 786 else 787 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 788} 789static bool isIntS16Immediate(SDValue Op, short &Imm) { 790 return isIntS16Immediate(Op.getNode(), Imm); 791} 792 793 794/// SelectAddressRegReg - Given the specified addressed, check to see if it 795/// can be represented as an indexed [r+r] operation. Returns false if it 796/// can be more efficiently represented with [r+imm]. 797bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 798 SDValue &Index, 799 SelectionDAG &DAG) const { 800 short imm = 0; 801 if (N.getOpcode() == ISD::ADD) { 802 if (isIntS16Immediate(N.getOperand(1), imm)) 803 return false; // r+i 804 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 805 return false; // r+i 806 807 Base = N.getOperand(0); 808 Index = N.getOperand(1); 809 return true; 810 } else if (N.getOpcode() == ISD::OR) { 811 if (isIntS16Immediate(N.getOperand(1), imm)) 812 return false; // r+i can fold it if we can. 813 814 // If this is an or of disjoint bitfields, we can codegen this as an add 815 // (for better address arithmetic) if the LHS and RHS of the OR are provably 816 // disjoint. 817 APInt LHSKnownZero, LHSKnownOne; 818 APInt RHSKnownZero, RHSKnownOne; 819 DAG.ComputeMaskedBits(N.getOperand(0), 820 APInt::getAllOnesValue(N.getOperand(0) 821 .getValueSizeInBits()), 822 LHSKnownZero, LHSKnownOne); 823 824 if (LHSKnownZero.getBoolValue()) { 825 DAG.ComputeMaskedBits(N.getOperand(1), 826 APInt::getAllOnesValue(N.getOperand(1) 827 .getValueSizeInBits()), 828 RHSKnownZero, RHSKnownOne); 829 // If all of the bits are known zero on the LHS or RHS, the add won't 830 // carry. 831 if (~(LHSKnownZero | RHSKnownZero) == 0) { 832 Base = N.getOperand(0); 833 Index = N.getOperand(1); 834 return true; 835 } 836 } 837 } 838 839 return false; 840} 841 842/// Returns true if the address N can be represented by a base register plus 843/// a signed 16-bit displacement [r+imm], and if it is not better 844/// represented as reg+reg. 845bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 846 SDValue &Base, 847 SelectionDAG &DAG) const { 848 // FIXME dl should come from parent load or store, not from address 849 DebugLoc dl = N.getDebugLoc(); 850 // If this can be more profitably realized as r+r, fail. 851 if (SelectAddressRegReg(N, Disp, Base, DAG)) 852 return false; 853 854 if (N.getOpcode() == ISD::ADD) { 855 short imm = 0; 856 if (isIntS16Immediate(N.getOperand(1), imm)) { 857 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 858 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 859 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 860 } else { 861 Base = N.getOperand(0); 862 } 863 return true; // [r+i] 864 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 865 // Match LOAD (ADD (X, Lo(G))). 866 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 867 && "Cannot handle constant offsets yet!"); 868 Disp = N.getOperand(1).getOperand(0); // The global address. 869 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 870 Disp.getOpcode() == ISD::TargetConstantPool || 871 Disp.getOpcode() == ISD::TargetJumpTable); 872 Base = N.getOperand(0); 873 return true; // [&g+r] 874 } 875 } else if (N.getOpcode() == ISD::OR) { 876 short imm = 0; 877 if (isIntS16Immediate(N.getOperand(1), imm)) { 878 // If this is an or of disjoint bitfields, we can codegen this as an add 879 // (for better address arithmetic) if the LHS and RHS of the OR are 880 // provably disjoint. 881 APInt LHSKnownZero, LHSKnownOne; 882 DAG.ComputeMaskedBits(N.getOperand(0), 883 APInt::getAllOnesValue(N.getOperand(0) 884 .getValueSizeInBits()), 885 LHSKnownZero, LHSKnownOne); 886 887 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 888 // If all of the bits are known zero on the LHS or RHS, the add won't 889 // carry. 890 Base = N.getOperand(0); 891 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 892 return true; 893 } 894 } 895 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 896 // Loading from a constant address. 897 898 // If this address fits entirely in a 16-bit sext immediate field, codegen 899 // this as "d, 0" 900 short Imm; 901 if (isIntS16Immediate(CN, Imm)) { 902 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 903 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 904 return true; 905 } 906 907 // Handle 32-bit sext immediates with LIS + addr mode. 908 if (CN->getValueType(0) == MVT::i32 || 909 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 910 int Addr = (int)CN->getZExtValue(); 911 912 // Otherwise, break this down into an LIS + disp. 913 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 914 915 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 916 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 917 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 918 return true; 919 } 920 } 921 922 Disp = DAG.getTargetConstant(0, getPointerTy()); 923 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 924 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 925 else 926 Base = N; 927 return true; // [r+0] 928} 929 930/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 931/// represented as an indexed [r+r] operation. 932bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 933 SDValue &Index, 934 SelectionDAG &DAG) const { 935 // Check to see if we can easily represent this as an [r+r] address. This 936 // will fail if it thinks that the address is more profitably represented as 937 // reg+imm, e.g. where imm = 0. 938 if (SelectAddressRegReg(N, Base, Index, DAG)) 939 return true; 940 941 // If the operand is an addition, always emit this as [r+r], since this is 942 // better (for code size, and execution, as the memop does the add for free) 943 // than emitting an explicit add. 944 if (N.getOpcode() == ISD::ADD) { 945 Base = N.getOperand(0); 946 Index = N.getOperand(1); 947 return true; 948 } 949 950 // Otherwise, do it the hard way, using R0 as the base register. 951 Base = DAG.getRegister(PPC::R0, N.getValueType()); 952 Index = N; 953 return true; 954} 955 956/// SelectAddressRegImmShift - Returns true if the address N can be 957/// represented by a base register plus a signed 14-bit displacement 958/// [r+imm*4]. Suitable for use by STD and friends. 959bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 960 SDValue &Base, 961 SelectionDAG &DAG) const { 962 // FIXME dl should come from the parent load or store, not the address 963 DebugLoc dl = N.getDebugLoc(); 964 // If this can be more profitably realized as r+r, fail. 965 if (SelectAddressRegReg(N, Disp, Base, DAG)) 966 return false; 967 968 if (N.getOpcode() == ISD::ADD) { 969 short imm = 0; 970 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 971 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 972 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 973 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 974 } else { 975 Base = N.getOperand(0); 976 } 977 return true; // [r+i] 978 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 979 // Match LOAD (ADD (X, Lo(G))). 980 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 981 && "Cannot handle constant offsets yet!"); 982 Disp = N.getOperand(1).getOperand(0); // The global address. 983 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 984 Disp.getOpcode() == ISD::TargetConstantPool || 985 Disp.getOpcode() == ISD::TargetJumpTable); 986 Base = N.getOperand(0); 987 return true; // [&g+r] 988 } 989 } else if (N.getOpcode() == ISD::OR) { 990 short imm = 0; 991 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 992 // If this is an or of disjoint bitfields, we can codegen this as an add 993 // (for better address arithmetic) if the LHS and RHS of the OR are 994 // provably disjoint. 995 APInt LHSKnownZero, LHSKnownOne; 996 DAG.ComputeMaskedBits(N.getOperand(0), 997 APInt::getAllOnesValue(N.getOperand(0) 998 .getValueSizeInBits()), 999 LHSKnownZero, LHSKnownOne); 1000 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1001 // If all of the bits are known zero on the LHS or RHS, the add won't 1002 // carry. 1003 Base = N.getOperand(0); 1004 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1005 return true; 1006 } 1007 } 1008 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1009 // Loading from a constant address. Verify low two bits are clear. 1010 if ((CN->getZExtValue() & 3) == 0) { 1011 // If this address fits entirely in a 14-bit sext immediate field, codegen 1012 // this as "d, 0" 1013 short Imm; 1014 if (isIntS16Immediate(CN, Imm)) { 1015 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1016 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 1017 return true; 1018 } 1019 1020 // Fold the low-part of 32-bit absolute addresses into addr mode. 1021 if (CN->getValueType(0) == MVT::i32 || 1022 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1023 int Addr = (int)CN->getZExtValue(); 1024 1025 // Otherwise, break this down into an LIS + disp. 1026 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1027 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1028 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1029 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1030 return true; 1031 } 1032 } 1033 } 1034 1035 Disp = DAG.getTargetConstant(0, getPointerTy()); 1036 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1037 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1038 else 1039 Base = N; 1040 return true; // [r+0] 1041} 1042 1043 1044/// getPreIndexedAddressParts - returns true by value, base pointer and 1045/// offset pointer and addressing mode by reference if the node's address 1046/// can be legally represented as pre-indexed load / store address. 1047bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1048 SDValue &Offset, 1049 ISD::MemIndexedMode &AM, 1050 SelectionDAG &DAG) const { 1051 // Disabled by default for now. 1052 if (!EnablePPCPreinc) return false; 1053 1054 SDValue Ptr; 1055 EVT VT; 1056 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1057 Ptr = LD->getBasePtr(); 1058 VT = LD->getMemoryVT(); 1059 1060 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1061 ST = ST; 1062 Ptr = ST->getBasePtr(); 1063 VT = ST->getMemoryVT(); 1064 } else 1065 return false; 1066 1067 // PowerPC doesn't have preinc load/store instructions for vectors. 1068 if (VT.isVector()) 1069 return false; 1070 1071 // TODO: Check reg+reg first. 1072 1073 // LDU/STU use reg+imm*4, others use reg+imm. 1074 if (VT != MVT::i64) { 1075 // reg + imm 1076 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1077 return false; 1078 } else { 1079 // reg + imm * 4. 1080 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1081 return false; 1082 } 1083 1084 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1085 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1086 // sext i32 to i64 when addr mode is r+i. 1087 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1088 LD->getExtensionType() == ISD::SEXTLOAD && 1089 isa<ConstantSDNode>(Offset)) 1090 return false; 1091 } 1092 1093 AM = ISD::PRE_INC; 1094 return true; 1095} 1096 1097//===----------------------------------------------------------------------===// 1098// LowerOperation implementation 1099//===----------------------------------------------------------------------===// 1100 1101SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1102 SelectionDAG &DAG) const { 1103 EVT PtrVT = Op.getValueType(); 1104 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1105 const Constant *C = CP->getConstVal(); 1106 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1107 SDValue Zero = DAG.getConstant(0, PtrVT); 1108 // FIXME there isn't really any debug info here 1109 DebugLoc dl = Op.getDebugLoc(); 1110 1111 const TargetMachine &TM = DAG.getTarget(); 1112 1113 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero); 1114 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero); 1115 1116 // If this is a non-darwin platform, we don't support non-static relo models 1117 // yet. 1118 if (TM.getRelocationModel() == Reloc::Static || 1119 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1120 // Generate non-pic code that has direct accesses to the constant pool. 1121 // The address of the global is just (hi(&g)+lo(&g)). 1122 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1123 } 1124 1125 if (TM.getRelocationModel() == Reloc::PIC_) { 1126 // With PIC, the first instruction is actually "GR+hi(&G)". 1127 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1128 DAG.getNode(PPCISD::GlobalBaseReg, 1129 DebugLoc(), PtrVT), Hi); 1130 } 1131 1132 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1133 return Lo; 1134} 1135 1136SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1137 EVT PtrVT = Op.getValueType(); 1138 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1139 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1140 SDValue Zero = DAG.getConstant(0, PtrVT); 1141 // FIXME there isn't really any debug loc here 1142 DebugLoc dl = Op.getDebugLoc(); 1143 1144 const TargetMachine &TM = DAG.getTarget(); 1145 1146 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero); 1147 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero); 1148 1149 // If this is a non-darwin platform, we don't support non-static relo models 1150 // yet. 1151 if (TM.getRelocationModel() == Reloc::Static || 1152 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1153 // Generate non-pic code that has direct accesses to the constant pool. 1154 // The address of the global is just (hi(&g)+lo(&g)). 1155 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1156 } 1157 1158 if (TM.getRelocationModel() == Reloc::PIC_) { 1159 // With PIC, the first instruction is actually "GR+hi(&G)". 1160 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1161 DAG.getNode(PPCISD::GlobalBaseReg, 1162 DebugLoc(), PtrVT), Hi); 1163 } 1164 1165 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1166 return Lo; 1167} 1168 1169SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1170 SelectionDAG &DAG) const { 1171 llvm_unreachable("TLS not implemented for PPC."); 1172 return SDValue(); // Not reached 1173} 1174 1175SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1176 SelectionDAG &DAG) const { 1177 EVT PtrVT = Op.getValueType(); 1178 DebugLoc DL = Op.getDebugLoc(); 1179 1180 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1181 SDValue TgtBA = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true); 1182 SDValue Zero = DAG.getConstant(0, PtrVT); 1183 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero); 1184 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero); 1185 1186 // If this is a non-darwin platform, we don't support non-static relo models 1187 // yet. 1188 const TargetMachine &TM = DAG.getTarget(); 1189 if (TM.getRelocationModel() == Reloc::Static || 1190 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1191 // Generate non-pic code that has direct accesses to globals. 1192 // The address of the global is just (hi(&g)+lo(&g)). 1193 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1194 } 1195 1196 if (TM.getRelocationModel() == Reloc::PIC_) { 1197 // With PIC, the first instruction is actually "GR+hi(&G)". 1198 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1199 DAG.getNode(PPCISD::GlobalBaseReg, 1200 DebugLoc(), PtrVT), Hi); 1201 } 1202 1203 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1204} 1205 1206SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1207 SelectionDAG &DAG) const { 1208 EVT PtrVT = Op.getValueType(); 1209 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1210 // FIXME there isn't really any debug info here 1211 DebugLoc dl = GSDN->getDebugLoc(); 1212 const GlobalValue *GV = GSDN->getGlobal(); 1213 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, GSDN->getOffset()); 1214 SDValue Zero = DAG.getConstant(0, PtrVT); 1215 1216 const TargetMachine &TM = DAG.getTarget(); 1217 1218 // 64-bit SVR4 ABI code is always position-independent. 1219 // The actual address of the GlobalValue is stored in the TOC. 1220 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1221 return DAG.getNode(PPCISD::TOC_ENTRY, dl, MVT::i64, GA, 1222 DAG.getRegister(PPC::X2, MVT::i64)); 1223 } 1224 1225 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero); 1226 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero); 1227 1228 // If this is a non-darwin platform, we don't support non-static relo models 1229 // yet. 1230 if (TM.getRelocationModel() == Reloc::Static || 1231 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1232 // Generate non-pic code that has direct accesses to globals. 1233 // The address of the global is just (hi(&g)+lo(&g)). 1234 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1235 } 1236 1237 if (TM.getRelocationModel() == Reloc::PIC_) { 1238 // With PIC, the first instruction is actually "GR+hi(&G)". 1239 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1240 DAG.getNode(PPCISD::GlobalBaseReg, 1241 DebugLoc(), PtrVT), Hi); 1242 } 1243 1244 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1245 1246 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) 1247 return Lo; 1248 1249 // If the global is weak or external, we have to go through the lazy 1250 // resolution stub. 1251 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, MachinePointerInfo(), 1252 false, false, 0); 1253} 1254 1255SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1256 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1257 DebugLoc dl = Op.getDebugLoc(); 1258 1259 // If we're comparing for equality to zero, expose the fact that this is 1260 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1261 // fold the new nodes. 1262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1263 if (C->isNullValue() && CC == ISD::SETEQ) { 1264 EVT VT = Op.getOperand(0).getValueType(); 1265 SDValue Zext = Op.getOperand(0); 1266 if (VT.bitsLT(MVT::i32)) { 1267 VT = MVT::i32; 1268 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1269 } 1270 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1271 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1272 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1273 DAG.getConstant(Log2b, MVT::i32)); 1274 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1275 } 1276 // Leave comparisons against 0 and -1 alone for now, since they're usually 1277 // optimized. FIXME: revisit this when we can custom lower all setcc 1278 // optimizations. 1279 if (C->isAllOnesValue() || C->isNullValue()) 1280 return SDValue(); 1281 } 1282 1283 // If we have an integer seteq/setne, turn it into a compare against zero 1284 // by xor'ing the rhs with the lhs, which is faster than setting a 1285 // condition register, reading it back out, and masking the correct bit. The 1286 // normal approach here uses sub to do this instead of xor. Using xor exposes 1287 // the result to other bit-twiddling opportunities. 1288 EVT LHSVT = Op.getOperand(0).getValueType(); 1289 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1290 EVT VT = Op.getValueType(); 1291 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1292 Op.getOperand(1)); 1293 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1294 } 1295 return SDValue(); 1296} 1297 1298SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1299 const PPCSubtarget &Subtarget) const { 1300 1301 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!"); 1302 return SDValue(); // Not reached 1303} 1304 1305SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, 1306 SelectionDAG &DAG) const { 1307 SDValue Chain = Op.getOperand(0); 1308 SDValue Trmp = Op.getOperand(1); // trampoline 1309 SDValue FPtr = Op.getOperand(2); // nested function 1310 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1311 DebugLoc dl = Op.getDebugLoc(); 1312 1313 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1314 bool isPPC64 = (PtrVT == MVT::i64); 1315 const Type *IntPtrTy = 1316 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType( 1317 *DAG.getContext()); 1318 1319 TargetLowering::ArgListTy Args; 1320 TargetLowering::ArgListEntry Entry; 1321 1322 Entry.Ty = IntPtrTy; 1323 Entry.Node = Trmp; Args.push_back(Entry); 1324 1325 // TrampSize == (isPPC64 ? 48 : 40); 1326 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1327 isPPC64 ? MVT::i64 : MVT::i32); 1328 Args.push_back(Entry); 1329 1330 Entry.Node = FPtr; Args.push_back(Entry); 1331 Entry.Node = Nest; Args.push_back(Entry); 1332 1333 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1334 std::pair<SDValue, SDValue> CallResult = 1335 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()), 1336 false, false, false, false, 0, CallingConv::C, false, 1337 /*isReturnValueUsed=*/true, 1338 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1339 Args, DAG, dl); 1340 1341 SDValue Ops[] = 1342 { CallResult.first, CallResult.second }; 1343 1344 return DAG.getMergeValues(Ops, 2, dl); 1345} 1346 1347SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1348 const PPCSubtarget &Subtarget) const { 1349 MachineFunction &MF = DAG.getMachineFunction(); 1350 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1351 1352 DebugLoc dl = Op.getDebugLoc(); 1353 1354 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1355 // vastart just stores the address of the VarArgsFrameIndex slot into the 1356 // memory location argument. 1357 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1358 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1359 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1360 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 1361 MachinePointerInfo(SV), 1362 false, false, 0); 1363 } 1364 1365 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1366 // We suppose the given va_list is already allocated. 1367 // 1368 // typedef struct { 1369 // char gpr; /* index into the array of 8 GPRs 1370 // * stored in the register save area 1371 // * gpr=0 corresponds to r3, 1372 // * gpr=1 to r4, etc. 1373 // */ 1374 // char fpr; /* index into the array of 8 FPRs 1375 // * stored in the register save area 1376 // * fpr=0 corresponds to f1, 1377 // * fpr=1 to f2, etc. 1378 // */ 1379 // char *overflow_arg_area; 1380 // /* location on stack that holds 1381 // * the next overflow argument 1382 // */ 1383 // char *reg_save_area; 1384 // /* where r3:r10 and f1:f8 (if saved) 1385 // * are stored 1386 // */ 1387 // } va_list[1]; 1388 1389 1390 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1391 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1392 1393 1394 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1395 1396 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1397 PtrVT); 1398 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1399 PtrVT); 1400 1401 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1402 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1403 1404 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1405 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1406 1407 uint64_t FPROffset = 1; 1408 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1409 1410 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1411 1412 // Store first byte : number of int regs 1413 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1414 Op.getOperand(1), 1415 MachinePointerInfo(SV), 1416 MVT::i8, false, false, 0); 1417 uint64_t nextOffset = FPROffset; 1418 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1419 ConstFPROffset); 1420 1421 // Store second byte : number of float regs 1422 SDValue secondStore = 1423 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, 1424 MachinePointerInfo(SV, nextOffset), MVT::i8, 1425 false, false, 0); 1426 nextOffset += StackOffset; 1427 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1428 1429 // Store second word : arguments given on stack 1430 SDValue thirdStore = 1431 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, 1432 MachinePointerInfo(SV, nextOffset), 1433 false, false, 0); 1434 nextOffset += FrameOffset; 1435 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1436 1437 // Store third word : arguments given in registers 1438 return DAG.getStore(thirdStore, dl, FR, nextPtr, 1439 MachinePointerInfo(SV, nextOffset), 1440 false, false, 0); 1441 1442} 1443 1444#include "PPCGenCallingConv.inc" 1445 1446static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 1447 CCValAssign::LocInfo &LocInfo, 1448 ISD::ArgFlagsTy &ArgFlags, 1449 CCState &State) { 1450 return true; 1451} 1452 1453static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, 1454 EVT &LocVT, 1455 CCValAssign::LocInfo &LocInfo, 1456 ISD::ArgFlagsTy &ArgFlags, 1457 CCState &State) { 1458 static const unsigned ArgRegs[] = { 1459 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1460 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1461 }; 1462 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1463 1464 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1465 1466 // Skip one register if the first unallocated register has an even register 1467 // number and there are still argument registers available which have not been 1468 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1469 // need to skip a register if RegNum is odd. 1470 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1471 State.AllocateReg(ArgRegs[RegNum]); 1472 } 1473 1474 // Always return false here, as this function only makes sure that the first 1475 // unallocated register has an odd register number and does not actually 1476 // allocate a register for the current argument. 1477 return false; 1478} 1479 1480static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, 1481 EVT &LocVT, 1482 CCValAssign::LocInfo &LocInfo, 1483 ISD::ArgFlagsTy &ArgFlags, 1484 CCState &State) { 1485 static const unsigned ArgRegs[] = { 1486 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1487 PPC::F8 1488 }; 1489 1490 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1491 1492 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1493 1494 // If there is only one Floating-point register left we need to put both f64 1495 // values of a split ppc_fp128 value on the stack. 1496 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1497 State.AllocateReg(ArgRegs[RegNum]); 1498 } 1499 1500 // Always return false here, as this function only makes sure that the two f64 1501 // values a ppc_fp128 value is split into are both passed in registers or both 1502 // passed on the stack and does not actually allocate a register for the 1503 // current argument. 1504 return false; 1505} 1506 1507/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1508/// on Darwin. 1509static const unsigned *GetFPR() { 1510 static const unsigned FPR[] = { 1511 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1512 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1513 }; 1514 1515 return FPR; 1516} 1517 1518/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1519/// the stack. 1520static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1521 unsigned PtrByteSize) { 1522 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1523 if (Flags.isByVal()) 1524 ArgSize = Flags.getByValSize(); 1525 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1526 1527 return ArgSize; 1528} 1529 1530SDValue 1531PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1532 CallingConv::ID CallConv, bool isVarArg, 1533 const SmallVectorImpl<ISD::InputArg> 1534 &Ins, 1535 DebugLoc dl, SelectionDAG &DAG, 1536 SmallVectorImpl<SDValue> &InVals) 1537 const { 1538 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 1539 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins, 1540 dl, DAG, InVals); 1541 } else { 1542 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1543 dl, DAG, InVals); 1544 } 1545} 1546 1547SDValue 1548PPCTargetLowering::LowerFormalArguments_SVR4( 1549 SDValue Chain, 1550 CallingConv::ID CallConv, bool isVarArg, 1551 const SmallVectorImpl<ISD::InputArg> 1552 &Ins, 1553 DebugLoc dl, SelectionDAG &DAG, 1554 SmallVectorImpl<SDValue> &InVals) const { 1555 1556 // 32-bit SVR4 ABI Stack Frame Layout: 1557 // +-----------------------------------+ 1558 // +--> | Back chain | 1559 // | +-----------------------------------+ 1560 // | | Floating-point register save area | 1561 // | +-----------------------------------+ 1562 // | | General register save area | 1563 // | +-----------------------------------+ 1564 // | | CR save word | 1565 // | +-----------------------------------+ 1566 // | | VRSAVE save word | 1567 // | +-----------------------------------+ 1568 // | | Alignment padding | 1569 // | +-----------------------------------+ 1570 // | | Vector register save area | 1571 // | +-----------------------------------+ 1572 // | | Local variable space | 1573 // | +-----------------------------------+ 1574 // | | Parameter list area | 1575 // | +-----------------------------------+ 1576 // | | LR save word | 1577 // | +-----------------------------------+ 1578 // SP--> +--- | Back chain | 1579 // +-----------------------------------+ 1580 // 1581 // Specifications: 1582 // System V Application Binary Interface PowerPC Processor Supplement 1583 // AltiVec Technology Programming Interface Manual 1584 1585 MachineFunction &MF = DAG.getMachineFunction(); 1586 MachineFrameInfo *MFI = MF.getFrameInfo(); 1587 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1588 1589 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1590 // Potential tail calls could cause overwriting of argument stack slots. 1591 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1592 unsigned PtrByteSize = 4; 1593 1594 // Assign locations to all of the incoming arguments. 1595 SmallVector<CCValAssign, 16> ArgLocs; 1596 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1597 *DAG.getContext()); 1598 1599 // Reserve space for the linkage area on the stack. 1600 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); 1601 1602 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); 1603 1604 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1605 CCValAssign &VA = ArgLocs[i]; 1606 1607 // Arguments stored in registers. 1608 if (VA.isRegLoc()) { 1609 TargetRegisterClass *RC; 1610 EVT ValVT = VA.getValVT(); 1611 1612 switch (ValVT.getSimpleVT().SimpleTy) { 1613 default: 1614 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1615 case MVT::i32: 1616 RC = PPC::GPRCRegisterClass; 1617 break; 1618 case MVT::f32: 1619 RC = PPC::F4RCRegisterClass; 1620 break; 1621 case MVT::f64: 1622 RC = PPC::F8RCRegisterClass; 1623 break; 1624 case MVT::v16i8: 1625 case MVT::v8i16: 1626 case MVT::v4i32: 1627 case MVT::v4f32: 1628 RC = PPC::VRRCRegisterClass; 1629 break; 1630 } 1631 1632 // Transform the arguments stored in physical registers into virtual ones. 1633 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1634 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1635 1636 InVals.push_back(ArgValue); 1637 } else { 1638 // Argument stored in memory. 1639 assert(VA.isMemLoc()); 1640 1641 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1642 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1643 isImmutable); 1644 1645 // Create load nodes to retrieve arguments from the stack. 1646 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1647 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1648 MachinePointerInfo(), 1649 false, false, 0)); 1650 } 1651 } 1652 1653 // Assign locations to all of the incoming aggregate by value arguments. 1654 // Aggregates passed by value are stored in the local variable space of the 1655 // caller's stack frame, right above the parameter list area. 1656 SmallVector<CCValAssign, 16> ByValArgLocs; 1657 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), 1658 ByValArgLocs, *DAG.getContext()); 1659 1660 // Reserve stack space for the allocations in CCInfo. 1661 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1662 1663 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal); 1664 1665 // Area that is at least reserved in the caller of this function. 1666 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1667 1668 // Set the size that is at least reserved in caller of this function. Tail 1669 // call optimized function's reserved stack space needs to be aligned so that 1670 // taking the difference between two stack areas will result in an aligned 1671 // stack. 1672 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1673 1674 MinReservedArea = 1675 std::max(MinReservedArea, 1676 PPCFrameInfo::getMinCallFrameSize(false, false)); 1677 1678 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 1679 getStackAlignment(); 1680 unsigned AlignMask = TargetAlign-1; 1681 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1682 1683 FI->setMinReservedArea(MinReservedArea); 1684 1685 SmallVector<SDValue, 8> MemOps; 1686 1687 // If the function takes variable number of arguments, make a frame index for 1688 // the start of the first vararg value... for expansion of llvm.va_start. 1689 if (isVarArg) { 1690 static const unsigned GPArgRegs[] = { 1691 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1692 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1693 }; 1694 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 1695 1696 static const unsigned FPArgRegs[] = { 1697 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1698 PPC::F8 1699 }; 1700 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 1701 1702 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 1703 NumGPArgRegs)); 1704 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 1705 NumFPArgRegs)); 1706 1707 // Make room for NumGPArgRegs and NumFPArgRegs. 1708 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 1709 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 1710 1711 FuncInfo->setVarArgsStackOffset( 1712 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1713 CCInfo.getNextStackOffset(), true)); 1714 1715 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 1716 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1717 1718 // The fixed integer arguments of a variadic function are stored to the 1719 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing 1720 // the result of va_next. 1721 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) { 1722 // Get an existing live-in vreg, or add a new one. 1723 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); 1724 if (!VReg) 1725 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 1726 1727 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1728 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1729 MachinePointerInfo(), false, false, 0); 1730 MemOps.push_back(Store); 1731 // Increment the address by four for the next argument to store 1732 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1733 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1734 } 1735 1736 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 1737 // is set. 1738 // The double arguments are stored to the VarArgsFrameIndex 1739 // on the stack. 1740 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) { 1741 // Get an existing live-in vreg, or add a new one. 1742 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); 1743 if (!VReg) 1744 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 1745 1746 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 1747 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1748 MachinePointerInfo(), false, false, 0); 1749 MemOps.push_back(Store); 1750 // Increment the address by eight for the next argument to store 1751 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1752 PtrVT); 1753 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1754 } 1755 } 1756 1757 if (!MemOps.empty()) 1758 Chain = DAG.getNode(ISD::TokenFactor, dl, 1759 MVT::Other, &MemOps[0], MemOps.size()); 1760 1761 return Chain; 1762} 1763 1764SDValue 1765PPCTargetLowering::LowerFormalArguments_Darwin( 1766 SDValue Chain, 1767 CallingConv::ID CallConv, bool isVarArg, 1768 const SmallVectorImpl<ISD::InputArg> 1769 &Ins, 1770 DebugLoc dl, SelectionDAG &DAG, 1771 SmallVectorImpl<SDValue> &InVals) const { 1772 // TODO: add description of PPC stack frame format, or at least some docs. 1773 // 1774 MachineFunction &MF = DAG.getMachineFunction(); 1775 MachineFrameInfo *MFI = MF.getFrameInfo(); 1776 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1777 1778 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1779 bool isPPC64 = PtrVT == MVT::i64; 1780 // Potential tail calls could cause overwriting of argument stack slots. 1781 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1782 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1783 1784 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); 1785 // Area that is at least reserved in caller of this function. 1786 unsigned MinReservedArea = ArgOffset; 1787 1788 static const unsigned GPR_32[] = { // 32-bit registers. 1789 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1790 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1791 }; 1792 static const unsigned GPR_64[] = { // 64-bit registers. 1793 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1794 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1795 }; 1796 1797 static const unsigned *FPR = GetFPR(); 1798 1799 static const unsigned VR[] = { 1800 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1801 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1802 }; 1803 1804 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1805 const unsigned Num_FPR_Regs = 13; 1806 const unsigned Num_VR_Regs = array_lengthof( VR); 1807 1808 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1809 1810 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1811 1812 // In 32-bit non-varargs functions, the stack space for vectors is after the 1813 // stack space for non-vectors. We do not use this space unless we have 1814 // too many vectors to fit in registers, something that only occurs in 1815 // constructed examples:), but we have to walk the arglist to figure 1816 // that out...for the pathological case, compute VecArgOffset as the 1817 // start of the vector parameter area. Computing VecArgOffset is the 1818 // entire point of the following loop. 1819 unsigned VecArgOffset = ArgOffset; 1820 if (!isVarArg && !isPPC64) { 1821 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 1822 ++ArgNo) { 1823 EVT ObjectVT = Ins[ArgNo].VT; 1824 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1825 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1826 1827 if (Flags.isByVal()) { 1828 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 1829 ObjSize = Flags.getByValSize(); 1830 unsigned ArgSize = 1831 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1832 VecArgOffset += ArgSize; 1833 continue; 1834 } 1835 1836 switch(ObjectVT.getSimpleVT().SimpleTy) { 1837 default: llvm_unreachable("Unhandled argument type!"); 1838 case MVT::i32: 1839 case MVT::f32: 1840 VecArgOffset += isPPC64 ? 8 : 4; 1841 break; 1842 case MVT::i64: // PPC64 1843 case MVT::f64: 1844 VecArgOffset += 8; 1845 break; 1846 case MVT::v4f32: 1847 case MVT::v4i32: 1848 case MVT::v8i16: 1849 case MVT::v16i8: 1850 // Nothing to do, we're only looking at Nonvector args here. 1851 break; 1852 } 1853 } 1854 } 1855 // We've found where the vector parameter area in memory is. Skip the 1856 // first 12 parameters; these don't use that memory. 1857 VecArgOffset = ((VecArgOffset+15)/16)*16; 1858 VecArgOffset += 12*16; 1859 1860 // Add DAG nodes to load the arguments or copy them out of registers. On 1861 // entry to a function on PPC, the arguments start after the linkage area, 1862 // although the first ones are often in registers. 1863 1864 SmallVector<SDValue, 8> MemOps; 1865 unsigned nAltivecParamsAtEnd = 0; 1866 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 1867 SDValue ArgVal; 1868 bool needsLoad = false; 1869 EVT ObjectVT = Ins[ArgNo].VT; 1870 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1871 unsigned ArgSize = ObjSize; 1872 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1873 1874 unsigned CurArgOffset = ArgOffset; 1875 1876 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 1877 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 1878 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 1879 if (isVarArg || isPPC64) { 1880 MinReservedArea = ((MinReservedArea+15)/16)*16; 1881 MinReservedArea += CalculateStackSlotSize(ObjectVT, 1882 Flags, 1883 PtrByteSize); 1884 } else nAltivecParamsAtEnd++; 1885 } else 1886 // Calculate min reserved area. 1887 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 1888 Flags, 1889 PtrByteSize); 1890 1891 // FIXME the codegen can be much improved in some cases. 1892 // We do not have to keep everything in memory. 1893 if (Flags.isByVal()) { 1894 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1895 ObjSize = Flags.getByValSize(); 1896 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1897 // Objects of size 1 and 2 are right justified, everything else is 1898 // left justified. This means the memory address is adjusted forwards. 1899 if (ObjSize==1 || ObjSize==2) { 1900 CurArgOffset = CurArgOffset + (4 - ObjSize); 1901 } 1902 // The value of the object is its address. 1903 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 1904 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1905 InVals.push_back(FIN); 1906 if (ObjSize==1 || ObjSize==2) { 1907 if (GPR_idx != Num_GPR_Regs) { 1908 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1909 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1910 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 1911 MachinePointerInfo(), 1912 ObjSize==1 ? MVT::i8 : MVT::i16, 1913 false, false, 0); 1914 MemOps.push_back(Store); 1915 ++GPR_idx; 1916 } 1917 1918 ArgOffset += PtrByteSize; 1919 1920 continue; 1921 } 1922 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 1923 // Store whatever pieces of the object are in registers 1924 // to memory. ArgVal will be address of the beginning of 1925 // the object. 1926 if (GPR_idx != Num_GPR_Regs) { 1927 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1928 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 1929 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1930 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1931 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1932 MachinePointerInfo(), 1933 false, false, 0); 1934 MemOps.push_back(Store); 1935 ++GPR_idx; 1936 ArgOffset += PtrByteSize; 1937 } else { 1938 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 1939 break; 1940 } 1941 } 1942 continue; 1943 } 1944 1945 switch (ObjectVT.getSimpleVT().SimpleTy) { 1946 default: llvm_unreachable("Unhandled argument type!"); 1947 case MVT::i32: 1948 if (!isPPC64) { 1949 if (GPR_idx != Num_GPR_Regs) { 1950 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1951 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 1952 ++GPR_idx; 1953 } else { 1954 needsLoad = true; 1955 ArgSize = PtrByteSize; 1956 } 1957 // All int arguments reserve stack space in the Darwin ABI. 1958 ArgOffset += PtrByteSize; 1959 break; 1960 } 1961 // FALLTHROUGH 1962 case MVT::i64: // PPC64 1963 if (GPR_idx != Num_GPR_Regs) { 1964 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 1965 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1966 1967 if (ObjectVT == MVT::i32) { 1968 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 1969 // value to MVT::i64 and then truncate to the correct register size. 1970 if (Flags.isSExt()) 1971 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 1972 DAG.getValueType(ObjectVT)); 1973 else if (Flags.isZExt()) 1974 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 1975 DAG.getValueType(ObjectVT)); 1976 1977 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 1978 } 1979 1980 ++GPR_idx; 1981 } else { 1982 needsLoad = true; 1983 ArgSize = PtrByteSize; 1984 } 1985 // All int arguments reserve stack space in the Darwin ABI. 1986 ArgOffset += 8; 1987 break; 1988 1989 case MVT::f32: 1990 case MVT::f64: 1991 // Every 4 bytes of argument space consumes one of the GPRs available for 1992 // argument passing. 1993 if (GPR_idx != Num_GPR_Regs) { 1994 ++GPR_idx; 1995 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1996 ++GPR_idx; 1997 } 1998 if (FPR_idx != Num_FPR_Regs) { 1999 unsigned VReg; 2000 2001 if (ObjectVT == MVT::f32) 2002 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2003 else 2004 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2005 2006 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2007 ++FPR_idx; 2008 } else { 2009 needsLoad = true; 2010 } 2011 2012 // All FP arguments reserve stack space in the Darwin ABI. 2013 ArgOffset += isPPC64 ? 8 : ObjSize; 2014 break; 2015 case MVT::v4f32: 2016 case MVT::v4i32: 2017 case MVT::v8i16: 2018 case MVT::v16i8: 2019 // Note that vector arguments in registers don't reserve stack space, 2020 // except in varargs functions. 2021 if (VR_idx != Num_VR_Regs) { 2022 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2023 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2024 if (isVarArg) { 2025 while ((ArgOffset % 16) != 0) { 2026 ArgOffset += PtrByteSize; 2027 if (GPR_idx != Num_GPR_Regs) 2028 GPR_idx++; 2029 } 2030 ArgOffset += 16; 2031 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2032 } 2033 ++VR_idx; 2034 } else { 2035 if (!isVarArg && !isPPC64) { 2036 // Vectors go after all the nonvectors. 2037 CurArgOffset = VecArgOffset; 2038 VecArgOffset += 16; 2039 } else { 2040 // Vectors are aligned. 2041 ArgOffset = ((ArgOffset+15)/16)*16; 2042 CurArgOffset = ArgOffset; 2043 ArgOffset += 16; 2044 } 2045 needsLoad = true; 2046 } 2047 break; 2048 } 2049 2050 // We need to load the argument to a virtual register if we determined above 2051 // that we ran out of physical registers of the appropriate type. 2052 if (needsLoad) { 2053 int FI = MFI->CreateFixedObject(ObjSize, 2054 CurArgOffset + (ArgSize - ObjSize), 2055 isImmutable); 2056 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2057 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2058 false, false, 0); 2059 } 2060 2061 InVals.push_back(ArgVal); 2062 } 2063 2064 // Set the size that is at least reserved in caller of this function. Tail 2065 // call optimized function's reserved stack space needs to be aligned so that 2066 // taking the difference between two stack areas will result in an aligned 2067 // stack. 2068 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2069 // Add the Altivec parameters at the end, if needed. 2070 if (nAltivecParamsAtEnd) { 2071 MinReservedArea = ((MinReservedArea+15)/16)*16; 2072 MinReservedArea += 16*nAltivecParamsAtEnd; 2073 } 2074 MinReservedArea = 2075 std::max(MinReservedArea, 2076 PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); 2077 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 2078 getStackAlignment(); 2079 unsigned AlignMask = TargetAlign-1; 2080 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2081 FI->setMinReservedArea(MinReservedArea); 2082 2083 // If the function takes variable number of arguments, make a frame index for 2084 // the start of the first vararg value... for expansion of llvm.va_start. 2085 if (isVarArg) { 2086 int Depth = ArgOffset; 2087 2088 FuncInfo->setVarArgsFrameIndex( 2089 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2090 Depth, true)); 2091 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2092 2093 // If this function is vararg, store any remaining integer argument regs 2094 // to their spots on the stack so that they may be loaded by deferencing the 2095 // result of va_next. 2096 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2097 unsigned VReg; 2098 2099 if (isPPC64) 2100 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2101 else 2102 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2103 2104 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2105 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2106 MachinePointerInfo(), false, false, 0); 2107 MemOps.push_back(Store); 2108 // Increment the address by four for the next argument to store 2109 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2110 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2111 } 2112 } 2113 2114 if (!MemOps.empty()) 2115 Chain = DAG.getNode(ISD::TokenFactor, dl, 2116 MVT::Other, &MemOps[0], MemOps.size()); 2117 2118 return Chain; 2119} 2120 2121/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus 2122/// linkage area for the Darwin ABI. 2123static unsigned 2124CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2125 bool isPPC64, 2126 bool isVarArg, 2127 unsigned CC, 2128 const SmallVectorImpl<ISD::OutputArg> 2129 &Outs, 2130 const SmallVectorImpl<SDValue> &OutVals, 2131 unsigned &nAltivecParamsAtEnd) { 2132 // Count how many bytes are to be pushed on the stack, including the linkage 2133 // area, and parameter passing area. We start with 24/48 bytes, which is 2134 // prereserved space for [SP][CR][LR][3 x unused]. 2135 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true); 2136 unsigned NumOps = Outs.size(); 2137 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2138 2139 // Add up all the space actually used. 2140 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2141 // they all go in registers, but we must reserve stack space for them for 2142 // possible use by the caller. In varargs or 64-bit calls, parameters are 2143 // assigned stack space in order, with padding so Altivec parameters are 2144 // 16-byte aligned. 2145 nAltivecParamsAtEnd = 0; 2146 for (unsigned i = 0; i != NumOps; ++i) { 2147 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2148 EVT ArgVT = Outs[i].VT; 2149 // Varargs Altivec parameters are padded to a 16 byte boundary. 2150 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2151 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2152 if (!isVarArg && !isPPC64) { 2153 // Non-varargs Altivec parameters go after all the non-Altivec 2154 // parameters; handle those later so we know how much padding we need. 2155 nAltivecParamsAtEnd++; 2156 continue; 2157 } 2158 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2159 NumBytes = ((NumBytes+15)/16)*16; 2160 } 2161 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2162 } 2163 2164 // Allow for Altivec parameters at the end, if needed. 2165 if (nAltivecParamsAtEnd) { 2166 NumBytes = ((NumBytes+15)/16)*16; 2167 NumBytes += 16*nAltivecParamsAtEnd; 2168 } 2169 2170 // The prolog code of the callee may store up to 8 GPR argument registers to 2171 // the stack, allowing va_start to index over them in memory if its varargs. 2172 // Because we cannot tell if this is needed on the caller side, we have to 2173 // conservatively assume that it is needed. As such, make sure we have at 2174 // least enough stack space for the caller to store the 8 GPRs. 2175 NumBytes = std::max(NumBytes, 2176 PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); 2177 2178 // Tail call needs the stack to be aligned. 2179 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) { 2180 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 2181 getStackAlignment(); 2182 unsigned AlignMask = TargetAlign-1; 2183 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2184 } 2185 2186 return NumBytes; 2187} 2188 2189/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2190/// adjusted to accomodate the arguments for the tailcall. 2191static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2192 unsigned ParamSize) { 2193 2194 if (!isTailCall) return 0; 2195 2196 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2197 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2198 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2199 // Remember only if the new adjustement is bigger. 2200 if (SPDiff < FI->getTailCallSPDelta()) 2201 FI->setTailCallSPDelta(SPDiff); 2202 2203 return SPDiff; 2204} 2205 2206/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2207/// for tail call optimization. Targets which want to do tail call 2208/// optimization should implement this function. 2209bool 2210PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2211 CallingConv::ID CalleeCC, 2212 bool isVarArg, 2213 const SmallVectorImpl<ISD::InputArg> &Ins, 2214 SelectionDAG& DAG) const { 2215 if (!GuaranteedTailCallOpt) 2216 return false; 2217 2218 // Variable argument functions are not supported. 2219 if (isVarArg) 2220 return false; 2221 2222 MachineFunction &MF = DAG.getMachineFunction(); 2223 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2224 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2225 // Functions containing by val parameters are not supported. 2226 for (unsigned i = 0; i != Ins.size(); i++) { 2227 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2228 if (Flags.isByVal()) return false; 2229 } 2230 2231 // Non PIC/GOT tail calls are supported. 2232 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2233 return true; 2234 2235 // At the moment we can only do local tail calls (in same module, hidden 2236 // or protected) if we are generating PIC. 2237 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2238 return G->getGlobal()->hasHiddenVisibility() 2239 || G->getGlobal()->hasProtectedVisibility(); 2240 } 2241 2242 return false; 2243} 2244 2245/// isCallCompatibleAddress - Return the immediate to use if the specified 2246/// 32-bit value is representable in the immediate field of a BxA instruction. 2247static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2248 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2249 if (!C) return 0; 2250 2251 int Addr = C->getZExtValue(); 2252 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2253 (Addr << 6 >> 6) != Addr) 2254 return 0; // Top 6 bits have to be sext of immediate. 2255 2256 return DAG.getConstant((int)C->getZExtValue() >> 2, 2257 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2258} 2259 2260namespace { 2261 2262struct TailCallArgumentInfo { 2263 SDValue Arg; 2264 SDValue FrameIdxOp; 2265 int FrameIdx; 2266 2267 TailCallArgumentInfo() : FrameIdx(0) {} 2268}; 2269 2270} 2271 2272/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2273static void 2274StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2275 SDValue Chain, 2276 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2277 SmallVector<SDValue, 8> &MemOpChains, 2278 DebugLoc dl) { 2279 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2280 SDValue Arg = TailCallArgs[i].Arg; 2281 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2282 int FI = TailCallArgs[i].FrameIdx; 2283 // Store relative to framepointer. 2284 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2285 MachinePointerInfo::getFixedStack(FI), 2286 false, false, 0)); 2287 } 2288} 2289 2290/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2291/// the appropriate stack slot for the tail call optimized function call. 2292static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2293 MachineFunction &MF, 2294 SDValue Chain, 2295 SDValue OldRetAddr, 2296 SDValue OldFP, 2297 int SPDiff, 2298 bool isPPC64, 2299 bool isDarwinABI, 2300 DebugLoc dl) { 2301 if (SPDiff) { 2302 // Calculate the new stack slot for the return address. 2303 int SlotSize = isPPC64 ? 8 : 4; 2304 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64, 2305 isDarwinABI); 2306 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2307 NewRetAddrLoc, true); 2308 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2309 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2310 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2311 MachinePointerInfo::getFixedStack(NewRetAddr), 2312 false, false, 0); 2313 2314 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2315 // slot as the FP is never overwritten. 2316 if (isDarwinABI) { 2317 int NewFPLoc = 2318 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2319 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2320 true); 2321 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2322 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2323 MachinePointerInfo::getFixedStack(NewFPIdx), 2324 false, false, 0); 2325 } 2326 } 2327 return Chain; 2328} 2329 2330/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2331/// the position of the argument. 2332static void 2333CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2334 SDValue Arg, int SPDiff, unsigned ArgOffset, 2335 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2336 int Offset = ArgOffset + SPDiff; 2337 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2338 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2339 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2340 SDValue FIN = DAG.getFrameIndex(FI, VT); 2341 TailCallArgumentInfo Info; 2342 Info.Arg = Arg; 2343 Info.FrameIdxOp = FIN; 2344 Info.FrameIdx = FI; 2345 TailCallArguments.push_back(Info); 2346} 2347 2348/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2349/// stack slot. Returns the chain as result and the loaded frame pointers in 2350/// LROpOut/FPOpout. Used when tail calling. 2351SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2352 int SPDiff, 2353 SDValue Chain, 2354 SDValue &LROpOut, 2355 SDValue &FPOpOut, 2356 bool isDarwinABI, 2357 DebugLoc dl) const { 2358 if (SPDiff) { 2359 // Load the LR and FP stack slot for later adjusting. 2360 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2361 LROpOut = getReturnAddrFrameIndex(DAG); 2362 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), 2363 false, false, 0); 2364 Chain = SDValue(LROpOut.getNode(), 1); 2365 2366 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2367 // slot as the FP is never overwritten. 2368 if (isDarwinABI) { 2369 FPOpOut = getFramePointerFrameIndex(DAG); 2370 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), 2371 false, false, 0); 2372 Chain = SDValue(FPOpOut.getNode(), 1); 2373 } 2374 } 2375 return Chain; 2376} 2377 2378/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2379/// by "Src" to address "Dst" of size "Size". Alignment information is 2380/// specified by the specific parameter attribute. The copy will be passed as 2381/// a byval function parameter. 2382/// Sometimes what we are copying is the end of a larger object, the part that 2383/// does not fit in registers. 2384static SDValue 2385CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2386 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2387 DebugLoc dl) { 2388 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 2389 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 2390 false, false, MachinePointerInfo(0), 2391 MachinePointerInfo(0)); 2392} 2393 2394/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2395/// tail calls. 2396static void 2397LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2398 SDValue Arg, SDValue PtrOff, int SPDiff, 2399 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2400 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2401 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, 2402 DebugLoc dl) { 2403 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2404 if (!isTailCall) { 2405 if (isVector) { 2406 SDValue StackPtr; 2407 if (isPPC64) 2408 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2409 else 2410 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2411 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 2412 DAG.getConstant(ArgOffset, PtrVT)); 2413 } 2414 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2415 MachinePointerInfo(), false, false, 0)); 2416 // Calculate and remember argument location. 2417 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2418 TailCallArguments); 2419} 2420 2421static 2422void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 2423 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 2424 SDValue LROp, SDValue FPOp, bool isDarwinABI, 2425 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 2426 MachineFunction &MF = DAG.getMachineFunction(); 2427 2428 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2429 // might overwrite each other in case of tail call optimization. 2430 SmallVector<SDValue, 8> MemOpChains2; 2431 // Do not flag preceeding copytoreg stuff together with the following stuff. 2432 InFlag = SDValue(); 2433 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2434 MemOpChains2, dl); 2435 if (!MemOpChains2.empty()) 2436 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2437 &MemOpChains2[0], MemOpChains2.size()); 2438 2439 // Store the return address to the appropriate stack slot. 2440 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2441 isPPC64, isDarwinABI, dl); 2442 2443 // Emit callseq_end just before tailcall node. 2444 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2445 DAG.getIntPtrConstant(0, true), InFlag); 2446 InFlag = Chain.getValue(1); 2447} 2448 2449static 2450unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 2451 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 2452 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 2453 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 2454 bool isPPC64, bool isSVR4ABI) { 2455 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2456 NodeTys.push_back(MVT::Other); // Returns a chain 2457 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 2458 2459 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 2460 2461 bool needIndirectCall = true; 2462 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 2463 // If this is an absolute destination address, use the munged value. 2464 Callee = SDValue(Dest, 0); 2465 needIndirectCall = false; 2466 } 2467 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 2468 // Use indirect calls for ALL functions calls in JIT mode, since the 2469 // far-call stubs may be outside relocation limits for a BL instruction. 2470 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) { 2471 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2472 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2473 // node so that legalize doesn't hack it. 2474 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2475 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2476 Callee.getValueType()); 2477 needIndirectCall = false; 2478 } 2479 } 2480 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2481 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 2482 Callee.getValueType()); 2483 needIndirectCall = false; 2484 } 2485 if (needIndirectCall) { 2486 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2487 // to do the call, we can't use PPCISD::CALL. 2488 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2489 2490 if (isSVR4ABI && isPPC64) { 2491 // Function pointers in the 64-bit SVR4 ABI do not point to the function 2492 // entry point, but to the function descriptor (the function entry point 2493 // address is part of the function descriptor though). 2494 // The function descriptor is a three doubleword structure with the 2495 // following fields: function entry point, TOC base address and 2496 // environment pointer. 2497 // Thus for a call through a function pointer, the following actions need 2498 // to be performed: 2499 // 1. Save the TOC of the caller in the TOC save area of its stack 2500 // frame (this is done in LowerCall_Darwin()). 2501 // 2. Load the address of the function entry point from the function 2502 // descriptor. 2503 // 3. Load the TOC of the callee from the function descriptor into r2. 2504 // 4. Load the environment pointer from the function descriptor into 2505 // r11. 2506 // 5. Branch to the function entry point address. 2507 // 6. On return of the callee, the TOC of the caller needs to be 2508 // restored (this is done in FinishCall()). 2509 // 2510 // All those operations are flagged together to ensure that no other 2511 // operations can be scheduled in between. E.g. without flagging the 2512 // operations together, a TOC access in the caller could be scheduled 2513 // between the load of the callee TOC and the branch to the callee, which 2514 // results in the TOC access going through the TOC of the callee instead 2515 // of going through the TOC of the caller, which leads to incorrect code. 2516 2517 // Load the address of the function entry point from the function 2518 // descriptor. 2519 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Flag); 2520 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 2521 InFlag.getNode() ? 3 : 2); 2522 Chain = LoadFuncPtr.getValue(1); 2523 InFlag = LoadFuncPtr.getValue(2); 2524 2525 // Load environment pointer into r11. 2526 // Offset of the environment pointer within the function descriptor. 2527 SDValue PtrOff = DAG.getIntPtrConstant(16); 2528 2529 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 2530 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 2531 InFlag); 2532 Chain = LoadEnvPtr.getValue(1); 2533 InFlag = LoadEnvPtr.getValue(2); 2534 2535 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 2536 InFlag); 2537 Chain = EnvVal.getValue(0); 2538 InFlag = EnvVal.getValue(1); 2539 2540 // Load TOC of the callee into r2. We are using a target-specific load 2541 // with r2 hard coded, because the result of a target-independent load 2542 // would never go directly into r2, since r2 is a reserved register (which 2543 // prevents the register allocator from allocating it), resulting in an 2544 // additional register being allocated and an unnecessary move instruction 2545 // being generated. 2546 VTs = DAG.getVTList(MVT::Other, MVT::Flag); 2547 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 2548 Callee, InFlag); 2549 Chain = LoadTOCPtr.getValue(0); 2550 InFlag = LoadTOCPtr.getValue(1); 2551 2552 MTCTROps[0] = Chain; 2553 MTCTROps[1] = LoadFuncPtr; 2554 MTCTROps[2] = InFlag; 2555 } 2556 2557 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 2558 2 + (InFlag.getNode() != 0)); 2559 InFlag = Chain.getValue(1); 2560 2561 NodeTys.clear(); 2562 NodeTys.push_back(MVT::Other); 2563 NodeTys.push_back(MVT::Flag); 2564 Ops.push_back(Chain); 2565 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 2566 Callee.setNode(0); 2567 // Add CTR register as callee so a bctr can be emitted later. 2568 if (isTailCall) 2569 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT)); 2570 } 2571 2572 // If this is a direct call, pass the chain and the callee. 2573 if (Callee.getNode()) { 2574 Ops.push_back(Chain); 2575 Ops.push_back(Callee); 2576 } 2577 // If this is a tail call add stack pointer delta. 2578 if (isTailCall) 2579 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2580 2581 // Add argument registers to the end of the list so that they are known live 2582 // into the call. 2583 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2584 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2585 RegsToPass[i].second.getValueType())); 2586 2587 return CallOpc; 2588} 2589 2590SDValue 2591PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2592 CallingConv::ID CallConv, bool isVarArg, 2593 const SmallVectorImpl<ISD::InputArg> &Ins, 2594 DebugLoc dl, SelectionDAG &DAG, 2595 SmallVectorImpl<SDValue> &InVals) const { 2596 2597 SmallVector<CCValAssign, 16> RVLocs; 2598 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(), 2599 RVLocs, *DAG.getContext()); 2600 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2601 2602 // Copy all of the result registers out of their specified physreg. 2603 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2604 CCValAssign &VA = RVLocs[i]; 2605 EVT VT = VA.getValVT(); 2606 assert(VA.isRegLoc() && "Can only return in registers!"); 2607 Chain = DAG.getCopyFromReg(Chain, dl, 2608 VA.getLocReg(), VT, InFlag).getValue(1); 2609 InVals.push_back(Chain.getValue(0)); 2610 InFlag = Chain.getValue(2); 2611 } 2612 2613 return Chain; 2614} 2615 2616SDValue 2617PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 2618 bool isTailCall, bool isVarArg, 2619 SelectionDAG &DAG, 2620 SmallVector<std::pair<unsigned, SDValue>, 8> 2621 &RegsToPass, 2622 SDValue InFlag, SDValue Chain, 2623 SDValue &Callee, 2624 int SPDiff, unsigned NumBytes, 2625 const SmallVectorImpl<ISD::InputArg> &Ins, 2626 SmallVectorImpl<SDValue> &InVals) const { 2627 std::vector<EVT> NodeTys; 2628 SmallVector<SDValue, 8> Ops; 2629 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 2630 isTailCall, RegsToPass, Ops, NodeTys, 2631 PPCSubTarget.isPPC64(), 2632 PPCSubTarget.isSVR4ABI()); 2633 2634 // When performing tail call optimization the callee pops its arguments off 2635 // the stack. Account for this here so these bytes can be pushed back on in 2636 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2637 int BytesCalleePops = 2638 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0; 2639 2640 if (InFlag.getNode()) 2641 Ops.push_back(InFlag); 2642 2643 // Emit tail call. 2644 if (isTailCall) { 2645 // If this is the first return lowered for this function, add the regs 2646 // to the liveout set for the function. 2647 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2648 SmallVector<CCValAssign, 16> RVLocs; 2649 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2650 *DAG.getContext()); 2651 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2652 for (unsigned i = 0; i != RVLocs.size(); ++i) 2653 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2654 } 2655 2656 assert(((Callee.getOpcode() == ISD::Register && 2657 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 2658 Callee.getOpcode() == ISD::TargetExternalSymbol || 2659 Callee.getOpcode() == ISD::TargetGlobalAddress || 2660 isa<ConstantSDNode>(Callee)) && 2661 "Expecting an global address, external symbol, absolute value or register"); 2662 2663 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 2664 } 2665 2666 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 2667 InFlag = Chain.getValue(1); 2668 2669 // Add a NOP immediately after the branch instruction when using the 64-bit 2670 // SVR4 ABI. At link time, if caller and callee are in a different module and 2671 // thus have a different TOC, the call will be replaced with a call to a stub 2672 // function which saves the current TOC, loads the TOC of the callee and 2673 // branches to the callee. The NOP will be replaced with a load instruction 2674 // which restores the TOC of the caller from the TOC save slot of the current 2675 // stack frame. If caller and callee belong to the same module (and have the 2676 // same TOC), the NOP will remain unchanged. 2677 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 2678 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag); 2679 if (CallOpc == PPCISD::BCTRL_SVR4) { 2680 // This is a call through a function pointer. 2681 // Restore the caller TOC from the save area into R2. 2682 // See PrepareCall() for more information about calls through function 2683 // pointers in the 64-bit SVR4 ABI. 2684 // We are using a target-specific load with r2 hard coded, because the 2685 // result of a target-independent load would never go directly into r2, 2686 // since r2 is a reserved register (which prevents the register allocator 2687 // from allocating it), resulting in an additional register being 2688 // allocated and an unnecessary move instruction being generated. 2689 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 2690 InFlag = Chain.getValue(1); 2691 } else { 2692 // Otherwise insert NOP. 2693 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag); 2694 } 2695 } 2696 2697 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2698 DAG.getIntPtrConstant(BytesCalleePops, true), 2699 InFlag); 2700 if (!Ins.empty()) 2701 InFlag = Chain.getValue(1); 2702 2703 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2704 Ins, dl, DAG, InVals); 2705} 2706 2707SDValue 2708PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2709 CallingConv::ID CallConv, bool isVarArg, 2710 bool &isTailCall, 2711 const SmallVectorImpl<ISD::OutputArg> &Outs, 2712 const SmallVectorImpl<SDValue> &OutVals, 2713 const SmallVectorImpl<ISD::InputArg> &Ins, 2714 DebugLoc dl, SelectionDAG &DAG, 2715 SmallVectorImpl<SDValue> &InVals) const { 2716 if (isTailCall) 2717 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 2718 Ins, DAG); 2719 2720 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 2721 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg, 2722 isTailCall, Outs, OutVals, Ins, 2723 dl, DAG, InVals); 2724 } else { 2725 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 2726 isTailCall, Outs, OutVals, Ins, 2727 dl, DAG, InVals); 2728 } 2729} 2730 2731SDValue 2732PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, 2733 CallingConv::ID CallConv, bool isVarArg, 2734 bool isTailCall, 2735 const SmallVectorImpl<ISD::OutputArg> &Outs, 2736 const SmallVectorImpl<SDValue> &OutVals, 2737 const SmallVectorImpl<ISD::InputArg> &Ins, 2738 DebugLoc dl, SelectionDAG &DAG, 2739 SmallVectorImpl<SDValue> &InVals) const { 2740 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description 2741 // of the 32-bit SVR4 ABI stack frame layout. 2742 2743 assert((CallConv == CallingConv::C || 2744 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 2745 2746 unsigned PtrByteSize = 4; 2747 2748 MachineFunction &MF = DAG.getMachineFunction(); 2749 2750 // Mark this function as potentially containing a function that contains a 2751 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2752 // and restoring the callers stack pointer in this functions epilog. This is 2753 // done because by tail calling the called function might overwrite the value 2754 // in this function's (MF) stack pointer stack slot 0(SP). 2755 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2756 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2757 2758 // Count how many bytes are to be pushed on the stack, including the linkage 2759 // area, parameter list area and the part of the local variable space which 2760 // contains copies of aggregates which are passed by value. 2761 2762 // Assign locations to all of the outgoing arguments. 2763 SmallVector<CCValAssign, 16> ArgLocs; 2764 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 2765 ArgLocs, *DAG.getContext()); 2766 2767 // Reserve space for the linkage area on the stack. 2768 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); 2769 2770 if (isVarArg) { 2771 // Handle fixed and variable vector arguments differently. 2772 // Fixed vector arguments go into registers as long as registers are 2773 // available. Variable vector arguments always go into memory. 2774 unsigned NumArgs = Outs.size(); 2775 2776 for (unsigned i = 0; i != NumArgs; ++i) { 2777 EVT ArgVT = Outs[i].VT; 2778 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2779 bool Result; 2780 2781 if (Outs[i].IsFixed) { 2782 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 2783 CCInfo); 2784 } else { 2785 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 2786 ArgFlags, CCInfo); 2787 } 2788 2789 if (Result) { 2790#ifndef NDEBUG 2791 errs() << "Call operand #" << i << " has unhandled type " 2792 << ArgVT.getEVTString() << "\n"; 2793#endif 2794 llvm_unreachable(0); 2795 } 2796 } 2797 } else { 2798 // All arguments are treated the same. 2799 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4); 2800 } 2801 2802 // Assign locations to all of the outgoing aggregate by value arguments. 2803 SmallVector<CCValAssign, 16> ByValArgLocs; 2804 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs, 2805 *DAG.getContext()); 2806 2807 // Reserve stack space for the allocations in CCInfo. 2808 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 2809 2810 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal); 2811 2812 // Size of the linkage area, parameter list area and the part of the local 2813 // space variable where copies of aggregates which are passed by value are 2814 // stored. 2815 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 2816 2817 // Calculate by how many bytes the stack has to be adjusted in case of tail 2818 // call optimization. 2819 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2820 2821 // Adjust the stack pointer for the new arguments... 2822 // These operations are automatically eliminated by the prolog/epilog pass 2823 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2824 SDValue CallSeqStart = Chain; 2825 2826 // Load the return address and frame pointer so it can be moved somewhere else 2827 // later. 2828 SDValue LROp, FPOp; 2829 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 2830 dl); 2831 2832 // Set up a copy of the stack pointer for use loading and storing any 2833 // arguments that may not fit in the registers available for argument 2834 // passing. 2835 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2836 2837 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2838 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2839 SmallVector<SDValue, 8> MemOpChains; 2840 2841 // Walk the register/memloc assignments, inserting copies/loads. 2842 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 2843 i != e; 2844 ++i) { 2845 CCValAssign &VA = ArgLocs[i]; 2846 SDValue Arg = OutVals[i]; 2847 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2848 2849 if (Flags.isByVal()) { 2850 // Argument is an aggregate which is passed by value, thus we need to 2851 // create a copy of it in the local variable space of the current stack 2852 // frame (which is the stack frame of the caller) and pass the address of 2853 // this copy to the callee. 2854 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 2855 CCValAssign &ByValVA = ByValArgLocs[j++]; 2856 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 2857 2858 // Memory reserved in the local variable space of the callers stack frame. 2859 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 2860 2861 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2862 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2863 2864 // Create a copy of the argument in the local area of the current 2865 // stack frame. 2866 SDValue MemcpyCall = 2867 CreateCopyOfByValArgument(Arg, PtrOff, 2868 CallSeqStart.getNode()->getOperand(0), 2869 Flags, DAG, dl); 2870 2871 // This must go outside the CALLSEQ_START..END. 2872 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2873 CallSeqStart.getNode()->getOperand(1)); 2874 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 2875 NewCallSeqStart.getNode()); 2876 Chain = CallSeqStart = NewCallSeqStart; 2877 2878 // Pass the address of the aggregate copy on the stack either in a 2879 // physical register or in the parameter list area of the current stack 2880 // frame to the callee. 2881 Arg = PtrOff; 2882 } 2883 2884 if (VA.isRegLoc()) { 2885 // Put argument in a physical register. 2886 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2887 } else { 2888 // Put argument in the parameter list area of the current stack frame. 2889 assert(VA.isMemLoc()); 2890 unsigned LocMemOffset = VA.getLocMemOffset(); 2891 2892 if (!isTailCall) { 2893 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2894 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2895 2896 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2897 MachinePointerInfo(), 2898 false, false, 0)); 2899 } else { 2900 // Calculate and remember argument location. 2901 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 2902 TailCallArguments); 2903 } 2904 } 2905 } 2906 2907 if (!MemOpChains.empty()) 2908 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2909 &MemOpChains[0], MemOpChains.size()); 2910 2911 // Build a sequence of copy-to-reg nodes chained together with token chain 2912 // and flag operands which copy the outgoing args into the appropriate regs. 2913 SDValue InFlag; 2914 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2915 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2916 RegsToPass[i].second, InFlag); 2917 InFlag = Chain.getValue(1); 2918 } 2919 2920 // Set CR6 to true if this is a vararg call. 2921 if (isVarArg) { 2922 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0); 2923 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag); 2924 InFlag = Chain.getValue(1); 2925 } 2926 2927 if (isTailCall) { 2928 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 2929 false, TailCallArguments); 2930 } 2931 2932 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 2933 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 2934 Ins, InVals); 2935} 2936 2937SDValue 2938PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 2939 CallingConv::ID CallConv, bool isVarArg, 2940 bool isTailCall, 2941 const SmallVectorImpl<ISD::OutputArg> &Outs, 2942 const SmallVectorImpl<SDValue> &OutVals, 2943 const SmallVectorImpl<ISD::InputArg> &Ins, 2944 DebugLoc dl, SelectionDAG &DAG, 2945 SmallVectorImpl<SDValue> &InVals) const { 2946 2947 unsigned NumOps = Outs.size(); 2948 2949 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2950 bool isPPC64 = PtrVT == MVT::i64; 2951 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2952 2953 MachineFunction &MF = DAG.getMachineFunction(); 2954 2955 // Mark this function as potentially containing a function that contains a 2956 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2957 // and restoring the callers stack pointer in this functions epilog. This is 2958 // done because by tail calling the called function might overwrite the value 2959 // in this function's (MF) stack pointer stack slot 0(SP). 2960 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2961 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2962 2963 unsigned nAltivecParamsAtEnd = 0; 2964 2965 // Count how many bytes are to be pushed on the stack, including the linkage 2966 // area, and parameter passing area. We start with 24/48 bytes, which is 2967 // prereserved space for [SP][CR][LR][3 x unused]. 2968 unsigned NumBytes = 2969 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 2970 Outs, OutVals, 2971 nAltivecParamsAtEnd); 2972 2973 // Calculate by how many bytes the stack has to be adjusted in case of tail 2974 // call optimization. 2975 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2976 2977 // To protect arguments on the stack from being clobbered in a tail call, 2978 // force all the loads to happen before doing any other lowering. 2979 if (isTailCall) 2980 Chain = DAG.getStackArgumentTokenFactor(Chain); 2981 2982 // Adjust the stack pointer for the new arguments... 2983 // These operations are automatically eliminated by the prolog/epilog pass 2984 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2985 SDValue CallSeqStart = Chain; 2986 2987 // Load the return address and frame pointer so it can be move somewhere else 2988 // later. 2989 SDValue LROp, FPOp; 2990 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 2991 dl); 2992 2993 // Set up a copy of the stack pointer for use loading and storing any 2994 // arguments that may not fit in the registers available for argument 2995 // passing. 2996 SDValue StackPtr; 2997 if (isPPC64) 2998 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2999 else 3000 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3001 3002 // Figure out which arguments are going to go in registers, and which in 3003 // memory. Also, if this is a vararg function, floating point operations 3004 // must be stored to our stack, and loaded into integer regs as well, if 3005 // any integer regs are available for argument passing. 3006 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); 3007 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 3008 3009 static const unsigned GPR_32[] = { // 32-bit registers. 3010 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 3011 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 3012 }; 3013 static const unsigned GPR_64[] = { // 64-bit registers. 3014 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3015 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3016 }; 3017 static const unsigned *FPR = GetFPR(); 3018 3019 static const unsigned VR[] = { 3020 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3021 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3022 }; 3023 const unsigned NumGPRs = array_lengthof(GPR_32); 3024 const unsigned NumFPRs = 13; 3025 const unsigned NumVRs = array_lengthof(VR); 3026 3027 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 3028 3029 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3030 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3031 3032 SmallVector<SDValue, 8> MemOpChains; 3033 for (unsigned i = 0; i != NumOps; ++i) { 3034 SDValue Arg = OutVals[i]; 3035 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3036 3037 // PtrOff will be used to store the current argument to the stack if a 3038 // register cannot be found for it. 3039 SDValue PtrOff; 3040 3041 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3042 3043 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3044 3045 // On PPC64, promote integers to 64-bit values. 3046 if (isPPC64 && Arg.getValueType() == MVT::i32) { 3047 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3048 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3049 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3050 } 3051 3052 // FIXME memcpy is used way more than necessary. Correctness first. 3053 if (Flags.isByVal()) { 3054 unsigned Size = Flags.getByValSize(); 3055 if (Size==1 || Size==2) { 3056 // Very small objects are passed right-justified. 3057 // Everything else is passed left-justified. 3058 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 3059 if (GPR_idx != NumGPRs) { 3060 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, dl, Chain, Arg, 3061 MachinePointerInfo(), VT, 3062 false, false, 0); 3063 MemOpChains.push_back(Load.getValue(1)); 3064 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3065 3066 ArgOffset += PtrByteSize; 3067 } else { 3068 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 3069 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3070 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 3071 CallSeqStart.getNode()->getOperand(0), 3072 Flags, DAG, dl); 3073 // This must go outside the CALLSEQ_START..END. 3074 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3075 CallSeqStart.getNode()->getOperand(1)); 3076 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3077 NewCallSeqStart.getNode()); 3078 Chain = CallSeqStart = NewCallSeqStart; 3079 ArgOffset += PtrByteSize; 3080 } 3081 continue; 3082 } 3083 // Copy entire object into memory. There are cases where gcc-generated 3084 // code assumes it is there, even if it could be put entirely into 3085 // registers. (This is not what the doc says.) 3086 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3087 CallSeqStart.getNode()->getOperand(0), 3088 Flags, DAG, dl); 3089 // This must go outside the CALLSEQ_START..END. 3090 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3091 CallSeqStart.getNode()->getOperand(1)); 3092 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); 3093 Chain = CallSeqStart = NewCallSeqStart; 3094 // And copy the pieces of it that fit into registers. 3095 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3096 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3097 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3098 if (GPR_idx != NumGPRs) { 3099 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 3100 MachinePointerInfo(), 3101 false, false, 0); 3102 MemOpChains.push_back(Load.getValue(1)); 3103 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3104 ArgOffset += PtrByteSize; 3105 } else { 3106 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3107 break; 3108 } 3109 } 3110 continue; 3111 } 3112 3113 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3114 default: llvm_unreachable("Unexpected ValueType for argument!"); 3115 case MVT::i32: 3116 case MVT::i64: 3117 if (GPR_idx != NumGPRs) { 3118 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3119 } else { 3120 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3121 isPPC64, isTailCall, false, MemOpChains, 3122 TailCallArguments, dl); 3123 } 3124 ArgOffset += PtrByteSize; 3125 break; 3126 case MVT::f32: 3127 case MVT::f64: 3128 if (FPR_idx != NumFPRs) { 3129 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3130 3131 if (isVarArg) { 3132 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3133 MachinePointerInfo(), false, false, 0); 3134 MemOpChains.push_back(Store); 3135 3136 // Float varargs are always shadowed in available integer registers 3137 if (GPR_idx != NumGPRs) { 3138 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3139 MachinePointerInfo(), false, false, 0); 3140 MemOpChains.push_back(Load.getValue(1)); 3141 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3142 } 3143 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 3144 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3145 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3146 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3147 MachinePointerInfo(), 3148 false, false, 0); 3149 MemOpChains.push_back(Load.getValue(1)); 3150 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3151 } 3152 } else { 3153 // If we have any FPRs remaining, we may also have GPRs remaining. 3154 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 3155 // GPRs. 3156 if (GPR_idx != NumGPRs) 3157 ++GPR_idx; 3158 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 3159 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 3160 ++GPR_idx; 3161 } 3162 } else { 3163 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3164 isPPC64, isTailCall, false, MemOpChains, 3165 TailCallArguments, dl); 3166 } 3167 if (isPPC64) 3168 ArgOffset += 8; 3169 else 3170 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 3171 break; 3172 case MVT::v4f32: 3173 case MVT::v4i32: 3174 case MVT::v8i16: 3175 case MVT::v16i8: 3176 if (isVarArg) { 3177 // These go aligned on the stack, or in the corresponding R registers 3178 // when within range. The Darwin PPC ABI doc claims they also go in 3179 // V registers; in fact gcc does this only for arguments that are 3180 // prototyped, not for those that match the ... We do it for all 3181 // arguments, seems to work. 3182 while (ArgOffset % 16 !=0) { 3183 ArgOffset += PtrByteSize; 3184 if (GPR_idx != NumGPRs) 3185 GPR_idx++; 3186 } 3187 // We could elide this store in the case where the object fits 3188 // entirely in R registers. Maybe later. 3189 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3190 DAG.getConstant(ArgOffset, PtrVT)); 3191 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3192 MachinePointerInfo(), false, false, 0); 3193 MemOpChains.push_back(Store); 3194 if (VR_idx != NumVRs) { 3195 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 3196 MachinePointerInfo(), 3197 false, false, 0); 3198 MemOpChains.push_back(Load.getValue(1)); 3199 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3200 } 3201 ArgOffset += 16; 3202 for (unsigned i=0; i<16; i+=PtrByteSize) { 3203 if (GPR_idx == NumGPRs) 3204 break; 3205 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3206 DAG.getConstant(i, PtrVT)); 3207 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 3208 false, false, 0); 3209 MemOpChains.push_back(Load.getValue(1)); 3210 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3211 } 3212 break; 3213 } 3214 3215 // Non-varargs Altivec params generally go in registers, but have 3216 // stack space allocated at the end. 3217 if (VR_idx != NumVRs) { 3218 // Doesn't have GPR space allocated. 3219 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3220 } else if (nAltivecParamsAtEnd==0) { 3221 // We are emitting Altivec params in order. 3222 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3223 isPPC64, isTailCall, true, MemOpChains, 3224 TailCallArguments, dl); 3225 ArgOffset += 16; 3226 } 3227 break; 3228 } 3229 } 3230 // If all Altivec parameters fit in registers, as they usually do, 3231 // they get stack space following the non-Altivec parameters. We 3232 // don't track this here because nobody below needs it. 3233 // If there are more Altivec parameters than fit in registers emit 3234 // the stores here. 3235 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 3236 unsigned j = 0; 3237 // Offset is aligned; skip 1st 12 params which go in V registers. 3238 ArgOffset = ((ArgOffset+15)/16)*16; 3239 ArgOffset += 12*16; 3240 for (unsigned i = 0; i != NumOps; ++i) { 3241 SDValue Arg = OutVals[i]; 3242 EVT ArgType = Outs[i].VT; 3243 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 3244 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 3245 if (++j > NumVRs) { 3246 SDValue PtrOff; 3247 // We are emitting Altivec params in order. 3248 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3249 isPPC64, isTailCall, true, MemOpChains, 3250 TailCallArguments, dl); 3251 ArgOffset += 16; 3252 } 3253 } 3254 } 3255 } 3256 3257 if (!MemOpChains.empty()) 3258 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3259 &MemOpChains[0], MemOpChains.size()); 3260 3261 // Check if this is an indirect call (MTCTR/BCTRL). 3262 // See PrepareCall() for more information about calls through function 3263 // pointers in the 64-bit SVR4 ABI. 3264 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() && 3265 !dyn_cast<GlobalAddressSDNode>(Callee) && 3266 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3267 !isBLACompatibleAddress(Callee, DAG)) { 3268 // Load r2 into a virtual register and store it to the TOC save area. 3269 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 3270 // TOC save area offset. 3271 SDValue PtrOff = DAG.getIntPtrConstant(40); 3272 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3273 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), 3274 false, false, 0); 3275 } 3276 3277 // On Darwin, R12 must contain the address of an indirect callee. This does 3278 // not mean the MTCTR instruction must use R12; it's easier to model this as 3279 // an extra parameter, so do that. 3280 if (!isTailCall && 3281 !dyn_cast<GlobalAddressSDNode>(Callee) && 3282 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3283 !isBLACompatibleAddress(Callee, DAG)) 3284 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 3285 PPC::R12), Callee)); 3286 3287 // Build a sequence of copy-to-reg nodes chained together with token chain 3288 // and flag operands which copy the outgoing args into the appropriate regs. 3289 SDValue InFlag; 3290 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3291 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3292 RegsToPass[i].second, InFlag); 3293 InFlag = Chain.getValue(1); 3294 } 3295 3296 if (isTailCall) { 3297 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 3298 FPOp, true, TailCallArguments); 3299 } 3300 3301 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3302 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3303 Ins, InVals); 3304} 3305 3306SDValue 3307PPCTargetLowering::LowerReturn(SDValue Chain, 3308 CallingConv::ID CallConv, bool isVarArg, 3309 const SmallVectorImpl<ISD::OutputArg> &Outs, 3310 const SmallVectorImpl<SDValue> &OutVals, 3311 DebugLoc dl, SelectionDAG &DAG) const { 3312 3313 SmallVector<CCValAssign, 16> RVLocs; 3314 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 3315 RVLocs, *DAG.getContext()); 3316 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 3317 3318 // If this is the first return lowered for this function, add the regs to the 3319 // liveout set for the function. 3320 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3321 for (unsigned i = 0; i != RVLocs.size(); ++i) 3322 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3323 } 3324 3325 SDValue Flag; 3326 3327 // Copy the result values into the output registers. 3328 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3329 CCValAssign &VA = RVLocs[i]; 3330 assert(VA.isRegLoc() && "Can only return in registers!"); 3331 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 3332 OutVals[i], Flag); 3333 Flag = Chain.getValue(1); 3334 } 3335 3336 if (Flag.getNode()) 3337 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 3338 else 3339 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 3340} 3341 3342SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 3343 const PPCSubtarget &Subtarget) const { 3344 // When we pop the dynamic allocation we need to restore the SP link. 3345 DebugLoc dl = Op.getDebugLoc(); 3346 3347 // Get the corect type for pointers. 3348 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3349 3350 // Construct the stack pointer operand. 3351 bool isPPC64 = Subtarget.isPPC64(); 3352 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 3353 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 3354 3355 // Get the operands for the STACKRESTORE. 3356 SDValue Chain = Op.getOperand(0); 3357 SDValue SaveSP = Op.getOperand(1); 3358 3359 // Load the old link SP. 3360 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, 3361 MachinePointerInfo(), 3362 false, false, 0); 3363 3364 // Restore the stack pointer. 3365 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 3366 3367 // Store the old link SP. 3368 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(), 3369 false, false, 0); 3370} 3371 3372 3373 3374SDValue 3375PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 3376 MachineFunction &MF = DAG.getMachineFunction(); 3377 bool isPPC64 = PPCSubTarget.isPPC64(); 3378 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3379 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3380 3381 // Get current frame pointer save index. The users of this index will be 3382 // primarily DYNALLOC instructions. 3383 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3384 int RASI = FI->getReturnAddrSaveIndex(); 3385 3386 // If the frame pointer save index hasn't been defined yet. 3387 if (!RASI) { 3388 // Find out what the fix offset of the frame pointer save area. 3389 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 3390 // Allocate the frame index for frame pointer save area. 3391 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 3392 // Save the result. 3393 FI->setReturnAddrSaveIndex(RASI); 3394 } 3395 return DAG.getFrameIndex(RASI, PtrVT); 3396} 3397 3398SDValue 3399PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 3400 MachineFunction &MF = DAG.getMachineFunction(); 3401 bool isPPC64 = PPCSubTarget.isPPC64(); 3402 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3403 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3404 3405 // Get current frame pointer save index. The users of this index will be 3406 // primarily DYNALLOC instructions. 3407 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3408 int FPSI = FI->getFramePointerSaveIndex(); 3409 3410 // If the frame pointer save index hasn't been defined yet. 3411 if (!FPSI) { 3412 // Find out what the fix offset of the frame pointer save area. 3413 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 3414 isDarwinABI); 3415 3416 // Allocate the frame index for frame pointer save area. 3417 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 3418 // Save the result. 3419 FI->setFramePointerSaveIndex(FPSI); 3420 } 3421 return DAG.getFrameIndex(FPSI, PtrVT); 3422} 3423 3424SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 3425 SelectionDAG &DAG, 3426 const PPCSubtarget &Subtarget) const { 3427 // Get the inputs. 3428 SDValue Chain = Op.getOperand(0); 3429 SDValue Size = Op.getOperand(1); 3430 DebugLoc dl = Op.getDebugLoc(); 3431 3432 // Get the corect type for pointers. 3433 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3434 // Negate the size. 3435 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 3436 DAG.getConstant(0, PtrVT), Size); 3437 // Construct a node for the frame pointer save index. 3438 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 3439 // Build a DYNALLOC node. 3440 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 3441 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 3442 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 3443} 3444 3445/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 3446/// possible. 3447SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 3448 // Not FP? Not a fsel. 3449 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 3450 !Op.getOperand(2).getValueType().isFloatingPoint()) 3451 return Op; 3452 3453 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 3454 3455 // Cannot handle SETEQ/SETNE. 3456 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 3457 3458 EVT ResVT = Op.getValueType(); 3459 EVT CmpVT = Op.getOperand(0).getValueType(); 3460 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3461 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 3462 DebugLoc dl = Op.getDebugLoc(); 3463 3464 // If the RHS of the comparison is a 0.0, we don't need to do the 3465 // subtraction at all. 3466 if (isFloatingPointZero(RHS)) 3467 switch (CC) { 3468 default: break; // SETUO etc aren't handled by fsel. 3469 case ISD::SETULT: 3470 case ISD::SETLT: 3471 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3472 case ISD::SETOGE: 3473 case ISD::SETGE: 3474 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3475 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3476 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 3477 case ISD::SETUGT: 3478 case ISD::SETGT: 3479 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3480 case ISD::SETOLE: 3481 case ISD::SETLE: 3482 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3483 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3484 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 3485 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 3486 } 3487 3488 SDValue Cmp; 3489 switch (CC) { 3490 default: break; // SETUO etc aren't handled by fsel. 3491 case ISD::SETULT: 3492 case ISD::SETLT: 3493 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3494 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3495 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3496 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3497 case ISD::SETOGE: 3498 case ISD::SETGE: 3499 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3500 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3501 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3502 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3503 case ISD::SETUGT: 3504 case ISD::SETGT: 3505 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3506 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3507 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3508 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3509 case ISD::SETOLE: 3510 case ISD::SETLE: 3511 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3512 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3513 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3514 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3515 } 3516 return Op; 3517} 3518 3519// FIXME: Split this code up when LegalizeDAGTypes lands. 3520SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 3521 DebugLoc dl) const { 3522 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 3523 SDValue Src = Op.getOperand(0); 3524 if (Src.getValueType() == MVT::f32) 3525 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 3526 3527 SDValue Tmp; 3528 switch (Op.getValueType().getSimpleVT().SimpleTy) { 3529 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 3530 case MVT::i32: 3531 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 3532 PPCISD::FCTIDZ, 3533 dl, MVT::f64, Src); 3534 break; 3535 case MVT::i64: 3536 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 3537 break; 3538 } 3539 3540 // Convert the FP value to an int value through memory. 3541 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 3542 3543 // Emit a store to the stack slot. 3544 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, 3545 MachinePointerInfo(), false, false, 0); 3546 3547 // Result is a load from the stack slot. If loading 4 bytes, make sure to 3548 // add in a bias. 3549 if (Op.getValueType() == MVT::i32) 3550 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 3551 DAG.getConstant(4, FIPtr.getValueType())); 3552 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(), 3553 false, false, 0); 3554} 3555 3556SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, 3557 SelectionDAG &DAG) const { 3558 DebugLoc dl = Op.getDebugLoc(); 3559 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 3560 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 3561 return SDValue(); 3562 3563 if (Op.getOperand(0).getValueType() == MVT::i64) { 3564 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl, 3565 MVT::f64, Op.getOperand(0)); 3566 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 3567 if (Op.getValueType() == MVT::f32) 3568 FP = DAG.getNode(ISD::FP_ROUND, dl, 3569 MVT::f32, FP, DAG.getIntPtrConstant(0)); 3570 return FP; 3571 } 3572 3573 assert(Op.getOperand(0).getValueType() == MVT::i32 && 3574 "Unhandled SINT_TO_FP type in custom expander!"); 3575 // Since we only generate this in 64-bit mode, we can take advantage of 3576 // 64-bit registers. In particular, sign extend the input value into the 3577 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 3578 // then lfd it and fcfid it. 3579 MachineFunction &MF = DAG.getMachineFunction(); 3580 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 3581 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 3582 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3583 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3584 3585 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 3586 Op.getOperand(0)); 3587 3588 // STD the extended value into the stack slot. 3589 MachineMemOperand *MMO = 3590 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 3591 MachineMemOperand::MOStore, 8, 8); 3592 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 3593 SDValue Store = 3594 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 3595 Ops, 4, MVT::i64, MMO); 3596 // Load the value as a double. 3597 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(), 3598 false, false, 0); 3599 3600 // FCFID it and return it. 3601 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 3602 if (Op.getValueType() == MVT::f32) 3603 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 3604 return FP; 3605} 3606 3607SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3608 SelectionDAG &DAG) const { 3609 DebugLoc dl = Op.getDebugLoc(); 3610 /* 3611 The rounding mode is in bits 30:31 of FPSR, and has the following 3612 settings: 3613 00 Round to nearest 3614 01 Round to 0 3615 10 Round to +inf 3616 11 Round to -inf 3617 3618 FLT_ROUNDS, on the other hand, expects the following: 3619 -1 Undefined 3620 0 Round to 0 3621 1 Round to nearest 3622 2 Round to +inf 3623 3 Round to -inf 3624 3625 To perform the conversion, we do: 3626 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 3627 */ 3628 3629 MachineFunction &MF = DAG.getMachineFunction(); 3630 EVT VT = Op.getValueType(); 3631 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3632 std::vector<EVT> NodeTys; 3633 SDValue MFFSreg, InFlag; 3634 3635 // Save FP Control Word to register 3636 NodeTys.push_back(MVT::f64); // return register 3637 NodeTys.push_back(MVT::Flag); // unused in this context 3638 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 3639 3640 // Save FP register to stack slot 3641 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 3642 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 3643 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 3644 StackSlot, MachinePointerInfo(), false, false,0); 3645 3646 // Load FP Control Word from low 32 bits of stack slot. 3647 SDValue Four = DAG.getConstant(4, PtrVT); 3648 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 3649 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), 3650 false, false, 0); 3651 3652 // Transform as necessary 3653 SDValue CWD1 = 3654 DAG.getNode(ISD::AND, dl, MVT::i32, 3655 CWD, DAG.getConstant(3, MVT::i32)); 3656 SDValue CWD2 = 3657 DAG.getNode(ISD::SRL, dl, MVT::i32, 3658 DAG.getNode(ISD::AND, dl, MVT::i32, 3659 DAG.getNode(ISD::XOR, dl, MVT::i32, 3660 CWD, DAG.getConstant(3, MVT::i32)), 3661 DAG.getConstant(3, MVT::i32)), 3662 DAG.getConstant(1, MVT::i32)); 3663 3664 SDValue RetVal = 3665 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 3666 3667 return DAG.getNode((VT.getSizeInBits() < 16 ? 3668 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 3669} 3670 3671SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3672 EVT VT = Op.getValueType(); 3673 unsigned BitWidth = VT.getSizeInBits(); 3674 DebugLoc dl = Op.getDebugLoc(); 3675 assert(Op.getNumOperands() == 3 && 3676 VT == Op.getOperand(1).getValueType() && 3677 "Unexpected SHL!"); 3678 3679 // Expand into a bunch of logical ops. Note that these ops 3680 // depend on the PPC behavior for oversized shift amounts. 3681 SDValue Lo = Op.getOperand(0); 3682 SDValue Hi = Op.getOperand(1); 3683 SDValue Amt = Op.getOperand(2); 3684 EVT AmtVT = Amt.getValueType(); 3685 3686 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3687 DAG.getConstant(BitWidth, AmtVT), Amt); 3688 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 3689 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 3690 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 3691 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3692 DAG.getConstant(-BitWidth, AmtVT)); 3693 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 3694 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3695 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 3696 SDValue OutOps[] = { OutLo, OutHi }; 3697 return DAG.getMergeValues(OutOps, 2, dl); 3698} 3699 3700SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3701 EVT VT = Op.getValueType(); 3702 DebugLoc dl = Op.getDebugLoc(); 3703 unsigned BitWidth = VT.getSizeInBits(); 3704 assert(Op.getNumOperands() == 3 && 3705 VT == Op.getOperand(1).getValueType() && 3706 "Unexpected SRL!"); 3707 3708 // Expand into a bunch of logical ops. Note that these ops 3709 // depend on the PPC behavior for oversized shift amounts. 3710 SDValue Lo = Op.getOperand(0); 3711 SDValue Hi = Op.getOperand(1); 3712 SDValue Amt = Op.getOperand(2); 3713 EVT AmtVT = Amt.getValueType(); 3714 3715 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3716 DAG.getConstant(BitWidth, AmtVT), Amt); 3717 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3718 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3719 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3720 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3721 DAG.getConstant(-BitWidth, AmtVT)); 3722 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 3723 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3724 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 3725 SDValue OutOps[] = { OutLo, OutHi }; 3726 return DAG.getMergeValues(OutOps, 2, dl); 3727} 3728 3729SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 3730 DebugLoc dl = Op.getDebugLoc(); 3731 EVT VT = Op.getValueType(); 3732 unsigned BitWidth = VT.getSizeInBits(); 3733 assert(Op.getNumOperands() == 3 && 3734 VT == Op.getOperand(1).getValueType() && 3735 "Unexpected SRA!"); 3736 3737 // Expand into a bunch of logical ops, followed by a select_cc. 3738 SDValue Lo = Op.getOperand(0); 3739 SDValue Hi = Op.getOperand(1); 3740 SDValue Amt = Op.getOperand(2); 3741 EVT AmtVT = Amt.getValueType(); 3742 3743 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3744 DAG.getConstant(BitWidth, AmtVT), Amt); 3745 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3746 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3747 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3748 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3749 DAG.getConstant(-BitWidth, AmtVT)); 3750 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 3751 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 3752 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 3753 Tmp4, Tmp6, ISD::SETLE); 3754 SDValue OutOps[] = { OutLo, OutHi }; 3755 return DAG.getMergeValues(OutOps, 2, dl); 3756} 3757 3758//===----------------------------------------------------------------------===// 3759// Vector related lowering. 3760// 3761 3762/// BuildSplatI - Build a canonical splati of Val with an element size of 3763/// SplatSize. Cast the result to VT. 3764static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 3765 SelectionDAG &DAG, DebugLoc dl) { 3766 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 3767 3768 static const EVT VTys[] = { // canonical VT to use for each size. 3769 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 3770 }; 3771 3772 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 3773 3774 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 3775 if (Val == -1) 3776 SplatSize = 1; 3777 3778 EVT CanonicalVT = VTys[SplatSize-1]; 3779 3780 // Build a canonical splat for this value. 3781 SDValue Elt = DAG.getConstant(Val, MVT::i32); 3782 SmallVector<SDValue, 8> Ops; 3783 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 3784 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 3785 &Ops[0], Ops.size()); 3786 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res); 3787} 3788 3789/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 3790/// specified intrinsic ID. 3791static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 3792 SelectionDAG &DAG, DebugLoc dl, 3793 EVT DestVT = MVT::Other) { 3794 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 3795 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3796 DAG.getConstant(IID, MVT::i32), LHS, RHS); 3797} 3798 3799/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 3800/// specified intrinsic ID. 3801static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 3802 SDValue Op2, SelectionDAG &DAG, 3803 DebugLoc dl, EVT DestVT = MVT::Other) { 3804 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 3805 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3806 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 3807} 3808 3809 3810/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 3811/// amount. The result has the specified value type. 3812static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 3813 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3814 // Force LHS/RHS to be the right type. 3815 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS); 3816 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS); 3817 3818 int Ops[16]; 3819 for (unsigned i = 0; i != 16; ++i) 3820 Ops[i] = i + Amt; 3821 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 3822 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); 3823} 3824 3825// If this is a case we can't handle, return null and let the default 3826// expansion code take care of it. If we CAN select this case, and if it 3827// selects to a single instruction, return Op. Otherwise, if we can codegen 3828// this case more efficiently than a constant pool load, lower it to the 3829// sequence of ops that should be used. 3830SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 3831 SelectionDAG &DAG) const { 3832 DebugLoc dl = Op.getDebugLoc(); 3833 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 3834 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 3835 3836 // Check if this is a splat of a constant value. 3837 APInt APSplatBits, APSplatUndef; 3838 unsigned SplatBitSize; 3839 bool HasAnyUndefs; 3840 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 3841 HasAnyUndefs, 0, true) || SplatBitSize > 32) 3842 return SDValue(); 3843 3844 unsigned SplatBits = APSplatBits.getZExtValue(); 3845 unsigned SplatUndef = APSplatUndef.getZExtValue(); 3846 unsigned SplatSize = SplatBitSize / 8; 3847 3848 // First, handle single instruction cases. 3849 3850 // All zeros? 3851 if (SplatBits == 0) { 3852 // Canonicalize all zero vectors to be v4i32. 3853 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 3854 SDValue Z = DAG.getConstant(0, MVT::i32); 3855 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 3856 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z); 3857 } 3858 return Op; 3859 } 3860 3861 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 3862 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 3863 (32-SplatBitSize)); 3864 if (SextVal >= -16 && SextVal <= 15) 3865 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 3866 3867 3868 // Two instruction sequences. 3869 3870 // If this value is in the range [-32,30] and is even, use: 3871 // tmp = VSPLTI[bhw], result = add tmp, tmp 3872 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 3873 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 3874 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 3875 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3876 } 3877 3878 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 3879 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 3880 // for fneg/fabs. 3881 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 3882 // Make -1 and vspltisw -1: 3883 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 3884 3885 // Make the VSLW intrinsic, computing 0x8000_0000. 3886 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 3887 OnesV, DAG, dl); 3888 3889 // xor by OnesV to invert it. 3890 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 3891 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3892 } 3893 3894 // Check to see if this is a wide variety of vsplti*, binop self cases. 3895 static const signed char SplatCsts[] = { 3896 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 3897 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 3898 }; 3899 3900 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 3901 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 3902 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 3903 int i = SplatCsts[idx]; 3904 3905 // Figure out what shift amount will be used by altivec if shifted by i in 3906 // this splat size. 3907 unsigned TypeShiftAmt = i & (SplatBitSize-1); 3908 3909 // vsplti + shl self. 3910 if (SextVal == (i << (int)TypeShiftAmt)) { 3911 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3912 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3913 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 3914 Intrinsic::ppc_altivec_vslw 3915 }; 3916 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3917 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3918 } 3919 3920 // vsplti + srl self. 3921 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3922 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3923 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3924 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 3925 Intrinsic::ppc_altivec_vsrw 3926 }; 3927 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3928 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3929 } 3930 3931 // vsplti + sra self. 3932 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3933 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3934 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3935 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 3936 Intrinsic::ppc_altivec_vsraw 3937 }; 3938 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3939 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3940 } 3941 3942 // vsplti + rol self. 3943 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 3944 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 3945 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3946 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3947 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 3948 Intrinsic::ppc_altivec_vrlw 3949 }; 3950 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3951 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3952 } 3953 3954 // t = vsplti c, result = vsldoi t, t, 1 3955 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) { 3956 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3957 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 3958 } 3959 // t = vsplti c, result = vsldoi t, t, 2 3960 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) { 3961 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3962 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 3963 } 3964 // t = vsplti c, result = vsldoi t, t, 3 3965 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) { 3966 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3967 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 3968 } 3969 } 3970 3971 // Three instruction sequences. 3972 3973 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 3974 if (SextVal >= 0 && SextVal <= 31) { 3975 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 3976 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3977 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 3978 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3979 } 3980 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 3981 if (SextVal >= -31 && SextVal <= 0) { 3982 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 3983 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3984 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 3985 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3986 } 3987 3988 return SDValue(); 3989} 3990 3991/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3992/// the specified operations to build the shuffle. 3993static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3994 SDValue RHS, SelectionDAG &DAG, 3995 DebugLoc dl) { 3996 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3997 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3998 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 3999 4000 enum { 4001 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4002 OP_VMRGHW, 4003 OP_VMRGLW, 4004 OP_VSPLTISW0, 4005 OP_VSPLTISW1, 4006 OP_VSPLTISW2, 4007 OP_VSPLTISW3, 4008 OP_VSLDOI4, 4009 OP_VSLDOI8, 4010 OP_VSLDOI12 4011 }; 4012 4013 if (OpNum == OP_COPY) { 4014 if (LHSID == (1*9+2)*9+3) return LHS; 4015 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4016 return RHS; 4017 } 4018 4019 SDValue OpLHS, OpRHS; 4020 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4021 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4022 4023 int ShufIdxs[16]; 4024 switch (OpNum) { 4025 default: llvm_unreachable("Unknown i32 permute!"); 4026 case OP_VMRGHW: 4027 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 4028 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 4029 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 4030 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 4031 break; 4032 case OP_VMRGLW: 4033 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 4034 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 4035 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 4036 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 4037 break; 4038 case OP_VSPLTISW0: 4039 for (unsigned i = 0; i != 16; ++i) 4040 ShufIdxs[i] = (i&3)+0; 4041 break; 4042 case OP_VSPLTISW1: 4043 for (unsigned i = 0; i != 16; ++i) 4044 ShufIdxs[i] = (i&3)+4; 4045 break; 4046 case OP_VSPLTISW2: 4047 for (unsigned i = 0; i != 16; ++i) 4048 ShufIdxs[i] = (i&3)+8; 4049 break; 4050 case OP_VSPLTISW3: 4051 for (unsigned i = 0; i != 16; ++i) 4052 ShufIdxs[i] = (i&3)+12; 4053 break; 4054 case OP_VSLDOI4: 4055 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 4056 case OP_VSLDOI8: 4057 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 4058 case OP_VSLDOI12: 4059 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 4060 } 4061 EVT VT = OpLHS.getValueType(); 4062 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS); 4063 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS); 4064 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 4065 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); 4066} 4067 4068/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 4069/// is a shuffle we can handle in a single instruction, return it. Otherwise, 4070/// return the code it can be lowered into. Worst case, it can always be 4071/// lowered into a vperm. 4072SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4073 SelectionDAG &DAG) const { 4074 DebugLoc dl = Op.getDebugLoc(); 4075 SDValue V1 = Op.getOperand(0); 4076 SDValue V2 = Op.getOperand(1); 4077 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4078 EVT VT = Op.getValueType(); 4079 4080 // Cases that are handled by instructions that take permute immediates 4081 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 4082 // selected by the instruction selector. 4083 if (V2.getOpcode() == ISD::UNDEF) { 4084 if (PPC::isSplatShuffleMask(SVOp, 1) || 4085 PPC::isSplatShuffleMask(SVOp, 2) || 4086 PPC::isSplatShuffleMask(SVOp, 4) || 4087 PPC::isVPKUWUMShuffleMask(SVOp, true) || 4088 PPC::isVPKUHUMShuffleMask(SVOp, true) || 4089 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 4090 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 4091 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 4092 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 4093 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 4094 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 4095 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 4096 return Op; 4097 } 4098 } 4099 4100 // Altivec has a variety of "shuffle immediates" that take two vector inputs 4101 // and produce a fixed permutation. If any of these match, do not lower to 4102 // VPERM. 4103 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 4104 PPC::isVPKUHUMShuffleMask(SVOp, false) || 4105 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 4106 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 4107 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 4108 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 4109 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 4110 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 4111 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 4112 return Op; 4113 4114 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 4115 // perfect shuffle table to emit an optimal matching sequence. 4116 SmallVector<int, 16> PermMask; 4117 SVOp->getMask(PermMask); 4118 4119 unsigned PFIndexes[4]; 4120 bool isFourElementShuffle = true; 4121 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 4122 unsigned EltNo = 8; // Start out undef. 4123 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 4124 if (PermMask[i*4+j] < 0) 4125 continue; // Undef, ignore it. 4126 4127 unsigned ByteSource = PermMask[i*4+j]; 4128 if ((ByteSource & 3) != j) { 4129 isFourElementShuffle = false; 4130 break; 4131 } 4132 4133 if (EltNo == 8) { 4134 EltNo = ByteSource/4; 4135 } else if (EltNo != ByteSource/4) { 4136 isFourElementShuffle = false; 4137 break; 4138 } 4139 } 4140 PFIndexes[i] = EltNo; 4141 } 4142 4143 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 4144 // perfect shuffle vector to determine if it is cost effective to do this as 4145 // discrete instructions, or whether we should use a vperm. 4146 if (isFourElementShuffle) { 4147 // Compute the index in the perfect shuffle table. 4148 unsigned PFTableIndex = 4149 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4150 4151 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4152 unsigned Cost = (PFEntry >> 30); 4153 4154 // Determining when to avoid vperm is tricky. Many things affect the cost 4155 // of vperm, particularly how many times the perm mask needs to be computed. 4156 // For example, if the perm mask can be hoisted out of a loop or is already 4157 // used (perhaps because there are multiple permutes with the same shuffle 4158 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 4159 // the loop requires an extra register. 4160 // 4161 // As a compromise, we only emit discrete instructions if the shuffle can be 4162 // generated in 3 or fewer operations. When we have loop information 4163 // available, if this block is within a loop, we should avoid using vperm 4164 // for 3-operation perms and use a constant pool load instead. 4165 if (Cost < 3) 4166 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4167 } 4168 4169 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 4170 // vector that will get spilled to the constant pool. 4171 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 4172 4173 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 4174 // that it is in input element units, not in bytes. Convert now. 4175 EVT EltVT = V1.getValueType().getVectorElementType(); 4176 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 4177 4178 SmallVector<SDValue, 16> ResultMask; 4179 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4180 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 4181 4182 for (unsigned j = 0; j != BytesPerElement; ++j) 4183 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 4184 MVT::i32)); 4185 } 4186 4187 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 4188 &ResultMask[0], ResultMask.size()); 4189 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 4190} 4191 4192/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 4193/// altivec comparison. If it is, return true and fill in Opc/isDot with 4194/// information about the intrinsic. 4195static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 4196 bool &isDot) { 4197 unsigned IntrinsicID = 4198 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 4199 CompareOpc = -1; 4200 isDot = false; 4201 switch (IntrinsicID) { 4202 default: return false; 4203 // Comparison predicates. 4204 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 4205 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 4206 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 4207 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 4208 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 4209 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 4210 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 4211 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 4212 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 4213 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 4214 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 4215 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 4216 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 4217 4218 // Normal Comparisons. 4219 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 4220 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 4221 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 4222 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 4223 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 4224 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 4225 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 4226 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 4227 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 4228 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 4229 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 4230 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 4231 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 4232 } 4233 return true; 4234} 4235 4236/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 4237/// lower, do it, otherwise return null. 4238SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 4239 SelectionDAG &DAG) const { 4240 // If this is a lowered altivec predicate compare, CompareOpc is set to the 4241 // opcode number of the comparison. 4242 DebugLoc dl = Op.getDebugLoc(); 4243 int CompareOpc; 4244 bool isDot; 4245 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 4246 return SDValue(); // Don't custom lower most intrinsics. 4247 4248 // If this is a non-dot comparison, make the VCMP node and we are done. 4249 if (!isDot) { 4250 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 4251 Op.getOperand(1), Op.getOperand(2), 4252 DAG.getConstant(CompareOpc, MVT::i32)); 4253 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp); 4254 } 4255 4256 // Create the PPCISD altivec 'dot' comparison node. 4257 SDValue Ops[] = { 4258 Op.getOperand(2), // LHS 4259 Op.getOperand(3), // RHS 4260 DAG.getConstant(CompareOpc, MVT::i32) 4261 }; 4262 std::vector<EVT> VTs; 4263 VTs.push_back(Op.getOperand(2).getValueType()); 4264 VTs.push_back(MVT::Flag); 4265 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 4266 4267 // Now that we have the comparison, emit a copy from the CR to a GPR. 4268 // This is flagged to the above dot comparison. 4269 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 4270 DAG.getRegister(PPC::CR6, MVT::i32), 4271 CompNode.getValue(1)); 4272 4273 // Unpack the result based on how the target uses it. 4274 unsigned BitNo; // Bit # of CR6. 4275 bool InvertBit; // Invert result? 4276 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 4277 default: // Can't happen, don't crash on invalid number though. 4278 case 0: // Return the value of the EQ bit of CR6. 4279 BitNo = 0; InvertBit = false; 4280 break; 4281 case 1: // Return the inverted value of the EQ bit of CR6. 4282 BitNo = 0; InvertBit = true; 4283 break; 4284 case 2: // Return the value of the LT bit of CR6. 4285 BitNo = 2; InvertBit = false; 4286 break; 4287 case 3: // Return the inverted value of the LT bit of CR6. 4288 BitNo = 2; InvertBit = true; 4289 break; 4290 } 4291 4292 // Shift the bit into the low position. 4293 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 4294 DAG.getConstant(8-(3-BitNo), MVT::i32)); 4295 // Isolate the bit. 4296 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 4297 DAG.getConstant(1, MVT::i32)); 4298 4299 // If we are supposed to, toggle the bit. 4300 if (InvertBit) 4301 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 4302 DAG.getConstant(1, MVT::i32)); 4303 return Flags; 4304} 4305 4306SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 4307 SelectionDAG &DAG) const { 4308 DebugLoc dl = Op.getDebugLoc(); 4309 // Create a stack slot that is 16-byte aligned. 4310 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4311 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 4312 EVT PtrVT = getPointerTy(); 4313 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4314 4315 // Store the input value into Value#0 of the stack slot. 4316 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 4317 Op.getOperand(0), FIdx, MachinePointerInfo(), 4318 false, false, 0); 4319 // Load it out. 4320 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), 4321 false, false, 0); 4322} 4323 4324SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 4325 DebugLoc dl = Op.getDebugLoc(); 4326 if (Op.getValueType() == MVT::v4i32) { 4327 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4328 4329 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 4330 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 4331 4332 SDValue RHSSwap = // = vrlw RHS, 16 4333 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 4334 4335 // Shrinkify inputs to v8i16. 4336 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS); 4337 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS); 4338 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap); 4339 4340 // Low parts multiplied together, generating 32-bit results (we ignore the 4341 // top parts). 4342 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 4343 LHS, RHS, DAG, dl, MVT::v4i32); 4344 4345 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 4346 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 4347 // Shift the high parts up 16 bits. 4348 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 4349 Neg16, DAG, dl); 4350 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 4351 } else if (Op.getValueType() == MVT::v8i16) { 4352 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4353 4354 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 4355 4356 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 4357 LHS, RHS, Zero, DAG, dl); 4358 } else if (Op.getValueType() == MVT::v16i8) { 4359 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4360 4361 // Multiply the even 8-bit parts, producing 16-bit sums. 4362 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 4363 LHS, RHS, DAG, dl, MVT::v8i16); 4364 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts); 4365 4366 // Multiply the odd 8-bit parts, producing 16-bit sums. 4367 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 4368 LHS, RHS, DAG, dl, MVT::v8i16); 4369 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts); 4370 4371 // Merge the results together. 4372 int Ops[16]; 4373 for (unsigned i = 0; i != 8; ++i) { 4374 Ops[i*2 ] = 2*i+1; 4375 Ops[i*2+1] = 2*i+1+16; 4376 } 4377 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 4378 } else { 4379 llvm_unreachable("Unknown mul to lower!"); 4380 } 4381} 4382 4383/// LowerOperation - Provide custom lowering hooks for some operations. 4384/// 4385SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4386 switch (Op.getOpcode()) { 4387 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 4388 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4389 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4390 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 4391 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 4392 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 4393 case ISD::SETCC: return LowerSETCC(Op, DAG); 4394 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 4395 case ISD::VASTART: 4396 return LowerVASTART(Op, DAG, PPCSubTarget); 4397 4398 case ISD::VAARG: 4399 return LowerVAARG(Op, DAG, PPCSubTarget); 4400 4401 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 4402 case ISD::DYNAMIC_STACKALLOC: 4403 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 4404 4405 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4406 case ISD::FP_TO_UINT: 4407 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 4408 Op.getDebugLoc()); 4409 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 4410 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4411 4412 // Lower 64-bit shifts. 4413 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 4414 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 4415 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 4416 4417 // Vector-related lowering. 4418 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 4419 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4420 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 4421 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 4422 case ISD::MUL: return LowerMUL(Op, DAG); 4423 4424 // Frame & Return address. 4425 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4426 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4427 } 4428 return SDValue(); 4429} 4430 4431void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 4432 SmallVectorImpl<SDValue>&Results, 4433 SelectionDAG &DAG) const { 4434 DebugLoc dl = N->getDebugLoc(); 4435 switch (N->getOpcode()) { 4436 default: 4437 assert(false && "Do not know how to custom type legalize this operation!"); 4438 return; 4439 case ISD::FP_ROUND_INREG: { 4440 assert(N->getValueType(0) == MVT::ppcf128); 4441 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 4442 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4443 MVT::f64, N->getOperand(0), 4444 DAG.getIntPtrConstant(0)); 4445 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4446 MVT::f64, N->getOperand(0), 4447 DAG.getIntPtrConstant(1)); 4448 4449 // This sequence changes FPSCR to do round-to-zero, adds the two halves 4450 // of the long double, and puts FPSCR back the way it was. We do not 4451 // actually model FPSCR. 4452 std::vector<EVT> NodeTys; 4453 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 4454 4455 NodeTys.push_back(MVT::f64); // Return register 4456 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 4457 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4458 MFFSreg = Result.getValue(0); 4459 InFlag = Result.getValue(1); 4460 4461 NodeTys.clear(); 4462 NodeTys.push_back(MVT::Flag); // Returns a flag 4463 Ops[0] = DAG.getConstant(31, MVT::i32); 4464 Ops[1] = InFlag; 4465 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 4466 InFlag = Result.getValue(0); 4467 4468 NodeTys.clear(); 4469 NodeTys.push_back(MVT::Flag); // Returns a flag 4470 Ops[0] = DAG.getConstant(30, MVT::i32); 4471 Ops[1] = InFlag; 4472 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 4473 InFlag = Result.getValue(0); 4474 4475 NodeTys.clear(); 4476 NodeTys.push_back(MVT::f64); // result of add 4477 NodeTys.push_back(MVT::Flag); // Returns a flag 4478 Ops[0] = Lo; 4479 Ops[1] = Hi; 4480 Ops[2] = InFlag; 4481 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 4482 FPreg = Result.getValue(0); 4483 InFlag = Result.getValue(1); 4484 4485 NodeTys.clear(); 4486 NodeTys.push_back(MVT::f64); 4487 Ops[0] = DAG.getConstant(1, MVT::i32); 4488 Ops[1] = MFFSreg; 4489 Ops[2] = FPreg; 4490 Ops[3] = InFlag; 4491 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 4492 FPreg = Result.getValue(0); 4493 4494 // We know the low half is about to be thrown away, so just use something 4495 // convenient. 4496 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 4497 FPreg, FPreg)); 4498 return; 4499 } 4500 case ISD::FP_TO_SINT: 4501 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 4502 return; 4503 } 4504} 4505 4506 4507//===----------------------------------------------------------------------===// 4508// Other Lowering Code 4509//===----------------------------------------------------------------------===// 4510 4511MachineBasicBlock * 4512PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 4513 bool is64bit, unsigned BinOpcode) const { 4514 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4515 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4516 4517 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4518 MachineFunction *F = BB->getParent(); 4519 MachineFunction::iterator It = BB; 4520 ++It; 4521 4522 unsigned dest = MI->getOperand(0).getReg(); 4523 unsigned ptrA = MI->getOperand(1).getReg(); 4524 unsigned ptrB = MI->getOperand(2).getReg(); 4525 unsigned incr = MI->getOperand(3).getReg(); 4526 DebugLoc dl = MI->getDebugLoc(); 4527 4528 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4529 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4530 F->insert(It, loopMBB); 4531 F->insert(It, exitMBB); 4532 exitMBB->splice(exitMBB->begin(), BB, 4533 llvm::next(MachineBasicBlock::iterator(MI)), 4534 BB->end()); 4535 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4536 4537 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4538 unsigned TmpReg = (!BinOpcode) ? incr : 4539 RegInfo.createVirtualRegister( 4540 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4541 (const TargetRegisterClass *) &PPC::GPRCRegClass); 4542 4543 // thisMBB: 4544 // ... 4545 // fallthrough --> loopMBB 4546 BB->addSuccessor(loopMBB); 4547 4548 // loopMBB: 4549 // l[wd]arx dest, ptr 4550 // add r0, dest, incr 4551 // st[wd]cx. r0, ptr 4552 // bne- loopMBB 4553 // fallthrough --> exitMBB 4554 BB = loopMBB; 4555 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4556 .addReg(ptrA).addReg(ptrB); 4557 if (BinOpcode) 4558 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 4559 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4560 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 4561 BuildMI(BB, dl, TII->get(PPC::BCC)) 4562 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4563 BB->addSuccessor(loopMBB); 4564 BB->addSuccessor(exitMBB); 4565 4566 // exitMBB: 4567 // ... 4568 BB = exitMBB; 4569 return BB; 4570} 4571 4572MachineBasicBlock * 4573PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 4574 MachineBasicBlock *BB, 4575 bool is8bit, // operation 4576 unsigned BinOpcode) const { 4577 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4578 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4579 // In 64 bit mode we have to use 64 bits for addresses, even though the 4580 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 4581 // registers without caring whether they're 32 or 64, but here we're 4582 // doing actual arithmetic on the addresses. 4583 bool is64bit = PPCSubTarget.isPPC64(); 4584 4585 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4586 MachineFunction *F = BB->getParent(); 4587 MachineFunction::iterator It = BB; 4588 ++It; 4589 4590 unsigned dest = MI->getOperand(0).getReg(); 4591 unsigned ptrA = MI->getOperand(1).getReg(); 4592 unsigned ptrB = MI->getOperand(2).getReg(); 4593 unsigned incr = MI->getOperand(3).getReg(); 4594 DebugLoc dl = MI->getDebugLoc(); 4595 4596 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4597 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4598 F->insert(It, loopMBB); 4599 F->insert(It, exitMBB); 4600 exitMBB->splice(exitMBB->begin(), BB, 4601 llvm::next(MachineBasicBlock::iterator(MI)), 4602 BB->end()); 4603 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4604 4605 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4606 const TargetRegisterClass *RC = 4607 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4608 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4609 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4610 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4611 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4612 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 4613 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4614 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4615 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4616 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4617 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 4618 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4619 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4620 unsigned Ptr1Reg; 4621 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 4622 4623 // thisMBB: 4624 // ... 4625 // fallthrough --> loopMBB 4626 BB->addSuccessor(loopMBB); 4627 4628 // The 4-byte load must be aligned, while a char or short may be 4629 // anywhere in the word. Hence all this nasty bookkeeping code. 4630 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4631 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4632 // xori shift, shift1, 24 [16] 4633 // rlwinm ptr, ptr1, 0, 0, 29 4634 // slw incr2, incr, shift 4635 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4636 // slw mask, mask2, shift 4637 // loopMBB: 4638 // lwarx tmpDest, ptr 4639 // add tmp, tmpDest, incr2 4640 // andc tmp2, tmpDest, mask 4641 // and tmp3, tmp, mask 4642 // or tmp4, tmp3, tmp2 4643 // stwcx. tmp4, ptr 4644 // bne- loopMBB 4645 // fallthrough --> exitMBB 4646 // srw dest, tmpDest, shift 4647 4648 if (ptrA!=PPC::R0) { 4649 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4650 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4651 .addReg(ptrA).addReg(ptrB); 4652 } else { 4653 Ptr1Reg = ptrB; 4654 } 4655 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4656 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4657 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4658 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4659 if (is64bit) 4660 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4661 .addReg(Ptr1Reg).addImm(0).addImm(61); 4662 else 4663 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4664 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4665 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 4666 .addReg(incr).addReg(ShiftReg); 4667 if (is8bit) 4668 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4669 else { 4670 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4671 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 4672 } 4673 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 4674 .addReg(Mask2Reg).addReg(ShiftReg); 4675 4676 BB = loopMBB; 4677 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 4678 .addReg(PPC::R0).addReg(PtrReg); 4679 if (BinOpcode) 4680 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 4681 .addReg(Incr2Reg).addReg(TmpDestReg); 4682 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 4683 .addReg(TmpDestReg).addReg(MaskReg); 4684 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 4685 .addReg(TmpReg).addReg(MaskReg); 4686 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 4687 .addReg(Tmp3Reg).addReg(Tmp2Reg); 4688 BuildMI(BB, dl, TII->get(PPC::STWCX)) 4689 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg); 4690 BuildMI(BB, dl, TII->get(PPC::BCC)) 4691 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4692 BB->addSuccessor(loopMBB); 4693 BB->addSuccessor(exitMBB); 4694 4695 // exitMBB: 4696 // ... 4697 BB = exitMBB; 4698 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg); 4699 return BB; 4700} 4701 4702MachineBasicBlock * 4703PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4704 MachineBasicBlock *BB) const { 4705 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4706 4707 // To "insert" these instructions we actually have to insert their 4708 // control-flow patterns. 4709 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4710 MachineFunction::iterator It = BB; 4711 ++It; 4712 4713 MachineFunction *F = BB->getParent(); 4714 4715 if (MI->getOpcode() == PPC::SELECT_CC_I4 || 4716 MI->getOpcode() == PPC::SELECT_CC_I8 || 4717 MI->getOpcode() == PPC::SELECT_CC_F4 || 4718 MI->getOpcode() == PPC::SELECT_CC_F8 || 4719 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 4720 4721 // The incoming instruction knows the destination vreg to set, the 4722 // condition code register to branch on, the true/false values to 4723 // select between, and a branch opcode to use. 4724 4725 // thisMBB: 4726 // ... 4727 // TrueVal = ... 4728 // cmpTY ccX, r1, r2 4729 // bCC copy1MBB 4730 // fallthrough --> copy0MBB 4731 MachineBasicBlock *thisMBB = BB; 4732 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4733 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4734 unsigned SelectPred = MI->getOperand(4).getImm(); 4735 DebugLoc dl = MI->getDebugLoc(); 4736 F->insert(It, copy0MBB); 4737 F->insert(It, sinkMBB); 4738 4739 // Transfer the remainder of BB and its successor edges to sinkMBB. 4740 sinkMBB->splice(sinkMBB->begin(), BB, 4741 llvm::next(MachineBasicBlock::iterator(MI)), 4742 BB->end()); 4743 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4744 4745 // Next, add the true and fallthrough blocks as its successors. 4746 BB->addSuccessor(copy0MBB); 4747 BB->addSuccessor(sinkMBB); 4748 4749 BuildMI(BB, dl, TII->get(PPC::BCC)) 4750 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 4751 4752 // copy0MBB: 4753 // %FalseValue = ... 4754 // # fallthrough to sinkMBB 4755 BB = copy0MBB; 4756 4757 // Update machine-CFG edges 4758 BB->addSuccessor(sinkMBB); 4759 4760 // sinkMBB: 4761 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4762 // ... 4763 BB = sinkMBB; 4764 BuildMI(*BB, BB->begin(), dl, 4765 TII->get(PPC::PHI), MI->getOperand(0).getReg()) 4766 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 4767 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4768 } 4769 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 4770 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 4771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 4772 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 4773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 4774 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 4775 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 4776 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 4777 4778 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 4779 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 4780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 4781 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 4782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 4783 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 4784 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 4785 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 4786 4787 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 4788 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 4789 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 4790 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 4791 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 4792 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 4793 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 4794 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 4795 4796 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 4797 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 4798 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 4799 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 4800 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 4801 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 4802 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 4803 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 4804 4805 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 4806 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 4807 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 4808 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 4809 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 4810 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 4811 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 4812 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 4813 4814 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 4815 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 4816 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 4817 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 4818 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 4819 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 4820 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 4821 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 4822 4823 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 4824 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 4825 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 4826 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 4827 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 4828 BB = EmitAtomicBinary(MI, BB, false, 0); 4829 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 4830 BB = EmitAtomicBinary(MI, BB, true, 0); 4831 4832 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 4833 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 4834 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 4835 4836 unsigned dest = MI->getOperand(0).getReg(); 4837 unsigned ptrA = MI->getOperand(1).getReg(); 4838 unsigned ptrB = MI->getOperand(2).getReg(); 4839 unsigned oldval = MI->getOperand(3).getReg(); 4840 unsigned newval = MI->getOperand(4).getReg(); 4841 DebugLoc dl = MI->getDebugLoc(); 4842 4843 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4844 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4845 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4846 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4847 F->insert(It, loop1MBB); 4848 F->insert(It, loop2MBB); 4849 F->insert(It, midMBB); 4850 F->insert(It, exitMBB); 4851 exitMBB->splice(exitMBB->begin(), BB, 4852 llvm::next(MachineBasicBlock::iterator(MI)), 4853 BB->end()); 4854 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4855 4856 // thisMBB: 4857 // ... 4858 // fallthrough --> loopMBB 4859 BB->addSuccessor(loop1MBB); 4860 4861 // loop1MBB: 4862 // l[wd]arx dest, ptr 4863 // cmp[wd] dest, oldval 4864 // bne- midMBB 4865 // loop2MBB: 4866 // st[wd]cx. newval, ptr 4867 // bne- loopMBB 4868 // b exitBB 4869 // midMBB: 4870 // st[wd]cx. dest, ptr 4871 // exitBB: 4872 BB = loop1MBB; 4873 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4874 .addReg(ptrA).addReg(ptrB); 4875 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 4876 .addReg(oldval).addReg(dest); 4877 BuildMI(BB, dl, TII->get(PPC::BCC)) 4878 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4879 BB->addSuccessor(loop2MBB); 4880 BB->addSuccessor(midMBB); 4881 4882 BB = loop2MBB; 4883 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4884 .addReg(newval).addReg(ptrA).addReg(ptrB); 4885 BuildMI(BB, dl, TII->get(PPC::BCC)) 4886 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 4887 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 4888 BB->addSuccessor(loop1MBB); 4889 BB->addSuccessor(exitMBB); 4890 4891 BB = midMBB; 4892 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4893 .addReg(dest).addReg(ptrA).addReg(ptrB); 4894 BB->addSuccessor(exitMBB); 4895 4896 // exitMBB: 4897 // ... 4898 BB = exitMBB; 4899 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 4900 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 4901 // We must use 64-bit registers for addresses when targeting 64-bit, 4902 // since we're actually doing arithmetic on them. Other registers 4903 // can be 32-bit. 4904 bool is64bit = PPCSubTarget.isPPC64(); 4905 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 4906 4907 unsigned dest = MI->getOperand(0).getReg(); 4908 unsigned ptrA = MI->getOperand(1).getReg(); 4909 unsigned ptrB = MI->getOperand(2).getReg(); 4910 unsigned oldval = MI->getOperand(3).getReg(); 4911 unsigned newval = MI->getOperand(4).getReg(); 4912 DebugLoc dl = MI->getDebugLoc(); 4913 4914 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4915 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4916 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4917 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4918 F->insert(It, loop1MBB); 4919 F->insert(It, loop2MBB); 4920 F->insert(It, midMBB); 4921 F->insert(It, exitMBB); 4922 exitMBB->splice(exitMBB->begin(), BB, 4923 llvm::next(MachineBasicBlock::iterator(MI)), 4924 BB->end()); 4925 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4926 4927 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4928 const TargetRegisterClass *RC = 4929 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4930 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4931 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4932 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4933 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4934 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 4935 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 4936 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 4937 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 4938 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4939 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4940 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4941 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4942 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4943 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4944 unsigned Ptr1Reg; 4945 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 4946 // thisMBB: 4947 // ... 4948 // fallthrough --> loopMBB 4949 BB->addSuccessor(loop1MBB); 4950 4951 // The 4-byte load must be aligned, while a char or short may be 4952 // anywhere in the word. Hence all this nasty bookkeeping code. 4953 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4954 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4955 // xori shift, shift1, 24 [16] 4956 // rlwinm ptr, ptr1, 0, 0, 29 4957 // slw newval2, newval, shift 4958 // slw oldval2, oldval,shift 4959 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4960 // slw mask, mask2, shift 4961 // and newval3, newval2, mask 4962 // and oldval3, oldval2, mask 4963 // loop1MBB: 4964 // lwarx tmpDest, ptr 4965 // and tmp, tmpDest, mask 4966 // cmpw tmp, oldval3 4967 // bne- midMBB 4968 // loop2MBB: 4969 // andc tmp2, tmpDest, mask 4970 // or tmp4, tmp2, newval3 4971 // stwcx. tmp4, ptr 4972 // bne- loop1MBB 4973 // b exitBB 4974 // midMBB: 4975 // stwcx. tmpDest, ptr 4976 // exitBB: 4977 // srw dest, tmpDest, shift 4978 if (ptrA!=PPC::R0) { 4979 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4980 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4981 .addReg(ptrA).addReg(ptrB); 4982 } else { 4983 Ptr1Reg = ptrB; 4984 } 4985 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4986 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4987 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4988 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4989 if (is64bit) 4990 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4991 .addReg(Ptr1Reg).addImm(0).addImm(61); 4992 else 4993 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4994 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4995 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 4996 .addReg(newval).addReg(ShiftReg); 4997 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 4998 .addReg(oldval).addReg(ShiftReg); 4999 if (is8bit) 5000 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 5001 else { 5002 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 5003 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 5004 .addReg(Mask3Reg).addImm(65535); 5005 } 5006 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5007 .addReg(Mask2Reg).addReg(ShiftReg); 5008 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 5009 .addReg(NewVal2Reg).addReg(MaskReg); 5010 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 5011 .addReg(OldVal2Reg).addReg(MaskReg); 5012 5013 BB = loop1MBB; 5014 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5015 .addReg(PPC::R0).addReg(PtrReg); 5016 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 5017 .addReg(TmpDestReg).addReg(MaskReg); 5018 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 5019 .addReg(TmpReg).addReg(OldVal3Reg); 5020 BuildMI(BB, dl, TII->get(PPC::BCC)) 5021 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 5022 BB->addSuccessor(loop2MBB); 5023 BB->addSuccessor(midMBB); 5024 5025 BB = loop2MBB; 5026 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 5027 .addReg(TmpDestReg).addReg(MaskReg); 5028 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 5029 .addReg(Tmp2Reg).addReg(NewVal3Reg); 5030 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 5031 .addReg(PPC::R0).addReg(PtrReg); 5032 BuildMI(BB, dl, TII->get(PPC::BCC)) 5033 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5034 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5035 BB->addSuccessor(loop1MBB); 5036 BB->addSuccessor(exitMBB); 5037 5038 BB = midMBB; 5039 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 5040 .addReg(PPC::R0).addReg(PtrReg); 5041 BB->addSuccessor(exitMBB); 5042 5043 // exitMBB: 5044 // ... 5045 BB = exitMBB; 5046 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); 5047 } else { 5048 llvm_unreachable("Unexpected instr type to insert"); 5049 } 5050 5051 MI->eraseFromParent(); // The pseudo instruction is gone now. 5052 return BB; 5053} 5054 5055//===----------------------------------------------------------------------===// 5056// Target Optimization Hooks 5057//===----------------------------------------------------------------------===// 5058 5059SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 5060 DAGCombinerInfo &DCI) const { 5061 const TargetMachine &TM = getTargetMachine(); 5062 SelectionDAG &DAG = DCI.DAG; 5063 DebugLoc dl = N->getDebugLoc(); 5064 switch (N->getOpcode()) { 5065 default: break; 5066 case PPCISD::SHL: 5067 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5068 if (C->isNullValue()) // 0 << V -> 0. 5069 return N->getOperand(0); 5070 } 5071 break; 5072 case PPCISD::SRL: 5073 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5074 if (C->isNullValue()) // 0 >>u V -> 0. 5075 return N->getOperand(0); 5076 } 5077 break; 5078 case PPCISD::SRA: 5079 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5080 if (C->isNullValue() || // 0 >>s V -> 0. 5081 C->isAllOnesValue()) // -1 >>s V -> -1. 5082 return N->getOperand(0); 5083 } 5084 break; 5085 5086 case ISD::SINT_TO_FP: 5087 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 5088 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 5089 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 5090 // We allow the src/dst to be either f32/f64, but the intermediate 5091 // type must be i64. 5092 if (N->getOperand(0).getValueType() == MVT::i64 && 5093 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 5094 SDValue Val = N->getOperand(0).getOperand(0); 5095 if (Val.getValueType() == MVT::f32) { 5096 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5097 DCI.AddToWorklist(Val.getNode()); 5098 } 5099 5100 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 5101 DCI.AddToWorklist(Val.getNode()); 5102 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 5103 DCI.AddToWorklist(Val.getNode()); 5104 if (N->getValueType(0) == MVT::f32) { 5105 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 5106 DAG.getIntPtrConstant(0)); 5107 DCI.AddToWorklist(Val.getNode()); 5108 } 5109 return Val; 5110 } else if (N->getOperand(0).getValueType() == MVT::i32) { 5111 // If the intermediate type is i32, we can avoid the load/store here 5112 // too. 5113 } 5114 } 5115 } 5116 break; 5117 case ISD::STORE: 5118 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 5119 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 5120 !cast<StoreSDNode>(N)->isTruncatingStore() && 5121 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 5122 N->getOperand(1).getValueType() == MVT::i32 && 5123 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 5124 SDValue Val = N->getOperand(1).getOperand(0); 5125 if (Val.getValueType() == MVT::f32) { 5126 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5127 DCI.AddToWorklist(Val.getNode()); 5128 } 5129 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 5130 DCI.AddToWorklist(Val.getNode()); 5131 5132 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 5133 N->getOperand(2), N->getOperand(3)); 5134 DCI.AddToWorklist(Val.getNode()); 5135 return Val; 5136 } 5137 5138 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 5139 if (cast<StoreSDNode>(N)->isUnindexed() && 5140 N->getOperand(1).getOpcode() == ISD::BSWAP && 5141 N->getOperand(1).getNode()->hasOneUse() && 5142 (N->getOperand(1).getValueType() == MVT::i32 || 5143 N->getOperand(1).getValueType() == MVT::i16)) { 5144 SDValue BSwapOp = N->getOperand(1).getOperand(0); 5145 // Do an any-extend to 32-bits if this is a half-word input. 5146 if (BSwapOp.getValueType() == MVT::i16) 5147 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 5148 5149 SDValue Ops[] = { 5150 N->getOperand(0), BSwapOp, N->getOperand(2), 5151 DAG.getValueType(N->getOperand(1).getValueType()) 5152 }; 5153 return 5154 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 5155 Ops, array_lengthof(Ops), 5156 cast<StoreSDNode>(N)->getMemoryVT(), 5157 cast<StoreSDNode>(N)->getMemOperand()); 5158 } 5159 break; 5160 case ISD::BSWAP: 5161 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 5162 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 5163 N->getOperand(0).hasOneUse() && 5164 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 5165 SDValue Load = N->getOperand(0); 5166 LoadSDNode *LD = cast<LoadSDNode>(Load); 5167 // Create the byte-swapping load. 5168 SDValue Ops[] = { 5169 LD->getChain(), // Chain 5170 LD->getBasePtr(), // Ptr 5171 DAG.getValueType(N->getValueType(0)) // VT 5172 }; 5173 SDValue BSLoad = 5174 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 5175 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 5176 LD->getMemoryVT(), LD->getMemOperand()); 5177 5178 // If this is an i16 load, insert the truncate. 5179 SDValue ResVal = BSLoad; 5180 if (N->getValueType(0) == MVT::i16) 5181 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 5182 5183 // First, combine the bswap away. This makes the value produced by the 5184 // load dead. 5185 DCI.CombineTo(N, ResVal); 5186 5187 // Next, combine the load away, we give it a bogus result value but a real 5188 // chain result. The result value is dead because the bswap is dead. 5189 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 5190 5191 // Return N so it doesn't get rechecked! 5192 return SDValue(N, 0); 5193 } 5194 5195 break; 5196 case PPCISD::VCMP: { 5197 // If a VCMPo node already exists with exactly the same operands as this 5198 // node, use its result instead of this node (VCMPo computes both a CR6 and 5199 // a normal output). 5200 // 5201 if (!N->getOperand(0).hasOneUse() && 5202 !N->getOperand(1).hasOneUse() && 5203 !N->getOperand(2).hasOneUse()) { 5204 5205 // Scan all of the users of the LHS, looking for VCMPo's that match. 5206 SDNode *VCMPoNode = 0; 5207 5208 SDNode *LHSN = N->getOperand(0).getNode(); 5209 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 5210 UI != E; ++UI) 5211 if (UI->getOpcode() == PPCISD::VCMPo && 5212 UI->getOperand(1) == N->getOperand(1) && 5213 UI->getOperand(2) == N->getOperand(2) && 5214 UI->getOperand(0) == N->getOperand(0)) { 5215 VCMPoNode = *UI; 5216 break; 5217 } 5218 5219 // If there is no VCMPo node, or if the flag value has a single use, don't 5220 // transform this. 5221 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 5222 break; 5223 5224 // Look at the (necessarily single) use of the flag value. If it has a 5225 // chain, this transformation is more complex. Note that multiple things 5226 // could use the value result, which we should ignore. 5227 SDNode *FlagUser = 0; 5228 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 5229 FlagUser == 0; ++UI) { 5230 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 5231 SDNode *User = *UI; 5232 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 5233 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 5234 FlagUser = User; 5235 break; 5236 } 5237 } 5238 } 5239 5240 // If the user is a MFCR instruction, we know this is safe. Otherwise we 5241 // give up for right now. 5242 if (FlagUser->getOpcode() == PPCISD::MFCR) 5243 return SDValue(VCMPoNode, 0); 5244 } 5245 break; 5246 } 5247 case ISD::BR_CC: { 5248 // If this is a branch on an altivec predicate comparison, lower this so 5249 // that we don't have to do a MFCR: instead, branch directly on CR6. This 5250 // lowering is done pre-legalize, because the legalizer lowers the predicate 5251 // compare down to code that is difficult to reassemble. 5252 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 5253 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 5254 int CompareOpc; 5255 bool isDot; 5256 5257 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 5258 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 5259 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 5260 assert(isDot && "Can't compare against a vector result!"); 5261 5262 // If this is a comparison against something other than 0/1, then we know 5263 // that the condition is never/always true. 5264 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 5265 if (Val != 0 && Val != 1) { 5266 if (CC == ISD::SETEQ) // Cond never true, remove branch. 5267 return N->getOperand(0); 5268 // Always !=, turn it into an unconditional branch. 5269 return DAG.getNode(ISD::BR, dl, MVT::Other, 5270 N->getOperand(0), N->getOperand(4)); 5271 } 5272 5273 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 5274 5275 // Create the PPCISD altivec 'dot' comparison node. 5276 std::vector<EVT> VTs; 5277 SDValue Ops[] = { 5278 LHS.getOperand(2), // LHS of compare 5279 LHS.getOperand(3), // RHS of compare 5280 DAG.getConstant(CompareOpc, MVT::i32) 5281 }; 5282 VTs.push_back(LHS.getOperand(2).getValueType()); 5283 VTs.push_back(MVT::Flag); 5284 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5285 5286 // Unpack the result based on how the target uses it. 5287 PPC::Predicate CompOpc; 5288 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 5289 default: // Can't happen, don't crash on invalid number though. 5290 case 0: // Branch on the value of the EQ bit of CR6. 5291 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 5292 break; 5293 case 1: // Branch on the inverted value of the EQ bit of CR6. 5294 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 5295 break; 5296 case 2: // Branch on the value of the LT bit of CR6. 5297 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 5298 break; 5299 case 3: // Branch on the inverted value of the LT bit of CR6. 5300 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 5301 break; 5302 } 5303 5304 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 5305 DAG.getConstant(CompOpc, MVT::i32), 5306 DAG.getRegister(PPC::CR6, MVT::i32), 5307 N->getOperand(4), CompNode.getValue(1)); 5308 } 5309 break; 5310 } 5311 } 5312 5313 return SDValue(); 5314} 5315 5316//===----------------------------------------------------------------------===// 5317// Inline Assembly Support 5318//===----------------------------------------------------------------------===// 5319 5320void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 5321 const APInt &Mask, 5322 APInt &KnownZero, 5323 APInt &KnownOne, 5324 const SelectionDAG &DAG, 5325 unsigned Depth) const { 5326 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 5327 switch (Op.getOpcode()) { 5328 default: break; 5329 case PPCISD::LBRX: { 5330 // lhbrx is known to have the top bits cleared out. 5331 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 5332 KnownZero = 0xFFFF0000; 5333 break; 5334 } 5335 case ISD::INTRINSIC_WO_CHAIN: { 5336 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 5337 default: break; 5338 case Intrinsic::ppc_altivec_vcmpbfp_p: 5339 case Intrinsic::ppc_altivec_vcmpeqfp_p: 5340 case Intrinsic::ppc_altivec_vcmpequb_p: 5341 case Intrinsic::ppc_altivec_vcmpequh_p: 5342 case Intrinsic::ppc_altivec_vcmpequw_p: 5343 case Intrinsic::ppc_altivec_vcmpgefp_p: 5344 case Intrinsic::ppc_altivec_vcmpgtfp_p: 5345 case Intrinsic::ppc_altivec_vcmpgtsb_p: 5346 case Intrinsic::ppc_altivec_vcmpgtsh_p: 5347 case Intrinsic::ppc_altivec_vcmpgtsw_p: 5348 case Intrinsic::ppc_altivec_vcmpgtub_p: 5349 case Intrinsic::ppc_altivec_vcmpgtuh_p: 5350 case Intrinsic::ppc_altivec_vcmpgtuw_p: 5351 KnownZero = ~1U; // All bits but the low one are known to be zero. 5352 break; 5353 } 5354 } 5355 } 5356} 5357 5358 5359/// getConstraintType - Given a constraint, return the type of 5360/// constraint it is for this target. 5361PPCTargetLowering::ConstraintType 5362PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 5363 if (Constraint.size() == 1) { 5364 switch (Constraint[0]) { 5365 default: break; 5366 case 'b': 5367 case 'r': 5368 case 'f': 5369 case 'v': 5370 case 'y': 5371 return C_RegisterClass; 5372 } 5373 } 5374 return TargetLowering::getConstraintType(Constraint); 5375} 5376 5377/// Examine constraint type and operand type and determine a weight value. 5378/// This object must already have been set up with the operand type 5379/// and the current alternative constraint selected. 5380TargetLowering::ConstraintWeight 5381PPCTargetLowering::getSingleConstraintMatchWeight( 5382 AsmOperandInfo &info, const char *constraint) const { 5383 ConstraintWeight weight = CW_Invalid; 5384 Value *CallOperandVal = info.CallOperandVal; 5385 // If we don't have a value, we can't do a match, 5386 // but allow it at the lowest weight. 5387 if (CallOperandVal == NULL) 5388 return CW_Default; 5389 const Type *type = CallOperandVal->getType(); 5390 // Look at the constraint type. 5391 switch (*constraint) { 5392 default: 5393 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 5394 break; 5395 case 'b': 5396 if (type->isIntegerTy()) 5397 weight = CW_Register; 5398 break; 5399 case 'f': 5400 if (type->isFloatTy()) 5401 weight = CW_Register; 5402 break; 5403 case 'd': 5404 if (type->isDoubleTy()) 5405 weight = CW_Register; 5406 break; 5407 case 'v': 5408 if (type->isVectorTy()) 5409 weight = CW_Register; 5410 break; 5411 case 'y': 5412 weight = CW_Register; 5413 break; 5414 } 5415 return weight; 5416} 5417 5418std::pair<unsigned, const TargetRegisterClass*> 5419PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5420 EVT VT) const { 5421 if (Constraint.size() == 1) { 5422 // GCC RS6000 Constraint Letters 5423 switch (Constraint[0]) { 5424 case 'b': // R1-R31 5425 case 'r': // R0-R31 5426 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 5427 return std::make_pair(0U, PPC::G8RCRegisterClass); 5428 return std::make_pair(0U, PPC::GPRCRegisterClass); 5429 case 'f': 5430 if (VT == MVT::f32) 5431 return std::make_pair(0U, PPC::F4RCRegisterClass); 5432 else if (VT == MVT::f64) 5433 return std::make_pair(0U, PPC::F8RCRegisterClass); 5434 break; 5435 case 'v': 5436 return std::make_pair(0U, PPC::VRRCRegisterClass); 5437 case 'y': // crrc 5438 return std::make_pair(0U, PPC::CRRCRegisterClass); 5439 } 5440 } 5441 5442 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5443} 5444 5445 5446/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5447/// vector. If it is invalid, don't add anything to Ops. 5448void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, 5449 std::vector<SDValue>&Ops, 5450 SelectionDAG &DAG) const { 5451 SDValue Result(0,0); 5452 switch (Letter) { 5453 default: break; 5454 case 'I': 5455 case 'J': 5456 case 'K': 5457 case 'L': 5458 case 'M': 5459 case 'N': 5460 case 'O': 5461 case 'P': { 5462 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 5463 if (!CST) return; // Must be an immediate to match. 5464 unsigned Value = CST->getZExtValue(); 5465 switch (Letter) { 5466 default: llvm_unreachable("Unknown constraint letter!"); 5467 case 'I': // "I" is a signed 16-bit constant. 5468 if ((short)Value == (int)Value) 5469 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5470 break; 5471 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 5472 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 5473 if ((short)Value == 0) 5474 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5475 break; 5476 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 5477 if ((Value >> 16) == 0) 5478 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5479 break; 5480 case 'M': // "M" is a constant that is greater than 31. 5481 if (Value > 31) 5482 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5483 break; 5484 case 'N': // "N" is a positive constant that is an exact power of two. 5485 if ((int)Value > 0 && isPowerOf2_32(Value)) 5486 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5487 break; 5488 case 'O': // "O" is the constant zero. 5489 if (Value == 0) 5490 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5491 break; 5492 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 5493 if ((short)-Value == (int)-Value) 5494 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5495 break; 5496 } 5497 break; 5498 } 5499 } 5500 5501 if (Result.getNode()) { 5502 Ops.push_back(Result); 5503 return; 5504 } 5505 5506 // Handle standard constraint letters. 5507 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); 5508} 5509 5510// isLegalAddressingMode - Return true if the addressing mode represented 5511// by AM is legal for this target, for a load/store of the specified type. 5512bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 5513 const Type *Ty) const { 5514 // FIXME: PPC does not allow r+i addressing modes for vectors! 5515 5516 // PPC allows a sign-extended 16-bit immediate field. 5517 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 5518 return false; 5519 5520 // No global is ever allowed as a base. 5521 if (AM.BaseGV) 5522 return false; 5523 5524 // PPC only support r+r, 5525 switch (AM.Scale) { 5526 case 0: // "r+i" or just "i", depending on HasBaseReg. 5527 break; 5528 case 1: 5529 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 5530 return false; 5531 // Otherwise we have r+r or r+i. 5532 break; 5533 case 2: 5534 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 5535 return false; 5536 // Allow 2*r as r+r. 5537 break; 5538 default: 5539 // No other scales are supported. 5540 return false; 5541 } 5542 5543 return true; 5544} 5545 5546/// isLegalAddressImmediate - Return true if the integer value can be used 5547/// as the offset of the target addressing mode for load / store of the 5548/// given type. 5549bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 5550 // PPC allows a sign-extended 16-bit immediate field. 5551 return (V > -(1 << 16) && V < (1 << 16)-1); 5552} 5553 5554bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 5555 return false; 5556} 5557 5558SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 5559 SelectionDAG &DAG) const { 5560 MachineFunction &MF = DAG.getMachineFunction(); 5561 MachineFrameInfo *MFI = MF.getFrameInfo(); 5562 MFI->setReturnAddressIsTaken(true); 5563 5564 DebugLoc dl = Op.getDebugLoc(); 5565 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5566 5567 // Make sure the function does not optimize away the store of the RA to 5568 // the stack. 5569 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 5570 FuncInfo->setLRStoreRequired(); 5571 bool isPPC64 = PPCSubTarget.isPPC64(); 5572 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 5573 5574 if (Depth > 0) { 5575 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 5576 SDValue Offset = 5577 5578 DAG.getConstant(PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI), 5579 isPPC64? MVT::i64 : MVT::i32); 5580 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5581 DAG.getNode(ISD::ADD, dl, getPointerTy(), 5582 FrameAddr, Offset), 5583 MachinePointerInfo(), false, false, 0); 5584 } 5585 5586 // Just load the return address off the stack. 5587 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 5588 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5589 RetAddrFI, MachinePointerInfo(), false, false, 0); 5590} 5591 5592SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 5593 SelectionDAG &DAG) const { 5594 DebugLoc dl = Op.getDebugLoc(); 5595 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5596 5597 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 5598 bool isPPC64 = PtrVT == MVT::i64; 5599 5600 MachineFunction &MF = DAG.getMachineFunction(); 5601 MachineFrameInfo *MFI = MF.getFrameInfo(); 5602 MFI->setFrameAddressIsTaken(true); 5603 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) && 5604 MFI->getStackSize() && 5605 !MF.getFunction()->hasFnAttr(Attribute::Naked); 5606 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) : 5607 (is31 ? PPC::R31 : PPC::R1); 5608 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 5609 PtrVT); 5610 while (Depth--) 5611 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 5612 FrameAddr, MachinePointerInfo(), false, false, 0); 5613 return FrameAddr; 5614} 5615 5616bool 5617PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 5618 // The PowerPC target isn't yet aware of offsets. 5619 return false; 5620} 5621 5622/// getOptimalMemOpType - Returns the target specific optimal type for load 5623/// and store operations as a result of memset, memcpy, and memmove 5624/// lowering. If DstAlign is zero that means it's safe to destination 5625/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 5626/// means there isn't a need to check it against alignment requirement, 5627/// probably because the source does not need to be loaded. If 5628/// 'NonScalarIntSafe' is true, that means it's safe to return a 5629/// non-scalar-integer type, e.g. empty string source, constant, or loaded 5630/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 5631/// constant so it does not need to be loaded. 5632/// It returns EVT::Other if the type should be determined using generic 5633/// target-independent logic. 5634EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 5635 unsigned DstAlign, unsigned SrcAlign, 5636 bool NonScalarIntSafe, 5637 bool MemcpyStrSrc, 5638 MachineFunction &MF) const { 5639 if (this->PPCSubTarget.isPPC64()) { 5640 return MVT::i64; 5641 } else { 5642 return MVT::i32; 5643 } 5644} 5645