PPCISelLowering.cpp revision 4db5acaf48c119b2bb7ad93b10dfcfe8b58dcfdb
1cf5933a716e7eb6bd5ff49aa62f3e76379ebaf51Chris Lattner//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman// 3b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell// The LLVM Compiler Infrastructure 4b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman// 8b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell//===----------------------------------------------------------------------===// 9237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner// 10befa499d45ffcc32bd9902518aec18589464e47cChris Lattner// This file implements the PPCISelLowering class. 11befa499d45ffcc32bd9902518aec18589464e47cChris Lattner// 12befa499d45ffcc32bd9902518aec18589464e47cChris Lattner//===----------------------------------------------------------------------===// 13237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner 14237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner#include "PPCISelLowering.h" 15237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner#include "PPCMachineFunctionInfo.h" 1686453c52ba02e743d29c08456e51006500041456Chris Lattner#include "PPCPerfectShuffle.h" 17237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner#include "PPCTargetMachine.h" 1847b14a4a6a455c7be169cfd312fcbe796f0ad426Misha Brukman#include "MCTargetDesc/PPCPredicates.h" 191f67ce4aa3f65619f54c8a3072539da5b0022841Dale Johannesen#include "llvm/ADT/STLExtras.h" 20237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner#include "llvm/ADT/VectorExtras.h" 21237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner#include "llvm/CodeGen/CallingConvLower.h" 22ff2dad312883e5da91fb9f4e3619b7d095867f3bChris Lattner#include "llvm/CodeGen/MachineFrameInfo.h" 236f7426ec2e46bb19cc9f9e75f1c355b35cf12d7dTanya Lattner#include "llvm/CodeGen/MachineFunction.h" 2412f0babca4459c253675700e1d707652d5b6ba17Chris Lattner#include "llvm/CodeGen/MachineInstrBuilder.h" 25237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 26551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/CodeGen/PseudoSourceValue.h" 27551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/CodeGen/SelectionDAG.h" 28ce63ffb52f249b62cdf2d250c128007b13f27e71Daniel Dunbar#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 2912f0babca4459c253675700e1d707652d5b6ba17Chris Lattner#include "llvm/CallingConv.h" 30551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/Constants.h" 31befa499d45ffcc32bd9902518aec18589464e47cChris Lattner#include "llvm/Function.h" 32a51bcb50b0c74adc741361824ef81dbefb715c53Chris Lattner#include "llvm/Intrinsics.h" 33d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke#include "llvm/Support/MathExtras.h" 3486453c52ba02e743d29c08456e51006500041456Chris Lattner#include "llvm/Target/TargetOptions.h" 3586453c52ba02e743d29c08456e51006500041456Chris Lattner#include "llvm/Support/CommandLine.h" 3686453c52ba02e743d29c08456e51006500041456Chris Lattner#include "llvm/Support/ErrorHandling.h" 37844731a7f1909f55935e3514c9e713a62d67662eDan Gohman#include "llvm/Support/raw_ostream.h" 385fee49eff92c2ae2f70eb84d136c31a706560750Dale Johannesen#include "llvm/DerivedTypes.h" 39cbfdf9644ce38fd3404469c26ac3c8466c940b6eDale Johannesenusing namespace llvm; 40237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner 41ae73dc1448d25b02cabc7c64c86c64371453dda8Dan Gohmanstatic bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 42ae73dc1448d25b02cabc7c64c86c64371453dda8Dan Gohman CCValAssign::LocInfo &LocInfo, 43237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner ISD::ArgFlagsTy &ArgFlags, 44ae73dc1448d25b02cabc7c64c86c64371453dda8Dan Gohman CCState &State); 45ae73dc1448d25b02cabc7c64c86c64371453dda8Dan Gohmanstatic bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 46120d053e3ba810b44047fbcb719824bed5673ca9Chris Lattner MVT &LocVT, 47ff2dad312883e5da91fb9f4e3619b7d095867f3bChris Lattner CCValAssign::LocInfo &LocInfo, 48ff2dad312883e5da91fb9f4e3619b7d095867f3bChris Lattner ISD::ArgFlagsTy &ArgFlags, 49ff2dad312883e5da91fb9f4e3619b7d095867f3bChris Lattner CCState &State); 50ff2dad312883e5da91fb9f4e3619b7d095867f3bChris Lattnerstatic bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 51ff2dad312883e5da91fb9f4e3619b7d095867f3bChris Lattner MVT &LocVT, 52ff2dad312883e5da91fb9f4e3619b7d095867f3bChris Lattner CCValAssign::LocInfo &LocInfo, 53ff2dad312883e5da91fb9f4e3619b7d095867f3bChris Lattner ISD::ArgFlagsTy &ArgFlags, 54befa499d45ffcc32bd9902518aec18589464e47cChris Lattner CCState &State); 55befa499d45ffcc32bd9902518aec18589464e47cChris Lattner 561f67ce4aa3f65619f54c8a3072539da5b0022841Dale Johannesenstatic cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 5716581bf931c0ccf2f8993397acfa4e1d509a68dcDale Johannesencl::desc("enable preincrement load/store generation on PPC (experimental)"), 5802a436c48ecff9e34d50ce0a2f861e5acdd9bf3fDan Gohman cl::Hidden); 59befa499d45ffcc32bd9902518aec18589464e47cChris Lattner 6066c75aaa028683c389c55b377ee2411b61081677Bill Wendlingstatic TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 6166c75aaa028683c389c55b377ee2411b61081677Bill Wendling if (TM.getSubtargetImpl()->isDarwin()) 6212f0babca4459c253675700e1d707652d5b6ba17Chris Lattner return new TargetLoweringObjectFileMachO(); 6312f0babca4459c253675700e1d707652d5b6ba17Chris Lattner 64fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman return new TargetLoweringObjectFileELF(); 658c1604e7d617622cb391f1c679ddf70ea03baedcBill Wendling} 668c1604e7d617622cb391f1c679ddf70ea03baedcBill Wendling 678c1604e7d617622cb391f1c679ddf70ea03baedcBill WendlingPPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 688c1604e7d617622cb391f1c679ddf70ea03baedcBill Wendling : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 698c1604e7d617622cb391f1c679ddf70ea03baedcBill Wendling 708c1604e7d617622cb391f1c679ddf70ea03baedcBill Wendling setPow2DivIsCheap(); 718c1604e7d617622cb391f1c679ddf70ea03baedcBill Wendling 728c1604e7d617622cb391f1c679ddf70ea03baedcBill Wendling // Use _setjmp/_longjmp instead of setjmp/longjmp. 7354970c032815edadb1b2988ea33f5a1173e5b29cChris Lattner setUseUnderscoreSetJmp(true); 7454970c032815edadb1b2988ea33f5a1173e5b29cChris Lattner setUseUnderscoreLongJmp(true); 75135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 76135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all 77befa499d45ffcc32bd9902518aec18589464e47cChris Lattner // arguments are at least 4/8 bytes aligned. 78ce63ffb52f249b62cdf2d250c128007b13f27e71Daniel Dunbar setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4); 79ce63ffb52f249b62cdf2d250c128007b13f27e71Daniel Dunbar 806f0a7687ab9a0509e847279fae27554ce7da0ba1Duncan Sands // Set up the register classes. 81fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 82befa499d45ffcc32bd9902518aec18589464e47cChris Lattner addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 836f0a7687ab9a0509e847279fae27554ce7da0ba1Duncan Sands addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 84fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman 851f67ce4aa3f65619f54c8a3072539da5b0022841Dale Johannesen // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 861f67ce4aa3f65619f54c8a3072539da5b0022841Dale Johannesen setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 87befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 88befa499d45ffcc32bd9902518aec18589464e47cChris Lattner 89befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setTruncStoreAction(MVT::f64, MVT::f32, Expand); 90befa499d45ffcc32bd9902518aec18589464e47cChris Lattner 91befa499d45ffcc32bd9902518aec18589464e47cChris Lattner // PowerPC has pre-inc load and store's. 92237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 931a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 941a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 951a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 961a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 97c5e1ec47c719806fcc882470595960512edc7441Daniel Dunbar setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 981a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 99c5e1ec47c719806fcc882470595960512edc7441Daniel Dunbar setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 10084a832f9272ed7f1a47c3e019c770b62e373cc6cBill Wendling setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 10184a832f9272ed7f1a47c3e019c770b62e373cc6cBill Wendling setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 102c5e1ec47c719806fcc882470595960512edc7441Daniel Dunbar 103c5e1ec47c719806fcc882470595960512edc7441Daniel Dunbar // This is used in the ppcf128->int sequence. Note it has different semantics 104c5e1ec47c719806fcc882470595960512edc7441Daniel Dunbar // from FP_ROUND: that rounds to nearest, this rounds to zero. 105c5e1ec47c719806fcc882470595960512edc7441Daniel Dunbar setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 10684a832f9272ed7f1a47c3e019c770b62e373cc6cBill Wendling 10784a832f9272ed7f1a47c3e019c770b62e373cc6cBill Wendling // PowerPC has no SREM/UREM instructions 108c5e1ec47c719806fcc882470595960512edc7441Daniel Dunbar setOperationAction(ISD::SREM, MVT::i32, Expand); 109c5e1ec47c719806fcc882470595960512edc7441Daniel Dunbar setOperationAction(ISD::UREM, MVT::i32, Expand); 110c5e1ec47c719806fcc882470595960512edc7441Daniel Dunbar setOperationAction(ISD::SREM, MVT::i64, Expand); 111c5e1ec47c719806fcc882470595960512edc7441Daniel Dunbar setOperationAction(ISD::UREM, MVT::i64, Expand); 1121a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar 1131a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 11484a832f9272ed7f1a47c3e019c770b62e373cc6cBill Wendling setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 11584a832f9272ed7f1a47c3e019c770b62e373cc6cBill Wendling setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 11684a832f9272ed7f1a47c3e019c770b62e373cc6cBill Wendling setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 1171a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 1181a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 119135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 1201a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 12184a832f9272ed7f1a47c3e019c770b62e373cc6cBill Wendling setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 12284a832f9272ed7f1a47c3e019c770b62e373cc6cBill Wendling 1231a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar // We don't support sin/cos/sqrt/fmod/pow 1241a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar setOperationAction(ISD::FSIN , MVT::f64, Expand); 125135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::FCOS , MVT::f64, Expand); 126135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::FREM , MVT::f64, Expand); 127135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::FPOW , MVT::f64, Expand); 128135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::FMA , MVT::f64, Expand); 1291a99dbfe3b70c83d3f3e4648b5868c04697cd77cDaniel Dunbar setOperationAction(ISD::FSIN , MVT::f32, Expand); 130237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner setOperationAction(ISD::FCOS , MVT::f32, Expand); 131237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner setOperationAction(ISD::FREM , MVT::f32, Expand); 132237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner setOperationAction(ISD::FPOW , MVT::f32, Expand); 13302a436c48ecff9e34d50ce0a2f861e5acdd9bf3fDan Gohman setOperationAction(ISD::FMA , MVT::f32, Expand); 134237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner 13516581bf931c0ccf2f8993397acfa4e1d509a68dcDale Johannesen setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 13684a832f9272ed7f1a47c3e019c770b62e373cc6cBill Wendling 137237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner // If we're enabling GP optimizations, use hardware square root 138befa499d45ffcc32bd9902518aec18589464e47cChris Lattner if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 139befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::FSQRT, MVT::f64, Expand); 140ce63ffb52f249b62cdf2d250c128007b13f27e71Daniel Dunbar setOperationAction(ISD::FSQRT, MVT::f32, Expand); 141237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner } 142237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner 143befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 144befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 145befa499d45ffcc32bd9902518aec18589464e47cChris Lattner 146befa499d45ffcc32bd9902518aec18589464e47cChris Lattner // PowerPC does not have BSWAP, CTPOP or CTTZ 147befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 148135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 149135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 150135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 151135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 152135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 153135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 154135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // PowerPC does not have ROTR 155135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::ROTR, MVT::i32 , Expand); 156135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::ROTR, MVT::i64 , Expand); 157135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 158135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // PowerPC does not have Select 159135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::SELECT, MVT::i32, Expand); 160135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::SELECT, MVT::i64, Expand); 161135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::SELECT, MVT::f32, Expand); 162135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::SELECT, MVT::f64, Expand); 163237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner 16484a832f9272ed7f1a47c3e019c770b62e373cc6cBill Wendling // PowerPC wants to turn select_cc of FP into fsel when possible. 165fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 166befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 167befa499d45ffcc32bd9902518aec18589464e47cChris Lattner 168befa499d45ffcc32bd9902518aec18589464e47cChris Lattner // PowerPC wants to optimize integer setcc a bit 169befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::SETCC, MVT::i32, Custom); 170befa499d45ffcc32bd9902518aec18589464e47cChris Lattner 171befa499d45ffcc32bd9902518aec18589464e47cChris Lattner // PowerPC does not have BRCOND which requires SetCC 172befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::BRCOND, MVT::Other, Expand); 173fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman 174befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::BR_JT, MVT::Other, Expand); 175befa499d45ffcc32bd9902518aec18589464e47cChris Lattner 176befa499d45ffcc32bd9902518aec18589464e47cChris Lattner // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 177befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 178befa499d45ffcc32bd9902518aec18589464e47cChris Lattner 179befa499d45ffcc32bd9902518aec18589464e47cChris Lattner // PowerPC does not have [U|S]INT_TO_FP 180befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 181befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 182135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 183135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::BITCAST, MVT::f32, Expand); 184135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::BITCAST, MVT::i32, Expand); 185135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::BITCAST, MVT::i64, Expand); 186135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::BITCAST, MVT::f64, Expand); 187135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 188135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // We cannot sextinreg(i1). Expand to shifts. 189135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 190135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 191135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 192135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 193135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 194135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 195befa499d45ffcc32bd9902518aec18589464e47cChris Lattner 196135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 197135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // We want to legalize GlobalAddress and ConstantPool nodes into the 198135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // appropriate instructions to materialize the address. 199befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 200135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 201135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 202135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 203135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::JumpTable, MVT::i32, Custom); 204135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 205135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 206135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 207135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 208135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::JumpTable, MVT::i64, Custom); 209135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 210135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // TRAP is legal. 211135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::TRAP, MVT::Other, Legal); 212135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 213135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // TRAMPOLINE is custom lowered. 214135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 215135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 216135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // VASTART needs to be custom lowered to use the VarArgsFrameIndex 217135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::VASTART , MVT::Other, Custom); 218135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 219135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // VAARG is custom lowered with the 32-bit SVR4 ABI. 220135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 221135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner && !TM.getSubtarget<PPCSubtarget>().isPPC64()) { 222135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::VAARG, MVT::Other, Custom); 223135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::VAARG, MVT::i64, Custom); 224135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner } else 225237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner setOperationAction(ISD::VAARG, MVT::Other, Expand); 226135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 227135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // Use the default implementation. 228135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::VACOPY , MVT::Other, Expand); 229135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::VAEND , MVT::Other, Expand); 230135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 231135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 232befa499d45ffcc32bd9902518aec18589464e47cChris Lattner setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 233237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 234775cbdd51a3b33dd5eb343689f65ab5cc8ac7118Chris Lattner 235237ef567f6764f24a47c63121cc0a599ddc8f56dChris Lattner // We want to custom lower some of our intrinsics. 236d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 23768d57e7ae80044401efd889270a12c71b3efb9abChris Lattner 23868d57e7ae80044401efd889270a12c71b3efb9abChris Lattner // Comparisons that require checking two conditions. 23968d57e7ae80044401efd889270a12c71b3efb9abChris Lattner setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 240b7c6bf1e073088635951435acedff793add1cefdDevang Patel setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 241b7c6bf1e073088635951435acedff793add1cefdDevang Patel setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 242b7c6bf1e073088635951435acedff793add1cefdDevang Patel setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 243135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 244135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 245b7c6bf1e073088635951435acedff793add1cefdDevang Patel setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 246135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 247135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 2483e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 2493e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 2503e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 2513e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner 2523e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 253135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // They also have instructions for converting between i64 and fp. 254135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 255135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 256135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 257135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 258135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // This is just the low 32 bits of a (signed) fp->i64 conversion. 259135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // We cannot do this with Promote because i64 is not a legal type. 260135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 261135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 262135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // FIXME: disable this lowered code. This generates 64-bit register values, 263135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // and we don't model the fact that the top part is clobbered by calls. We 264135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // need to flag these together so that the value isn't live across a call. 265135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 266135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner } else { 267135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // PowerPC does not have FP_TO_UINT on 32-bit implementations. 268135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 269135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner } 270135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 271135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 272135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // 64-bit PowerPC implementations can support i64 types directly 273135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 274135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 275135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 276fd93908ae8b9684fe71c239e3c6cfe13ff6a2663Misha Brukman // 64-bit PowerPC wants to expand i128 shifts itself. 277135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 278135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 27968d57e7ae80044401efd889270a12c71b3efb9abChris Lattner setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 2803e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner } else { 2813e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner // 32-bit PowerPC wants to expand i64 shifts itself. 2823e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 2833e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 284135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 285135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner } 286135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner 287135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 2883e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner // First set operation action for all vector types to expand. Then we 289135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner // will selectively turn on ones that can be effectively codegen'd. 290135755dae4c3fa8003b76150689d5064aa4612eeChris Lattner for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 2911f67ce4aa3f65619f54c8a3072539da5b0022841Dale Johannesen i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 2923e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 2933e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner 2943e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner // add/sub are legal for all supported vector VT's. 2953e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner setOperationAction(ISD::ADD , VT, Legal); 2963e1358a9fa1ebd3f51c94eb69da55d693895fe7cChris Lattner setOperationAction(ISD::SUB , VT, Legal); 29768d57e7ae80044401efd889270a12c71b3efb9abChris Lattner 29868d57e7ae80044401efd889270a12c71b3efb9abChris Lattner // We promote all shuffles to v16i8. 299 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 300 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 301 302 // We promote all non-typed operations to v4i32. 303 setOperationAction(ISD::AND , VT, Promote); 304 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 305 setOperationAction(ISD::OR , VT, Promote); 306 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 307 setOperationAction(ISD::XOR , VT, Promote); 308 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 309 setOperationAction(ISD::LOAD , VT, Promote); 310 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 311 setOperationAction(ISD::SELECT, VT, Promote); 312 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 313 setOperationAction(ISD::STORE, VT, Promote); 314 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 315 316 // No other operations are legal. 317 setOperationAction(ISD::MUL , VT, Expand); 318 setOperationAction(ISD::SDIV, VT, Expand); 319 setOperationAction(ISD::SREM, VT, Expand); 320 setOperationAction(ISD::UDIV, VT, Expand); 321 setOperationAction(ISD::UREM, VT, Expand); 322 setOperationAction(ISD::FDIV, VT, Expand); 323 setOperationAction(ISD::FNEG, VT, Expand); 324 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 325 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 326 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 327 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 328 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 329 setOperationAction(ISD::UDIVREM, VT, Expand); 330 setOperationAction(ISD::SDIVREM, VT, Expand); 331 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 332 setOperationAction(ISD::FPOW, VT, Expand); 333 setOperationAction(ISD::CTPOP, VT, Expand); 334 setOperationAction(ISD::CTLZ, VT, Expand); 335 setOperationAction(ISD::CTTZ, VT, Expand); 336 } 337 338 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 339 // with merges, splats, etc. 340 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 341 342 setOperationAction(ISD::AND , MVT::v4i32, Legal); 343 setOperationAction(ISD::OR , MVT::v4i32, Legal); 344 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 345 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 346 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 347 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 348 349 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 350 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 351 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 352 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 353 354 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 355 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 356 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 357 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 358 359 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 360 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 361 362 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 363 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 364 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 365 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 366 } 367 368 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 369 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 370 371 setBooleanContents(ZeroOrOneBooleanContent); 372 373 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 374 setStackPointerRegisterToSaveRestore(PPC::X1); 375 setExceptionPointerRegister(PPC::X3); 376 setExceptionSelectorRegister(PPC::X4); 377 } else { 378 setStackPointerRegisterToSaveRestore(PPC::R1); 379 setExceptionPointerRegister(PPC::R3); 380 setExceptionSelectorRegister(PPC::R4); 381 } 382 383 // We have target-specific dag combine patterns for the following nodes: 384 setTargetDAGCombine(ISD::SINT_TO_FP); 385 setTargetDAGCombine(ISD::STORE); 386 setTargetDAGCombine(ISD::BR_CC); 387 setTargetDAGCombine(ISD::BSWAP); 388 389 // Darwin long double math library functions have $LDBL128 appended. 390 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 391 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 392 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 393 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 394 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 395 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 396 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 397 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 398 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 399 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 400 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 401 } 402 403 setMinFunctionAlignment(2); 404 if (PPCSubTarget.isDarwin()) 405 setPrefFunctionAlignment(4); 406 407 setInsertFencesForAtomic(true); 408 409 computeRegisterProperties(); 410} 411 412/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 413/// function arguments in the caller parameter area. 414unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const { 415 const TargetMachine &TM = getTargetMachine(); 416 // Darwin passes everything on 4 byte boundary. 417 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 418 return 4; 419 // FIXME SVR4 TBD 420 return 4; 421} 422 423const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 424 switch (Opcode) { 425 default: return 0; 426 case PPCISD::FSEL: return "PPCISD::FSEL"; 427 case PPCISD::FCFID: return "PPCISD::FCFID"; 428 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 429 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 430 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 431 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 432 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 433 case PPCISD::VPERM: return "PPCISD::VPERM"; 434 case PPCISD::Hi: return "PPCISD::Hi"; 435 case PPCISD::Lo: return "PPCISD::Lo"; 436 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 437 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 438 case PPCISD::LOAD: return "PPCISD::LOAD"; 439 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 440 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 441 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 442 case PPCISD::SRL: return "PPCISD::SRL"; 443 case PPCISD::SRA: return "PPCISD::SRA"; 444 case PPCISD::SHL: return "PPCISD::SHL"; 445 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 446 case PPCISD::STD_32: return "PPCISD::STD_32"; 447 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 448 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 449 case PPCISD::NOP: return "PPCISD::NOP"; 450 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 451 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 452 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 453 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 454 case PPCISD::MFCR: return "PPCISD::MFCR"; 455 case PPCISD::VCMP: return "PPCISD::VCMP"; 456 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 457 case PPCISD::LBRX: return "PPCISD::LBRX"; 458 case PPCISD::STBRX: return "PPCISD::STBRX"; 459 case PPCISD::LARX: return "PPCISD::LARX"; 460 case PPCISD::STCX: return "PPCISD::STCX"; 461 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 462 case PPCISD::MFFS: return "PPCISD::MFFS"; 463 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 464 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 465 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 466 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 467 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 468 } 469} 470 471MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const { 472 return MVT::i32; 473} 474 475//===----------------------------------------------------------------------===// 476// Node matching predicates, for use by the tblgen matching code. 477//===----------------------------------------------------------------------===// 478 479/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 480static bool isFloatingPointZero(SDValue Op) { 481 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 482 return CFP->getValueAPF().isZero(); 483 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 484 // Maybe this has already been legalized into the constant pool? 485 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 486 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 487 return CFP->getValueAPF().isZero(); 488 } 489 return false; 490} 491 492/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 493/// true if Op is undef or if it matches the specified value. 494static bool isConstantOrUndef(int Op, int Val) { 495 return Op < 0 || Op == Val; 496} 497 498/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 499/// VPKUHUM instruction. 500bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 501 if (!isUnary) { 502 for (unsigned i = 0; i != 16; ++i) 503 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 504 return false; 505 } else { 506 for (unsigned i = 0; i != 8; ++i) 507 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 508 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 509 return false; 510 } 511 return true; 512} 513 514/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 515/// VPKUWUM instruction. 516bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 517 if (!isUnary) { 518 for (unsigned i = 0; i != 16; i += 2) 519 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 520 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 521 return false; 522 } else { 523 for (unsigned i = 0; i != 8; i += 2) 524 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 525 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 526 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 527 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 528 return false; 529 } 530 return true; 531} 532 533/// isVMerge - Common function, used to match vmrg* shuffles. 534/// 535static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 536 unsigned LHSStart, unsigned RHSStart) { 537 assert(N->getValueType(0) == MVT::v16i8 && 538 "PPC only supports shuffles by bytes!"); 539 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 540 "Unsupported merge size!"); 541 542 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 543 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 544 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 545 LHSStart+j+i*UnitSize) || 546 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 547 RHSStart+j+i*UnitSize)) 548 return false; 549 } 550 return true; 551} 552 553/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 554/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 555bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 556 bool isUnary) { 557 if (!isUnary) 558 return isVMerge(N, UnitSize, 8, 24); 559 return isVMerge(N, UnitSize, 8, 8); 560} 561 562/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 563/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 564bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 565 bool isUnary) { 566 if (!isUnary) 567 return isVMerge(N, UnitSize, 0, 16); 568 return isVMerge(N, UnitSize, 0, 0); 569} 570 571 572/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 573/// amount, otherwise return -1. 574int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 575 assert(N->getValueType(0) == MVT::v16i8 && 576 "PPC only supports shuffles by bytes!"); 577 578 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 579 580 // Find the first non-undef value in the shuffle mask. 581 unsigned i; 582 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 583 /*search*/; 584 585 if (i == 16) return -1; // all undef. 586 587 // Otherwise, check to see if the rest of the elements are consecutively 588 // numbered from this value. 589 unsigned ShiftAmt = SVOp->getMaskElt(i); 590 if (ShiftAmt < i) return -1; 591 ShiftAmt -= i; 592 593 if (!isUnary) { 594 // Check the rest of the elements to see if they are consecutive. 595 for (++i; i != 16; ++i) 596 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 597 return -1; 598 } else { 599 // Check the rest of the elements to see if they are consecutive. 600 for (++i; i != 16; ++i) 601 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 602 return -1; 603 } 604 return ShiftAmt; 605} 606 607/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 608/// specifies a splat of a single element that is suitable for input to 609/// VSPLTB/VSPLTH/VSPLTW. 610bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 611 assert(N->getValueType(0) == MVT::v16i8 && 612 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 613 614 // This is a splat operation if each element of the permute is the same, and 615 // if the value doesn't reference the second vector. 616 unsigned ElementBase = N->getMaskElt(0); 617 618 // FIXME: Handle UNDEF elements too! 619 if (ElementBase >= 16) 620 return false; 621 622 // Check that the indices are consecutive, in the case of a multi-byte element 623 // splatted with a v16i8 mask. 624 for (unsigned i = 1; i != EltSize; ++i) 625 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 626 return false; 627 628 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 629 if (N->getMaskElt(i) < 0) continue; 630 for (unsigned j = 0; j != EltSize; ++j) 631 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 632 return false; 633 } 634 return true; 635} 636 637/// isAllNegativeZeroVector - Returns true if all elements of build_vector 638/// are -0.0. 639bool PPC::isAllNegativeZeroVector(SDNode *N) { 640 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 641 642 APInt APVal, APUndef; 643 unsigned BitSize; 644 bool HasAnyUndefs; 645 646 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 647 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 648 return CFP->getValueAPF().isNegZero(); 649 650 return false; 651} 652 653/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 654/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 655unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 656 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 657 assert(isSplatShuffleMask(SVOp, EltSize)); 658 return SVOp->getMaskElt(0) / EltSize; 659} 660 661/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 662/// by using a vspltis[bhw] instruction of the specified element size, return 663/// the constant being splatted. The ByteSize field indicates the number of 664/// bytes of each element [124] -> [bhw]. 665SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 666 SDValue OpVal(0, 0); 667 668 // If ByteSize of the splat is bigger than the element size of the 669 // build_vector, then we have a case where we are checking for a splat where 670 // multiple elements of the buildvector are folded together into a single 671 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 672 unsigned EltSize = 16/N->getNumOperands(); 673 if (EltSize < ByteSize) { 674 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 675 SDValue UniquedVals[4]; 676 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 677 678 // See if all of the elements in the buildvector agree across. 679 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 680 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 681 // If the element isn't a constant, bail fully out. 682 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 683 684 685 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 686 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 687 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 688 return SDValue(); // no match. 689 } 690 691 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 692 // either constant or undef values that are identical for each chunk. See 693 // if these chunks can form into a larger vspltis*. 694 695 // Check to see if all of the leading entries are either 0 or -1. If 696 // neither, then this won't fit into the immediate field. 697 bool LeadingZero = true; 698 bool LeadingOnes = true; 699 for (unsigned i = 0; i != Multiple-1; ++i) { 700 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 701 702 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 703 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 704 } 705 // Finally, check the least significant entry. 706 if (LeadingZero) { 707 if (UniquedVals[Multiple-1].getNode() == 0) 708 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 709 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 710 if (Val < 16) 711 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 712 } 713 if (LeadingOnes) { 714 if (UniquedVals[Multiple-1].getNode() == 0) 715 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 716 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 717 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 718 return DAG.getTargetConstant(Val, MVT::i32); 719 } 720 721 return SDValue(); 722 } 723 724 // Check to see if this buildvec has a single non-undef value in its elements. 725 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 726 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 727 if (OpVal.getNode() == 0) 728 OpVal = N->getOperand(i); 729 else if (OpVal != N->getOperand(i)) 730 return SDValue(); 731 } 732 733 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 734 735 unsigned ValSizeInBytes = EltSize; 736 uint64_t Value = 0; 737 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 738 Value = CN->getZExtValue(); 739 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 740 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 741 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 742 } 743 744 // If the splat value is larger than the element value, then we can never do 745 // this splat. The only case that we could fit the replicated bits into our 746 // immediate field for would be zero, and we prefer to use vxor for it. 747 if (ValSizeInBytes < ByteSize) return SDValue(); 748 749 // If the element value is larger than the splat value, cut it in half and 750 // check to see if the two halves are equal. Continue doing this until we 751 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 752 while (ValSizeInBytes > ByteSize) { 753 ValSizeInBytes >>= 1; 754 755 // If the top half equals the bottom half, we're still ok. 756 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 757 (Value & ((1 << (8*ValSizeInBytes))-1))) 758 return SDValue(); 759 } 760 761 // Properly sign extend the value. 762 int ShAmt = (4-ByteSize)*8; 763 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 764 765 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 766 if (MaskVal == 0) return SDValue(); 767 768 // Finally, if this value fits in a 5 bit sext field, return it 769 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 770 return DAG.getTargetConstant(MaskVal, MVT::i32); 771 return SDValue(); 772} 773 774//===----------------------------------------------------------------------===// 775// Addressing Mode Selection 776//===----------------------------------------------------------------------===// 777 778/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 779/// or 64-bit immediate, and if the value can be accurately represented as a 780/// sign extension from a 16-bit value. If so, this returns true and the 781/// immediate. 782static bool isIntS16Immediate(SDNode *N, short &Imm) { 783 if (N->getOpcode() != ISD::Constant) 784 return false; 785 786 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 787 if (N->getValueType(0) == MVT::i32) 788 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 789 else 790 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 791} 792static bool isIntS16Immediate(SDValue Op, short &Imm) { 793 return isIntS16Immediate(Op.getNode(), Imm); 794} 795 796 797/// SelectAddressRegReg - Given the specified addressed, check to see if it 798/// can be represented as an indexed [r+r] operation. Returns false if it 799/// can be more efficiently represented with [r+imm]. 800bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 801 SDValue &Index, 802 SelectionDAG &DAG) const { 803 short imm = 0; 804 if (N.getOpcode() == ISD::ADD) { 805 if (isIntS16Immediate(N.getOperand(1), imm)) 806 return false; // r+i 807 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 808 return false; // r+i 809 810 Base = N.getOperand(0); 811 Index = N.getOperand(1); 812 return true; 813 } else if (N.getOpcode() == ISD::OR) { 814 if (isIntS16Immediate(N.getOperand(1), imm)) 815 return false; // r+i can fold it if we can. 816 817 // If this is an or of disjoint bitfields, we can codegen this as an add 818 // (for better address arithmetic) if the LHS and RHS of the OR are provably 819 // disjoint. 820 APInt LHSKnownZero, LHSKnownOne; 821 APInt RHSKnownZero, RHSKnownOne; 822 DAG.ComputeMaskedBits(N.getOperand(0), 823 APInt::getAllOnesValue(N.getOperand(0) 824 .getValueSizeInBits()), 825 LHSKnownZero, LHSKnownOne); 826 827 if (LHSKnownZero.getBoolValue()) { 828 DAG.ComputeMaskedBits(N.getOperand(1), 829 APInt::getAllOnesValue(N.getOperand(1) 830 .getValueSizeInBits()), 831 RHSKnownZero, RHSKnownOne); 832 // If all of the bits are known zero on the LHS or RHS, the add won't 833 // carry. 834 if (~(LHSKnownZero | RHSKnownZero) == 0) { 835 Base = N.getOperand(0); 836 Index = N.getOperand(1); 837 return true; 838 } 839 } 840 } 841 842 return false; 843} 844 845/// Returns true if the address N can be represented by a base register plus 846/// a signed 16-bit displacement [r+imm], and if it is not better 847/// represented as reg+reg. 848bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 849 SDValue &Base, 850 SelectionDAG &DAG) const { 851 // FIXME dl should come from parent load or store, not from address 852 DebugLoc dl = N.getDebugLoc(); 853 // If this can be more profitably realized as r+r, fail. 854 if (SelectAddressRegReg(N, Disp, Base, DAG)) 855 return false; 856 857 if (N.getOpcode() == ISD::ADD) { 858 short imm = 0; 859 if (isIntS16Immediate(N.getOperand(1), imm)) { 860 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 861 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 862 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 863 } else { 864 Base = N.getOperand(0); 865 } 866 return true; // [r+i] 867 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 868 // Match LOAD (ADD (X, Lo(G))). 869 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 870 && "Cannot handle constant offsets yet!"); 871 Disp = N.getOperand(1).getOperand(0); // The global address. 872 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 873 Disp.getOpcode() == ISD::TargetConstantPool || 874 Disp.getOpcode() == ISD::TargetJumpTable); 875 Base = N.getOperand(0); 876 return true; // [&g+r] 877 } 878 } else if (N.getOpcode() == ISD::OR) { 879 short imm = 0; 880 if (isIntS16Immediate(N.getOperand(1), imm)) { 881 // If this is an or of disjoint bitfields, we can codegen this as an add 882 // (for better address arithmetic) if the LHS and RHS of the OR are 883 // provably disjoint. 884 APInt LHSKnownZero, LHSKnownOne; 885 DAG.ComputeMaskedBits(N.getOperand(0), 886 APInt::getAllOnesValue(N.getOperand(0) 887 .getValueSizeInBits()), 888 LHSKnownZero, LHSKnownOne); 889 890 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 891 // If all of the bits are known zero on the LHS or RHS, the add won't 892 // carry. 893 Base = N.getOperand(0); 894 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 895 return true; 896 } 897 } 898 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 899 // Loading from a constant address. 900 901 // If this address fits entirely in a 16-bit sext immediate field, codegen 902 // this as "d, 0" 903 short Imm; 904 if (isIntS16Immediate(CN, Imm)) { 905 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 906 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 907 CN->getValueType(0)); 908 return true; 909 } 910 911 // Handle 32-bit sext immediates with LIS + addr mode. 912 if (CN->getValueType(0) == MVT::i32 || 913 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 914 int Addr = (int)CN->getZExtValue(); 915 916 // Otherwise, break this down into an LIS + disp. 917 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 918 919 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 920 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 921 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 922 return true; 923 } 924 } 925 926 Disp = DAG.getTargetConstant(0, getPointerTy()); 927 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 928 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 929 else 930 Base = N; 931 return true; // [r+0] 932} 933 934/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 935/// represented as an indexed [r+r] operation. 936bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 937 SDValue &Index, 938 SelectionDAG &DAG) const { 939 // Check to see if we can easily represent this as an [r+r] address. This 940 // will fail if it thinks that the address is more profitably represented as 941 // reg+imm, e.g. where imm = 0. 942 if (SelectAddressRegReg(N, Base, Index, DAG)) 943 return true; 944 945 // If the operand is an addition, always emit this as [r+r], since this is 946 // better (for code size, and execution, as the memop does the add for free) 947 // than emitting an explicit add. 948 if (N.getOpcode() == ISD::ADD) { 949 Base = N.getOperand(0); 950 Index = N.getOperand(1); 951 return true; 952 } 953 954 // Otherwise, do it the hard way, using R0 as the base register. 955 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 956 N.getValueType()); 957 Index = N; 958 return true; 959} 960 961/// SelectAddressRegImmShift - Returns true if the address N can be 962/// represented by a base register plus a signed 14-bit displacement 963/// [r+imm*4]. Suitable for use by STD and friends. 964bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 965 SDValue &Base, 966 SelectionDAG &DAG) const { 967 // FIXME dl should come from the parent load or store, not the address 968 DebugLoc dl = N.getDebugLoc(); 969 // If this can be more profitably realized as r+r, fail. 970 if (SelectAddressRegReg(N, Disp, Base, DAG)) 971 return false; 972 973 if (N.getOpcode() == ISD::ADD) { 974 short imm = 0; 975 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 976 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 977 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 978 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 979 } else { 980 Base = N.getOperand(0); 981 } 982 return true; // [r+i] 983 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 984 // Match LOAD (ADD (X, Lo(G))). 985 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 986 && "Cannot handle constant offsets yet!"); 987 Disp = N.getOperand(1).getOperand(0); // The global address. 988 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 989 Disp.getOpcode() == ISD::TargetConstantPool || 990 Disp.getOpcode() == ISD::TargetJumpTable); 991 Base = N.getOperand(0); 992 return true; // [&g+r] 993 } 994 } else if (N.getOpcode() == ISD::OR) { 995 short imm = 0; 996 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 997 // If this is an or of disjoint bitfields, we can codegen this as an add 998 // (for better address arithmetic) if the LHS and RHS of the OR are 999 // provably disjoint. 1000 APInt LHSKnownZero, LHSKnownOne; 1001 DAG.ComputeMaskedBits(N.getOperand(0), 1002 APInt::getAllOnesValue(N.getOperand(0) 1003 .getValueSizeInBits()), 1004 LHSKnownZero, LHSKnownOne); 1005 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1006 // If all of the bits are known zero on the LHS or RHS, the add won't 1007 // carry. 1008 Base = N.getOperand(0); 1009 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1010 return true; 1011 } 1012 } 1013 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1014 // Loading from a constant address. Verify low two bits are clear. 1015 if ((CN->getZExtValue() & 3) == 0) { 1016 // If this address fits entirely in a 14-bit sext immediate field, codegen 1017 // this as "d, 0" 1018 short Imm; 1019 if (isIntS16Immediate(CN, Imm)) { 1020 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1021 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1022 CN->getValueType(0)); 1023 return true; 1024 } 1025 1026 // Fold the low-part of 32-bit absolute addresses into addr mode. 1027 if (CN->getValueType(0) == MVT::i32 || 1028 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1029 int Addr = (int)CN->getZExtValue(); 1030 1031 // Otherwise, break this down into an LIS + disp. 1032 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1033 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1034 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1035 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1036 return true; 1037 } 1038 } 1039 } 1040 1041 Disp = DAG.getTargetConstant(0, getPointerTy()); 1042 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1043 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1044 else 1045 Base = N; 1046 return true; // [r+0] 1047} 1048 1049 1050/// getPreIndexedAddressParts - returns true by value, base pointer and 1051/// offset pointer and addressing mode by reference if the node's address 1052/// can be legally represented as pre-indexed load / store address. 1053bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1054 SDValue &Offset, 1055 ISD::MemIndexedMode &AM, 1056 SelectionDAG &DAG) const { 1057 // Disabled by default for now. 1058 if (!EnablePPCPreinc) return false; 1059 1060 SDValue Ptr; 1061 EVT VT; 1062 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1063 Ptr = LD->getBasePtr(); 1064 VT = LD->getMemoryVT(); 1065 1066 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1067 Ptr = ST->getBasePtr(); 1068 VT = ST->getMemoryVT(); 1069 } else 1070 return false; 1071 1072 // PowerPC doesn't have preinc load/store instructions for vectors. 1073 if (VT.isVector()) 1074 return false; 1075 1076 // TODO: Check reg+reg first. 1077 1078 // LDU/STU use reg+imm*4, others use reg+imm. 1079 if (VT != MVT::i64) { 1080 // reg + imm 1081 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1082 return false; 1083 } else { 1084 // reg + imm * 4. 1085 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1086 return false; 1087 } 1088 1089 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1090 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1091 // sext i32 to i64 when addr mode is r+i. 1092 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1093 LD->getExtensionType() == ISD::SEXTLOAD && 1094 isa<ConstantSDNode>(Offset)) 1095 return false; 1096 } 1097 1098 AM = ISD::PRE_INC; 1099 return true; 1100} 1101 1102//===----------------------------------------------------------------------===// 1103// LowerOperation implementation 1104//===----------------------------------------------------------------------===// 1105 1106/// GetLabelAccessInfo - Return true if we should reference labels using a 1107/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. 1108static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, 1109 unsigned &LoOpFlags, const GlobalValue *GV = 0) { 1110 HiOpFlags = PPCII::MO_HA16; 1111 LoOpFlags = PPCII::MO_LO16; 1112 1113 // Don't use the pic base if not in PIC relocation model. Or if we are on a 1114 // non-darwin platform. We don't support PIC on other platforms yet. 1115 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ && 1116 TM.getSubtarget<PPCSubtarget>().isDarwin(); 1117 if (isPIC) { 1118 HiOpFlags |= PPCII::MO_PIC_FLAG; 1119 LoOpFlags |= PPCII::MO_PIC_FLAG; 1120 } 1121 1122 // If this is a reference to a global value that requires a non-lazy-ptr, make 1123 // sure that instruction lowering adds it. 1124 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) { 1125 HiOpFlags |= PPCII::MO_NLP_FLAG; 1126 LoOpFlags |= PPCII::MO_NLP_FLAG; 1127 1128 if (GV->hasHiddenVisibility()) { 1129 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1130 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; 1131 } 1132 } 1133 1134 return isPIC; 1135} 1136 1137static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, 1138 SelectionDAG &DAG) { 1139 EVT PtrVT = HiPart.getValueType(); 1140 SDValue Zero = DAG.getConstant(0, PtrVT); 1141 DebugLoc DL = HiPart.getDebugLoc(); 1142 1143 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero); 1144 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero); 1145 1146 // With PIC, the first instruction is actually "GR+hi(&G)". 1147 if (isPIC) 1148 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1149 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi); 1150 1151 // Generate non-pic code that has direct accesses to the constant pool. 1152 // The address of the global is just (hi(&g)+lo(&g)). 1153 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1154} 1155 1156SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1157 SelectionDAG &DAG) const { 1158 EVT PtrVT = Op.getValueType(); 1159 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1160 const Constant *C = CP->getConstVal(); 1161 1162 unsigned MOHiFlag, MOLoFlag; 1163 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1164 SDValue CPIHi = 1165 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag); 1166 SDValue CPILo = 1167 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag); 1168 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG); 1169} 1170 1171SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1172 EVT PtrVT = Op.getValueType(); 1173 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1174 1175 unsigned MOHiFlag, MOLoFlag; 1176 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1177 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag); 1178 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag); 1179 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG); 1180} 1181 1182SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1183 SelectionDAG &DAG) const { 1184 EVT PtrVT = Op.getValueType(); 1185 1186 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1187 1188 unsigned MOHiFlag, MOLoFlag; 1189 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag); 1190 SDValue TgtBAHi = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOHiFlag); 1191 SDValue TgtBALo = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOLoFlag); 1192 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG); 1193} 1194 1195SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1196 SelectionDAG &DAG) const { 1197 EVT PtrVT = Op.getValueType(); 1198 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1199 DebugLoc DL = GSDN->getDebugLoc(); 1200 const GlobalValue *GV = GSDN->getGlobal(); 1201 1202 // 64-bit SVR4 ABI code is always position-independent. 1203 // The actual address of the GlobalValue is stored in the TOC. 1204 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1205 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset()); 1206 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA, 1207 DAG.getRegister(PPC::X2, MVT::i64)); 1208 } 1209 1210 unsigned MOHiFlag, MOLoFlag; 1211 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV); 1212 1213 SDValue GAHi = 1214 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag); 1215 SDValue GALo = 1216 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); 1217 1218 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG); 1219 1220 // If the global reference is actually to a non-lazy-pointer, we have to do an 1221 // extra load to get the address of the global. 1222 if (MOHiFlag & PPCII::MO_NLP_FLAG) 1223 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(), 1224 false, false, 0); 1225 return Ptr; 1226} 1227 1228SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1229 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1230 DebugLoc dl = Op.getDebugLoc(); 1231 1232 // If we're comparing for equality to zero, expose the fact that this is 1233 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1234 // fold the new nodes. 1235 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1236 if (C->isNullValue() && CC == ISD::SETEQ) { 1237 EVT VT = Op.getOperand(0).getValueType(); 1238 SDValue Zext = Op.getOperand(0); 1239 if (VT.bitsLT(MVT::i32)) { 1240 VT = MVT::i32; 1241 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1242 } 1243 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1244 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1245 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1246 DAG.getConstant(Log2b, MVT::i32)); 1247 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1248 } 1249 // Leave comparisons against 0 and -1 alone for now, since they're usually 1250 // optimized. FIXME: revisit this when we can custom lower all setcc 1251 // optimizations. 1252 if (C->isAllOnesValue() || C->isNullValue()) 1253 return SDValue(); 1254 } 1255 1256 // If we have an integer seteq/setne, turn it into a compare against zero 1257 // by xor'ing the rhs with the lhs, which is faster than setting a 1258 // condition register, reading it back out, and masking the correct bit. The 1259 // normal approach here uses sub to do this instead of xor. Using xor exposes 1260 // the result to other bit-twiddling opportunities. 1261 EVT LHSVT = Op.getOperand(0).getValueType(); 1262 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1263 EVT VT = Op.getValueType(); 1264 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1265 Op.getOperand(1)); 1266 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1267 } 1268 return SDValue(); 1269} 1270 1271SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1272 const PPCSubtarget &Subtarget) const { 1273 SDNode *Node = Op.getNode(); 1274 EVT VT = Node->getValueType(0); 1275 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1276 SDValue InChain = Node->getOperand(0); 1277 SDValue VAListPtr = Node->getOperand(1); 1278 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1279 DebugLoc dl = Node->getDebugLoc(); 1280 1281 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); 1282 1283 // gpr_index 1284 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1285 VAListPtr, MachinePointerInfo(SV), MVT::i8, 1286 false, false, 0); 1287 InChain = GprIndex.getValue(1); 1288 1289 if (VT == MVT::i64) { 1290 // Check if GprIndex is even 1291 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, 1292 DAG.getConstant(1, MVT::i32)); 1293 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, 1294 DAG.getConstant(0, MVT::i32), ISD::SETNE); 1295 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, 1296 DAG.getConstant(1, MVT::i32)); 1297 // Align GprIndex to be even if it isn't 1298 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, 1299 GprIndex); 1300 } 1301 1302 // fpr index is 1 byte after gpr 1303 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1304 DAG.getConstant(1, MVT::i32)); 1305 1306 // fpr 1307 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, 1308 FprPtr, MachinePointerInfo(SV), MVT::i8, 1309 false, false, 0); 1310 InChain = FprIndex.getValue(1); 1311 1312 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1313 DAG.getConstant(8, MVT::i32)); 1314 1315 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, 1316 DAG.getConstant(4, MVT::i32)); 1317 1318 // areas 1319 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, 1320 MachinePointerInfo(), false, false, 0); 1321 InChain = OverflowArea.getValue(1); 1322 1323 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, 1324 MachinePointerInfo(), false, false, 0); 1325 InChain = RegSaveArea.getValue(1); 1326 1327 // select overflow_area if index > 8 1328 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, 1329 DAG.getConstant(8, MVT::i32), ISD::SETLT); 1330 1331 // adjustment constant gpr_index * 4/8 1332 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, 1333 VT.isInteger() ? GprIndex : FprIndex, 1334 DAG.getConstant(VT.isInteger() ? 4 : 8, 1335 MVT::i32)); 1336 1337 // OurReg = RegSaveArea + RegConstant 1338 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea, 1339 RegConstant); 1340 1341 // Floating types are 32 bytes into RegSaveArea 1342 if (VT.isFloatingPoint()) 1343 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg, 1344 DAG.getConstant(32, MVT::i32)); 1345 1346 // increase {f,g}pr_index by 1 (or 2 if VT is i64) 1347 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, 1348 VT.isInteger() ? GprIndex : FprIndex, 1349 DAG.getConstant(VT == MVT::i64 ? 2 : 1, 1350 MVT::i32)); 1351 1352 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1, 1353 VT.isInteger() ? VAListPtr : FprPtr, 1354 MachinePointerInfo(SV), 1355 MVT::i8, false, false, 0); 1356 1357 // determine if we should load from reg_save_area or overflow_area 1358 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea); 1359 1360 // increase overflow_area by 4/8 if gpr/fpr > 8 1361 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea, 1362 DAG.getConstant(VT.isInteger() ? 4 : 8, 1363 MVT::i32)); 1364 1365 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, 1366 OverflowAreaPlusN); 1367 1368 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, 1369 OverflowAreaPtr, 1370 MachinePointerInfo(), 1371 MVT::i32, false, false, 0); 1372 1373 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), false, false, 0); 1374} 1375 1376SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, 1377 SelectionDAG &DAG) const { 1378 SDValue Chain = Op.getOperand(0); 1379 SDValue Trmp = Op.getOperand(1); // trampoline 1380 SDValue FPtr = Op.getOperand(2); // nested function 1381 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1382 DebugLoc dl = Op.getDebugLoc(); 1383 1384 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1385 bool isPPC64 = (PtrVT == MVT::i64); 1386 Type *IntPtrTy = 1387 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType( 1388 *DAG.getContext()); 1389 1390 TargetLowering::ArgListTy Args; 1391 TargetLowering::ArgListEntry Entry; 1392 1393 Entry.Ty = IntPtrTy; 1394 Entry.Node = Trmp; Args.push_back(Entry); 1395 1396 // TrampSize == (isPPC64 ? 48 : 40); 1397 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1398 isPPC64 ? MVT::i64 : MVT::i32); 1399 Args.push_back(Entry); 1400 1401 Entry.Node = FPtr; Args.push_back(Entry); 1402 Entry.Node = Nest; Args.push_back(Entry); 1403 1404 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1405 std::pair<SDValue, SDValue> CallResult = 1406 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()), 1407 false, false, false, false, 0, CallingConv::C, false, 1408 /*isReturnValueUsed=*/true, 1409 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1410 Args, DAG, dl); 1411 1412 SDValue Ops[] = 1413 { CallResult.first, CallResult.second }; 1414 1415 return DAG.getMergeValues(Ops, 2, dl); 1416} 1417 1418SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1419 const PPCSubtarget &Subtarget) const { 1420 MachineFunction &MF = DAG.getMachineFunction(); 1421 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1422 1423 DebugLoc dl = Op.getDebugLoc(); 1424 1425 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1426 // vastart just stores the address of the VarArgsFrameIndex slot into the 1427 // memory location argument. 1428 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1429 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1430 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1431 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 1432 MachinePointerInfo(SV), 1433 false, false, 0); 1434 } 1435 1436 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1437 // We suppose the given va_list is already allocated. 1438 // 1439 // typedef struct { 1440 // char gpr; /* index into the array of 8 GPRs 1441 // * stored in the register save area 1442 // * gpr=0 corresponds to r3, 1443 // * gpr=1 to r4, etc. 1444 // */ 1445 // char fpr; /* index into the array of 8 FPRs 1446 // * stored in the register save area 1447 // * fpr=0 corresponds to f1, 1448 // * fpr=1 to f2, etc. 1449 // */ 1450 // char *overflow_arg_area; 1451 // /* location on stack that holds 1452 // * the next overflow argument 1453 // */ 1454 // char *reg_save_area; 1455 // /* where r3:r10 and f1:f8 (if saved) 1456 // * are stored 1457 // */ 1458 // } va_list[1]; 1459 1460 1461 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1462 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1463 1464 1465 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1466 1467 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1468 PtrVT); 1469 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1470 PtrVT); 1471 1472 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1473 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1474 1475 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1476 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1477 1478 uint64_t FPROffset = 1; 1479 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1480 1481 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1482 1483 // Store first byte : number of int regs 1484 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1485 Op.getOperand(1), 1486 MachinePointerInfo(SV), 1487 MVT::i8, false, false, 0); 1488 uint64_t nextOffset = FPROffset; 1489 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1490 ConstFPROffset); 1491 1492 // Store second byte : number of float regs 1493 SDValue secondStore = 1494 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, 1495 MachinePointerInfo(SV, nextOffset), MVT::i8, 1496 false, false, 0); 1497 nextOffset += StackOffset; 1498 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1499 1500 // Store second word : arguments given on stack 1501 SDValue thirdStore = 1502 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, 1503 MachinePointerInfo(SV, nextOffset), 1504 false, false, 0); 1505 nextOffset += FrameOffset; 1506 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1507 1508 // Store third word : arguments given in registers 1509 return DAG.getStore(thirdStore, dl, FR, nextPtr, 1510 MachinePointerInfo(SV, nextOffset), 1511 false, false, 0); 1512 1513} 1514 1515#include "PPCGenCallingConv.inc" 1516 1517static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 1518 CCValAssign::LocInfo &LocInfo, 1519 ISD::ArgFlagsTy &ArgFlags, 1520 CCState &State) { 1521 return true; 1522} 1523 1524static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 1525 MVT &LocVT, 1526 CCValAssign::LocInfo &LocInfo, 1527 ISD::ArgFlagsTy &ArgFlags, 1528 CCState &State) { 1529 static const unsigned ArgRegs[] = { 1530 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1531 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1532 }; 1533 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1534 1535 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1536 1537 // Skip one register if the first unallocated register has an even register 1538 // number and there are still argument registers available which have not been 1539 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1540 // need to skip a register if RegNum is odd. 1541 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1542 State.AllocateReg(ArgRegs[RegNum]); 1543 } 1544 1545 // Always return false here, as this function only makes sure that the first 1546 // unallocated register has an odd register number and does not actually 1547 // allocate a register for the current argument. 1548 return false; 1549} 1550 1551static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 1552 MVT &LocVT, 1553 CCValAssign::LocInfo &LocInfo, 1554 ISD::ArgFlagsTy &ArgFlags, 1555 CCState &State) { 1556 static const unsigned ArgRegs[] = { 1557 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1558 PPC::F8 1559 }; 1560 1561 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1562 1563 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1564 1565 // If there is only one Floating-point register left we need to put both f64 1566 // values of a split ppc_fp128 value on the stack. 1567 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1568 State.AllocateReg(ArgRegs[RegNum]); 1569 } 1570 1571 // Always return false here, as this function only makes sure that the two f64 1572 // values a ppc_fp128 value is split into are both passed in registers or both 1573 // passed on the stack and does not actually allocate a register for the 1574 // current argument. 1575 return false; 1576} 1577 1578/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1579/// on Darwin. 1580static const unsigned *GetFPR() { 1581 static const unsigned FPR[] = { 1582 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1583 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1584 }; 1585 1586 return FPR; 1587} 1588 1589/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1590/// the stack. 1591static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1592 unsigned PtrByteSize) { 1593 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1594 if (Flags.isByVal()) 1595 ArgSize = Flags.getByValSize(); 1596 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1597 1598 return ArgSize; 1599} 1600 1601SDValue 1602PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1603 CallingConv::ID CallConv, bool isVarArg, 1604 const SmallVectorImpl<ISD::InputArg> 1605 &Ins, 1606 DebugLoc dl, SelectionDAG &DAG, 1607 SmallVectorImpl<SDValue> &InVals) 1608 const { 1609 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 1610 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins, 1611 dl, DAG, InVals); 1612 } else { 1613 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1614 dl, DAG, InVals); 1615 } 1616} 1617 1618SDValue 1619PPCTargetLowering::LowerFormalArguments_SVR4( 1620 SDValue Chain, 1621 CallingConv::ID CallConv, bool isVarArg, 1622 const SmallVectorImpl<ISD::InputArg> 1623 &Ins, 1624 DebugLoc dl, SelectionDAG &DAG, 1625 SmallVectorImpl<SDValue> &InVals) const { 1626 1627 // 32-bit SVR4 ABI Stack Frame Layout: 1628 // +-----------------------------------+ 1629 // +--> | Back chain | 1630 // | +-----------------------------------+ 1631 // | | Floating-point register save area | 1632 // | +-----------------------------------+ 1633 // | | General register save area | 1634 // | +-----------------------------------+ 1635 // | | CR save word | 1636 // | +-----------------------------------+ 1637 // | | VRSAVE save word | 1638 // | +-----------------------------------+ 1639 // | | Alignment padding | 1640 // | +-----------------------------------+ 1641 // | | Vector register save area | 1642 // | +-----------------------------------+ 1643 // | | Local variable space | 1644 // | +-----------------------------------+ 1645 // | | Parameter list area | 1646 // | +-----------------------------------+ 1647 // | | LR save word | 1648 // | +-----------------------------------+ 1649 // SP--> +--- | Back chain | 1650 // +-----------------------------------+ 1651 // 1652 // Specifications: 1653 // System V Application Binary Interface PowerPC Processor Supplement 1654 // AltiVec Technology Programming Interface Manual 1655 1656 MachineFunction &MF = DAG.getMachineFunction(); 1657 MachineFrameInfo *MFI = MF.getFrameInfo(); 1658 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1659 1660 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1661 // Potential tail calls could cause overwriting of argument stack slots. 1662 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1663 unsigned PtrByteSize = 4; 1664 1665 // Assign locations to all of the incoming arguments. 1666 SmallVector<CCValAssign, 16> ArgLocs; 1667 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1668 getTargetMachine(), ArgLocs, *DAG.getContext()); 1669 1670 // Reserve space for the linkage area on the stack. 1671 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 1672 1673 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); 1674 1675 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1676 CCValAssign &VA = ArgLocs[i]; 1677 1678 // Arguments stored in registers. 1679 if (VA.isRegLoc()) { 1680 TargetRegisterClass *RC; 1681 EVT ValVT = VA.getValVT(); 1682 1683 switch (ValVT.getSimpleVT().SimpleTy) { 1684 default: 1685 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1686 case MVT::i32: 1687 RC = PPC::GPRCRegisterClass; 1688 break; 1689 case MVT::f32: 1690 RC = PPC::F4RCRegisterClass; 1691 break; 1692 case MVT::f64: 1693 RC = PPC::F8RCRegisterClass; 1694 break; 1695 case MVT::v16i8: 1696 case MVT::v8i16: 1697 case MVT::v4i32: 1698 case MVT::v4f32: 1699 RC = PPC::VRRCRegisterClass; 1700 break; 1701 } 1702 1703 // Transform the arguments stored in physical registers into virtual ones. 1704 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1705 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1706 1707 InVals.push_back(ArgValue); 1708 } else { 1709 // Argument stored in memory. 1710 assert(VA.isMemLoc()); 1711 1712 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1713 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1714 isImmutable); 1715 1716 // Create load nodes to retrieve arguments from the stack. 1717 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1718 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1719 MachinePointerInfo(), 1720 false, false, 0)); 1721 } 1722 } 1723 1724 // Assign locations to all of the incoming aggregate by value arguments. 1725 // Aggregates passed by value are stored in the local variable space of the 1726 // caller's stack frame, right above the parameter list area. 1727 SmallVector<CCValAssign, 16> ByValArgLocs; 1728 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1729 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 1730 1731 // Reserve stack space for the allocations in CCInfo. 1732 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1733 1734 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal); 1735 1736 // Area that is at least reserved in the caller of this function. 1737 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1738 1739 // Set the size that is at least reserved in caller of this function. Tail 1740 // call optimized function's reserved stack space needs to be aligned so that 1741 // taking the difference between two stack areas will result in an aligned 1742 // stack. 1743 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1744 1745 MinReservedArea = 1746 std::max(MinReservedArea, 1747 PPCFrameLowering::getMinCallFrameSize(false, false)); 1748 1749 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 1750 getStackAlignment(); 1751 unsigned AlignMask = TargetAlign-1; 1752 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1753 1754 FI->setMinReservedArea(MinReservedArea); 1755 1756 SmallVector<SDValue, 8> MemOps; 1757 1758 // If the function takes variable number of arguments, make a frame index for 1759 // the start of the first vararg value... for expansion of llvm.va_start. 1760 if (isVarArg) { 1761 static const unsigned GPArgRegs[] = { 1762 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1763 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1764 }; 1765 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 1766 1767 static const unsigned FPArgRegs[] = { 1768 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1769 PPC::F8 1770 }; 1771 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 1772 1773 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 1774 NumGPArgRegs)); 1775 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 1776 NumFPArgRegs)); 1777 1778 // Make room for NumGPArgRegs and NumFPArgRegs. 1779 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 1780 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 1781 1782 FuncInfo->setVarArgsStackOffset( 1783 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1784 CCInfo.getNextStackOffset(), true)); 1785 1786 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 1787 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1788 1789 // The fixed integer arguments of a variadic function are stored to the 1790 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing 1791 // the result of va_next. 1792 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) { 1793 // Get an existing live-in vreg, or add a new one. 1794 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); 1795 if (!VReg) 1796 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 1797 1798 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1799 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1800 MachinePointerInfo(), false, false, 0); 1801 MemOps.push_back(Store); 1802 // Increment the address by four for the next argument to store 1803 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1804 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1805 } 1806 1807 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 1808 // is set. 1809 // The double arguments are stored to the VarArgsFrameIndex 1810 // on the stack. 1811 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) { 1812 // Get an existing live-in vreg, or add a new one. 1813 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); 1814 if (!VReg) 1815 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 1816 1817 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 1818 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1819 MachinePointerInfo(), false, false, 0); 1820 MemOps.push_back(Store); 1821 // Increment the address by eight for the next argument to store 1822 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1823 PtrVT); 1824 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1825 } 1826 } 1827 1828 if (!MemOps.empty()) 1829 Chain = DAG.getNode(ISD::TokenFactor, dl, 1830 MVT::Other, &MemOps[0], MemOps.size()); 1831 1832 return Chain; 1833} 1834 1835SDValue 1836PPCTargetLowering::LowerFormalArguments_Darwin( 1837 SDValue Chain, 1838 CallingConv::ID CallConv, bool isVarArg, 1839 const SmallVectorImpl<ISD::InputArg> 1840 &Ins, 1841 DebugLoc dl, SelectionDAG &DAG, 1842 SmallVectorImpl<SDValue> &InVals) const { 1843 // TODO: add description of PPC stack frame format, or at least some docs. 1844 // 1845 MachineFunction &MF = DAG.getMachineFunction(); 1846 MachineFrameInfo *MFI = MF.getFrameInfo(); 1847 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1848 1849 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1850 bool isPPC64 = PtrVT == MVT::i64; 1851 // Potential tail calls could cause overwriting of argument stack slots. 1852 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1853 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1854 1855 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 1856 // Area that is at least reserved in caller of this function. 1857 unsigned MinReservedArea = ArgOffset; 1858 1859 static const unsigned GPR_32[] = { // 32-bit registers. 1860 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1861 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1862 }; 1863 static const unsigned GPR_64[] = { // 64-bit registers. 1864 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1865 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1866 }; 1867 1868 static const unsigned *FPR = GetFPR(); 1869 1870 static const unsigned VR[] = { 1871 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1872 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1873 }; 1874 1875 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1876 const unsigned Num_FPR_Regs = 13; 1877 const unsigned Num_VR_Regs = array_lengthof( VR); 1878 1879 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1880 1881 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1882 1883 // In 32-bit non-varargs functions, the stack space for vectors is after the 1884 // stack space for non-vectors. We do not use this space unless we have 1885 // too many vectors to fit in registers, something that only occurs in 1886 // constructed examples:), but we have to walk the arglist to figure 1887 // that out...for the pathological case, compute VecArgOffset as the 1888 // start of the vector parameter area. Computing VecArgOffset is the 1889 // entire point of the following loop. 1890 unsigned VecArgOffset = ArgOffset; 1891 if (!isVarArg && !isPPC64) { 1892 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 1893 ++ArgNo) { 1894 EVT ObjectVT = Ins[ArgNo].VT; 1895 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1896 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1897 1898 if (Flags.isByVal()) { 1899 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 1900 ObjSize = Flags.getByValSize(); 1901 unsigned ArgSize = 1902 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1903 VecArgOffset += ArgSize; 1904 continue; 1905 } 1906 1907 switch(ObjectVT.getSimpleVT().SimpleTy) { 1908 default: llvm_unreachable("Unhandled argument type!"); 1909 case MVT::i32: 1910 case MVT::f32: 1911 VecArgOffset += isPPC64 ? 8 : 4; 1912 break; 1913 case MVT::i64: // PPC64 1914 case MVT::f64: 1915 VecArgOffset += 8; 1916 break; 1917 case MVT::v4f32: 1918 case MVT::v4i32: 1919 case MVT::v8i16: 1920 case MVT::v16i8: 1921 // Nothing to do, we're only looking at Nonvector args here. 1922 break; 1923 } 1924 } 1925 } 1926 // We've found where the vector parameter area in memory is. Skip the 1927 // first 12 parameters; these don't use that memory. 1928 VecArgOffset = ((VecArgOffset+15)/16)*16; 1929 VecArgOffset += 12*16; 1930 1931 // Add DAG nodes to load the arguments or copy them out of registers. On 1932 // entry to a function on PPC, the arguments start after the linkage area, 1933 // although the first ones are often in registers. 1934 1935 SmallVector<SDValue, 8> MemOps; 1936 unsigned nAltivecParamsAtEnd = 0; 1937 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 1938 SDValue ArgVal; 1939 bool needsLoad = false; 1940 EVT ObjectVT = Ins[ArgNo].VT; 1941 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1942 unsigned ArgSize = ObjSize; 1943 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1944 1945 unsigned CurArgOffset = ArgOffset; 1946 1947 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 1948 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 1949 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 1950 if (isVarArg || isPPC64) { 1951 MinReservedArea = ((MinReservedArea+15)/16)*16; 1952 MinReservedArea += CalculateStackSlotSize(ObjectVT, 1953 Flags, 1954 PtrByteSize); 1955 } else nAltivecParamsAtEnd++; 1956 } else 1957 // Calculate min reserved area. 1958 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 1959 Flags, 1960 PtrByteSize); 1961 1962 // FIXME the codegen can be much improved in some cases. 1963 // We do not have to keep everything in memory. 1964 if (Flags.isByVal()) { 1965 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1966 ObjSize = Flags.getByValSize(); 1967 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1968 // Objects of size 1 and 2 are right justified, everything else is 1969 // left justified. This means the memory address is adjusted forwards. 1970 if (ObjSize==1 || ObjSize==2) { 1971 CurArgOffset = CurArgOffset + (4 - ObjSize); 1972 } 1973 // The value of the object is its address. 1974 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 1975 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1976 InVals.push_back(FIN); 1977 if (ObjSize==1 || ObjSize==2) { 1978 if (GPR_idx != Num_GPR_Regs) { 1979 unsigned VReg; 1980 if (isPPC64) 1981 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 1982 else 1983 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1984 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1985 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 1986 MachinePointerInfo(), 1987 ObjSize==1 ? MVT::i8 : MVT::i16, 1988 false, false, 0); 1989 MemOps.push_back(Store); 1990 ++GPR_idx; 1991 } 1992 1993 ArgOffset += PtrByteSize; 1994 1995 continue; 1996 } 1997 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 1998 // Store whatever pieces of the object are in registers 1999 // to memory. ArgVal will be address of the beginning of 2000 // the object. 2001 if (GPR_idx != Num_GPR_Regs) { 2002 unsigned VReg; 2003 if (isPPC64) 2004 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2005 else 2006 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2007 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 2008 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2009 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2010 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2011 MachinePointerInfo(), 2012 false, false, 0); 2013 MemOps.push_back(Store); 2014 ++GPR_idx; 2015 ArgOffset += PtrByteSize; 2016 } else { 2017 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 2018 break; 2019 } 2020 } 2021 continue; 2022 } 2023 2024 switch (ObjectVT.getSimpleVT().SimpleTy) { 2025 default: llvm_unreachable("Unhandled argument type!"); 2026 case MVT::i32: 2027 if (!isPPC64) { 2028 if (GPR_idx != Num_GPR_Regs) { 2029 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2030 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2031 ++GPR_idx; 2032 } else { 2033 needsLoad = true; 2034 ArgSize = PtrByteSize; 2035 } 2036 // All int arguments reserve stack space in the Darwin ABI. 2037 ArgOffset += PtrByteSize; 2038 break; 2039 } 2040 // FALLTHROUGH 2041 case MVT::i64: // PPC64 2042 if (GPR_idx != Num_GPR_Regs) { 2043 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2044 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 2045 2046 if (ObjectVT == MVT::i32) { 2047 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 2048 // value to MVT::i64 and then truncate to the correct register size. 2049 if (Flags.isSExt()) 2050 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 2051 DAG.getValueType(ObjectVT)); 2052 else if (Flags.isZExt()) 2053 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 2054 DAG.getValueType(ObjectVT)); 2055 2056 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 2057 } 2058 2059 ++GPR_idx; 2060 } else { 2061 needsLoad = true; 2062 ArgSize = PtrByteSize; 2063 } 2064 // All int arguments reserve stack space in the Darwin ABI. 2065 ArgOffset += 8; 2066 break; 2067 2068 case MVT::f32: 2069 case MVT::f64: 2070 // Every 4 bytes of argument space consumes one of the GPRs available for 2071 // argument passing. 2072 if (GPR_idx != Num_GPR_Regs) { 2073 ++GPR_idx; 2074 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 2075 ++GPR_idx; 2076 } 2077 if (FPR_idx != Num_FPR_Regs) { 2078 unsigned VReg; 2079 2080 if (ObjectVT == MVT::f32) 2081 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2082 else 2083 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2084 2085 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2086 ++FPR_idx; 2087 } else { 2088 needsLoad = true; 2089 } 2090 2091 // All FP arguments reserve stack space in the Darwin ABI. 2092 ArgOffset += isPPC64 ? 8 : ObjSize; 2093 break; 2094 case MVT::v4f32: 2095 case MVT::v4i32: 2096 case MVT::v8i16: 2097 case MVT::v16i8: 2098 // Note that vector arguments in registers don't reserve stack space, 2099 // except in varargs functions. 2100 if (VR_idx != Num_VR_Regs) { 2101 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2102 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2103 if (isVarArg) { 2104 while ((ArgOffset % 16) != 0) { 2105 ArgOffset += PtrByteSize; 2106 if (GPR_idx != Num_GPR_Regs) 2107 GPR_idx++; 2108 } 2109 ArgOffset += 16; 2110 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2111 } 2112 ++VR_idx; 2113 } else { 2114 if (!isVarArg && !isPPC64) { 2115 // Vectors go after all the nonvectors. 2116 CurArgOffset = VecArgOffset; 2117 VecArgOffset += 16; 2118 } else { 2119 // Vectors are aligned. 2120 ArgOffset = ((ArgOffset+15)/16)*16; 2121 CurArgOffset = ArgOffset; 2122 ArgOffset += 16; 2123 } 2124 needsLoad = true; 2125 } 2126 break; 2127 } 2128 2129 // We need to load the argument to a virtual register if we determined above 2130 // that we ran out of physical registers of the appropriate type. 2131 if (needsLoad) { 2132 int FI = MFI->CreateFixedObject(ObjSize, 2133 CurArgOffset + (ArgSize - ObjSize), 2134 isImmutable); 2135 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2136 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2137 false, false, 0); 2138 } 2139 2140 InVals.push_back(ArgVal); 2141 } 2142 2143 // Set the size that is at least reserved in caller of this function. Tail 2144 // call optimized function's reserved stack space needs to be aligned so that 2145 // taking the difference between two stack areas will result in an aligned 2146 // stack. 2147 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2148 // Add the Altivec parameters at the end, if needed. 2149 if (nAltivecParamsAtEnd) { 2150 MinReservedArea = ((MinReservedArea+15)/16)*16; 2151 MinReservedArea += 16*nAltivecParamsAtEnd; 2152 } 2153 MinReservedArea = 2154 std::max(MinReservedArea, 2155 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2156 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2157 getStackAlignment(); 2158 unsigned AlignMask = TargetAlign-1; 2159 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2160 FI->setMinReservedArea(MinReservedArea); 2161 2162 // If the function takes variable number of arguments, make a frame index for 2163 // the start of the first vararg value... for expansion of llvm.va_start. 2164 if (isVarArg) { 2165 int Depth = ArgOffset; 2166 2167 FuncInfo->setVarArgsFrameIndex( 2168 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2169 Depth, true)); 2170 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2171 2172 // If this function is vararg, store any remaining integer argument regs 2173 // to their spots on the stack so that they may be loaded by deferencing the 2174 // result of va_next. 2175 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2176 unsigned VReg; 2177 2178 if (isPPC64) 2179 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2180 else 2181 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2182 2183 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2184 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2185 MachinePointerInfo(), false, false, 0); 2186 MemOps.push_back(Store); 2187 // Increment the address by four for the next argument to store 2188 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2189 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2190 } 2191 } 2192 2193 if (!MemOps.empty()) 2194 Chain = DAG.getNode(ISD::TokenFactor, dl, 2195 MVT::Other, &MemOps[0], MemOps.size()); 2196 2197 return Chain; 2198} 2199 2200/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus 2201/// linkage area for the Darwin ABI. 2202static unsigned 2203CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2204 bool isPPC64, 2205 bool isVarArg, 2206 unsigned CC, 2207 const SmallVectorImpl<ISD::OutputArg> 2208 &Outs, 2209 const SmallVectorImpl<SDValue> &OutVals, 2210 unsigned &nAltivecParamsAtEnd) { 2211 // Count how many bytes are to be pushed on the stack, including the linkage 2212 // area, and parameter passing area. We start with 24/48 bytes, which is 2213 // prereserved space for [SP][CR][LR][3 x unused]. 2214 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true); 2215 unsigned NumOps = Outs.size(); 2216 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2217 2218 // Add up all the space actually used. 2219 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2220 // they all go in registers, but we must reserve stack space for them for 2221 // possible use by the caller. In varargs or 64-bit calls, parameters are 2222 // assigned stack space in order, with padding so Altivec parameters are 2223 // 16-byte aligned. 2224 nAltivecParamsAtEnd = 0; 2225 for (unsigned i = 0; i != NumOps; ++i) { 2226 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2227 EVT ArgVT = Outs[i].VT; 2228 // Varargs Altivec parameters are padded to a 16 byte boundary. 2229 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2230 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2231 if (!isVarArg && !isPPC64) { 2232 // Non-varargs Altivec parameters go after all the non-Altivec 2233 // parameters; handle those later so we know how much padding we need. 2234 nAltivecParamsAtEnd++; 2235 continue; 2236 } 2237 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2238 NumBytes = ((NumBytes+15)/16)*16; 2239 } 2240 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2241 } 2242 2243 // Allow for Altivec parameters at the end, if needed. 2244 if (nAltivecParamsAtEnd) { 2245 NumBytes = ((NumBytes+15)/16)*16; 2246 NumBytes += 16*nAltivecParamsAtEnd; 2247 } 2248 2249 // The prolog code of the callee may store up to 8 GPR argument registers to 2250 // the stack, allowing va_start to index over them in memory if its varargs. 2251 // Because we cannot tell if this is needed on the caller side, we have to 2252 // conservatively assume that it is needed. As such, make sure we have at 2253 // least enough stack space for the caller to store the 8 GPRs. 2254 NumBytes = std::max(NumBytes, 2255 PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); 2256 2257 // Tail call needs the stack to be aligned. 2258 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) { 2259 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> 2260 getStackAlignment(); 2261 unsigned AlignMask = TargetAlign-1; 2262 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2263 } 2264 2265 return NumBytes; 2266} 2267 2268/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2269/// adjusted to accommodate the arguments for the tailcall. 2270static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2271 unsigned ParamSize) { 2272 2273 if (!isTailCall) return 0; 2274 2275 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2276 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2277 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2278 // Remember only if the new adjustement is bigger. 2279 if (SPDiff < FI->getTailCallSPDelta()) 2280 FI->setTailCallSPDelta(SPDiff); 2281 2282 return SPDiff; 2283} 2284 2285/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2286/// for tail call optimization. Targets which want to do tail call 2287/// optimization should implement this function. 2288bool 2289PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2290 CallingConv::ID CalleeCC, 2291 bool isVarArg, 2292 const SmallVectorImpl<ISD::InputArg> &Ins, 2293 SelectionDAG& DAG) const { 2294 if (!GuaranteedTailCallOpt) 2295 return false; 2296 2297 // Variable argument functions are not supported. 2298 if (isVarArg) 2299 return false; 2300 2301 MachineFunction &MF = DAG.getMachineFunction(); 2302 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2303 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2304 // Functions containing by val parameters are not supported. 2305 for (unsigned i = 0; i != Ins.size(); i++) { 2306 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2307 if (Flags.isByVal()) return false; 2308 } 2309 2310 // Non PIC/GOT tail calls are supported. 2311 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2312 return true; 2313 2314 // At the moment we can only do local tail calls (in same module, hidden 2315 // or protected) if we are generating PIC. 2316 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2317 return G->getGlobal()->hasHiddenVisibility() 2318 || G->getGlobal()->hasProtectedVisibility(); 2319 } 2320 2321 return false; 2322} 2323 2324/// isCallCompatibleAddress - Return the immediate to use if the specified 2325/// 32-bit value is representable in the immediate field of a BxA instruction. 2326static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2327 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2328 if (!C) return 0; 2329 2330 int Addr = C->getZExtValue(); 2331 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2332 (Addr << 6 >> 6) != Addr) 2333 return 0; // Top 6 bits have to be sext of immediate. 2334 2335 return DAG.getConstant((int)C->getZExtValue() >> 2, 2336 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2337} 2338 2339namespace { 2340 2341struct TailCallArgumentInfo { 2342 SDValue Arg; 2343 SDValue FrameIdxOp; 2344 int FrameIdx; 2345 2346 TailCallArgumentInfo() : FrameIdx(0) {} 2347}; 2348 2349} 2350 2351/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2352static void 2353StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2354 SDValue Chain, 2355 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2356 SmallVector<SDValue, 8> &MemOpChains, 2357 DebugLoc dl) { 2358 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2359 SDValue Arg = TailCallArgs[i].Arg; 2360 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2361 int FI = TailCallArgs[i].FrameIdx; 2362 // Store relative to framepointer. 2363 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2364 MachinePointerInfo::getFixedStack(FI), 2365 false, false, 0)); 2366 } 2367} 2368 2369/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2370/// the appropriate stack slot for the tail call optimized function call. 2371static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2372 MachineFunction &MF, 2373 SDValue Chain, 2374 SDValue OldRetAddr, 2375 SDValue OldFP, 2376 int SPDiff, 2377 bool isPPC64, 2378 bool isDarwinABI, 2379 DebugLoc dl) { 2380 if (SPDiff) { 2381 // Calculate the new stack slot for the return address. 2382 int SlotSize = isPPC64 ? 8 : 4; 2383 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64, 2384 isDarwinABI); 2385 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2386 NewRetAddrLoc, true); 2387 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2388 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2389 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2390 MachinePointerInfo::getFixedStack(NewRetAddr), 2391 false, false, 0); 2392 2393 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2394 // slot as the FP is never overwritten. 2395 if (isDarwinABI) { 2396 int NewFPLoc = 2397 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2398 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2399 true); 2400 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2401 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2402 MachinePointerInfo::getFixedStack(NewFPIdx), 2403 false, false, 0); 2404 } 2405 } 2406 return Chain; 2407} 2408 2409/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2410/// the position of the argument. 2411static void 2412CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2413 SDValue Arg, int SPDiff, unsigned ArgOffset, 2414 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2415 int Offset = ArgOffset + SPDiff; 2416 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2417 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2418 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2419 SDValue FIN = DAG.getFrameIndex(FI, VT); 2420 TailCallArgumentInfo Info; 2421 Info.Arg = Arg; 2422 Info.FrameIdxOp = FIN; 2423 Info.FrameIdx = FI; 2424 TailCallArguments.push_back(Info); 2425} 2426 2427/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2428/// stack slot. Returns the chain as result and the loaded frame pointers in 2429/// LROpOut/FPOpout. Used when tail calling. 2430SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2431 int SPDiff, 2432 SDValue Chain, 2433 SDValue &LROpOut, 2434 SDValue &FPOpOut, 2435 bool isDarwinABI, 2436 DebugLoc dl) const { 2437 if (SPDiff) { 2438 // Load the LR and FP stack slot for later adjusting. 2439 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2440 LROpOut = getReturnAddrFrameIndex(DAG); 2441 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), 2442 false, false, 0); 2443 Chain = SDValue(LROpOut.getNode(), 1); 2444 2445 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2446 // slot as the FP is never overwritten. 2447 if (isDarwinABI) { 2448 FPOpOut = getFramePointerFrameIndex(DAG); 2449 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), 2450 false, false, 0); 2451 Chain = SDValue(FPOpOut.getNode(), 1); 2452 } 2453 } 2454 return Chain; 2455} 2456 2457/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2458/// by "Src" to address "Dst" of size "Size". Alignment information is 2459/// specified by the specific parameter attribute. The copy will be passed as 2460/// a byval function parameter. 2461/// Sometimes what we are copying is the end of a larger object, the part that 2462/// does not fit in registers. 2463static SDValue 2464CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2465 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2466 DebugLoc dl) { 2467 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 2468 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 2469 false, false, MachinePointerInfo(0), 2470 MachinePointerInfo(0)); 2471} 2472 2473/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2474/// tail calls. 2475static void 2476LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2477 SDValue Arg, SDValue PtrOff, int SPDiff, 2478 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2479 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2480 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, 2481 DebugLoc dl) { 2482 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2483 if (!isTailCall) { 2484 if (isVector) { 2485 SDValue StackPtr; 2486 if (isPPC64) 2487 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2488 else 2489 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2490 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 2491 DAG.getConstant(ArgOffset, PtrVT)); 2492 } 2493 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2494 MachinePointerInfo(), false, false, 0)); 2495 // Calculate and remember argument location. 2496 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2497 TailCallArguments); 2498} 2499 2500static 2501void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 2502 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 2503 SDValue LROp, SDValue FPOp, bool isDarwinABI, 2504 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 2505 MachineFunction &MF = DAG.getMachineFunction(); 2506 2507 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2508 // might overwrite each other in case of tail call optimization. 2509 SmallVector<SDValue, 8> MemOpChains2; 2510 // Do not flag preceding copytoreg stuff together with the following stuff. 2511 InFlag = SDValue(); 2512 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2513 MemOpChains2, dl); 2514 if (!MemOpChains2.empty()) 2515 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2516 &MemOpChains2[0], MemOpChains2.size()); 2517 2518 // Store the return address to the appropriate stack slot. 2519 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2520 isPPC64, isDarwinABI, dl); 2521 2522 // Emit callseq_end just before tailcall node. 2523 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2524 DAG.getIntPtrConstant(0, true), InFlag); 2525 InFlag = Chain.getValue(1); 2526} 2527 2528static 2529unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 2530 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 2531 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 2532 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 2533 const PPCSubtarget &PPCSubTarget) { 2534 2535 bool isPPC64 = PPCSubTarget.isPPC64(); 2536 bool isSVR4ABI = PPCSubTarget.isSVR4ABI(); 2537 2538 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2539 NodeTys.push_back(MVT::Other); // Returns a chain 2540 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. 2541 2542 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 2543 2544 bool needIndirectCall = true; 2545 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 2546 // If this is an absolute destination address, use the munged value. 2547 Callee = SDValue(Dest, 0); 2548 needIndirectCall = false; 2549 } 2550 2551 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2552 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 2553 // Use indirect calls for ALL functions calls in JIT mode, since the 2554 // far-call stubs may be outside relocation limits for a BL instruction. 2555 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) { 2556 unsigned OpFlags = 0; 2557 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 2558 (PPCSubTarget.getTargetTriple().isMacOSX() && 2559 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) && 2560 (G->getGlobal()->isDeclaration() || 2561 G->getGlobal()->isWeakForLinker())) { 2562 // PC-relative references to external symbols should go through $stub, 2563 // unless we're building with the leopard linker or later, which 2564 // automatically synthesizes these stubs. 2565 OpFlags = PPCII::MO_DARWIN_STUB; 2566 } 2567 2568 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, 2569 // every direct call is) turn it into a TargetGlobalAddress / 2570 // TargetExternalSymbol node so that legalize doesn't hack it. 2571 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2572 Callee.getValueType(), 2573 0, OpFlags); 2574 needIndirectCall = false; 2575 } 2576 } 2577 2578 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2579 unsigned char OpFlags = 0; 2580 2581 if (DAG.getTarget().getRelocationModel() != Reloc::Static && 2582 (PPCSubTarget.getTargetTriple().isMacOSX() && 2583 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) { 2584 // PC-relative references to external symbols should go through $stub, 2585 // unless we're building with the leopard linker or later, which 2586 // automatically synthesizes these stubs. 2587 OpFlags = PPCII::MO_DARWIN_STUB; 2588 } 2589 2590 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(), 2591 OpFlags); 2592 needIndirectCall = false; 2593 } 2594 2595 if (needIndirectCall) { 2596 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2597 // to do the call, we can't use PPCISD::CALL. 2598 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2599 2600 if (isSVR4ABI && isPPC64) { 2601 // Function pointers in the 64-bit SVR4 ABI do not point to the function 2602 // entry point, but to the function descriptor (the function entry point 2603 // address is part of the function descriptor though). 2604 // The function descriptor is a three doubleword structure with the 2605 // following fields: function entry point, TOC base address and 2606 // environment pointer. 2607 // Thus for a call through a function pointer, the following actions need 2608 // to be performed: 2609 // 1. Save the TOC of the caller in the TOC save area of its stack 2610 // frame (this is done in LowerCall_Darwin()). 2611 // 2. Load the address of the function entry point from the function 2612 // descriptor. 2613 // 3. Load the TOC of the callee from the function descriptor into r2. 2614 // 4. Load the environment pointer from the function descriptor into 2615 // r11. 2616 // 5. Branch to the function entry point address. 2617 // 6. On return of the callee, the TOC of the caller needs to be 2618 // restored (this is done in FinishCall()). 2619 // 2620 // All those operations are flagged together to ensure that no other 2621 // operations can be scheduled in between. E.g. without flagging the 2622 // operations together, a TOC access in the caller could be scheduled 2623 // between the load of the callee TOC and the branch to the callee, which 2624 // results in the TOC access going through the TOC of the callee instead 2625 // of going through the TOC of the caller, which leads to incorrect code. 2626 2627 // Load the address of the function entry point from the function 2628 // descriptor. 2629 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue); 2630 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 2631 InFlag.getNode() ? 3 : 2); 2632 Chain = LoadFuncPtr.getValue(1); 2633 InFlag = LoadFuncPtr.getValue(2); 2634 2635 // Load environment pointer into r11. 2636 // Offset of the environment pointer within the function descriptor. 2637 SDValue PtrOff = DAG.getIntPtrConstant(16); 2638 2639 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 2640 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 2641 InFlag); 2642 Chain = LoadEnvPtr.getValue(1); 2643 InFlag = LoadEnvPtr.getValue(2); 2644 2645 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 2646 InFlag); 2647 Chain = EnvVal.getValue(0); 2648 InFlag = EnvVal.getValue(1); 2649 2650 // Load TOC of the callee into r2. We are using a target-specific load 2651 // with r2 hard coded, because the result of a target-independent load 2652 // would never go directly into r2, since r2 is a reserved register (which 2653 // prevents the register allocator from allocating it), resulting in an 2654 // additional register being allocated and an unnecessary move instruction 2655 // being generated. 2656 VTs = DAG.getVTList(MVT::Other, MVT::Glue); 2657 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 2658 Callee, InFlag); 2659 Chain = LoadTOCPtr.getValue(0); 2660 InFlag = LoadTOCPtr.getValue(1); 2661 2662 MTCTROps[0] = Chain; 2663 MTCTROps[1] = LoadFuncPtr; 2664 MTCTROps[2] = InFlag; 2665 } 2666 2667 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 2668 2 + (InFlag.getNode() != 0)); 2669 InFlag = Chain.getValue(1); 2670 2671 NodeTys.clear(); 2672 NodeTys.push_back(MVT::Other); 2673 NodeTys.push_back(MVT::Glue); 2674 Ops.push_back(Chain); 2675 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 2676 Callee.setNode(0); 2677 // Add CTR register as callee so a bctr can be emitted later. 2678 if (isTailCall) 2679 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); 2680 } 2681 2682 // If this is a direct call, pass the chain and the callee. 2683 if (Callee.getNode()) { 2684 Ops.push_back(Chain); 2685 Ops.push_back(Callee); 2686 } 2687 // If this is a tail call add stack pointer delta. 2688 if (isTailCall) 2689 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2690 2691 // Add argument registers to the end of the list so that they are known live 2692 // into the call. 2693 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2694 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2695 RegsToPass[i].second.getValueType())); 2696 2697 return CallOpc; 2698} 2699 2700SDValue 2701PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2702 CallingConv::ID CallConv, bool isVarArg, 2703 const SmallVectorImpl<ISD::InputArg> &Ins, 2704 DebugLoc dl, SelectionDAG &DAG, 2705 SmallVectorImpl<SDValue> &InVals) const { 2706 2707 SmallVector<CCValAssign, 16> RVLocs; 2708 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2709 getTargetMachine(), RVLocs, *DAG.getContext()); 2710 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2711 2712 // Copy all of the result registers out of their specified physreg. 2713 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2714 CCValAssign &VA = RVLocs[i]; 2715 EVT VT = VA.getValVT(); 2716 assert(VA.isRegLoc() && "Can only return in registers!"); 2717 Chain = DAG.getCopyFromReg(Chain, dl, 2718 VA.getLocReg(), VT, InFlag).getValue(1); 2719 InVals.push_back(Chain.getValue(0)); 2720 InFlag = Chain.getValue(2); 2721 } 2722 2723 return Chain; 2724} 2725 2726SDValue 2727PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 2728 bool isTailCall, bool isVarArg, 2729 SelectionDAG &DAG, 2730 SmallVector<std::pair<unsigned, SDValue>, 8> 2731 &RegsToPass, 2732 SDValue InFlag, SDValue Chain, 2733 SDValue &Callee, 2734 int SPDiff, unsigned NumBytes, 2735 const SmallVectorImpl<ISD::InputArg> &Ins, 2736 SmallVectorImpl<SDValue> &InVals) const { 2737 std::vector<EVT> NodeTys; 2738 SmallVector<SDValue, 8> Ops; 2739 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 2740 isTailCall, RegsToPass, Ops, NodeTys, 2741 PPCSubTarget); 2742 2743 // When performing tail call optimization the callee pops its arguments off 2744 // the stack. Account for this here so these bytes can be pushed back on in 2745 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2746 int BytesCalleePops = 2747 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0; 2748 2749 if (InFlag.getNode()) 2750 Ops.push_back(InFlag); 2751 2752 // Emit tail call. 2753 if (isTailCall) { 2754 // If this is the first return lowered for this function, add the regs 2755 // to the liveout set for the function. 2756 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2757 SmallVector<CCValAssign, 16> RVLocs; 2758 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2759 getTargetMachine(), RVLocs, *DAG.getContext()); 2760 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2761 for (unsigned i = 0; i != RVLocs.size(); ++i) 2762 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2763 } 2764 2765 assert(((Callee.getOpcode() == ISD::Register && 2766 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 2767 Callee.getOpcode() == ISD::TargetExternalSymbol || 2768 Callee.getOpcode() == ISD::TargetGlobalAddress || 2769 isa<ConstantSDNode>(Callee)) && 2770 "Expecting an global address, external symbol, absolute value or register"); 2771 2772 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 2773 } 2774 2775 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 2776 InFlag = Chain.getValue(1); 2777 2778 // Add a NOP immediately after the branch instruction when using the 64-bit 2779 // SVR4 ABI. At link time, if caller and callee are in a different module and 2780 // thus have a different TOC, the call will be replaced with a call to a stub 2781 // function which saves the current TOC, loads the TOC of the callee and 2782 // branches to the callee. The NOP will be replaced with a load instruction 2783 // which restores the TOC of the caller from the TOC save slot of the current 2784 // stack frame. If caller and callee belong to the same module (and have the 2785 // same TOC), the NOP will remain unchanged. 2786 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 2787 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); 2788 if (CallOpc == PPCISD::BCTRL_SVR4) { 2789 // This is a call through a function pointer. 2790 // Restore the caller TOC from the save area into R2. 2791 // See PrepareCall() for more information about calls through function 2792 // pointers in the 64-bit SVR4 ABI. 2793 // We are using a target-specific load with r2 hard coded, because the 2794 // result of a target-independent load would never go directly into r2, 2795 // since r2 is a reserved register (which prevents the register allocator 2796 // from allocating it), resulting in an additional register being 2797 // allocated and an unnecessary move instruction being generated. 2798 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 2799 InFlag = Chain.getValue(1); 2800 } else { 2801 // Otherwise insert NOP. 2802 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Glue, InFlag); 2803 } 2804 } 2805 2806 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2807 DAG.getIntPtrConstant(BytesCalleePops, true), 2808 InFlag); 2809 if (!Ins.empty()) 2810 InFlag = Chain.getValue(1); 2811 2812 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2813 Ins, dl, DAG, InVals); 2814} 2815 2816SDValue 2817PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2818 CallingConv::ID CallConv, bool isVarArg, 2819 bool &isTailCall, 2820 const SmallVectorImpl<ISD::OutputArg> &Outs, 2821 const SmallVectorImpl<SDValue> &OutVals, 2822 const SmallVectorImpl<ISD::InputArg> &Ins, 2823 DebugLoc dl, SelectionDAG &DAG, 2824 SmallVectorImpl<SDValue> &InVals) const { 2825 if (isTailCall) 2826 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 2827 Ins, DAG); 2828 2829 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) 2830 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg, 2831 isTailCall, Outs, OutVals, Ins, 2832 dl, DAG, InVals); 2833 2834 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 2835 isTailCall, Outs, OutVals, Ins, 2836 dl, DAG, InVals); 2837} 2838 2839SDValue 2840PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, 2841 CallingConv::ID CallConv, bool isVarArg, 2842 bool isTailCall, 2843 const SmallVectorImpl<ISD::OutputArg> &Outs, 2844 const SmallVectorImpl<SDValue> &OutVals, 2845 const SmallVectorImpl<ISD::InputArg> &Ins, 2846 DebugLoc dl, SelectionDAG &DAG, 2847 SmallVectorImpl<SDValue> &InVals) const { 2848 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description 2849 // of the 32-bit SVR4 ABI stack frame layout. 2850 2851 assert((CallConv == CallingConv::C || 2852 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 2853 2854 unsigned PtrByteSize = 4; 2855 2856 MachineFunction &MF = DAG.getMachineFunction(); 2857 2858 // Mark this function as potentially containing a function that contains a 2859 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2860 // and restoring the callers stack pointer in this functions epilog. This is 2861 // done because by tail calling the called function might overwrite the value 2862 // in this function's (MF) stack pointer stack slot 0(SP). 2863 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2864 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2865 2866 // Count how many bytes are to be pushed on the stack, including the linkage 2867 // area, parameter list area and the part of the local variable space which 2868 // contains copies of aggregates which are passed by value. 2869 2870 // Assign locations to all of the outgoing arguments. 2871 SmallVector<CCValAssign, 16> ArgLocs; 2872 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2873 getTargetMachine(), ArgLocs, *DAG.getContext()); 2874 2875 // Reserve space for the linkage area on the stack. 2876 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); 2877 2878 if (isVarArg) { 2879 // Handle fixed and variable vector arguments differently. 2880 // Fixed vector arguments go into registers as long as registers are 2881 // available. Variable vector arguments always go into memory. 2882 unsigned NumArgs = Outs.size(); 2883 2884 for (unsigned i = 0; i != NumArgs; ++i) { 2885 MVT ArgVT = Outs[i].VT; 2886 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2887 bool Result; 2888 2889 if (Outs[i].IsFixed) { 2890 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 2891 CCInfo); 2892 } else { 2893 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 2894 ArgFlags, CCInfo); 2895 } 2896 2897 if (Result) { 2898#ifndef NDEBUG 2899 errs() << "Call operand #" << i << " has unhandled type " 2900 << EVT(ArgVT).getEVTString() << "\n"; 2901#endif 2902 llvm_unreachable(0); 2903 } 2904 } 2905 } else { 2906 // All arguments are treated the same. 2907 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4); 2908 } 2909 2910 // Assign locations to all of the outgoing aggregate by value arguments. 2911 SmallVector<CCValAssign, 16> ByValArgLocs; 2912 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2913 getTargetMachine(), ByValArgLocs, *DAG.getContext()); 2914 2915 // Reserve stack space for the allocations in CCInfo. 2916 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 2917 2918 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal); 2919 2920 // Size of the linkage area, parameter list area and the part of the local 2921 // space variable where copies of aggregates which are passed by value are 2922 // stored. 2923 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 2924 2925 // Calculate by how many bytes the stack has to be adjusted in case of tail 2926 // call optimization. 2927 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2928 2929 // Adjust the stack pointer for the new arguments... 2930 // These operations are automatically eliminated by the prolog/epilog pass 2931 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2932 SDValue CallSeqStart = Chain; 2933 2934 // Load the return address and frame pointer so it can be moved somewhere else 2935 // later. 2936 SDValue LROp, FPOp; 2937 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 2938 dl); 2939 2940 // Set up a copy of the stack pointer for use loading and storing any 2941 // arguments that may not fit in the registers available for argument 2942 // passing. 2943 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2944 2945 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2946 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2947 SmallVector<SDValue, 8> MemOpChains; 2948 2949 // Walk the register/memloc assignments, inserting copies/loads. 2950 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 2951 i != e; 2952 ++i) { 2953 CCValAssign &VA = ArgLocs[i]; 2954 SDValue Arg = OutVals[i]; 2955 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2956 2957 if (Flags.isByVal()) { 2958 // Argument is an aggregate which is passed by value, thus we need to 2959 // create a copy of it in the local variable space of the current stack 2960 // frame (which is the stack frame of the caller) and pass the address of 2961 // this copy to the callee. 2962 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 2963 CCValAssign &ByValVA = ByValArgLocs[j++]; 2964 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 2965 2966 // Memory reserved in the local variable space of the callers stack frame. 2967 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 2968 2969 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2970 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2971 2972 // Create a copy of the argument in the local area of the current 2973 // stack frame. 2974 SDValue MemcpyCall = 2975 CreateCopyOfByValArgument(Arg, PtrOff, 2976 CallSeqStart.getNode()->getOperand(0), 2977 Flags, DAG, dl); 2978 2979 // This must go outside the CALLSEQ_START..END. 2980 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2981 CallSeqStart.getNode()->getOperand(1)); 2982 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 2983 NewCallSeqStart.getNode()); 2984 Chain = CallSeqStart = NewCallSeqStart; 2985 2986 // Pass the address of the aggregate copy on the stack either in a 2987 // physical register or in the parameter list area of the current stack 2988 // frame to the callee. 2989 Arg = PtrOff; 2990 } 2991 2992 if (VA.isRegLoc()) { 2993 // Put argument in a physical register. 2994 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2995 } else { 2996 // Put argument in the parameter list area of the current stack frame. 2997 assert(VA.isMemLoc()); 2998 unsigned LocMemOffset = VA.getLocMemOffset(); 2999 3000 if (!isTailCall) { 3001 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 3002 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 3003 3004 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 3005 MachinePointerInfo(), 3006 false, false, 0)); 3007 } else { 3008 // Calculate and remember argument location. 3009 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 3010 TailCallArguments); 3011 } 3012 } 3013 } 3014 3015 if (!MemOpChains.empty()) 3016 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3017 &MemOpChains[0], MemOpChains.size()); 3018 3019 // Set CR6 to true if this is a vararg call. 3020 if (isVarArg) { 3021 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0); 3022 RegsToPass.push_back(std::make_pair(unsigned(PPC::CR1EQ), SetCR)); 3023 } 3024 3025 // Build a sequence of copy-to-reg nodes chained together with token chain 3026 // and flag operands which copy the outgoing args into the appropriate regs. 3027 SDValue InFlag; 3028 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3029 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3030 RegsToPass[i].second, InFlag); 3031 InFlag = Chain.getValue(1); 3032 } 3033 3034 if (isTailCall) 3035 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 3036 false, TailCallArguments); 3037 3038 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3039 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3040 Ins, InVals); 3041} 3042 3043SDValue 3044PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 3045 CallingConv::ID CallConv, bool isVarArg, 3046 bool isTailCall, 3047 const SmallVectorImpl<ISD::OutputArg> &Outs, 3048 const SmallVectorImpl<SDValue> &OutVals, 3049 const SmallVectorImpl<ISD::InputArg> &Ins, 3050 DebugLoc dl, SelectionDAG &DAG, 3051 SmallVectorImpl<SDValue> &InVals) const { 3052 3053 unsigned NumOps = Outs.size(); 3054 3055 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3056 bool isPPC64 = PtrVT == MVT::i64; 3057 unsigned PtrByteSize = isPPC64 ? 8 : 4; 3058 3059 MachineFunction &MF = DAG.getMachineFunction(); 3060 3061 // Mark this function as potentially containing a function that contains a 3062 // tail call. As a consequence the frame pointer will be used for dynamicalloc 3063 // and restoring the callers stack pointer in this functions epilog. This is 3064 // done because by tail calling the called function might overwrite the value 3065 // in this function's (MF) stack pointer stack slot 0(SP). 3066 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 3067 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 3068 3069 unsigned nAltivecParamsAtEnd = 0; 3070 3071 // Count how many bytes are to be pushed on the stack, including the linkage 3072 // area, and parameter passing area. We start with 24/48 bytes, which is 3073 // prereserved space for [SP][CR][LR][3 x unused]. 3074 unsigned NumBytes = 3075 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 3076 Outs, OutVals, 3077 nAltivecParamsAtEnd); 3078 3079 // Calculate by how many bytes the stack has to be adjusted in case of tail 3080 // call optimization. 3081 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 3082 3083 // To protect arguments on the stack from being clobbered in a tail call, 3084 // force all the loads to happen before doing any other lowering. 3085 if (isTailCall) 3086 Chain = DAG.getStackArgumentTokenFactor(Chain); 3087 3088 // Adjust the stack pointer for the new arguments... 3089 // These operations are automatically eliminated by the prolog/epilog pass 3090 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 3091 SDValue CallSeqStart = Chain; 3092 3093 // Load the return address and frame pointer so it can be move somewhere else 3094 // later. 3095 SDValue LROp, FPOp; 3096 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 3097 dl); 3098 3099 // Set up a copy of the stack pointer for use loading and storing any 3100 // arguments that may not fit in the registers available for argument 3101 // passing. 3102 SDValue StackPtr; 3103 if (isPPC64) 3104 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3105 else 3106 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3107 3108 // Figure out which arguments are going to go in registers, and which in 3109 // memory. Also, if this is a vararg function, floating point operations 3110 // must be stored to our stack, and loaded into integer regs as well, if 3111 // any integer regs are available for argument passing. 3112 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); 3113 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 3114 3115 static const unsigned GPR_32[] = { // 32-bit registers. 3116 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 3117 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 3118 }; 3119 static const unsigned GPR_64[] = { // 64-bit registers. 3120 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3121 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3122 }; 3123 static const unsigned *FPR = GetFPR(); 3124 3125 static const unsigned VR[] = { 3126 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3127 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3128 }; 3129 const unsigned NumGPRs = array_lengthof(GPR_32); 3130 const unsigned NumFPRs = 13; 3131 const unsigned NumVRs = array_lengthof(VR); 3132 3133 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 3134 3135 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3136 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3137 3138 SmallVector<SDValue, 8> MemOpChains; 3139 for (unsigned i = 0; i != NumOps; ++i) { 3140 SDValue Arg = OutVals[i]; 3141 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3142 3143 // PtrOff will be used to store the current argument to the stack if a 3144 // register cannot be found for it. 3145 SDValue PtrOff; 3146 3147 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3148 3149 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3150 3151 // On PPC64, promote integers to 64-bit values. 3152 if (isPPC64 && Arg.getValueType() == MVT::i32) { 3153 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3154 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3155 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3156 } 3157 3158 // FIXME memcpy is used way more than necessary. Correctness first. 3159 if (Flags.isByVal()) { 3160 unsigned Size = Flags.getByValSize(); 3161 if (Size==1 || Size==2) { 3162 // Very small objects are passed right-justified. 3163 // Everything else is passed left-justified. 3164 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 3165 if (GPR_idx != NumGPRs) { 3166 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, 3167 MachinePointerInfo(), VT, 3168 false, false, 0); 3169 MemOpChains.push_back(Load.getValue(1)); 3170 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3171 3172 ArgOffset += PtrByteSize; 3173 } else { 3174 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 3175 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3176 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 3177 CallSeqStart.getNode()->getOperand(0), 3178 Flags, DAG, dl); 3179 // This must go outside the CALLSEQ_START..END. 3180 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3181 CallSeqStart.getNode()->getOperand(1)); 3182 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3183 NewCallSeqStart.getNode()); 3184 Chain = CallSeqStart = NewCallSeqStart; 3185 ArgOffset += PtrByteSize; 3186 } 3187 continue; 3188 } 3189 // Copy entire object into memory. There are cases where gcc-generated 3190 // code assumes it is there, even if it could be put entirely into 3191 // registers. (This is not what the doc says.) 3192 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3193 CallSeqStart.getNode()->getOperand(0), 3194 Flags, DAG, dl); 3195 // This must go outside the CALLSEQ_START..END. 3196 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3197 CallSeqStart.getNode()->getOperand(1)); 3198 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); 3199 Chain = CallSeqStart = NewCallSeqStart; 3200 // And copy the pieces of it that fit into registers. 3201 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3202 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3203 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3204 if (GPR_idx != NumGPRs) { 3205 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 3206 MachinePointerInfo(), 3207 false, false, 0); 3208 MemOpChains.push_back(Load.getValue(1)); 3209 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3210 ArgOffset += PtrByteSize; 3211 } else { 3212 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3213 break; 3214 } 3215 } 3216 continue; 3217 } 3218 3219 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3220 default: llvm_unreachable("Unexpected ValueType for argument!"); 3221 case MVT::i32: 3222 case MVT::i64: 3223 if (GPR_idx != NumGPRs) { 3224 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3225 } else { 3226 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3227 isPPC64, isTailCall, false, MemOpChains, 3228 TailCallArguments, dl); 3229 } 3230 ArgOffset += PtrByteSize; 3231 break; 3232 case MVT::f32: 3233 case MVT::f64: 3234 if (FPR_idx != NumFPRs) { 3235 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3236 3237 if (isVarArg) { 3238 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3239 MachinePointerInfo(), false, false, 0); 3240 MemOpChains.push_back(Store); 3241 3242 // Float varargs are always shadowed in available integer registers 3243 if (GPR_idx != NumGPRs) { 3244 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3245 MachinePointerInfo(), false, false, 0); 3246 MemOpChains.push_back(Load.getValue(1)); 3247 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3248 } 3249 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 3250 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3251 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3252 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3253 MachinePointerInfo(), 3254 false, false, 0); 3255 MemOpChains.push_back(Load.getValue(1)); 3256 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3257 } 3258 } else { 3259 // If we have any FPRs remaining, we may also have GPRs remaining. 3260 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 3261 // GPRs. 3262 if (GPR_idx != NumGPRs) 3263 ++GPR_idx; 3264 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 3265 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 3266 ++GPR_idx; 3267 } 3268 } else { 3269 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3270 isPPC64, isTailCall, false, MemOpChains, 3271 TailCallArguments, dl); 3272 } 3273 if (isPPC64) 3274 ArgOffset += 8; 3275 else 3276 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 3277 break; 3278 case MVT::v4f32: 3279 case MVT::v4i32: 3280 case MVT::v8i16: 3281 case MVT::v16i8: 3282 if (isVarArg) { 3283 // These go aligned on the stack, or in the corresponding R registers 3284 // when within range. The Darwin PPC ABI doc claims they also go in 3285 // V registers; in fact gcc does this only for arguments that are 3286 // prototyped, not for those that match the ... We do it for all 3287 // arguments, seems to work. 3288 while (ArgOffset % 16 !=0) { 3289 ArgOffset += PtrByteSize; 3290 if (GPR_idx != NumGPRs) 3291 GPR_idx++; 3292 } 3293 // We could elide this store in the case where the object fits 3294 // entirely in R registers. Maybe later. 3295 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3296 DAG.getConstant(ArgOffset, PtrVT)); 3297 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3298 MachinePointerInfo(), false, false, 0); 3299 MemOpChains.push_back(Store); 3300 if (VR_idx != NumVRs) { 3301 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 3302 MachinePointerInfo(), 3303 false, false, 0); 3304 MemOpChains.push_back(Load.getValue(1)); 3305 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3306 } 3307 ArgOffset += 16; 3308 for (unsigned i=0; i<16; i+=PtrByteSize) { 3309 if (GPR_idx == NumGPRs) 3310 break; 3311 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3312 DAG.getConstant(i, PtrVT)); 3313 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 3314 false, false, 0); 3315 MemOpChains.push_back(Load.getValue(1)); 3316 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3317 } 3318 break; 3319 } 3320 3321 // Non-varargs Altivec params generally go in registers, but have 3322 // stack space allocated at the end. 3323 if (VR_idx != NumVRs) { 3324 // Doesn't have GPR space allocated. 3325 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3326 } else if (nAltivecParamsAtEnd==0) { 3327 // We are emitting Altivec params in order. 3328 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3329 isPPC64, isTailCall, true, MemOpChains, 3330 TailCallArguments, dl); 3331 ArgOffset += 16; 3332 } 3333 break; 3334 } 3335 } 3336 // If all Altivec parameters fit in registers, as they usually do, 3337 // they get stack space following the non-Altivec parameters. We 3338 // don't track this here because nobody below needs it. 3339 // If there are more Altivec parameters than fit in registers emit 3340 // the stores here. 3341 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 3342 unsigned j = 0; 3343 // Offset is aligned; skip 1st 12 params which go in V registers. 3344 ArgOffset = ((ArgOffset+15)/16)*16; 3345 ArgOffset += 12*16; 3346 for (unsigned i = 0; i != NumOps; ++i) { 3347 SDValue Arg = OutVals[i]; 3348 EVT ArgType = Outs[i].VT; 3349 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 3350 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 3351 if (++j > NumVRs) { 3352 SDValue PtrOff; 3353 // We are emitting Altivec params in order. 3354 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3355 isPPC64, isTailCall, true, MemOpChains, 3356 TailCallArguments, dl); 3357 ArgOffset += 16; 3358 } 3359 } 3360 } 3361 } 3362 3363 if (!MemOpChains.empty()) 3364 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3365 &MemOpChains[0], MemOpChains.size()); 3366 3367 // Check if this is an indirect call (MTCTR/BCTRL). 3368 // See PrepareCall() for more information about calls through function 3369 // pointers in the 64-bit SVR4 ABI. 3370 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() && 3371 !dyn_cast<GlobalAddressSDNode>(Callee) && 3372 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3373 !isBLACompatibleAddress(Callee, DAG)) { 3374 // Load r2 into a virtual register and store it to the TOC save area. 3375 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 3376 // TOC save area offset. 3377 SDValue PtrOff = DAG.getIntPtrConstant(40); 3378 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3379 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), 3380 false, false, 0); 3381 } 3382 3383 // On Darwin, R12 must contain the address of an indirect callee. This does 3384 // not mean the MTCTR instruction must use R12; it's easier to model this as 3385 // an extra parameter, so do that. 3386 if (!isTailCall && 3387 !dyn_cast<GlobalAddressSDNode>(Callee) && 3388 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3389 !isBLACompatibleAddress(Callee, DAG)) 3390 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 3391 PPC::R12), Callee)); 3392 3393 // Build a sequence of copy-to-reg nodes chained together with token chain 3394 // and flag operands which copy the outgoing args into the appropriate regs. 3395 SDValue InFlag; 3396 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3397 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3398 RegsToPass[i].second, InFlag); 3399 InFlag = Chain.getValue(1); 3400 } 3401 3402 if (isTailCall) 3403 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 3404 FPOp, true, TailCallArguments); 3405 3406 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3407 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3408 Ins, InVals); 3409} 3410 3411SDValue 3412PPCTargetLowering::LowerReturn(SDValue Chain, 3413 CallingConv::ID CallConv, bool isVarArg, 3414 const SmallVectorImpl<ISD::OutputArg> &Outs, 3415 const SmallVectorImpl<SDValue> &OutVals, 3416 DebugLoc dl, SelectionDAG &DAG) const { 3417 3418 SmallVector<CCValAssign, 16> RVLocs; 3419 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3420 getTargetMachine(), RVLocs, *DAG.getContext()); 3421 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 3422 3423 // If this is the first return lowered for this function, add the regs to the 3424 // liveout set for the function. 3425 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3426 for (unsigned i = 0; i != RVLocs.size(); ++i) 3427 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3428 } 3429 3430 SDValue Flag; 3431 3432 // Copy the result values into the output registers. 3433 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3434 CCValAssign &VA = RVLocs[i]; 3435 assert(VA.isRegLoc() && "Can only return in registers!"); 3436 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 3437 OutVals[i], Flag); 3438 Flag = Chain.getValue(1); 3439 } 3440 3441 if (Flag.getNode()) 3442 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 3443 else 3444 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 3445} 3446 3447SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 3448 const PPCSubtarget &Subtarget) const { 3449 // When we pop the dynamic allocation we need to restore the SP link. 3450 DebugLoc dl = Op.getDebugLoc(); 3451 3452 // Get the corect type for pointers. 3453 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3454 3455 // Construct the stack pointer operand. 3456 bool isPPC64 = Subtarget.isPPC64(); 3457 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 3458 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 3459 3460 // Get the operands for the STACKRESTORE. 3461 SDValue Chain = Op.getOperand(0); 3462 SDValue SaveSP = Op.getOperand(1); 3463 3464 // Load the old link SP. 3465 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, 3466 MachinePointerInfo(), 3467 false, false, 0); 3468 3469 // Restore the stack pointer. 3470 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 3471 3472 // Store the old link SP. 3473 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(), 3474 false, false, 0); 3475} 3476 3477 3478 3479SDValue 3480PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 3481 MachineFunction &MF = DAG.getMachineFunction(); 3482 bool isPPC64 = PPCSubTarget.isPPC64(); 3483 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3484 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3485 3486 // Get current frame pointer save index. The users of this index will be 3487 // primarily DYNALLOC instructions. 3488 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3489 int RASI = FI->getReturnAddrSaveIndex(); 3490 3491 // If the frame pointer save index hasn't been defined yet. 3492 if (!RASI) { 3493 // Find out what the fix offset of the frame pointer save area. 3494 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 3495 // Allocate the frame index for frame pointer save area. 3496 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 3497 // Save the result. 3498 FI->setReturnAddrSaveIndex(RASI); 3499 } 3500 return DAG.getFrameIndex(RASI, PtrVT); 3501} 3502 3503SDValue 3504PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 3505 MachineFunction &MF = DAG.getMachineFunction(); 3506 bool isPPC64 = PPCSubTarget.isPPC64(); 3507 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3508 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3509 3510 // Get current frame pointer save index. The users of this index will be 3511 // primarily DYNALLOC instructions. 3512 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3513 int FPSI = FI->getFramePointerSaveIndex(); 3514 3515 // If the frame pointer save index hasn't been defined yet. 3516 if (!FPSI) { 3517 // Find out what the fix offset of the frame pointer save area. 3518 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, 3519 isDarwinABI); 3520 3521 // Allocate the frame index for frame pointer save area. 3522 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 3523 // Save the result. 3524 FI->setFramePointerSaveIndex(FPSI); 3525 } 3526 return DAG.getFrameIndex(FPSI, PtrVT); 3527} 3528 3529SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 3530 SelectionDAG &DAG, 3531 const PPCSubtarget &Subtarget) const { 3532 // Get the inputs. 3533 SDValue Chain = Op.getOperand(0); 3534 SDValue Size = Op.getOperand(1); 3535 DebugLoc dl = Op.getDebugLoc(); 3536 3537 // Get the corect type for pointers. 3538 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3539 // Negate the size. 3540 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 3541 DAG.getConstant(0, PtrVT), Size); 3542 // Construct a node for the frame pointer save index. 3543 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 3544 // Build a DYNALLOC node. 3545 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 3546 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 3547 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 3548} 3549 3550/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 3551/// possible. 3552SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 3553 // Not FP? Not a fsel. 3554 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 3555 !Op.getOperand(2).getValueType().isFloatingPoint()) 3556 return Op; 3557 3558 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 3559 3560 // Cannot handle SETEQ/SETNE. 3561 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 3562 3563 EVT ResVT = Op.getValueType(); 3564 EVT CmpVT = Op.getOperand(0).getValueType(); 3565 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3566 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 3567 DebugLoc dl = Op.getDebugLoc(); 3568 3569 // If the RHS of the comparison is a 0.0, we don't need to do the 3570 // subtraction at all. 3571 if (isFloatingPointZero(RHS)) 3572 switch (CC) { 3573 default: break; // SETUO etc aren't handled by fsel. 3574 case ISD::SETULT: 3575 case ISD::SETLT: 3576 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3577 case ISD::SETOGE: 3578 case ISD::SETGE: 3579 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3580 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3581 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 3582 case ISD::SETUGT: 3583 case ISD::SETGT: 3584 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3585 case ISD::SETOLE: 3586 case ISD::SETLE: 3587 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3588 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3589 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 3590 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 3591 } 3592 3593 SDValue Cmp; 3594 switch (CC) { 3595 default: break; // SETUO etc aren't handled by fsel. 3596 case ISD::SETULT: 3597 case ISD::SETLT: 3598 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3599 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3600 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3601 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3602 case ISD::SETOGE: 3603 case ISD::SETGE: 3604 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3605 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3606 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3607 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3608 case ISD::SETUGT: 3609 case ISD::SETGT: 3610 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3611 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3612 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3613 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3614 case ISD::SETOLE: 3615 case ISD::SETLE: 3616 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3617 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3618 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3619 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3620 } 3621 return Op; 3622} 3623 3624// FIXME: Split this code up when LegalizeDAGTypes lands. 3625SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 3626 DebugLoc dl) const { 3627 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 3628 SDValue Src = Op.getOperand(0); 3629 if (Src.getValueType() == MVT::f32) 3630 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 3631 3632 SDValue Tmp; 3633 switch (Op.getValueType().getSimpleVT().SimpleTy) { 3634 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 3635 case MVT::i32: 3636 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 3637 PPCISD::FCTIDZ, 3638 dl, MVT::f64, Src); 3639 break; 3640 case MVT::i64: 3641 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 3642 break; 3643 } 3644 3645 // Convert the FP value to an int value through memory. 3646 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 3647 3648 // Emit a store to the stack slot. 3649 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, 3650 MachinePointerInfo(), false, false, 0); 3651 3652 // Result is a load from the stack slot. If loading 4 bytes, make sure to 3653 // add in a bias. 3654 if (Op.getValueType() == MVT::i32) 3655 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 3656 DAG.getConstant(4, FIPtr.getValueType())); 3657 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(), 3658 false, false, 0); 3659} 3660 3661SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, 3662 SelectionDAG &DAG) const { 3663 DebugLoc dl = Op.getDebugLoc(); 3664 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 3665 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 3666 return SDValue(); 3667 3668 if (Op.getOperand(0).getValueType() == MVT::i64) { 3669 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0)); 3670 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 3671 if (Op.getValueType() == MVT::f32) 3672 FP = DAG.getNode(ISD::FP_ROUND, dl, 3673 MVT::f32, FP, DAG.getIntPtrConstant(0)); 3674 return FP; 3675 } 3676 3677 assert(Op.getOperand(0).getValueType() == MVT::i32 && 3678 "Unhandled SINT_TO_FP type in custom expander!"); 3679 // Since we only generate this in 64-bit mode, we can take advantage of 3680 // 64-bit registers. In particular, sign extend the input value into the 3681 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 3682 // then lfd it and fcfid it. 3683 MachineFunction &MF = DAG.getMachineFunction(); 3684 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 3685 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 3686 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3687 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3688 3689 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 3690 Op.getOperand(0)); 3691 3692 // STD the extended value into the stack slot. 3693 MachineMemOperand *MMO = 3694 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 3695 MachineMemOperand::MOStore, 8, 8); 3696 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 3697 SDValue Store = 3698 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 3699 Ops, 4, MVT::i64, MMO); 3700 // Load the value as a double. 3701 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(), 3702 false, false, 0); 3703 3704 // FCFID it and return it. 3705 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 3706 if (Op.getValueType() == MVT::f32) 3707 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 3708 return FP; 3709} 3710 3711SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3712 SelectionDAG &DAG) const { 3713 DebugLoc dl = Op.getDebugLoc(); 3714 /* 3715 The rounding mode is in bits 30:31 of FPSR, and has the following 3716 settings: 3717 00 Round to nearest 3718 01 Round to 0 3719 10 Round to +inf 3720 11 Round to -inf 3721 3722 FLT_ROUNDS, on the other hand, expects the following: 3723 -1 Undefined 3724 0 Round to 0 3725 1 Round to nearest 3726 2 Round to +inf 3727 3 Round to -inf 3728 3729 To perform the conversion, we do: 3730 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 3731 */ 3732 3733 MachineFunction &MF = DAG.getMachineFunction(); 3734 EVT VT = Op.getValueType(); 3735 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3736 std::vector<EVT> NodeTys; 3737 SDValue MFFSreg, InFlag; 3738 3739 // Save FP Control Word to register 3740 NodeTys.push_back(MVT::f64); // return register 3741 NodeTys.push_back(MVT::Glue); // unused in this context 3742 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 3743 3744 // Save FP register to stack slot 3745 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 3746 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 3747 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 3748 StackSlot, MachinePointerInfo(), false, false,0); 3749 3750 // Load FP Control Word from low 32 bits of stack slot. 3751 SDValue Four = DAG.getConstant(4, PtrVT); 3752 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 3753 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), 3754 false, false, 0); 3755 3756 // Transform as necessary 3757 SDValue CWD1 = 3758 DAG.getNode(ISD::AND, dl, MVT::i32, 3759 CWD, DAG.getConstant(3, MVT::i32)); 3760 SDValue CWD2 = 3761 DAG.getNode(ISD::SRL, dl, MVT::i32, 3762 DAG.getNode(ISD::AND, dl, MVT::i32, 3763 DAG.getNode(ISD::XOR, dl, MVT::i32, 3764 CWD, DAG.getConstant(3, MVT::i32)), 3765 DAG.getConstant(3, MVT::i32)), 3766 DAG.getConstant(1, MVT::i32)); 3767 3768 SDValue RetVal = 3769 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 3770 3771 return DAG.getNode((VT.getSizeInBits() < 16 ? 3772 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 3773} 3774 3775SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3776 EVT VT = Op.getValueType(); 3777 unsigned BitWidth = VT.getSizeInBits(); 3778 DebugLoc dl = Op.getDebugLoc(); 3779 assert(Op.getNumOperands() == 3 && 3780 VT == Op.getOperand(1).getValueType() && 3781 "Unexpected SHL!"); 3782 3783 // Expand into a bunch of logical ops. Note that these ops 3784 // depend on the PPC behavior for oversized shift amounts. 3785 SDValue Lo = Op.getOperand(0); 3786 SDValue Hi = Op.getOperand(1); 3787 SDValue Amt = Op.getOperand(2); 3788 EVT AmtVT = Amt.getValueType(); 3789 3790 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3791 DAG.getConstant(BitWidth, AmtVT), Amt); 3792 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 3793 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 3794 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 3795 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3796 DAG.getConstant(-BitWidth, AmtVT)); 3797 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 3798 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3799 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 3800 SDValue OutOps[] = { OutLo, OutHi }; 3801 return DAG.getMergeValues(OutOps, 2, dl); 3802} 3803 3804SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3805 EVT VT = Op.getValueType(); 3806 DebugLoc dl = Op.getDebugLoc(); 3807 unsigned BitWidth = VT.getSizeInBits(); 3808 assert(Op.getNumOperands() == 3 && 3809 VT == Op.getOperand(1).getValueType() && 3810 "Unexpected SRL!"); 3811 3812 // Expand into a bunch of logical ops. Note that these ops 3813 // depend on the PPC behavior for oversized shift amounts. 3814 SDValue Lo = Op.getOperand(0); 3815 SDValue Hi = Op.getOperand(1); 3816 SDValue Amt = Op.getOperand(2); 3817 EVT AmtVT = Amt.getValueType(); 3818 3819 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3820 DAG.getConstant(BitWidth, AmtVT), Amt); 3821 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3822 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3823 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3824 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3825 DAG.getConstant(-BitWidth, AmtVT)); 3826 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 3827 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3828 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 3829 SDValue OutOps[] = { OutLo, OutHi }; 3830 return DAG.getMergeValues(OutOps, 2, dl); 3831} 3832 3833SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 3834 DebugLoc dl = Op.getDebugLoc(); 3835 EVT VT = Op.getValueType(); 3836 unsigned BitWidth = VT.getSizeInBits(); 3837 assert(Op.getNumOperands() == 3 && 3838 VT == Op.getOperand(1).getValueType() && 3839 "Unexpected SRA!"); 3840 3841 // Expand into a bunch of logical ops, followed by a select_cc. 3842 SDValue Lo = Op.getOperand(0); 3843 SDValue Hi = Op.getOperand(1); 3844 SDValue Amt = Op.getOperand(2); 3845 EVT AmtVT = Amt.getValueType(); 3846 3847 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3848 DAG.getConstant(BitWidth, AmtVT), Amt); 3849 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3850 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3851 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3852 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3853 DAG.getConstant(-BitWidth, AmtVT)); 3854 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 3855 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 3856 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 3857 Tmp4, Tmp6, ISD::SETLE); 3858 SDValue OutOps[] = { OutLo, OutHi }; 3859 return DAG.getMergeValues(OutOps, 2, dl); 3860} 3861 3862//===----------------------------------------------------------------------===// 3863// Vector related lowering. 3864// 3865 3866/// BuildSplatI - Build a canonical splati of Val with an element size of 3867/// SplatSize. Cast the result to VT. 3868static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 3869 SelectionDAG &DAG, DebugLoc dl) { 3870 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 3871 3872 static const EVT VTys[] = { // canonical VT to use for each size. 3873 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 3874 }; 3875 3876 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 3877 3878 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 3879 if (Val == -1) 3880 SplatSize = 1; 3881 3882 EVT CanonicalVT = VTys[SplatSize-1]; 3883 3884 // Build a canonical splat for this value. 3885 SDValue Elt = DAG.getConstant(Val, MVT::i32); 3886 SmallVector<SDValue, 8> Ops; 3887 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 3888 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 3889 &Ops[0], Ops.size()); 3890 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res); 3891} 3892 3893/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 3894/// specified intrinsic ID. 3895static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 3896 SelectionDAG &DAG, DebugLoc dl, 3897 EVT DestVT = MVT::Other) { 3898 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 3899 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3900 DAG.getConstant(IID, MVT::i32), LHS, RHS); 3901} 3902 3903/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 3904/// specified intrinsic ID. 3905static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 3906 SDValue Op2, SelectionDAG &DAG, 3907 DebugLoc dl, EVT DestVT = MVT::Other) { 3908 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 3909 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3910 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 3911} 3912 3913 3914/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 3915/// amount. The result has the specified value type. 3916static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 3917 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3918 // Force LHS/RHS to be the right type. 3919 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); 3920 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); 3921 3922 int Ops[16]; 3923 for (unsigned i = 0; i != 16; ++i) 3924 Ops[i] = i + Amt; 3925 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 3926 return DAG.getNode(ISD::BITCAST, dl, VT, T); 3927} 3928 3929// If this is a case we can't handle, return null and let the default 3930// expansion code take care of it. If we CAN select this case, and if it 3931// selects to a single instruction, return Op. Otherwise, if we can codegen 3932// this case more efficiently than a constant pool load, lower it to the 3933// sequence of ops that should be used. 3934SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 3935 SelectionDAG &DAG) const { 3936 DebugLoc dl = Op.getDebugLoc(); 3937 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 3938 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 3939 3940 // Check if this is a splat of a constant value. 3941 APInt APSplatBits, APSplatUndef; 3942 unsigned SplatBitSize; 3943 bool HasAnyUndefs; 3944 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 3945 HasAnyUndefs, 0, true) || SplatBitSize > 32) 3946 return SDValue(); 3947 3948 unsigned SplatBits = APSplatBits.getZExtValue(); 3949 unsigned SplatUndef = APSplatUndef.getZExtValue(); 3950 unsigned SplatSize = SplatBitSize / 8; 3951 3952 // First, handle single instruction cases. 3953 3954 // All zeros? 3955 if (SplatBits == 0) { 3956 // Canonicalize all zero vectors to be v4i32. 3957 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 3958 SDValue Z = DAG.getConstant(0, MVT::i32); 3959 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 3960 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z); 3961 } 3962 return Op; 3963 } 3964 3965 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 3966 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 3967 (32-SplatBitSize)); 3968 if (SextVal >= -16 && SextVal <= 15) 3969 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 3970 3971 3972 // Two instruction sequences. 3973 3974 // If this value is in the range [-32,30] and is even, use: 3975 // tmp = VSPLTI[bhw], result = add tmp, tmp 3976 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 3977 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 3978 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 3979 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 3980 } 3981 3982 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 3983 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 3984 // for fneg/fabs. 3985 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 3986 // Make -1 and vspltisw -1: 3987 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 3988 3989 // Make the VSLW intrinsic, computing 0x8000_0000. 3990 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 3991 OnesV, DAG, dl); 3992 3993 // xor by OnesV to invert it. 3994 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 3995 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 3996 } 3997 3998 // Check to see if this is a wide variety of vsplti*, binop self cases. 3999 static const signed char SplatCsts[] = { 4000 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 4001 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 4002 }; 4003 4004 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 4005 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 4006 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 4007 int i = SplatCsts[idx]; 4008 4009 // Figure out what shift amount will be used by altivec if shifted by i in 4010 // this splat size. 4011 unsigned TypeShiftAmt = i & (SplatBitSize-1); 4012 4013 // vsplti + shl self. 4014 if (SextVal == (i << (int)TypeShiftAmt)) { 4015 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4016 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4017 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 4018 Intrinsic::ppc_altivec_vslw 4019 }; 4020 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4021 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4022 } 4023 4024 // vsplti + srl self. 4025 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 4026 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4027 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4028 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 4029 Intrinsic::ppc_altivec_vsrw 4030 }; 4031 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4032 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4033 } 4034 4035 // vsplti + sra self. 4036 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 4037 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4038 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4039 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 4040 Intrinsic::ppc_altivec_vsraw 4041 }; 4042 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4043 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4044 } 4045 4046 // vsplti + rol self. 4047 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 4048 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 4049 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 4050 static const unsigned IIDs[] = { // Intrinsic to use for each size. 4051 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 4052 Intrinsic::ppc_altivec_vrlw 4053 }; 4054 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 4055 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); 4056 } 4057 4058 // t = vsplti c, result = vsldoi t, t, 1 4059 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) { 4060 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 4061 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 4062 } 4063 // t = vsplti c, result = vsldoi t, t, 2 4064 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) { 4065 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 4066 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 4067 } 4068 // t = vsplti c, result = vsldoi t, t, 3 4069 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) { 4070 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 4071 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 4072 } 4073 } 4074 4075 // Three instruction sequences. 4076 4077 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 4078 if (SextVal >= 0 && SextVal <= 31) { 4079 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 4080 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 4081 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 4082 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 4083 } 4084 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 4085 if (SextVal >= -31 && SextVal <= 0) { 4086 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 4087 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 4088 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 4089 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS); 4090 } 4091 4092 return SDValue(); 4093} 4094 4095/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4096/// the specified operations to build the shuffle. 4097static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4098 SDValue RHS, SelectionDAG &DAG, 4099 DebugLoc dl) { 4100 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4101 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 4102 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 4103 4104 enum { 4105 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4106 OP_VMRGHW, 4107 OP_VMRGLW, 4108 OP_VSPLTISW0, 4109 OP_VSPLTISW1, 4110 OP_VSPLTISW2, 4111 OP_VSPLTISW3, 4112 OP_VSLDOI4, 4113 OP_VSLDOI8, 4114 OP_VSLDOI12 4115 }; 4116 4117 if (OpNum == OP_COPY) { 4118 if (LHSID == (1*9+2)*9+3) return LHS; 4119 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4120 return RHS; 4121 } 4122 4123 SDValue OpLHS, OpRHS; 4124 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4125 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4126 4127 int ShufIdxs[16]; 4128 switch (OpNum) { 4129 default: llvm_unreachable("Unknown i32 permute!"); 4130 case OP_VMRGHW: 4131 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 4132 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 4133 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 4134 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 4135 break; 4136 case OP_VMRGLW: 4137 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 4138 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 4139 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 4140 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 4141 break; 4142 case OP_VSPLTISW0: 4143 for (unsigned i = 0; i != 16; ++i) 4144 ShufIdxs[i] = (i&3)+0; 4145 break; 4146 case OP_VSPLTISW1: 4147 for (unsigned i = 0; i != 16; ++i) 4148 ShufIdxs[i] = (i&3)+4; 4149 break; 4150 case OP_VSPLTISW2: 4151 for (unsigned i = 0; i != 16; ++i) 4152 ShufIdxs[i] = (i&3)+8; 4153 break; 4154 case OP_VSPLTISW3: 4155 for (unsigned i = 0; i != 16; ++i) 4156 ShufIdxs[i] = (i&3)+12; 4157 break; 4158 case OP_VSLDOI4: 4159 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 4160 case OP_VSLDOI8: 4161 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 4162 case OP_VSLDOI12: 4163 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 4164 } 4165 EVT VT = OpLHS.getValueType(); 4166 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); 4167 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); 4168 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 4169 return DAG.getNode(ISD::BITCAST, dl, VT, T); 4170} 4171 4172/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 4173/// is a shuffle we can handle in a single instruction, return it. Otherwise, 4174/// return the code it can be lowered into. Worst case, it can always be 4175/// lowered into a vperm. 4176SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4177 SelectionDAG &DAG) const { 4178 DebugLoc dl = Op.getDebugLoc(); 4179 SDValue V1 = Op.getOperand(0); 4180 SDValue V2 = Op.getOperand(1); 4181 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4182 EVT VT = Op.getValueType(); 4183 4184 // Cases that are handled by instructions that take permute immediates 4185 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 4186 // selected by the instruction selector. 4187 if (V2.getOpcode() == ISD::UNDEF) { 4188 if (PPC::isSplatShuffleMask(SVOp, 1) || 4189 PPC::isSplatShuffleMask(SVOp, 2) || 4190 PPC::isSplatShuffleMask(SVOp, 4) || 4191 PPC::isVPKUWUMShuffleMask(SVOp, true) || 4192 PPC::isVPKUHUMShuffleMask(SVOp, true) || 4193 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 4194 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 4195 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 4196 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 4197 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 4198 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 4199 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 4200 return Op; 4201 } 4202 } 4203 4204 // Altivec has a variety of "shuffle immediates" that take two vector inputs 4205 // and produce a fixed permutation. If any of these match, do not lower to 4206 // VPERM. 4207 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 4208 PPC::isVPKUHUMShuffleMask(SVOp, false) || 4209 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 4210 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 4211 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 4212 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 4213 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 4214 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 4215 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 4216 return Op; 4217 4218 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 4219 // perfect shuffle table to emit an optimal matching sequence. 4220 SmallVector<int, 16> PermMask; 4221 SVOp->getMask(PermMask); 4222 4223 unsigned PFIndexes[4]; 4224 bool isFourElementShuffle = true; 4225 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 4226 unsigned EltNo = 8; // Start out undef. 4227 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 4228 if (PermMask[i*4+j] < 0) 4229 continue; // Undef, ignore it. 4230 4231 unsigned ByteSource = PermMask[i*4+j]; 4232 if ((ByteSource & 3) != j) { 4233 isFourElementShuffle = false; 4234 break; 4235 } 4236 4237 if (EltNo == 8) { 4238 EltNo = ByteSource/4; 4239 } else if (EltNo != ByteSource/4) { 4240 isFourElementShuffle = false; 4241 break; 4242 } 4243 } 4244 PFIndexes[i] = EltNo; 4245 } 4246 4247 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 4248 // perfect shuffle vector to determine if it is cost effective to do this as 4249 // discrete instructions, or whether we should use a vperm. 4250 if (isFourElementShuffle) { 4251 // Compute the index in the perfect shuffle table. 4252 unsigned PFTableIndex = 4253 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4254 4255 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4256 unsigned Cost = (PFEntry >> 30); 4257 4258 // Determining when to avoid vperm is tricky. Many things affect the cost 4259 // of vperm, particularly how many times the perm mask needs to be computed. 4260 // For example, if the perm mask can be hoisted out of a loop or is already 4261 // used (perhaps because there are multiple permutes with the same shuffle 4262 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 4263 // the loop requires an extra register. 4264 // 4265 // As a compromise, we only emit discrete instructions if the shuffle can be 4266 // generated in 3 or fewer operations. When we have loop information 4267 // available, if this block is within a loop, we should avoid using vperm 4268 // for 3-operation perms and use a constant pool load instead. 4269 if (Cost < 3) 4270 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4271 } 4272 4273 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 4274 // vector that will get spilled to the constant pool. 4275 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 4276 4277 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 4278 // that it is in input element units, not in bytes. Convert now. 4279 EVT EltVT = V1.getValueType().getVectorElementType(); 4280 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 4281 4282 SmallVector<SDValue, 16> ResultMask; 4283 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4284 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 4285 4286 for (unsigned j = 0; j != BytesPerElement; ++j) 4287 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 4288 MVT::i32)); 4289 } 4290 4291 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 4292 &ResultMask[0], ResultMask.size()); 4293 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 4294} 4295 4296/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 4297/// altivec comparison. If it is, return true and fill in Opc/isDot with 4298/// information about the intrinsic. 4299static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 4300 bool &isDot) { 4301 unsigned IntrinsicID = 4302 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 4303 CompareOpc = -1; 4304 isDot = false; 4305 switch (IntrinsicID) { 4306 default: return false; 4307 // Comparison predicates. 4308 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 4309 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 4310 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 4311 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 4312 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 4313 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 4314 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 4315 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 4316 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 4317 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 4318 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 4319 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 4320 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 4321 4322 // Normal Comparisons. 4323 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 4324 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 4325 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 4326 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 4327 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 4328 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 4329 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 4330 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 4331 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 4332 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 4333 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 4334 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 4335 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 4336 } 4337 return true; 4338} 4339 4340/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 4341/// lower, do it, otherwise return null. 4342SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 4343 SelectionDAG &DAG) const { 4344 // If this is a lowered altivec predicate compare, CompareOpc is set to the 4345 // opcode number of the comparison. 4346 DebugLoc dl = Op.getDebugLoc(); 4347 int CompareOpc; 4348 bool isDot; 4349 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 4350 return SDValue(); // Don't custom lower most intrinsics. 4351 4352 // If this is a non-dot comparison, make the VCMP node and we are done. 4353 if (!isDot) { 4354 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 4355 Op.getOperand(1), Op.getOperand(2), 4356 DAG.getConstant(CompareOpc, MVT::i32)); 4357 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp); 4358 } 4359 4360 // Create the PPCISD altivec 'dot' comparison node. 4361 SDValue Ops[] = { 4362 Op.getOperand(2), // LHS 4363 Op.getOperand(3), // RHS 4364 DAG.getConstant(CompareOpc, MVT::i32) 4365 }; 4366 std::vector<EVT> VTs; 4367 VTs.push_back(Op.getOperand(2).getValueType()); 4368 VTs.push_back(MVT::Glue); 4369 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 4370 4371 // Now that we have the comparison, emit a copy from the CR to a GPR. 4372 // This is flagged to the above dot comparison. 4373 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 4374 DAG.getRegister(PPC::CR6, MVT::i32), 4375 CompNode.getValue(1)); 4376 4377 // Unpack the result based on how the target uses it. 4378 unsigned BitNo; // Bit # of CR6. 4379 bool InvertBit; // Invert result? 4380 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 4381 default: // Can't happen, don't crash on invalid number though. 4382 case 0: // Return the value of the EQ bit of CR6. 4383 BitNo = 0; InvertBit = false; 4384 break; 4385 case 1: // Return the inverted value of the EQ bit of CR6. 4386 BitNo = 0; InvertBit = true; 4387 break; 4388 case 2: // Return the value of the LT bit of CR6. 4389 BitNo = 2; InvertBit = false; 4390 break; 4391 case 3: // Return the inverted value of the LT bit of CR6. 4392 BitNo = 2; InvertBit = true; 4393 break; 4394 } 4395 4396 // Shift the bit into the low position. 4397 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 4398 DAG.getConstant(8-(3-BitNo), MVT::i32)); 4399 // Isolate the bit. 4400 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 4401 DAG.getConstant(1, MVT::i32)); 4402 4403 // If we are supposed to, toggle the bit. 4404 if (InvertBit) 4405 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 4406 DAG.getConstant(1, MVT::i32)); 4407 return Flags; 4408} 4409 4410SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 4411 SelectionDAG &DAG) const { 4412 DebugLoc dl = Op.getDebugLoc(); 4413 // Create a stack slot that is 16-byte aligned. 4414 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4415 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 4416 EVT PtrVT = getPointerTy(); 4417 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4418 4419 // Store the input value into Value#0 of the stack slot. 4420 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 4421 Op.getOperand(0), FIdx, MachinePointerInfo(), 4422 false, false, 0); 4423 // Load it out. 4424 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), 4425 false, false, 0); 4426} 4427 4428SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 4429 DebugLoc dl = Op.getDebugLoc(); 4430 if (Op.getValueType() == MVT::v4i32) { 4431 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4432 4433 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 4434 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 4435 4436 SDValue RHSSwap = // = vrlw RHS, 16 4437 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 4438 4439 // Shrinkify inputs to v8i16. 4440 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); 4441 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); 4442 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); 4443 4444 // Low parts multiplied together, generating 32-bit results (we ignore the 4445 // top parts). 4446 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 4447 LHS, RHS, DAG, dl, MVT::v4i32); 4448 4449 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 4450 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 4451 // Shift the high parts up 16 bits. 4452 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 4453 Neg16, DAG, dl); 4454 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 4455 } else if (Op.getValueType() == MVT::v8i16) { 4456 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4457 4458 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 4459 4460 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 4461 LHS, RHS, Zero, DAG, dl); 4462 } else if (Op.getValueType() == MVT::v16i8) { 4463 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4464 4465 // Multiply the even 8-bit parts, producing 16-bit sums. 4466 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 4467 LHS, RHS, DAG, dl, MVT::v8i16); 4468 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); 4469 4470 // Multiply the odd 8-bit parts, producing 16-bit sums. 4471 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 4472 LHS, RHS, DAG, dl, MVT::v8i16); 4473 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); 4474 4475 // Merge the results together. 4476 int Ops[16]; 4477 for (unsigned i = 0; i != 8; ++i) { 4478 Ops[i*2 ] = 2*i+1; 4479 Ops[i*2+1] = 2*i+1+16; 4480 } 4481 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 4482 } else { 4483 llvm_unreachable("Unknown mul to lower!"); 4484 } 4485} 4486 4487/// LowerOperation - Provide custom lowering hooks for some operations. 4488/// 4489SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4490 switch (Op.getOpcode()) { 4491 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 4492 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4493 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4494 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 4495 case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for PPC"); 4496 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 4497 case ISD::SETCC: return LowerSETCC(Op, DAG); 4498 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 4499 case ISD::VASTART: 4500 return LowerVASTART(Op, DAG, PPCSubTarget); 4501 4502 case ISD::VAARG: 4503 return LowerVAARG(Op, DAG, PPCSubTarget); 4504 4505 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 4506 case ISD::DYNAMIC_STACKALLOC: 4507 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 4508 4509 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4510 case ISD::FP_TO_UINT: 4511 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 4512 Op.getDebugLoc()); 4513 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 4514 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4515 4516 // Lower 64-bit shifts. 4517 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 4518 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 4519 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 4520 4521 // Vector-related lowering. 4522 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 4523 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4524 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 4525 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 4526 case ISD::MUL: return LowerMUL(Op, DAG); 4527 4528 // Frame & Return address. 4529 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4530 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4531 } 4532 return SDValue(); 4533} 4534 4535void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 4536 SmallVectorImpl<SDValue>&Results, 4537 SelectionDAG &DAG) const { 4538 const TargetMachine &TM = getTargetMachine(); 4539 DebugLoc dl = N->getDebugLoc(); 4540 switch (N->getOpcode()) { 4541 default: 4542 assert(false && "Do not know how to custom type legalize this operation!"); 4543 return; 4544 case ISD::VAARG: { 4545 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 4546 || TM.getSubtarget<PPCSubtarget>().isPPC64()) 4547 return; 4548 4549 EVT VT = N->getValueType(0); 4550 4551 if (VT == MVT::i64) { 4552 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget); 4553 4554 Results.push_back(NewNode); 4555 Results.push_back(NewNode.getValue(1)); 4556 } 4557 return; 4558 } 4559 case ISD::FP_ROUND_INREG: { 4560 assert(N->getValueType(0) == MVT::ppcf128); 4561 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 4562 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4563 MVT::f64, N->getOperand(0), 4564 DAG.getIntPtrConstant(0)); 4565 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4566 MVT::f64, N->getOperand(0), 4567 DAG.getIntPtrConstant(1)); 4568 4569 // This sequence changes FPSCR to do round-to-zero, adds the two halves 4570 // of the long double, and puts FPSCR back the way it was. We do not 4571 // actually model FPSCR. 4572 std::vector<EVT> NodeTys; 4573 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 4574 4575 NodeTys.push_back(MVT::f64); // Return register 4576 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns 4577 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4578 MFFSreg = Result.getValue(0); 4579 InFlag = Result.getValue(1); 4580 4581 NodeTys.clear(); 4582 NodeTys.push_back(MVT::Glue); // Returns a flag 4583 Ops[0] = DAG.getConstant(31, MVT::i32); 4584 Ops[1] = InFlag; 4585 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 4586 InFlag = Result.getValue(0); 4587 4588 NodeTys.clear(); 4589 NodeTys.push_back(MVT::Glue); // Returns a flag 4590 Ops[0] = DAG.getConstant(30, MVT::i32); 4591 Ops[1] = InFlag; 4592 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 4593 InFlag = Result.getValue(0); 4594 4595 NodeTys.clear(); 4596 NodeTys.push_back(MVT::f64); // result of add 4597 NodeTys.push_back(MVT::Glue); // Returns a flag 4598 Ops[0] = Lo; 4599 Ops[1] = Hi; 4600 Ops[2] = InFlag; 4601 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 4602 FPreg = Result.getValue(0); 4603 InFlag = Result.getValue(1); 4604 4605 NodeTys.clear(); 4606 NodeTys.push_back(MVT::f64); 4607 Ops[0] = DAG.getConstant(1, MVT::i32); 4608 Ops[1] = MFFSreg; 4609 Ops[2] = FPreg; 4610 Ops[3] = InFlag; 4611 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 4612 FPreg = Result.getValue(0); 4613 4614 // We know the low half is about to be thrown away, so just use something 4615 // convenient. 4616 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 4617 FPreg, FPreg)); 4618 return; 4619 } 4620 case ISD::FP_TO_SINT: 4621 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 4622 return; 4623 } 4624} 4625 4626 4627//===----------------------------------------------------------------------===// 4628// Other Lowering Code 4629//===----------------------------------------------------------------------===// 4630 4631MachineBasicBlock * 4632PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 4633 bool is64bit, unsigned BinOpcode) const { 4634 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4635 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4636 4637 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4638 MachineFunction *F = BB->getParent(); 4639 MachineFunction::iterator It = BB; 4640 ++It; 4641 4642 unsigned dest = MI->getOperand(0).getReg(); 4643 unsigned ptrA = MI->getOperand(1).getReg(); 4644 unsigned ptrB = MI->getOperand(2).getReg(); 4645 unsigned incr = MI->getOperand(3).getReg(); 4646 DebugLoc dl = MI->getDebugLoc(); 4647 4648 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4649 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4650 F->insert(It, loopMBB); 4651 F->insert(It, exitMBB); 4652 exitMBB->splice(exitMBB->begin(), BB, 4653 llvm::next(MachineBasicBlock::iterator(MI)), 4654 BB->end()); 4655 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4656 4657 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4658 unsigned TmpReg = (!BinOpcode) ? incr : 4659 RegInfo.createVirtualRegister( 4660 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4661 (const TargetRegisterClass *) &PPC::GPRCRegClass); 4662 4663 // thisMBB: 4664 // ... 4665 // fallthrough --> loopMBB 4666 BB->addSuccessor(loopMBB); 4667 4668 // loopMBB: 4669 // l[wd]arx dest, ptr 4670 // add r0, dest, incr 4671 // st[wd]cx. r0, ptr 4672 // bne- loopMBB 4673 // fallthrough --> exitMBB 4674 BB = loopMBB; 4675 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4676 .addReg(ptrA).addReg(ptrB); 4677 if (BinOpcode) 4678 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 4679 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4680 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 4681 BuildMI(BB, dl, TII->get(PPC::BCC)) 4682 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4683 BB->addSuccessor(loopMBB); 4684 BB->addSuccessor(exitMBB); 4685 4686 // exitMBB: 4687 // ... 4688 BB = exitMBB; 4689 return BB; 4690} 4691 4692MachineBasicBlock * 4693PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 4694 MachineBasicBlock *BB, 4695 bool is8bit, // operation 4696 unsigned BinOpcode) const { 4697 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4698 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4699 // In 64 bit mode we have to use 64 bits for addresses, even though the 4700 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 4701 // registers without caring whether they're 32 or 64, but here we're 4702 // doing actual arithmetic on the addresses. 4703 bool is64bit = PPCSubTarget.isPPC64(); 4704 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 4705 4706 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4707 MachineFunction *F = BB->getParent(); 4708 MachineFunction::iterator It = BB; 4709 ++It; 4710 4711 unsigned dest = MI->getOperand(0).getReg(); 4712 unsigned ptrA = MI->getOperand(1).getReg(); 4713 unsigned ptrB = MI->getOperand(2).getReg(); 4714 unsigned incr = MI->getOperand(3).getReg(); 4715 DebugLoc dl = MI->getDebugLoc(); 4716 4717 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4718 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4719 F->insert(It, loopMBB); 4720 F->insert(It, exitMBB); 4721 exitMBB->splice(exitMBB->begin(), BB, 4722 llvm::next(MachineBasicBlock::iterator(MI)), 4723 BB->end()); 4724 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4725 4726 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4727 const TargetRegisterClass *RC = 4728 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4729 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4730 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4731 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4732 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4733 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 4734 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4735 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4736 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4737 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4738 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 4739 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4740 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4741 unsigned Ptr1Reg; 4742 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 4743 4744 // thisMBB: 4745 // ... 4746 // fallthrough --> loopMBB 4747 BB->addSuccessor(loopMBB); 4748 4749 // The 4-byte load must be aligned, while a char or short may be 4750 // anywhere in the word. Hence all this nasty bookkeeping code. 4751 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4752 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4753 // xori shift, shift1, 24 [16] 4754 // rlwinm ptr, ptr1, 0, 0, 29 4755 // slw incr2, incr, shift 4756 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4757 // slw mask, mask2, shift 4758 // loopMBB: 4759 // lwarx tmpDest, ptr 4760 // add tmp, tmpDest, incr2 4761 // andc tmp2, tmpDest, mask 4762 // and tmp3, tmp, mask 4763 // or tmp4, tmp3, tmp2 4764 // stwcx. tmp4, ptr 4765 // bne- loopMBB 4766 // fallthrough --> exitMBB 4767 // srw dest, tmpDest, shift 4768 if (ptrA != ZeroReg) { 4769 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4770 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4771 .addReg(ptrA).addReg(ptrB); 4772 } else { 4773 Ptr1Reg = ptrB; 4774 } 4775 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4776 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4777 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4778 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4779 if (is64bit) 4780 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4781 .addReg(Ptr1Reg).addImm(0).addImm(61); 4782 else 4783 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4784 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4785 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 4786 .addReg(incr).addReg(ShiftReg); 4787 if (is8bit) 4788 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4789 else { 4790 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4791 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 4792 } 4793 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 4794 .addReg(Mask2Reg).addReg(ShiftReg); 4795 4796 BB = loopMBB; 4797 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 4798 .addReg(ZeroReg).addReg(PtrReg); 4799 if (BinOpcode) 4800 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 4801 .addReg(Incr2Reg).addReg(TmpDestReg); 4802 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 4803 .addReg(TmpDestReg).addReg(MaskReg); 4804 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 4805 .addReg(TmpReg).addReg(MaskReg); 4806 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 4807 .addReg(Tmp3Reg).addReg(Tmp2Reg); 4808 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4809 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg); 4810 BuildMI(BB, dl, TII->get(PPC::BCC)) 4811 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4812 BB->addSuccessor(loopMBB); 4813 BB->addSuccessor(exitMBB); 4814 4815 // exitMBB: 4816 // ... 4817 BB = exitMBB; 4818 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg) 4819 .addReg(ShiftReg); 4820 return BB; 4821} 4822 4823MachineBasicBlock * 4824PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4825 MachineBasicBlock *BB) const { 4826 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4827 4828 // To "insert" these instructions we actually have to insert their 4829 // control-flow patterns. 4830 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4831 MachineFunction::iterator It = BB; 4832 ++It; 4833 4834 MachineFunction *F = BB->getParent(); 4835 4836 if (MI->getOpcode() == PPC::SELECT_CC_I4 || 4837 MI->getOpcode() == PPC::SELECT_CC_I8 || 4838 MI->getOpcode() == PPC::SELECT_CC_F4 || 4839 MI->getOpcode() == PPC::SELECT_CC_F8 || 4840 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 4841 4842 // The incoming instruction knows the destination vreg to set, the 4843 // condition code register to branch on, the true/false values to 4844 // select between, and a branch opcode to use. 4845 4846 // thisMBB: 4847 // ... 4848 // TrueVal = ... 4849 // cmpTY ccX, r1, r2 4850 // bCC copy1MBB 4851 // fallthrough --> copy0MBB 4852 MachineBasicBlock *thisMBB = BB; 4853 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4854 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4855 unsigned SelectPred = MI->getOperand(4).getImm(); 4856 DebugLoc dl = MI->getDebugLoc(); 4857 F->insert(It, copy0MBB); 4858 F->insert(It, sinkMBB); 4859 4860 // Transfer the remainder of BB and its successor edges to sinkMBB. 4861 sinkMBB->splice(sinkMBB->begin(), BB, 4862 llvm::next(MachineBasicBlock::iterator(MI)), 4863 BB->end()); 4864 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4865 4866 // Next, add the true and fallthrough blocks as its successors. 4867 BB->addSuccessor(copy0MBB); 4868 BB->addSuccessor(sinkMBB); 4869 4870 BuildMI(BB, dl, TII->get(PPC::BCC)) 4871 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 4872 4873 // copy0MBB: 4874 // %FalseValue = ... 4875 // # fallthrough to sinkMBB 4876 BB = copy0MBB; 4877 4878 // Update machine-CFG edges 4879 BB->addSuccessor(sinkMBB); 4880 4881 // sinkMBB: 4882 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4883 // ... 4884 BB = sinkMBB; 4885 BuildMI(*BB, BB->begin(), dl, 4886 TII->get(PPC::PHI), MI->getOperand(0).getReg()) 4887 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 4888 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4889 } 4890 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 4891 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 4892 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 4893 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 4894 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 4895 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 4896 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 4897 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 4898 4899 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 4900 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 4901 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 4902 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 4903 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 4904 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 4905 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 4906 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 4907 4908 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 4909 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 4910 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 4911 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 4912 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 4913 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 4914 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 4915 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 4916 4917 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 4918 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 4919 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 4920 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 4921 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 4922 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 4923 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 4924 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 4925 4926 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 4927 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 4928 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 4929 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 4930 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 4931 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 4932 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 4933 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 4934 4935 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 4936 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 4937 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 4938 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 4939 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 4940 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 4941 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 4942 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 4943 4944 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 4945 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 4946 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 4947 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 4948 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 4949 BB = EmitAtomicBinary(MI, BB, false, 0); 4950 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 4951 BB = EmitAtomicBinary(MI, BB, true, 0); 4952 4953 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 4954 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 4955 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 4956 4957 unsigned dest = MI->getOperand(0).getReg(); 4958 unsigned ptrA = MI->getOperand(1).getReg(); 4959 unsigned ptrB = MI->getOperand(2).getReg(); 4960 unsigned oldval = MI->getOperand(3).getReg(); 4961 unsigned newval = MI->getOperand(4).getReg(); 4962 DebugLoc dl = MI->getDebugLoc(); 4963 4964 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4965 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4966 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4967 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4968 F->insert(It, loop1MBB); 4969 F->insert(It, loop2MBB); 4970 F->insert(It, midMBB); 4971 F->insert(It, exitMBB); 4972 exitMBB->splice(exitMBB->begin(), BB, 4973 llvm::next(MachineBasicBlock::iterator(MI)), 4974 BB->end()); 4975 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4976 4977 // thisMBB: 4978 // ... 4979 // fallthrough --> loopMBB 4980 BB->addSuccessor(loop1MBB); 4981 4982 // loop1MBB: 4983 // l[wd]arx dest, ptr 4984 // cmp[wd] dest, oldval 4985 // bne- midMBB 4986 // loop2MBB: 4987 // st[wd]cx. newval, ptr 4988 // bne- loopMBB 4989 // b exitBB 4990 // midMBB: 4991 // st[wd]cx. dest, ptr 4992 // exitBB: 4993 BB = loop1MBB; 4994 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4995 .addReg(ptrA).addReg(ptrB); 4996 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 4997 .addReg(oldval).addReg(dest); 4998 BuildMI(BB, dl, TII->get(PPC::BCC)) 4999 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 5000 BB->addSuccessor(loop2MBB); 5001 BB->addSuccessor(midMBB); 5002 5003 BB = loop2MBB; 5004 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5005 .addReg(newval).addReg(ptrA).addReg(ptrB); 5006 BuildMI(BB, dl, TII->get(PPC::BCC)) 5007 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5008 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5009 BB->addSuccessor(loop1MBB); 5010 BB->addSuccessor(exitMBB); 5011 5012 BB = midMBB; 5013 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 5014 .addReg(dest).addReg(ptrA).addReg(ptrB); 5015 BB->addSuccessor(exitMBB); 5016 5017 // exitMBB: 5018 // ... 5019 BB = exitMBB; 5020 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 5021 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 5022 // We must use 64-bit registers for addresses when targeting 64-bit, 5023 // since we're actually doing arithmetic on them. Other registers 5024 // can be 32-bit. 5025 bool is64bit = PPCSubTarget.isPPC64(); 5026 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 5027 5028 unsigned dest = MI->getOperand(0).getReg(); 5029 unsigned ptrA = MI->getOperand(1).getReg(); 5030 unsigned ptrB = MI->getOperand(2).getReg(); 5031 unsigned oldval = MI->getOperand(3).getReg(); 5032 unsigned newval = MI->getOperand(4).getReg(); 5033 DebugLoc dl = MI->getDebugLoc(); 5034 5035 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 5036 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 5037 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 5038 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 5039 F->insert(It, loop1MBB); 5040 F->insert(It, loop2MBB); 5041 F->insert(It, midMBB); 5042 F->insert(It, exitMBB); 5043 exitMBB->splice(exitMBB->begin(), BB, 5044 llvm::next(MachineBasicBlock::iterator(MI)), 5045 BB->end()); 5046 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5047 5048 MachineRegisterInfo &RegInfo = F->getRegInfo(); 5049 const TargetRegisterClass *RC = 5050 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 5051 (const TargetRegisterClass *) &PPC::GPRCRegClass; 5052 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 5053 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 5054 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 5055 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 5056 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 5057 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 5058 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 5059 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 5060 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 5061 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 5062 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 5063 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 5064 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 5065 unsigned Ptr1Reg; 5066 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 5067 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 5068 // thisMBB: 5069 // ... 5070 // fallthrough --> loopMBB 5071 BB->addSuccessor(loop1MBB); 5072 5073 // The 4-byte load must be aligned, while a char or short may be 5074 // anywhere in the word. Hence all this nasty bookkeeping code. 5075 // add ptr1, ptrA, ptrB [copy if ptrA==0] 5076 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 5077 // xori shift, shift1, 24 [16] 5078 // rlwinm ptr, ptr1, 0, 0, 29 5079 // slw newval2, newval, shift 5080 // slw oldval2, oldval,shift 5081 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 5082 // slw mask, mask2, shift 5083 // and newval3, newval2, mask 5084 // and oldval3, oldval2, mask 5085 // loop1MBB: 5086 // lwarx tmpDest, ptr 5087 // and tmp, tmpDest, mask 5088 // cmpw tmp, oldval3 5089 // bne- midMBB 5090 // loop2MBB: 5091 // andc tmp2, tmpDest, mask 5092 // or tmp4, tmp2, newval3 5093 // stwcx. tmp4, ptr 5094 // bne- loop1MBB 5095 // b exitBB 5096 // midMBB: 5097 // stwcx. tmpDest, ptr 5098 // exitBB: 5099 // srw dest, tmpDest, shift 5100 if (ptrA != ZeroReg) { 5101 Ptr1Reg = RegInfo.createVirtualRegister(RC); 5102 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 5103 .addReg(ptrA).addReg(ptrB); 5104 } else { 5105 Ptr1Reg = ptrB; 5106 } 5107 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 5108 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 5109 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 5110 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 5111 if (is64bit) 5112 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 5113 .addReg(Ptr1Reg).addImm(0).addImm(61); 5114 else 5115 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 5116 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 5117 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 5118 .addReg(newval).addReg(ShiftReg); 5119 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 5120 .addReg(oldval).addReg(ShiftReg); 5121 if (is8bit) 5122 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 5123 else { 5124 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 5125 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 5126 .addReg(Mask3Reg).addImm(65535); 5127 } 5128 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5129 .addReg(Mask2Reg).addReg(ShiftReg); 5130 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 5131 .addReg(NewVal2Reg).addReg(MaskReg); 5132 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 5133 .addReg(OldVal2Reg).addReg(MaskReg); 5134 5135 BB = loop1MBB; 5136 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5137 .addReg(ZeroReg).addReg(PtrReg); 5138 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 5139 .addReg(TmpDestReg).addReg(MaskReg); 5140 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 5141 .addReg(TmpReg).addReg(OldVal3Reg); 5142 BuildMI(BB, dl, TII->get(PPC::BCC)) 5143 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 5144 BB->addSuccessor(loop2MBB); 5145 BB->addSuccessor(midMBB); 5146 5147 BB = loop2MBB; 5148 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 5149 .addReg(TmpDestReg).addReg(MaskReg); 5150 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 5151 .addReg(Tmp2Reg).addReg(NewVal3Reg); 5152 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 5153 .addReg(ZeroReg).addReg(PtrReg); 5154 BuildMI(BB, dl, TII->get(PPC::BCC)) 5155 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5156 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5157 BB->addSuccessor(loop1MBB); 5158 BB->addSuccessor(exitMBB); 5159 5160 BB = midMBB; 5161 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 5162 .addReg(ZeroReg).addReg(PtrReg); 5163 BB->addSuccessor(exitMBB); 5164 5165 // exitMBB: 5166 // ... 5167 BB = exitMBB; 5168 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) 5169 .addReg(ShiftReg); 5170 } else { 5171 llvm_unreachable("Unexpected instr type to insert"); 5172 } 5173 5174 MI->eraseFromParent(); // The pseudo instruction is gone now. 5175 return BB; 5176} 5177 5178//===----------------------------------------------------------------------===// 5179// Target Optimization Hooks 5180//===----------------------------------------------------------------------===// 5181 5182SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 5183 DAGCombinerInfo &DCI) const { 5184 const TargetMachine &TM = getTargetMachine(); 5185 SelectionDAG &DAG = DCI.DAG; 5186 DebugLoc dl = N->getDebugLoc(); 5187 switch (N->getOpcode()) { 5188 default: break; 5189 case PPCISD::SHL: 5190 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5191 if (C->isNullValue()) // 0 << V -> 0. 5192 return N->getOperand(0); 5193 } 5194 break; 5195 case PPCISD::SRL: 5196 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5197 if (C->isNullValue()) // 0 >>u V -> 0. 5198 return N->getOperand(0); 5199 } 5200 break; 5201 case PPCISD::SRA: 5202 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5203 if (C->isNullValue() || // 0 >>s V -> 0. 5204 C->isAllOnesValue()) // -1 >>s V -> -1. 5205 return N->getOperand(0); 5206 } 5207 break; 5208 5209 case ISD::SINT_TO_FP: 5210 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 5211 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 5212 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 5213 // We allow the src/dst to be either f32/f64, but the intermediate 5214 // type must be i64. 5215 if (N->getOperand(0).getValueType() == MVT::i64 && 5216 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 5217 SDValue Val = N->getOperand(0).getOperand(0); 5218 if (Val.getValueType() == MVT::f32) { 5219 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5220 DCI.AddToWorklist(Val.getNode()); 5221 } 5222 5223 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 5224 DCI.AddToWorklist(Val.getNode()); 5225 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 5226 DCI.AddToWorklist(Val.getNode()); 5227 if (N->getValueType(0) == MVT::f32) { 5228 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 5229 DAG.getIntPtrConstant(0)); 5230 DCI.AddToWorklist(Val.getNode()); 5231 } 5232 return Val; 5233 } else if (N->getOperand(0).getValueType() == MVT::i32) { 5234 // If the intermediate type is i32, we can avoid the load/store here 5235 // too. 5236 } 5237 } 5238 } 5239 break; 5240 case ISD::STORE: 5241 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 5242 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 5243 !cast<StoreSDNode>(N)->isTruncatingStore() && 5244 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 5245 N->getOperand(1).getValueType() == MVT::i32 && 5246 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 5247 SDValue Val = N->getOperand(1).getOperand(0); 5248 if (Val.getValueType() == MVT::f32) { 5249 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5250 DCI.AddToWorklist(Val.getNode()); 5251 } 5252 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 5253 DCI.AddToWorklist(Val.getNode()); 5254 5255 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 5256 N->getOperand(2), N->getOperand(3)); 5257 DCI.AddToWorklist(Val.getNode()); 5258 return Val; 5259 } 5260 5261 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 5262 if (cast<StoreSDNode>(N)->isUnindexed() && 5263 N->getOperand(1).getOpcode() == ISD::BSWAP && 5264 N->getOperand(1).getNode()->hasOneUse() && 5265 (N->getOperand(1).getValueType() == MVT::i32 || 5266 N->getOperand(1).getValueType() == MVT::i16)) { 5267 SDValue BSwapOp = N->getOperand(1).getOperand(0); 5268 // Do an any-extend to 32-bits if this is a half-word input. 5269 if (BSwapOp.getValueType() == MVT::i16) 5270 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 5271 5272 SDValue Ops[] = { 5273 N->getOperand(0), BSwapOp, N->getOperand(2), 5274 DAG.getValueType(N->getOperand(1).getValueType()) 5275 }; 5276 return 5277 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 5278 Ops, array_lengthof(Ops), 5279 cast<StoreSDNode>(N)->getMemoryVT(), 5280 cast<StoreSDNode>(N)->getMemOperand()); 5281 } 5282 break; 5283 case ISD::BSWAP: 5284 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 5285 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 5286 N->getOperand(0).hasOneUse() && 5287 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 5288 SDValue Load = N->getOperand(0); 5289 LoadSDNode *LD = cast<LoadSDNode>(Load); 5290 // Create the byte-swapping load. 5291 SDValue Ops[] = { 5292 LD->getChain(), // Chain 5293 LD->getBasePtr(), // Ptr 5294 DAG.getValueType(N->getValueType(0)) // VT 5295 }; 5296 SDValue BSLoad = 5297 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 5298 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 5299 LD->getMemoryVT(), LD->getMemOperand()); 5300 5301 // If this is an i16 load, insert the truncate. 5302 SDValue ResVal = BSLoad; 5303 if (N->getValueType(0) == MVT::i16) 5304 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 5305 5306 // First, combine the bswap away. This makes the value produced by the 5307 // load dead. 5308 DCI.CombineTo(N, ResVal); 5309 5310 // Next, combine the load away, we give it a bogus result value but a real 5311 // chain result. The result value is dead because the bswap is dead. 5312 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 5313 5314 // Return N so it doesn't get rechecked! 5315 return SDValue(N, 0); 5316 } 5317 5318 break; 5319 case PPCISD::VCMP: { 5320 // If a VCMPo node already exists with exactly the same operands as this 5321 // node, use its result instead of this node (VCMPo computes both a CR6 and 5322 // a normal output). 5323 // 5324 if (!N->getOperand(0).hasOneUse() && 5325 !N->getOperand(1).hasOneUse() && 5326 !N->getOperand(2).hasOneUse()) { 5327 5328 // Scan all of the users of the LHS, looking for VCMPo's that match. 5329 SDNode *VCMPoNode = 0; 5330 5331 SDNode *LHSN = N->getOperand(0).getNode(); 5332 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 5333 UI != E; ++UI) 5334 if (UI->getOpcode() == PPCISD::VCMPo && 5335 UI->getOperand(1) == N->getOperand(1) && 5336 UI->getOperand(2) == N->getOperand(2) && 5337 UI->getOperand(0) == N->getOperand(0)) { 5338 VCMPoNode = *UI; 5339 break; 5340 } 5341 5342 // If there is no VCMPo node, or if the flag value has a single use, don't 5343 // transform this. 5344 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 5345 break; 5346 5347 // Look at the (necessarily single) use of the flag value. If it has a 5348 // chain, this transformation is more complex. Note that multiple things 5349 // could use the value result, which we should ignore. 5350 SDNode *FlagUser = 0; 5351 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 5352 FlagUser == 0; ++UI) { 5353 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 5354 SDNode *User = *UI; 5355 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 5356 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 5357 FlagUser = User; 5358 break; 5359 } 5360 } 5361 } 5362 5363 // If the user is a MFCR instruction, we know this is safe. Otherwise we 5364 // give up for right now. 5365 if (FlagUser->getOpcode() == PPCISD::MFCR) 5366 return SDValue(VCMPoNode, 0); 5367 } 5368 break; 5369 } 5370 case ISD::BR_CC: { 5371 // If this is a branch on an altivec predicate comparison, lower this so 5372 // that we don't have to do a MFCR: instead, branch directly on CR6. This 5373 // lowering is done pre-legalize, because the legalizer lowers the predicate 5374 // compare down to code that is difficult to reassemble. 5375 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 5376 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 5377 int CompareOpc; 5378 bool isDot; 5379 5380 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 5381 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 5382 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 5383 assert(isDot && "Can't compare against a vector result!"); 5384 5385 // If this is a comparison against something other than 0/1, then we know 5386 // that the condition is never/always true. 5387 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 5388 if (Val != 0 && Val != 1) { 5389 if (CC == ISD::SETEQ) // Cond never true, remove branch. 5390 return N->getOperand(0); 5391 // Always !=, turn it into an unconditional branch. 5392 return DAG.getNode(ISD::BR, dl, MVT::Other, 5393 N->getOperand(0), N->getOperand(4)); 5394 } 5395 5396 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 5397 5398 // Create the PPCISD altivec 'dot' comparison node. 5399 std::vector<EVT> VTs; 5400 SDValue Ops[] = { 5401 LHS.getOperand(2), // LHS of compare 5402 LHS.getOperand(3), // RHS of compare 5403 DAG.getConstant(CompareOpc, MVT::i32) 5404 }; 5405 VTs.push_back(LHS.getOperand(2).getValueType()); 5406 VTs.push_back(MVT::Glue); 5407 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5408 5409 // Unpack the result based on how the target uses it. 5410 PPC::Predicate CompOpc; 5411 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 5412 default: // Can't happen, don't crash on invalid number though. 5413 case 0: // Branch on the value of the EQ bit of CR6. 5414 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 5415 break; 5416 case 1: // Branch on the inverted value of the EQ bit of CR6. 5417 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 5418 break; 5419 case 2: // Branch on the value of the LT bit of CR6. 5420 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 5421 break; 5422 case 3: // Branch on the inverted value of the LT bit of CR6. 5423 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 5424 break; 5425 } 5426 5427 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 5428 DAG.getConstant(CompOpc, MVT::i32), 5429 DAG.getRegister(PPC::CR6, MVT::i32), 5430 N->getOperand(4), CompNode.getValue(1)); 5431 } 5432 break; 5433 } 5434 } 5435 5436 return SDValue(); 5437} 5438 5439//===----------------------------------------------------------------------===// 5440// Inline Assembly Support 5441//===----------------------------------------------------------------------===// 5442 5443void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 5444 const APInt &Mask, 5445 APInt &KnownZero, 5446 APInt &KnownOne, 5447 const SelectionDAG &DAG, 5448 unsigned Depth) const { 5449 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 5450 switch (Op.getOpcode()) { 5451 default: break; 5452 case PPCISD::LBRX: { 5453 // lhbrx is known to have the top bits cleared out. 5454 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 5455 KnownZero = 0xFFFF0000; 5456 break; 5457 } 5458 case ISD::INTRINSIC_WO_CHAIN: { 5459 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 5460 default: break; 5461 case Intrinsic::ppc_altivec_vcmpbfp_p: 5462 case Intrinsic::ppc_altivec_vcmpeqfp_p: 5463 case Intrinsic::ppc_altivec_vcmpequb_p: 5464 case Intrinsic::ppc_altivec_vcmpequh_p: 5465 case Intrinsic::ppc_altivec_vcmpequw_p: 5466 case Intrinsic::ppc_altivec_vcmpgefp_p: 5467 case Intrinsic::ppc_altivec_vcmpgtfp_p: 5468 case Intrinsic::ppc_altivec_vcmpgtsb_p: 5469 case Intrinsic::ppc_altivec_vcmpgtsh_p: 5470 case Intrinsic::ppc_altivec_vcmpgtsw_p: 5471 case Intrinsic::ppc_altivec_vcmpgtub_p: 5472 case Intrinsic::ppc_altivec_vcmpgtuh_p: 5473 case Intrinsic::ppc_altivec_vcmpgtuw_p: 5474 KnownZero = ~1U; // All bits but the low one are known to be zero. 5475 break; 5476 } 5477 } 5478 } 5479} 5480 5481 5482/// getConstraintType - Given a constraint, return the type of 5483/// constraint it is for this target. 5484PPCTargetLowering::ConstraintType 5485PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 5486 if (Constraint.size() == 1) { 5487 switch (Constraint[0]) { 5488 default: break; 5489 case 'b': 5490 case 'r': 5491 case 'f': 5492 case 'v': 5493 case 'y': 5494 return C_RegisterClass; 5495 } 5496 } 5497 return TargetLowering::getConstraintType(Constraint); 5498} 5499 5500/// Examine constraint type and operand type and determine a weight value. 5501/// This object must already have been set up with the operand type 5502/// and the current alternative constraint selected. 5503TargetLowering::ConstraintWeight 5504PPCTargetLowering::getSingleConstraintMatchWeight( 5505 AsmOperandInfo &info, const char *constraint) const { 5506 ConstraintWeight weight = CW_Invalid; 5507 Value *CallOperandVal = info.CallOperandVal; 5508 // If we don't have a value, we can't do a match, 5509 // but allow it at the lowest weight. 5510 if (CallOperandVal == NULL) 5511 return CW_Default; 5512 Type *type = CallOperandVal->getType(); 5513 // Look at the constraint type. 5514 switch (*constraint) { 5515 default: 5516 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 5517 break; 5518 case 'b': 5519 if (type->isIntegerTy()) 5520 weight = CW_Register; 5521 break; 5522 case 'f': 5523 if (type->isFloatTy()) 5524 weight = CW_Register; 5525 break; 5526 case 'd': 5527 if (type->isDoubleTy()) 5528 weight = CW_Register; 5529 break; 5530 case 'v': 5531 if (type->isVectorTy()) 5532 weight = CW_Register; 5533 break; 5534 case 'y': 5535 weight = CW_Register; 5536 break; 5537 } 5538 return weight; 5539} 5540 5541std::pair<unsigned, const TargetRegisterClass*> 5542PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5543 EVT VT) const { 5544 if (Constraint.size() == 1) { 5545 // GCC RS6000 Constraint Letters 5546 switch (Constraint[0]) { 5547 case 'b': // R1-R31 5548 case 'r': // R0-R31 5549 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 5550 return std::make_pair(0U, PPC::G8RCRegisterClass); 5551 return std::make_pair(0U, PPC::GPRCRegisterClass); 5552 case 'f': 5553 if (VT == MVT::f32) 5554 return std::make_pair(0U, PPC::F4RCRegisterClass); 5555 else if (VT == MVT::f64) 5556 return std::make_pair(0U, PPC::F8RCRegisterClass); 5557 break; 5558 case 'v': 5559 return std::make_pair(0U, PPC::VRRCRegisterClass); 5560 case 'y': // crrc 5561 return std::make_pair(0U, PPC::CRRCRegisterClass); 5562 } 5563 } 5564 5565 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5566} 5567 5568 5569/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5570/// vector. If it is invalid, don't add anything to Ops. 5571void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 5572 std::string &Constraint, 5573 std::vector<SDValue>&Ops, 5574 SelectionDAG &DAG) const { 5575 SDValue Result(0,0); 5576 5577 // Only support length 1 constraints. 5578 if (Constraint.length() > 1) return; 5579 5580 char Letter = Constraint[0]; 5581 switch (Letter) { 5582 default: break; 5583 case 'I': 5584 case 'J': 5585 case 'K': 5586 case 'L': 5587 case 'M': 5588 case 'N': 5589 case 'O': 5590 case 'P': { 5591 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 5592 if (!CST) return; // Must be an immediate to match. 5593 unsigned Value = CST->getZExtValue(); 5594 switch (Letter) { 5595 default: llvm_unreachable("Unknown constraint letter!"); 5596 case 'I': // "I" is a signed 16-bit constant. 5597 if ((short)Value == (int)Value) 5598 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5599 break; 5600 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 5601 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 5602 if ((short)Value == 0) 5603 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5604 break; 5605 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 5606 if ((Value >> 16) == 0) 5607 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5608 break; 5609 case 'M': // "M" is a constant that is greater than 31. 5610 if (Value > 31) 5611 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5612 break; 5613 case 'N': // "N" is a positive constant that is an exact power of two. 5614 if ((int)Value > 0 && isPowerOf2_32(Value)) 5615 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5616 break; 5617 case 'O': // "O" is the constant zero. 5618 if (Value == 0) 5619 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5620 break; 5621 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 5622 if ((short)-Value == (int)-Value) 5623 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5624 break; 5625 } 5626 break; 5627 } 5628 } 5629 5630 if (Result.getNode()) { 5631 Ops.push_back(Result); 5632 return; 5633 } 5634 5635 // Handle standard constraint letters. 5636 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 5637} 5638 5639// isLegalAddressingMode - Return true if the addressing mode represented 5640// by AM is legal for this target, for a load/store of the specified type. 5641bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 5642 Type *Ty) const { 5643 // FIXME: PPC does not allow r+i addressing modes for vectors! 5644 5645 // PPC allows a sign-extended 16-bit immediate field. 5646 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 5647 return false; 5648 5649 // No global is ever allowed as a base. 5650 if (AM.BaseGV) 5651 return false; 5652 5653 // PPC only support r+r, 5654 switch (AM.Scale) { 5655 case 0: // "r+i" or just "i", depending on HasBaseReg. 5656 break; 5657 case 1: 5658 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 5659 return false; 5660 // Otherwise we have r+r or r+i. 5661 break; 5662 case 2: 5663 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 5664 return false; 5665 // Allow 2*r as r+r. 5666 break; 5667 default: 5668 // No other scales are supported. 5669 return false; 5670 } 5671 5672 return true; 5673} 5674 5675/// isLegalAddressImmediate - Return true if the integer value can be used 5676/// as the offset of the target addressing mode for load / store of the 5677/// given type. 5678bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{ 5679 // PPC allows a sign-extended 16-bit immediate field. 5680 return (V > -(1 << 16) && V < (1 << 16)-1); 5681} 5682 5683bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 5684 return false; 5685} 5686 5687SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 5688 SelectionDAG &DAG) const { 5689 MachineFunction &MF = DAG.getMachineFunction(); 5690 MachineFrameInfo *MFI = MF.getFrameInfo(); 5691 MFI->setReturnAddressIsTaken(true); 5692 5693 DebugLoc dl = Op.getDebugLoc(); 5694 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5695 5696 // Make sure the function does not optimize away the store of the RA to 5697 // the stack. 5698 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 5699 FuncInfo->setLRStoreRequired(); 5700 bool isPPC64 = PPCSubTarget.isPPC64(); 5701 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 5702 5703 if (Depth > 0) { 5704 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 5705 SDValue Offset = 5706 5707 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI), 5708 isPPC64? MVT::i64 : MVT::i32); 5709 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5710 DAG.getNode(ISD::ADD, dl, getPointerTy(), 5711 FrameAddr, Offset), 5712 MachinePointerInfo(), false, false, 0); 5713 } 5714 5715 // Just load the return address off the stack. 5716 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 5717 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5718 RetAddrFI, MachinePointerInfo(), false, false, 0); 5719} 5720 5721SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 5722 SelectionDAG &DAG) const { 5723 DebugLoc dl = Op.getDebugLoc(); 5724 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5725 5726 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 5727 bool isPPC64 = PtrVT == MVT::i64; 5728 5729 MachineFunction &MF = DAG.getMachineFunction(); 5730 MachineFrameInfo *MFI = MF.getFrameInfo(); 5731 MFI->setFrameAddressIsTaken(true); 5732 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) && 5733 MFI->getStackSize() && 5734 !MF.getFunction()->hasFnAttr(Attribute::Naked); 5735 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) : 5736 (is31 ? PPC::R31 : PPC::R1); 5737 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 5738 PtrVT); 5739 while (Depth--) 5740 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 5741 FrameAddr, MachinePointerInfo(), false, false, 0); 5742 return FrameAddr; 5743} 5744 5745bool 5746PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 5747 // The PowerPC target isn't yet aware of offsets. 5748 return false; 5749} 5750 5751/// getOptimalMemOpType - Returns the target specific optimal type for load 5752/// and store operations as a result of memset, memcpy, and memmove 5753/// lowering. If DstAlign is zero that means it's safe to destination 5754/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 5755/// means there isn't a need to check it against alignment requirement, 5756/// probably because the source does not need to be loaded. If 5757/// 'NonScalarIntSafe' is true, that means it's safe to return a 5758/// non-scalar-integer type, e.g. empty string source, constant, or loaded 5759/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 5760/// constant so it does not need to be loaded. 5761/// It returns EVT::Other if the type should be determined using generic 5762/// target-independent logic. 5763EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 5764 unsigned DstAlign, unsigned SrcAlign, 5765 bool NonScalarIntSafe, 5766 bool MemcpyStrSrc, 5767 MachineFunction &MF) const { 5768 if (this->PPCSubTarget.isPPC64()) { 5769 return MVT::i64; 5770 } else { 5771 return MVT::i32; 5772 } 5773} 5774