PPCISelLowering.cpp revision 4f9af2ef65febd20e73ef00d868d3fb94db7afd9
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCMachineFunctionInfo.h" 16#include "PPCPerfectShuffle.h" 17#include "PPCPredicates.h" 18#include "PPCTargetMachine.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/VectorExtras.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/CodeGen/PseudoSourceValue.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 29#include "llvm/CallingConv.h" 30#include "llvm/Constants.h" 31#include "llvm/Function.h" 32#include "llvm/Intrinsics.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/DerivedTypes.h" 39using namespace llvm; 40 41static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 42 CCValAssign::LocInfo &LocInfo, 43 ISD::ArgFlagsTy &ArgFlags, 44 CCState &State); 45static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, 46 EVT &LocVT, 47 CCValAssign::LocInfo &LocInfo, 48 ISD::ArgFlagsTy &ArgFlags, 49 CCState &State); 50static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, 51 EVT &LocVT, 52 CCValAssign::LocInfo &LocInfo, 53 ISD::ArgFlagsTy &ArgFlags, 54 CCState &State); 55 56static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc", 57cl::desc("enable preincrement load/store generation on PPC (experimental)"), 58 cl::Hidden); 59 60static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { 61 if (TM.getSubtargetImpl()->isDarwin()) 62 return new TargetLoweringObjectFileMachO(); 63 64 return new TargetLoweringObjectFileELF(); 65} 66 67PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) 68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 69 70 setPow2DivIsCheap(); 71 72 // Use _setjmp/_longjmp instead of setjmp/longjmp. 73 setUseUnderscoreSetJmp(true); 74 setUseUnderscoreLongJmp(true); 75 76 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all 77 // arguments are at least 4/8 bytes aligned. 78 setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4); 79 80 // Set up the register classes. 81 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 82 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 83 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 84 85 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 86 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 87 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); 88 89 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 90 91 // PowerPC has pre-inc load and store's. 92 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 93 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); 94 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); 95 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); 96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); 97 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 98 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); 99 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); 100 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); 101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); 102 103 // This is used in the ppcf128->int sequence. Note it has different semantics 104 // from FP_ROUND: that rounds to nearest, this rounds to zero. 105 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); 106 107 // PowerPC has no SREM/UREM instructions 108 setOperationAction(ISD::SREM, MVT::i32, Expand); 109 setOperationAction(ISD::UREM, MVT::i32, Expand); 110 setOperationAction(ISD::SREM, MVT::i64, Expand); 111 setOperationAction(ISD::UREM, MVT::i64, Expand); 112 113 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. 114 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 116 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 117 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 118 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 119 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 120 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 121 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 122 123 // We don't support sin/cos/sqrt/fmod/pow 124 setOperationAction(ISD::FSIN , MVT::f64, Expand); 125 setOperationAction(ISD::FCOS , MVT::f64, Expand); 126 setOperationAction(ISD::FREM , MVT::f64, Expand); 127 setOperationAction(ISD::FPOW , MVT::f64, Expand); 128 setOperationAction(ISD::FSIN , MVT::f32, Expand); 129 setOperationAction(ISD::FCOS , MVT::f32, Expand); 130 setOperationAction(ISD::FREM , MVT::f32, Expand); 131 setOperationAction(ISD::FPOW , MVT::f32, Expand); 132 133 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 134 135 // If we're enabling GP optimizations, use hardware square root 136 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 137 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 138 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 139 } 140 141 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 142 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 143 144 // PowerPC does not have BSWAP, CTPOP or CTTZ 145 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); 146 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 147 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 148 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); 149 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); 150 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); 151 152 // PowerPC does not have ROTR 153 setOperationAction(ISD::ROTR, MVT::i32 , Expand); 154 setOperationAction(ISD::ROTR, MVT::i64 , Expand); 155 156 // PowerPC does not have Select 157 setOperationAction(ISD::SELECT, MVT::i32, Expand); 158 setOperationAction(ISD::SELECT, MVT::i64, Expand); 159 setOperationAction(ISD::SELECT, MVT::f32, Expand); 160 setOperationAction(ISD::SELECT, MVT::f64, Expand); 161 162 // PowerPC wants to turn select_cc of FP into fsel when possible. 163 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 164 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 165 166 // PowerPC wants to optimize integer setcc a bit 167 setOperationAction(ISD::SETCC, MVT::i32, Custom); 168 169 // PowerPC does not have BRCOND which requires SetCC 170 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 171 172 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 173 174 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 175 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 176 177 // PowerPC does not have [U|S]INT_TO_FP 178 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 179 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 180 181 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 182 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 183 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); 184 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); 185 186 // We cannot sextinreg(i1). Expand to shifts. 187 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 188 189 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 190 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 191 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 192 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 193 194 195 // We want to legalize GlobalAddress and ConstantPool nodes into the 196 // appropriate instructions to materialize the address. 197 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 199 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 200 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 201 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 202 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 203 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 204 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 206 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 207 208 // TRAP is legal. 209 setOperationAction(ISD::TRAP, MVT::Other, Legal); 210 211 // TRAMPOLINE is custom lowered. 212 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); 213 214 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 215 setOperationAction(ISD::VASTART , MVT::Other, Custom); 216 217 // VAARG is custom lowered with the 32-bit SVR4 ABI. 218 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI() 219 && !TM.getSubtarget<PPCSubtarget>().isPPC64()) 220 setOperationAction(ISD::VAARG, MVT::Other, Custom); 221 else 222 setOperationAction(ISD::VAARG, MVT::Other, Expand); 223 224 // Use the default implementation. 225 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 226 setOperationAction(ISD::VAEND , MVT::Other, Expand); 227 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 228 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); 229 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 230 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); 231 232 // We want to custom lower some of our intrinsics. 233 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 234 235 // Comparisons that require checking two conditions. 236 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 237 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 238 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 239 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 240 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); 241 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); 242 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 243 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 244 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 245 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 246 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); 247 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); 248 249 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 250 // They also have instructions for converting between i64 and fp. 251 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 252 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 253 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 254 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 255 // This is just the low 32 bits of a (signed) fp->i64 conversion. 256 // We cannot do this with Promote because i64 is not a legal type. 257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 258 259 // FIXME: disable this lowered code. This generates 64-bit register values, 260 // and we don't model the fact that the top part is clobbered by calls. We 261 // need to flag these together so that the value isn't live across a call. 262 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 263 } else { 264 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 265 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 266 } 267 268 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { 269 // 64-bit PowerPC implementations can support i64 types directly 270 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 271 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 272 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 273 // 64-bit PowerPC wants to expand i128 shifts itself. 274 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); 275 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); 276 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); 277 } else { 278 // 32-bit PowerPC wants to expand i64 shifts itself. 279 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 280 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 281 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 282 } 283 284 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 285 // First set operation action for all vector types to expand. Then we 286 // will selectively turn on ones that can be effectively codegen'd. 287 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 288 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 289 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; 290 291 // add/sub are legal for all supported vector VT's. 292 setOperationAction(ISD::ADD , VT, Legal); 293 setOperationAction(ISD::SUB , VT, Legal); 294 295 // We promote all shuffles to v16i8. 296 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 297 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); 298 299 // We promote all non-typed operations to v4i32. 300 setOperationAction(ISD::AND , VT, Promote); 301 AddPromotedToType (ISD::AND , VT, MVT::v4i32); 302 setOperationAction(ISD::OR , VT, Promote); 303 AddPromotedToType (ISD::OR , VT, MVT::v4i32); 304 setOperationAction(ISD::XOR , VT, Promote); 305 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); 306 setOperationAction(ISD::LOAD , VT, Promote); 307 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); 308 setOperationAction(ISD::SELECT, VT, Promote); 309 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); 310 setOperationAction(ISD::STORE, VT, Promote); 311 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); 312 313 // No other operations are legal. 314 setOperationAction(ISD::MUL , VT, Expand); 315 setOperationAction(ISD::SDIV, VT, Expand); 316 setOperationAction(ISD::SREM, VT, Expand); 317 setOperationAction(ISD::UDIV, VT, Expand); 318 setOperationAction(ISD::UREM, VT, Expand); 319 setOperationAction(ISD::FDIV, VT, Expand); 320 setOperationAction(ISD::FNEG, VT, Expand); 321 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); 322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); 323 setOperationAction(ISD::BUILD_VECTOR, VT, Expand); 324 setOperationAction(ISD::UMUL_LOHI, VT, Expand); 325 setOperationAction(ISD::SMUL_LOHI, VT, Expand); 326 setOperationAction(ISD::UDIVREM, VT, Expand); 327 setOperationAction(ISD::SDIVREM, VT, Expand); 328 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand); 329 setOperationAction(ISD::FPOW, VT, Expand); 330 setOperationAction(ISD::CTPOP, VT, Expand); 331 setOperationAction(ISD::CTLZ, VT, Expand); 332 setOperationAction(ISD::CTTZ, VT, Expand); 333 } 334 335 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle 336 // with merges, splats, etc. 337 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); 338 339 setOperationAction(ISD::AND , MVT::v4i32, Legal); 340 setOperationAction(ISD::OR , MVT::v4i32, Legal); 341 setOperationAction(ISD::XOR , MVT::v4i32, Legal); 342 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); 343 setOperationAction(ISD::SELECT, MVT::v4i32, Expand); 344 setOperationAction(ISD::STORE , MVT::v4i32, Legal); 345 346 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 347 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 348 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); 349 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); 350 351 setOperationAction(ISD::MUL, MVT::v4f32, Legal); 352 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 353 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 354 setOperationAction(ISD::MUL, MVT::v16i8, Custom); 355 356 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); 357 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); 358 359 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); 360 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); 361 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); 362 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 363 } 364 365 setShiftAmountType(MVT::i32); 366 setBooleanContents(ZeroOrOneBooleanContent); 367 368 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { 369 setStackPointerRegisterToSaveRestore(PPC::X1); 370 setExceptionPointerRegister(PPC::X3); 371 setExceptionSelectorRegister(PPC::X4); 372 } else { 373 setStackPointerRegisterToSaveRestore(PPC::R1); 374 setExceptionPointerRegister(PPC::R3); 375 setExceptionSelectorRegister(PPC::R4); 376 } 377 378 // We have target-specific dag combine patterns for the following nodes: 379 setTargetDAGCombine(ISD::SINT_TO_FP); 380 setTargetDAGCombine(ISD::STORE); 381 setTargetDAGCombine(ISD::BR_CC); 382 setTargetDAGCombine(ISD::BSWAP); 383 384 // Darwin long double math library functions have $LDBL128 appended. 385 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) { 386 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); 387 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); 388 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); 389 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); 390 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); 391 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); 392 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); 393 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); 394 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); 395 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); 396 } 397 398 computeRegisterProperties(); 399} 400 401/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 402/// function arguments in the caller parameter area. 403unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const { 404 const TargetMachine &TM = getTargetMachine(); 405 // Darwin passes everything on 4 byte boundary. 406 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) 407 return 4; 408 // FIXME SVR4 TBD 409 return 4; 410} 411 412const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { 413 switch (Opcode) { 414 default: return 0; 415 case PPCISD::FSEL: return "PPCISD::FSEL"; 416 case PPCISD::FCFID: return "PPCISD::FCFID"; 417 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; 418 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; 419 case PPCISD::STFIWX: return "PPCISD::STFIWX"; 420 case PPCISD::VMADDFP: return "PPCISD::VMADDFP"; 421 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP"; 422 case PPCISD::VPERM: return "PPCISD::VPERM"; 423 case PPCISD::Hi: return "PPCISD::Hi"; 424 case PPCISD::Lo: return "PPCISD::Lo"; 425 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; 426 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE"; 427 case PPCISD::LOAD: return "PPCISD::LOAD"; 428 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC"; 429 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; 430 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; 431 case PPCISD::SRL: return "PPCISD::SRL"; 432 case PPCISD::SRA: return "PPCISD::SRA"; 433 case PPCISD::SHL: return "PPCISD::SHL"; 434 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32"; 435 case PPCISD::STD_32: return "PPCISD::STD_32"; 436 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4"; 437 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin"; 438 case PPCISD::NOP: return "PPCISD::NOP"; 439 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 440 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin"; 441 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4"; 442 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; 443 case PPCISD::MFCR: return "PPCISD::MFCR"; 444 case PPCISD::VCMP: return "PPCISD::VCMP"; 445 case PPCISD::VCMPo: return "PPCISD::VCMPo"; 446 case PPCISD::LBRX: return "PPCISD::LBRX"; 447 case PPCISD::STBRX: return "PPCISD::STBRX"; 448 case PPCISD::LARX: return "PPCISD::LARX"; 449 case PPCISD::STCX: return "PPCISD::STCX"; 450 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; 451 case PPCISD::MFFS: return "PPCISD::MFFS"; 452 case PPCISD::MTFSB0: return "PPCISD::MTFSB0"; 453 case PPCISD::MTFSB1: return "PPCISD::MTFSB1"; 454 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; 455 case PPCISD::MTFSF: return "PPCISD::MTFSF"; 456 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; 457 } 458} 459 460MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const { 461 return MVT::i32; 462} 463 464/// getFunctionAlignment - Return the Log2 alignment of this function. 465unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const { 466 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) 467 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4; 468 else 469 return 2; 470} 471 472//===----------------------------------------------------------------------===// 473// Node matching predicates, for use by the tblgen matching code. 474//===----------------------------------------------------------------------===// 475 476/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 477static bool isFloatingPointZero(SDValue Op) { 478 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 479 return CFP->getValueAPF().isZero(); 480 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 481 // Maybe this has already been legalized into the constant pool? 482 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 483 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 484 return CFP->getValueAPF().isZero(); 485 } 486 return false; 487} 488 489/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return 490/// true if Op is undef or if it matches the specified value. 491static bool isConstantOrUndef(int Op, int Val) { 492 return Op < 0 || Op == Val; 493} 494 495/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 496/// VPKUHUM instruction. 497bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 498 if (!isUnary) { 499 for (unsigned i = 0; i != 16; ++i) 500 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) 501 return false; 502 } else { 503 for (unsigned i = 0; i != 8; ++i) 504 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) || 505 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1)) 506 return false; 507 } 508 return true; 509} 510 511/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 512/// VPKUWUM instruction. 513bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { 514 if (!isUnary) { 515 for (unsigned i = 0; i != 16; i += 2) 516 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 517 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) 518 return false; 519 } else { 520 for (unsigned i = 0; i != 8; i += 2) 521 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || 522 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) || 523 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) || 524 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3)) 525 return false; 526 } 527 return true; 528} 529 530/// isVMerge - Common function, used to match vmrg* shuffles. 531/// 532static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, 533 unsigned LHSStart, unsigned RHSStart) { 534 assert(N->getValueType(0) == MVT::v16i8 && 535 "PPC only supports shuffles by bytes!"); 536 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && 537 "Unsupported merge size!"); 538 539 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units 540 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit 541 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), 542 LHSStart+j+i*UnitSize) || 543 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), 544 RHSStart+j+i*UnitSize)) 545 return false; 546 } 547 return true; 548} 549 550/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 551/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 552bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 553 bool isUnary) { 554 if (!isUnary) 555 return isVMerge(N, UnitSize, 8, 24); 556 return isVMerge(N, UnitSize, 8, 8); 557} 558 559/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 560/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 561bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 562 bool isUnary) { 563 if (!isUnary) 564 return isVMerge(N, UnitSize, 0, 16); 565 return isVMerge(N, UnitSize, 0, 0); 566} 567 568 569/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift 570/// amount, otherwise return -1. 571int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { 572 assert(N->getValueType(0) == MVT::v16i8 && 573 "PPC only supports shuffles by bytes!"); 574 575 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 576 577 // Find the first non-undef value in the shuffle mask. 578 unsigned i; 579 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) 580 /*search*/; 581 582 if (i == 16) return -1; // all undef. 583 584 // Otherwise, check to see if the rest of the elements are consecutively 585 // numbered from this value. 586 unsigned ShiftAmt = SVOp->getMaskElt(i); 587 if (ShiftAmt < i) return -1; 588 ShiftAmt -= i; 589 590 if (!isUnary) { 591 // Check the rest of the elements to see if they are consecutive. 592 for (++i; i != 16; ++i) 593 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) 594 return -1; 595 } else { 596 // Check the rest of the elements to see if they are consecutive. 597 for (++i; i != 16; ++i) 598 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) 599 return -1; 600 } 601 return ShiftAmt; 602} 603 604/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 605/// specifies a splat of a single element that is suitable for input to 606/// VSPLTB/VSPLTH/VSPLTW. 607bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { 608 assert(N->getValueType(0) == MVT::v16i8 && 609 (EltSize == 1 || EltSize == 2 || EltSize == 4)); 610 611 // This is a splat operation if each element of the permute is the same, and 612 // if the value doesn't reference the second vector. 613 unsigned ElementBase = N->getMaskElt(0); 614 615 // FIXME: Handle UNDEF elements too! 616 if (ElementBase >= 16) 617 return false; 618 619 // Check that the indices are consecutive, in the case of a multi-byte element 620 // splatted with a v16i8 mask. 621 for (unsigned i = 1; i != EltSize; ++i) 622 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) 623 return false; 624 625 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { 626 if (N->getMaskElt(i) < 0) continue; 627 for (unsigned j = 0; j != EltSize; ++j) 628 if (N->getMaskElt(i+j) != N->getMaskElt(j)) 629 return false; 630 } 631 return true; 632} 633 634/// isAllNegativeZeroVector - Returns true if all elements of build_vector 635/// are -0.0. 636bool PPC::isAllNegativeZeroVector(SDNode *N) { 637 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N); 638 639 APInt APVal, APUndef; 640 unsigned BitSize; 641 bool HasAnyUndefs; 642 643 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true)) 644 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 645 return CFP->getValueAPF().isNegZero(); 646 647 return false; 648} 649 650/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 651/// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 652unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) { 653 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 654 assert(isSplatShuffleMask(SVOp, EltSize)); 655 return SVOp->getMaskElt(0) / EltSize; 656} 657 658/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed 659/// by using a vspltis[bhw] instruction of the specified element size, return 660/// the constant being splatted. The ByteSize field indicates the number of 661/// bytes of each element [124] -> [bhw]. 662SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { 663 SDValue OpVal(0, 0); 664 665 // If ByteSize of the splat is bigger than the element size of the 666 // build_vector, then we have a case where we are checking for a splat where 667 // multiple elements of the buildvector are folded together into a single 668 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). 669 unsigned EltSize = 16/N->getNumOperands(); 670 if (EltSize < ByteSize) { 671 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. 672 SDValue UniquedVals[4]; 673 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); 674 675 // See if all of the elements in the buildvector agree across. 676 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 677 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 678 // If the element isn't a constant, bail fully out. 679 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue(); 680 681 682 if (UniquedVals[i&(Multiple-1)].getNode() == 0) 683 UniquedVals[i&(Multiple-1)] = N->getOperand(i); 684 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) 685 return SDValue(); // no match. 686 } 687 688 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains 689 // either constant or undef values that are identical for each chunk. See 690 // if these chunks can form into a larger vspltis*. 691 692 // Check to see if all of the leading entries are either 0 or -1. If 693 // neither, then this won't fit into the immediate field. 694 bool LeadingZero = true; 695 bool LeadingOnes = true; 696 for (unsigned i = 0; i != Multiple-1; ++i) { 697 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs. 698 699 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue(); 700 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue(); 701 } 702 // Finally, check the least significant entry. 703 if (LeadingZero) { 704 if (UniquedVals[Multiple-1].getNode() == 0) 705 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef 706 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); 707 if (Val < 16) 708 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) 709 } 710 if (LeadingOnes) { 711 if (UniquedVals[Multiple-1].getNode() == 0) 712 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef 713 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); 714 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) 715 return DAG.getTargetConstant(Val, MVT::i32); 716 } 717 718 return SDValue(); 719 } 720 721 // Check to see if this buildvec has a single non-undef value in its elements. 722 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 723 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 724 if (OpVal.getNode() == 0) 725 OpVal = N->getOperand(i); 726 else if (OpVal != N->getOperand(i)) 727 return SDValue(); 728 } 729 730 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def. 731 732 unsigned ValSizeInBytes = EltSize; 733 uint64_t Value = 0; 734 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { 735 Value = CN->getZExtValue(); 736 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { 737 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); 738 Value = FloatToBits(CN->getValueAPF().convertToFloat()); 739 } 740 741 // If the splat value is larger than the element value, then we can never do 742 // this splat. The only case that we could fit the replicated bits into our 743 // immediate field for would be zero, and we prefer to use vxor for it. 744 if (ValSizeInBytes < ByteSize) return SDValue(); 745 746 // If the element value is larger than the splat value, cut it in half and 747 // check to see if the two halves are equal. Continue doing this until we 748 // get to ByteSize. This allows us to handle 0x01010101 as 0x01. 749 while (ValSizeInBytes > ByteSize) { 750 ValSizeInBytes >>= 1; 751 752 // If the top half equals the bottom half, we're still ok. 753 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) != 754 (Value & ((1 << (8*ValSizeInBytes))-1))) 755 return SDValue(); 756 } 757 758 // Properly sign extend the value. 759 int ShAmt = (4-ByteSize)*8; 760 int MaskVal = ((int)Value << ShAmt) >> ShAmt; 761 762 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. 763 if (MaskVal == 0) return SDValue(); 764 765 // Finally, if this value fits in a 5 bit sext field, return it 766 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) 767 return DAG.getTargetConstant(MaskVal, MVT::i32); 768 return SDValue(); 769} 770 771//===----------------------------------------------------------------------===// 772// Addressing Mode Selection 773//===----------------------------------------------------------------------===// 774 775/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 776/// or 64-bit immediate, and if the value can be accurately represented as a 777/// sign extension from a 16-bit value. If so, this returns true and the 778/// immediate. 779static bool isIntS16Immediate(SDNode *N, short &Imm) { 780 if (N->getOpcode() != ISD::Constant) 781 return false; 782 783 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 784 if (N->getValueType(0) == MVT::i32) 785 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 786 else 787 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 788} 789static bool isIntS16Immediate(SDValue Op, short &Imm) { 790 return isIntS16Immediate(Op.getNode(), Imm); 791} 792 793 794/// SelectAddressRegReg - Given the specified addressed, check to see if it 795/// can be represented as an indexed [r+r] operation. Returns false if it 796/// can be more efficiently represented with [r+imm]. 797bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base, 798 SDValue &Index, 799 SelectionDAG &DAG) const { 800 short imm = 0; 801 if (N.getOpcode() == ISD::ADD) { 802 if (isIntS16Immediate(N.getOperand(1), imm)) 803 return false; // r+i 804 if (N.getOperand(1).getOpcode() == PPCISD::Lo) 805 return false; // r+i 806 807 Base = N.getOperand(0); 808 Index = N.getOperand(1); 809 return true; 810 } else if (N.getOpcode() == ISD::OR) { 811 if (isIntS16Immediate(N.getOperand(1), imm)) 812 return false; // r+i can fold it if we can. 813 814 // If this is an or of disjoint bitfields, we can codegen this as an add 815 // (for better address arithmetic) if the LHS and RHS of the OR are provably 816 // disjoint. 817 APInt LHSKnownZero, LHSKnownOne; 818 APInt RHSKnownZero, RHSKnownOne; 819 DAG.ComputeMaskedBits(N.getOperand(0), 820 APInt::getAllOnesValue(N.getOperand(0) 821 .getValueSizeInBits()), 822 LHSKnownZero, LHSKnownOne); 823 824 if (LHSKnownZero.getBoolValue()) { 825 DAG.ComputeMaskedBits(N.getOperand(1), 826 APInt::getAllOnesValue(N.getOperand(1) 827 .getValueSizeInBits()), 828 RHSKnownZero, RHSKnownOne); 829 // If all of the bits are known zero on the LHS or RHS, the add won't 830 // carry. 831 if (~(LHSKnownZero | RHSKnownZero) == 0) { 832 Base = N.getOperand(0); 833 Index = N.getOperand(1); 834 return true; 835 } 836 } 837 } 838 839 return false; 840} 841 842/// Returns true if the address N can be represented by a base register plus 843/// a signed 16-bit displacement [r+imm], and if it is not better 844/// represented as reg+reg. 845bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, 846 SDValue &Base, 847 SelectionDAG &DAG) const { 848 // FIXME dl should come from parent load or store, not from address 849 DebugLoc dl = N.getDebugLoc(); 850 // If this can be more profitably realized as r+r, fail. 851 if (SelectAddressRegReg(N, Disp, Base, DAG)) 852 return false; 853 854 if (N.getOpcode() == ISD::ADD) { 855 short imm = 0; 856 if (isIntS16Immediate(N.getOperand(1), imm)) { 857 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 858 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 859 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 860 } else { 861 Base = N.getOperand(0); 862 } 863 return true; // [r+i] 864 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 865 // Match LOAD (ADD (X, Lo(G))). 866 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 867 && "Cannot handle constant offsets yet!"); 868 Disp = N.getOperand(1).getOperand(0); // The global address. 869 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 870 Disp.getOpcode() == ISD::TargetConstantPool || 871 Disp.getOpcode() == ISD::TargetJumpTable); 872 Base = N.getOperand(0); 873 return true; // [&g+r] 874 } 875 } else if (N.getOpcode() == ISD::OR) { 876 short imm = 0; 877 if (isIntS16Immediate(N.getOperand(1), imm)) { 878 // If this is an or of disjoint bitfields, we can codegen this as an add 879 // (for better address arithmetic) if the LHS and RHS of the OR are 880 // provably disjoint. 881 APInt LHSKnownZero, LHSKnownOne; 882 DAG.ComputeMaskedBits(N.getOperand(0), 883 APInt::getAllOnesValue(N.getOperand(0) 884 .getValueSizeInBits()), 885 LHSKnownZero, LHSKnownOne); 886 887 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 888 // If all of the bits are known zero on the LHS or RHS, the add won't 889 // carry. 890 Base = N.getOperand(0); 891 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); 892 return true; 893 } 894 } 895 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 896 // Loading from a constant address. 897 898 // If this address fits entirely in a 16-bit sext immediate field, codegen 899 // this as "d, 0" 900 short Imm; 901 if (isIntS16Immediate(CN, Imm)) { 902 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0)); 903 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 904 return true; 905 } 906 907 // Handle 32-bit sext immediates with LIS + addr mode. 908 if (CN->getValueType(0) == MVT::i32 || 909 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 910 int Addr = (int)CN->getZExtValue(); 911 912 // Otherwise, break this down into an LIS + disp. 913 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); 914 915 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); 916 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 917 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); 918 return true; 919 } 920 } 921 922 Disp = DAG.getTargetConstant(0, getPointerTy()); 923 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 924 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 925 else 926 Base = N; 927 return true; // [r+0] 928} 929 930/// SelectAddressRegRegOnly - Given the specified addressed, force it to be 931/// represented as an indexed [r+r] operation. 932bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base, 933 SDValue &Index, 934 SelectionDAG &DAG) const { 935 // Check to see if we can easily represent this as an [r+r] address. This 936 // will fail if it thinks that the address is more profitably represented as 937 // reg+imm, e.g. where imm = 0. 938 if (SelectAddressRegReg(N, Base, Index, DAG)) 939 return true; 940 941 // If the operand is an addition, always emit this as [r+r], since this is 942 // better (for code size, and execution, as the memop does the add for free) 943 // than emitting an explicit add. 944 if (N.getOpcode() == ISD::ADD) { 945 Base = N.getOperand(0); 946 Index = N.getOperand(1); 947 return true; 948 } 949 950 // Otherwise, do it the hard way, using R0 as the base register. 951 Base = DAG.getRegister(PPC::R0, N.getValueType()); 952 Index = N; 953 return true; 954} 955 956/// SelectAddressRegImmShift - Returns true if the address N can be 957/// represented by a base register plus a signed 14-bit displacement 958/// [r+imm*4]. Suitable for use by STD and friends. 959bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, 960 SDValue &Base, 961 SelectionDAG &DAG) const { 962 // FIXME dl should come from the parent load or store, not the address 963 DebugLoc dl = N.getDebugLoc(); 964 // If this can be more profitably realized as r+r, fail. 965 if (SelectAddressRegReg(N, Disp, Base, DAG)) 966 return false; 967 968 if (N.getOpcode() == ISD::ADD) { 969 short imm = 0; 970 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 971 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 972 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { 973 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 974 } else { 975 Base = N.getOperand(0); 976 } 977 return true; // [r+i] 978 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { 979 // Match LOAD (ADD (X, Lo(G))). 980 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() 981 && "Cannot handle constant offsets yet!"); 982 Disp = N.getOperand(1).getOperand(0); // The global address. 983 assert(Disp.getOpcode() == ISD::TargetGlobalAddress || 984 Disp.getOpcode() == ISD::TargetConstantPool || 985 Disp.getOpcode() == ISD::TargetJumpTable); 986 Base = N.getOperand(0); 987 return true; // [&g+r] 988 } 989 } else if (N.getOpcode() == ISD::OR) { 990 short imm = 0; 991 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { 992 // If this is an or of disjoint bitfields, we can codegen this as an add 993 // (for better address arithmetic) if the LHS and RHS of the OR are 994 // provably disjoint. 995 APInt LHSKnownZero, LHSKnownOne; 996 DAG.ComputeMaskedBits(N.getOperand(0), 997 APInt::getAllOnesValue(N.getOperand(0) 998 .getValueSizeInBits()), 999 LHSKnownZero, LHSKnownOne); 1000 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { 1001 // If all of the bits are known zero on the LHS or RHS, the add won't 1002 // carry. 1003 Base = N.getOperand(0); 1004 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); 1005 return true; 1006 } 1007 } 1008 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 1009 // Loading from a constant address. Verify low two bits are clear. 1010 if ((CN->getZExtValue() & 3) == 0) { 1011 // If this address fits entirely in a 14-bit sext immediate field, codegen 1012 // this as "d, 0" 1013 short Imm; 1014 if (isIntS16Immediate(CN, Imm)) { 1015 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); 1016 Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); 1017 return true; 1018 } 1019 1020 // Fold the low-part of 32-bit absolute addresses into addr mode. 1021 if (CN->getValueType(0) == MVT::i32 || 1022 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { 1023 int Addr = (int)CN->getZExtValue(); 1024 1025 // Otherwise, break this down into an LIS + disp. 1026 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); 1027 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); 1028 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1029 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); 1030 return true; 1031 } 1032 } 1033 } 1034 1035 Disp = DAG.getTargetConstant(0, getPointerTy()); 1036 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) 1037 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); 1038 else 1039 Base = N; 1040 return true; // [r+0] 1041} 1042 1043 1044/// getPreIndexedAddressParts - returns true by value, base pointer and 1045/// offset pointer and addressing mode by reference if the node's address 1046/// can be legally represented as pre-indexed load / store address. 1047bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1048 SDValue &Offset, 1049 ISD::MemIndexedMode &AM, 1050 SelectionDAG &DAG) const { 1051 // Disabled by default for now. 1052 if (!EnablePPCPreinc) return false; 1053 1054 SDValue Ptr; 1055 EVT VT; 1056 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1057 Ptr = LD->getBasePtr(); 1058 VT = LD->getMemoryVT(); 1059 1060 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1061 ST = ST; 1062 Ptr = ST->getBasePtr(); 1063 VT = ST->getMemoryVT(); 1064 } else 1065 return false; 1066 1067 // PowerPC doesn't have preinc load/store instructions for vectors. 1068 if (VT.isVector()) 1069 return false; 1070 1071 // TODO: Check reg+reg first. 1072 1073 // LDU/STU use reg+imm*4, others use reg+imm. 1074 if (VT != MVT::i64) { 1075 // reg + imm 1076 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) 1077 return false; 1078 } else { 1079 // reg + imm * 4. 1080 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG)) 1081 return false; 1082 } 1083 1084 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1085 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of 1086 // sext i32 to i64 when addr mode is r+i. 1087 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && 1088 LD->getExtensionType() == ISD::SEXTLOAD && 1089 isa<ConstantSDNode>(Offset)) 1090 return false; 1091 } 1092 1093 AM = ISD::PRE_INC; 1094 return true; 1095} 1096 1097//===----------------------------------------------------------------------===// 1098// LowerOperation implementation 1099//===----------------------------------------------------------------------===// 1100 1101SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, 1102 SelectionDAG &DAG) const { 1103 EVT PtrVT = Op.getValueType(); 1104 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1105 const Constant *C = CP->getConstVal(); 1106 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); 1107 SDValue Zero = DAG.getConstant(0, PtrVT); 1108 // FIXME there isn't really any debug info here 1109 DebugLoc dl = Op.getDebugLoc(); 1110 1111 const TargetMachine &TM = DAG.getTarget(); 1112 1113 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero); 1114 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero); 1115 1116 // If this is a non-darwin platform, we don't support non-static relo models 1117 // yet. 1118 if (TM.getRelocationModel() == Reloc::Static || 1119 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1120 // Generate non-pic code that has direct accesses to the constant pool. 1121 // The address of the global is just (hi(&g)+lo(&g)). 1122 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1123 } 1124 1125 if (TM.getRelocationModel() == Reloc::PIC_) { 1126 // With PIC, the first instruction is actually "GR+hi(&G)". 1127 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1128 DAG.getNode(PPCISD::GlobalBaseReg, 1129 DebugLoc(), PtrVT), Hi); 1130 } 1131 1132 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1133 return Lo; 1134} 1135 1136SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 1137 EVT PtrVT = Op.getValueType(); 1138 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1139 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); 1140 SDValue Zero = DAG.getConstant(0, PtrVT); 1141 // FIXME there isn't really any debug loc here 1142 DebugLoc dl = Op.getDebugLoc(); 1143 1144 const TargetMachine &TM = DAG.getTarget(); 1145 1146 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero); 1147 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero); 1148 1149 // If this is a non-darwin platform, we don't support non-static relo models 1150 // yet. 1151 if (TM.getRelocationModel() == Reloc::Static || 1152 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1153 // Generate non-pic code that has direct accesses to the constant pool. 1154 // The address of the global is just (hi(&g)+lo(&g)). 1155 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1156 } 1157 1158 if (TM.getRelocationModel() == Reloc::PIC_) { 1159 // With PIC, the first instruction is actually "GR+hi(&G)". 1160 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1161 DAG.getNode(PPCISD::GlobalBaseReg, 1162 DebugLoc(), PtrVT), Hi); 1163 } 1164 1165 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1166 return Lo; 1167} 1168 1169SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1170 SelectionDAG &DAG) const { 1171 llvm_unreachable("TLS not implemented for PPC."); 1172 return SDValue(); // Not reached 1173} 1174 1175SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, 1176 SelectionDAG &DAG) const { 1177 EVT PtrVT = Op.getValueType(); 1178 DebugLoc DL = Op.getDebugLoc(); 1179 1180 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1181 SDValue TgtBA = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true); 1182 SDValue Zero = DAG.getConstant(0, PtrVT); 1183 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero); 1184 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero); 1185 1186 // If this is a non-darwin platform, we don't support non-static relo models 1187 // yet. 1188 const TargetMachine &TM = DAG.getTarget(); 1189 if (TM.getRelocationModel() == Reloc::Static || 1190 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1191 // Generate non-pic code that has direct accesses to globals. 1192 // The address of the global is just (hi(&g)+lo(&g)). 1193 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1194 } 1195 1196 if (TM.getRelocationModel() == Reloc::PIC_) { 1197 // With PIC, the first instruction is actually "GR+hi(&G)". 1198 Hi = DAG.getNode(ISD::ADD, DL, PtrVT, 1199 DAG.getNode(PPCISD::GlobalBaseReg, 1200 DebugLoc(), PtrVT), Hi); 1201 } 1202 1203 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1204} 1205 1206SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, 1207 SelectionDAG &DAG) const { 1208 EVT PtrVT = Op.getValueType(); 1209 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); 1210 // FIXME there isn't really any debug info here 1211 DebugLoc dl = GSDN->getDebugLoc(); 1212 const GlobalValue *GV = GSDN->getGlobal(); 1213 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, GSDN->getOffset()); 1214 SDValue Zero = DAG.getConstant(0, PtrVT); 1215 1216 const TargetMachine &TM = DAG.getTarget(); 1217 1218 // 64-bit SVR4 ABI code is always position-independent. 1219 // The actual address of the GlobalValue is stored in the TOC. 1220 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) { 1221 return DAG.getNode(PPCISD::TOC_ENTRY, dl, MVT::i64, GA, 1222 DAG.getRegister(PPC::X2, MVT::i64)); 1223 } 1224 1225 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero); 1226 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero); 1227 1228 // If this is a non-darwin platform, we don't support non-static relo models 1229 // yet. 1230 if (TM.getRelocationModel() == Reloc::Static || 1231 !TM.getSubtarget<PPCSubtarget>().isDarwin()) { 1232 // Generate non-pic code that has direct accesses to globals. 1233 // The address of the global is just (hi(&g)+lo(&g)). 1234 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1235 } 1236 1237 if (TM.getRelocationModel() == Reloc::PIC_) { 1238 // With PIC, the first instruction is actually "GR+hi(&G)". 1239 Hi = DAG.getNode(ISD::ADD, dl, PtrVT, 1240 DAG.getNode(PPCISD::GlobalBaseReg, 1241 DebugLoc(), PtrVT), Hi); 1242 } 1243 1244 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo); 1245 1246 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) 1247 return Lo; 1248 1249 // If the global is weak or external, we have to go through the lazy 1250 // resolution stub. 1251 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, MachinePointerInfo(), 1252 false, false, 0); 1253} 1254 1255SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1256 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 1257 DebugLoc dl = Op.getDebugLoc(); 1258 1259 // If we're comparing for equality to zero, expose the fact that this is 1260 // implented as a ctlz/srl pair on ppc, so that the dag combiner can 1261 // fold the new nodes. 1262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1263 if (C->isNullValue() && CC == ISD::SETEQ) { 1264 EVT VT = Op.getOperand(0).getValueType(); 1265 SDValue Zext = Op.getOperand(0); 1266 if (VT.bitsLT(MVT::i32)) { 1267 VT = MVT::i32; 1268 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); 1269 } 1270 unsigned Log2b = Log2_32(VT.getSizeInBits()); 1271 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); 1272 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, 1273 DAG.getConstant(Log2b, MVT::i32)); 1274 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); 1275 } 1276 // Leave comparisons against 0 and -1 alone for now, since they're usually 1277 // optimized. FIXME: revisit this when we can custom lower all setcc 1278 // optimizations. 1279 if (C->isAllOnesValue() || C->isNullValue()) 1280 return SDValue(); 1281 } 1282 1283 // If we have an integer seteq/setne, turn it into a compare against zero 1284 // by xor'ing the rhs with the lhs, which is faster than setting a 1285 // condition register, reading it back out, and masking the correct bit. The 1286 // normal approach here uses sub to do this instead of xor. Using xor exposes 1287 // the result to other bit-twiddling opportunities. 1288 EVT LHSVT = Op.getOperand(0).getValueType(); 1289 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { 1290 EVT VT = Op.getValueType(); 1291 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), 1292 Op.getOperand(1)); 1293 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); 1294 } 1295 return SDValue(); 1296} 1297 1298SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, 1299 const PPCSubtarget &Subtarget) const { 1300 1301 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!"); 1302 return SDValue(); // Not reached 1303} 1304 1305SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, 1306 SelectionDAG &DAG) const { 1307 SDValue Chain = Op.getOperand(0); 1308 SDValue Trmp = Op.getOperand(1); // trampoline 1309 SDValue FPtr = Op.getOperand(2); // nested function 1310 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 1311 DebugLoc dl = Op.getDebugLoc(); 1312 1313 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1314 bool isPPC64 = (PtrVT == MVT::i64); 1315 const Type *IntPtrTy = 1316 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType( 1317 *DAG.getContext()); 1318 1319 TargetLowering::ArgListTy Args; 1320 TargetLowering::ArgListEntry Entry; 1321 1322 Entry.Ty = IntPtrTy; 1323 Entry.Node = Trmp; Args.push_back(Entry); 1324 1325 // TrampSize == (isPPC64 ? 48 : 40); 1326 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, 1327 isPPC64 ? MVT::i64 : MVT::i32); 1328 Args.push_back(Entry); 1329 1330 Entry.Node = FPtr; Args.push_back(Entry); 1331 Entry.Node = Nest; Args.push_back(Entry); 1332 1333 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) 1334 std::pair<SDValue, SDValue> CallResult = 1335 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()), 1336 false, false, false, false, 0, CallingConv::C, false, 1337 /*isReturnValueUsed=*/true, 1338 DAG.getExternalSymbol("__trampoline_setup", PtrVT), 1339 Args, DAG, dl); 1340 1341 SDValue Ops[] = 1342 { CallResult.first, CallResult.second }; 1343 1344 return DAG.getMergeValues(Ops, 2, dl); 1345} 1346 1347SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, 1348 const PPCSubtarget &Subtarget) const { 1349 MachineFunction &MF = DAG.getMachineFunction(); 1350 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1351 1352 DebugLoc dl = Op.getDebugLoc(); 1353 1354 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { 1355 // vastart just stores the address of the VarArgsFrameIndex slot into the 1356 // memory location argument. 1357 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1358 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1359 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1360 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 1361 MachinePointerInfo(SV), 1362 false, false, 0); 1363 } 1364 1365 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct. 1366 // We suppose the given va_list is already allocated. 1367 // 1368 // typedef struct { 1369 // char gpr; /* index into the array of 8 GPRs 1370 // * stored in the register save area 1371 // * gpr=0 corresponds to r3, 1372 // * gpr=1 to r4, etc. 1373 // */ 1374 // char fpr; /* index into the array of 8 FPRs 1375 // * stored in the register save area 1376 // * fpr=0 corresponds to f1, 1377 // * fpr=1 to f2, etc. 1378 // */ 1379 // char *overflow_arg_area; 1380 // /* location on stack that holds 1381 // * the next overflow argument 1382 // */ 1383 // char *reg_save_area; 1384 // /* where r3:r10 and f1:f8 (if saved) 1385 // * are stored 1386 // */ 1387 // } va_list[1]; 1388 1389 1390 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); 1391 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); 1392 1393 1394 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1395 1396 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), 1397 PtrVT); 1398 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1399 PtrVT); 1400 1401 uint64_t FrameOffset = PtrVT.getSizeInBits()/8; 1402 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT); 1403 1404 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; 1405 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT); 1406 1407 uint64_t FPROffset = 1; 1408 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT); 1409 1410 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1411 1412 // Store first byte : number of int regs 1413 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, 1414 Op.getOperand(1), 1415 MachinePointerInfo(SV), 1416 MVT::i8, false, false, 0); 1417 uint64_t nextOffset = FPROffset; 1418 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), 1419 ConstFPROffset); 1420 1421 // Store second byte : number of float regs 1422 SDValue secondStore = 1423 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, 1424 MachinePointerInfo(SV, nextOffset), MVT::i8, 1425 false, false, 0); 1426 nextOffset += StackOffset; 1427 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); 1428 1429 // Store second word : arguments given on stack 1430 SDValue thirdStore = 1431 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, 1432 MachinePointerInfo(SV, nextOffset), 1433 false, false, 0); 1434 nextOffset += FrameOffset; 1435 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset); 1436 1437 // Store third word : arguments given in registers 1438 return DAG.getStore(thirdStore, dl, FR, nextPtr, 1439 MachinePointerInfo(SV, nextOffset), 1440 false, false, 0); 1441 1442} 1443 1444#include "PPCGenCallingConv.inc" 1445 1446static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, 1447 CCValAssign::LocInfo &LocInfo, 1448 ISD::ArgFlagsTy &ArgFlags, 1449 CCState &State) { 1450 return true; 1451} 1452 1453static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, 1454 EVT &LocVT, 1455 CCValAssign::LocInfo &LocInfo, 1456 ISD::ArgFlagsTy &ArgFlags, 1457 CCState &State) { 1458 static const unsigned ArgRegs[] = { 1459 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1460 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1461 }; 1462 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1463 1464 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1465 1466 // Skip one register if the first unallocated register has an even register 1467 // number and there are still argument registers available which have not been 1468 // allocated yet. RegNum is actually an index into ArgRegs, which means we 1469 // need to skip a register if RegNum is odd. 1470 if (RegNum != NumArgRegs && RegNum % 2 == 1) { 1471 State.AllocateReg(ArgRegs[RegNum]); 1472 } 1473 1474 // Always return false here, as this function only makes sure that the first 1475 // unallocated register has an odd register number and does not actually 1476 // allocate a register for the current argument. 1477 return false; 1478} 1479 1480static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, 1481 EVT &LocVT, 1482 CCValAssign::LocInfo &LocInfo, 1483 ISD::ArgFlagsTy &ArgFlags, 1484 CCState &State) { 1485 static const unsigned ArgRegs[] = { 1486 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1487 PPC::F8 1488 }; 1489 1490 const unsigned NumArgRegs = array_lengthof(ArgRegs); 1491 1492 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); 1493 1494 // If there is only one Floating-point register left we need to put both f64 1495 // values of a split ppc_fp128 value on the stack. 1496 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { 1497 State.AllocateReg(ArgRegs[RegNum]); 1498 } 1499 1500 // Always return false here, as this function only makes sure that the two f64 1501 // values a ppc_fp128 value is split into are both passed in registers or both 1502 // passed on the stack and does not actually allocate a register for the 1503 // current argument. 1504 return false; 1505} 1506 1507/// GetFPR - Get the set of FP registers that should be allocated for arguments, 1508/// on Darwin. 1509static const unsigned *GetFPR() { 1510 static const unsigned FPR[] = { 1511 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1512 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1513 }; 1514 1515 return FPR; 1516} 1517 1518/// CalculateStackSlotSize - Calculates the size reserved for this argument on 1519/// the stack. 1520static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, 1521 unsigned PtrByteSize) { 1522 unsigned ArgSize = ArgVT.getSizeInBits()/8; 1523 if (Flags.isByVal()) 1524 ArgSize = Flags.getByValSize(); 1525 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1526 1527 return ArgSize; 1528} 1529 1530SDValue 1531PPCTargetLowering::LowerFormalArguments(SDValue Chain, 1532 CallingConv::ID CallConv, bool isVarArg, 1533 const SmallVectorImpl<ISD::InputArg> 1534 &Ins, 1535 DebugLoc dl, SelectionDAG &DAG, 1536 SmallVectorImpl<SDValue> &InVals) 1537 const { 1538 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 1539 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins, 1540 dl, DAG, InVals); 1541 } else { 1542 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, 1543 dl, DAG, InVals); 1544 } 1545} 1546 1547SDValue 1548PPCTargetLowering::LowerFormalArguments_SVR4( 1549 SDValue Chain, 1550 CallingConv::ID CallConv, bool isVarArg, 1551 const SmallVectorImpl<ISD::InputArg> 1552 &Ins, 1553 DebugLoc dl, SelectionDAG &DAG, 1554 SmallVectorImpl<SDValue> &InVals) const { 1555 1556 // 32-bit SVR4 ABI Stack Frame Layout: 1557 // +-----------------------------------+ 1558 // +--> | Back chain | 1559 // | +-----------------------------------+ 1560 // | | Floating-point register save area | 1561 // | +-----------------------------------+ 1562 // | | General register save area | 1563 // | +-----------------------------------+ 1564 // | | CR save word | 1565 // | +-----------------------------------+ 1566 // | | VRSAVE save word | 1567 // | +-----------------------------------+ 1568 // | | Alignment padding | 1569 // | +-----------------------------------+ 1570 // | | Vector register save area | 1571 // | +-----------------------------------+ 1572 // | | Local variable space | 1573 // | +-----------------------------------+ 1574 // | | Parameter list area | 1575 // | +-----------------------------------+ 1576 // | | LR save word | 1577 // | +-----------------------------------+ 1578 // SP--> +--- | Back chain | 1579 // +-----------------------------------+ 1580 // 1581 // Specifications: 1582 // System V Application Binary Interface PowerPC Processor Supplement 1583 // AltiVec Technology Programming Interface Manual 1584 1585 MachineFunction &MF = DAG.getMachineFunction(); 1586 MachineFrameInfo *MFI = MF.getFrameInfo(); 1587 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1588 1589 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1590 // Potential tail calls could cause overwriting of argument stack slots. 1591 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1592 unsigned PtrByteSize = 4; 1593 1594 // Assign locations to all of the incoming arguments. 1595 SmallVector<CCValAssign, 16> ArgLocs; 1596 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, 1597 *DAG.getContext()); 1598 1599 // Reserve space for the linkage area on the stack. 1600 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); 1601 1602 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); 1603 1604 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1605 CCValAssign &VA = ArgLocs[i]; 1606 1607 // Arguments stored in registers. 1608 if (VA.isRegLoc()) { 1609 TargetRegisterClass *RC; 1610 EVT ValVT = VA.getValVT(); 1611 1612 switch (ValVT.getSimpleVT().SimpleTy) { 1613 default: 1614 llvm_unreachable("ValVT not supported by formal arguments Lowering"); 1615 case MVT::i32: 1616 RC = PPC::GPRCRegisterClass; 1617 break; 1618 case MVT::f32: 1619 RC = PPC::F4RCRegisterClass; 1620 break; 1621 case MVT::f64: 1622 RC = PPC::F8RCRegisterClass; 1623 break; 1624 case MVT::v16i8: 1625 case MVT::v8i16: 1626 case MVT::v4i32: 1627 case MVT::v4f32: 1628 RC = PPC::VRRCRegisterClass; 1629 break; 1630 } 1631 1632 // Transform the arguments stored in physical registers into virtual ones. 1633 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1634 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT); 1635 1636 InVals.push_back(ArgValue); 1637 } else { 1638 // Argument stored in memory. 1639 assert(VA.isMemLoc()); 1640 1641 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1642 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1643 isImmutable); 1644 1645 // Create load nodes to retrieve arguments from the stack. 1646 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1647 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 1648 MachinePointerInfo(), 1649 false, false, 0)); 1650 } 1651 } 1652 1653 // Assign locations to all of the incoming aggregate by value arguments. 1654 // Aggregates passed by value are stored in the local variable space of the 1655 // caller's stack frame, right above the parameter list area. 1656 SmallVector<CCValAssign, 16> ByValArgLocs; 1657 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), 1658 ByValArgLocs, *DAG.getContext()); 1659 1660 // Reserve stack space for the allocations in CCInfo. 1661 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 1662 1663 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal); 1664 1665 // Area that is at least reserved in the caller of this function. 1666 unsigned MinReservedArea = CCByValInfo.getNextStackOffset(); 1667 1668 // Set the size that is at least reserved in caller of this function. Tail 1669 // call optimized function's reserved stack space needs to be aligned so that 1670 // taking the difference between two stack areas will result in an aligned 1671 // stack. 1672 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1673 1674 MinReservedArea = 1675 std::max(MinReservedArea, 1676 PPCFrameInfo::getMinCallFrameSize(false, false)); 1677 1678 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 1679 getStackAlignment(); 1680 unsigned AlignMask = TargetAlign-1; 1681 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 1682 1683 FI->setMinReservedArea(MinReservedArea); 1684 1685 SmallVector<SDValue, 8> MemOps; 1686 1687 // If the function takes variable number of arguments, make a frame index for 1688 // the start of the first vararg value... for expansion of llvm.va_start. 1689 if (isVarArg) { 1690 static const unsigned GPArgRegs[] = { 1691 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1692 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1693 }; 1694 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); 1695 1696 static const unsigned FPArgRegs[] = { 1697 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1698 PPC::F8 1699 }; 1700 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs); 1701 1702 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs, 1703 NumGPArgRegs)); 1704 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs, 1705 NumFPArgRegs)); 1706 1707 // Make room for NumGPArgRegs and NumFPArgRegs. 1708 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + 1709 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8; 1710 1711 FuncInfo->setVarArgsStackOffset( 1712 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 1713 CCInfo.getNextStackOffset(), true)); 1714 1715 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false)); 1716 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 1717 1718 // The fixed integer arguments of a variadic function are stored to the 1719 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing 1720 // the result of va_next. 1721 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) { 1722 // Get an existing live-in vreg, or add a new one. 1723 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); 1724 if (!VReg) 1725 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); 1726 1727 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1728 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1729 MachinePointerInfo(), false, false, 0); 1730 MemOps.push_back(Store); 1731 // Increment the address by four for the next argument to store 1732 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 1733 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1734 } 1735 1736 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6 1737 // is set. 1738 // The double arguments are stored to the VarArgsFrameIndex 1739 // on the stack. 1740 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) { 1741 // Get an existing live-in vreg, or add a new one. 1742 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); 1743 if (!VReg) 1744 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); 1745 1746 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); 1747 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1748 MachinePointerInfo(), false, false, 0); 1749 MemOps.push_back(Store); 1750 // Increment the address by eight for the next argument to store 1751 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8, 1752 PtrVT); 1753 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 1754 } 1755 } 1756 1757 if (!MemOps.empty()) 1758 Chain = DAG.getNode(ISD::TokenFactor, dl, 1759 MVT::Other, &MemOps[0], MemOps.size()); 1760 1761 return Chain; 1762} 1763 1764SDValue 1765PPCTargetLowering::LowerFormalArguments_Darwin( 1766 SDValue Chain, 1767 CallingConv::ID CallConv, bool isVarArg, 1768 const SmallVectorImpl<ISD::InputArg> 1769 &Ins, 1770 DebugLoc dl, SelectionDAG &DAG, 1771 SmallVectorImpl<SDValue> &InVals) const { 1772 // TODO: add description of PPC stack frame format, or at least some docs. 1773 // 1774 MachineFunction &MF = DAG.getMachineFunction(); 1775 MachineFrameInfo *MFI = MF.getFrameInfo(); 1776 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 1777 1778 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1779 bool isPPC64 = PtrVT == MVT::i64; 1780 // Potential tail calls could cause overwriting of argument stack slots. 1781 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); 1782 unsigned PtrByteSize = isPPC64 ? 8 : 4; 1783 1784 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); 1785 // Area that is at least reserved in caller of this function. 1786 unsigned MinReservedArea = ArgOffset; 1787 1788 static const unsigned GPR_32[] = { // 32-bit registers. 1789 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1790 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1791 }; 1792 static const unsigned GPR_64[] = { // 64-bit registers. 1793 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 1794 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 1795 }; 1796 1797 static const unsigned *FPR = GetFPR(); 1798 1799 static const unsigned VR[] = { 1800 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 1801 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 1802 }; 1803 1804 const unsigned Num_GPR_Regs = array_lengthof(GPR_32); 1805 const unsigned Num_FPR_Regs = 13; 1806 const unsigned Num_VR_Regs = array_lengthof( VR); 1807 1808 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 1809 1810 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 1811 1812 // In 32-bit non-varargs functions, the stack space for vectors is after the 1813 // stack space for non-vectors. We do not use this space unless we have 1814 // too many vectors to fit in registers, something that only occurs in 1815 // constructed examples:), but we have to walk the arglist to figure 1816 // that out...for the pathological case, compute VecArgOffset as the 1817 // start of the vector parameter area. Computing VecArgOffset is the 1818 // entire point of the following loop. 1819 unsigned VecArgOffset = ArgOffset; 1820 if (!isVarArg && !isPPC64) { 1821 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; 1822 ++ArgNo) { 1823 EVT ObjectVT = Ins[ArgNo].VT; 1824 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1825 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1826 1827 if (Flags.isByVal()) { 1828 // ObjSize is the true size, ArgSize rounded up to multiple of regs. 1829 ObjSize = Flags.getByValSize(); 1830 unsigned ArgSize = 1831 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1832 VecArgOffset += ArgSize; 1833 continue; 1834 } 1835 1836 switch(ObjectVT.getSimpleVT().SimpleTy) { 1837 default: llvm_unreachable("Unhandled argument type!"); 1838 case MVT::i32: 1839 case MVT::f32: 1840 VecArgOffset += isPPC64 ? 8 : 4; 1841 break; 1842 case MVT::i64: // PPC64 1843 case MVT::f64: 1844 VecArgOffset += 8; 1845 break; 1846 case MVT::v4f32: 1847 case MVT::v4i32: 1848 case MVT::v8i16: 1849 case MVT::v16i8: 1850 // Nothing to do, we're only looking at Nonvector args here. 1851 break; 1852 } 1853 } 1854 } 1855 // We've found where the vector parameter area in memory is. Skip the 1856 // first 12 parameters; these don't use that memory. 1857 VecArgOffset = ((VecArgOffset+15)/16)*16; 1858 VecArgOffset += 12*16; 1859 1860 // Add DAG nodes to load the arguments or copy them out of registers. On 1861 // entry to a function on PPC, the arguments start after the linkage area, 1862 // although the first ones are often in registers. 1863 1864 SmallVector<SDValue, 8> MemOps; 1865 unsigned nAltivecParamsAtEnd = 0; 1866 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { 1867 SDValue ArgVal; 1868 bool needsLoad = false; 1869 EVT ObjectVT = Ins[ArgNo].VT; 1870 unsigned ObjSize = ObjectVT.getSizeInBits()/8; 1871 unsigned ArgSize = ObjSize; 1872 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; 1873 1874 unsigned CurArgOffset = ArgOffset; 1875 1876 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. 1877 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || 1878 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { 1879 if (isVarArg || isPPC64) { 1880 MinReservedArea = ((MinReservedArea+15)/16)*16; 1881 MinReservedArea += CalculateStackSlotSize(ObjectVT, 1882 Flags, 1883 PtrByteSize); 1884 } else nAltivecParamsAtEnd++; 1885 } else 1886 // Calculate min reserved area. 1887 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT, 1888 Flags, 1889 PtrByteSize); 1890 1891 // FIXME the codegen can be much improved in some cases. 1892 // We do not have to keep everything in memory. 1893 if (Flags.isByVal()) { 1894 // ObjSize is the true size, ArgSize rounded up to multiple of registers. 1895 ObjSize = Flags.getByValSize(); 1896 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; 1897 // Objects of size 1 and 2 are right justified, everything else is 1898 // left justified. This means the memory address is adjusted forwards. 1899 if (ObjSize==1 || ObjSize==2) { 1900 CurArgOffset = CurArgOffset + (4 - ObjSize); 1901 } 1902 // The value of the object is its address. 1903 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true); 1904 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1905 InVals.push_back(FIN); 1906 if (ObjSize==1 || ObjSize==2) { 1907 if (GPR_idx != Num_GPR_Regs) { 1908 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1909 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1910 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, 1911 MachinePointerInfo(), 1912 ObjSize==1 ? MVT::i8 : MVT::i16, 1913 false, false, 0); 1914 MemOps.push_back(Store); 1915 ++GPR_idx; 1916 } 1917 1918 ArgOffset += PtrByteSize; 1919 1920 continue; 1921 } 1922 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) { 1923 // Store whatever pieces of the object are in registers 1924 // to memory. ArgVal will be address of the beginning of 1925 // the object. 1926 if (GPR_idx != Num_GPR_Regs) { 1927 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1928 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true); 1929 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 1930 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 1931 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1932 MachinePointerInfo(), 1933 false, false, 0); 1934 MemOps.push_back(Store); 1935 ++GPR_idx; 1936 ArgOffset += PtrByteSize; 1937 } else { 1938 ArgOffset += ArgSize - (ArgOffset-CurArgOffset); 1939 break; 1940 } 1941 } 1942 continue; 1943 } 1944 1945 switch (ObjectVT.getSimpleVT().SimpleTy) { 1946 default: llvm_unreachable("Unhandled argument type!"); 1947 case MVT::i32: 1948 if (!isPPC64) { 1949 if (GPR_idx != Num_GPR_Regs) { 1950 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 1951 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 1952 ++GPR_idx; 1953 } else { 1954 needsLoad = true; 1955 ArgSize = PtrByteSize; 1956 } 1957 // All int arguments reserve stack space in the Darwin ABI. 1958 ArgOffset += PtrByteSize; 1959 break; 1960 } 1961 // FALLTHROUGH 1962 case MVT::i64: // PPC64 1963 if (GPR_idx != Num_GPR_Regs) { 1964 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 1965 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1966 1967 if (ObjectVT == MVT::i32) { 1968 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote 1969 // value to MVT::i64 and then truncate to the correct register size. 1970 if (Flags.isSExt()) 1971 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, 1972 DAG.getValueType(ObjectVT)); 1973 else if (Flags.isZExt()) 1974 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, 1975 DAG.getValueType(ObjectVT)); 1976 1977 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); 1978 } 1979 1980 ++GPR_idx; 1981 } else { 1982 needsLoad = true; 1983 ArgSize = PtrByteSize; 1984 } 1985 // All int arguments reserve stack space in the Darwin ABI. 1986 ArgOffset += 8; 1987 break; 1988 1989 case MVT::f32: 1990 case MVT::f64: 1991 // Every 4 bytes of argument space consumes one of the GPRs available for 1992 // argument passing. 1993 if (GPR_idx != Num_GPR_Regs) { 1994 ++GPR_idx; 1995 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64) 1996 ++GPR_idx; 1997 } 1998 if (FPR_idx != Num_FPR_Regs) { 1999 unsigned VReg; 2000 2001 if (ObjectVT == MVT::f32) 2002 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); 2003 else 2004 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); 2005 2006 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2007 ++FPR_idx; 2008 } else { 2009 needsLoad = true; 2010 } 2011 2012 // All FP arguments reserve stack space in the Darwin ABI. 2013 ArgOffset += isPPC64 ? 8 : ObjSize; 2014 break; 2015 case MVT::v4f32: 2016 case MVT::v4i32: 2017 case MVT::v8i16: 2018 case MVT::v16i8: 2019 // Note that vector arguments in registers don't reserve stack space, 2020 // except in varargs functions. 2021 if (VR_idx != Num_VR_Regs) { 2022 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); 2023 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); 2024 if (isVarArg) { 2025 while ((ArgOffset % 16) != 0) { 2026 ArgOffset += PtrByteSize; 2027 if (GPR_idx != Num_GPR_Regs) 2028 GPR_idx++; 2029 } 2030 ArgOffset += 16; 2031 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64? 2032 } 2033 ++VR_idx; 2034 } else { 2035 if (!isVarArg && !isPPC64) { 2036 // Vectors go after all the nonvectors. 2037 CurArgOffset = VecArgOffset; 2038 VecArgOffset += 16; 2039 } else { 2040 // Vectors are aligned. 2041 ArgOffset = ((ArgOffset+15)/16)*16; 2042 CurArgOffset = ArgOffset; 2043 ArgOffset += 16; 2044 } 2045 needsLoad = true; 2046 } 2047 break; 2048 } 2049 2050 // We need to load the argument to a virtual register if we determined above 2051 // that we ran out of physical registers of the appropriate type. 2052 if (needsLoad) { 2053 int FI = MFI->CreateFixedObject(ObjSize, 2054 CurArgOffset + (ArgSize - ObjSize), 2055 isImmutable); 2056 SDValue FIN = DAG.getFrameIndex(FI, PtrVT); 2057 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), 2058 false, false, 0); 2059 } 2060 2061 InVals.push_back(ArgVal); 2062 } 2063 2064 // Set the size that is at least reserved in caller of this function. Tail 2065 // call optimized function's reserved stack space needs to be aligned so that 2066 // taking the difference between two stack areas will result in an aligned 2067 // stack. 2068 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 2069 // Add the Altivec parameters at the end, if needed. 2070 if (nAltivecParamsAtEnd) { 2071 MinReservedArea = ((MinReservedArea+15)/16)*16; 2072 MinReservedArea += 16*nAltivecParamsAtEnd; 2073 } 2074 MinReservedArea = 2075 std::max(MinReservedArea, 2076 PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); 2077 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 2078 getStackAlignment(); 2079 unsigned AlignMask = TargetAlign-1; 2080 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; 2081 FI->setMinReservedArea(MinReservedArea); 2082 2083 // If the function takes variable number of arguments, make a frame index for 2084 // the start of the first vararg value... for expansion of llvm.va_start. 2085 if (isVarArg) { 2086 int Depth = ArgOffset; 2087 2088 FuncInfo->setVarArgsFrameIndex( 2089 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, 2090 Depth, true)); 2091 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2092 2093 // If this function is vararg, store any remaining integer argument regs 2094 // to their spots on the stack so that they may be loaded by deferencing the 2095 // result of va_next. 2096 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { 2097 unsigned VReg; 2098 2099 if (isPPC64) 2100 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); 2101 else 2102 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); 2103 2104 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); 2105 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 2106 MachinePointerInfo(), false, false, 0); 2107 MemOps.push_back(Store); 2108 // Increment the address by four for the next argument to store 2109 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT); 2110 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); 2111 } 2112 } 2113 2114 if (!MemOps.empty()) 2115 Chain = DAG.getNode(ISD::TokenFactor, dl, 2116 MVT::Other, &MemOps[0], MemOps.size()); 2117 2118 return Chain; 2119} 2120 2121/// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus 2122/// linkage area for the Darwin ABI. 2123static unsigned 2124CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, 2125 bool isPPC64, 2126 bool isVarArg, 2127 unsigned CC, 2128 const SmallVectorImpl<ISD::OutputArg> 2129 &Outs, 2130 const SmallVectorImpl<SDValue> &OutVals, 2131 unsigned &nAltivecParamsAtEnd) { 2132 // Count how many bytes are to be pushed on the stack, including the linkage 2133 // area, and parameter passing area. We start with 24/48 bytes, which is 2134 // prereserved space for [SP][CR][LR][3 x unused]. 2135 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true); 2136 unsigned NumOps = Outs.size(); 2137 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2138 2139 // Add up all the space actually used. 2140 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually 2141 // they all go in registers, but we must reserve stack space for them for 2142 // possible use by the caller. In varargs or 64-bit calls, parameters are 2143 // assigned stack space in order, with padding so Altivec parameters are 2144 // 16-byte aligned. 2145 nAltivecParamsAtEnd = 0; 2146 for (unsigned i = 0; i != NumOps; ++i) { 2147 SDValue Arg = OutVals[i]; 2148 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2149 EVT ArgVT = Outs[i].VT; 2150 // Varargs Altivec parameters are padded to a 16 byte boundary. 2151 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || 2152 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { 2153 if (!isVarArg && !isPPC64) { 2154 // Non-varargs Altivec parameters go after all the non-Altivec 2155 // parameters; handle those later so we know how much padding we need. 2156 nAltivecParamsAtEnd++; 2157 continue; 2158 } 2159 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. 2160 NumBytes = ((NumBytes+15)/16)*16; 2161 } 2162 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); 2163 } 2164 2165 // Allow for Altivec parameters at the end, if needed. 2166 if (nAltivecParamsAtEnd) { 2167 NumBytes = ((NumBytes+15)/16)*16; 2168 NumBytes += 16*nAltivecParamsAtEnd; 2169 } 2170 2171 // The prolog code of the callee may store up to 8 GPR argument registers to 2172 // the stack, allowing va_start to index over them in memory if its varargs. 2173 // Because we cannot tell if this is needed on the caller side, we have to 2174 // conservatively assume that it is needed. As such, make sure we have at 2175 // least enough stack space for the caller to store the 8 GPRs. 2176 NumBytes = std::max(NumBytes, 2177 PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); 2178 2179 // Tail call needs the stack to be aligned. 2180 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) { 2181 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> 2182 getStackAlignment(); 2183 unsigned AlignMask = TargetAlign-1; 2184 NumBytes = (NumBytes + AlignMask) & ~AlignMask; 2185 } 2186 2187 return NumBytes; 2188} 2189 2190/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be 2191/// adjusted to accomodate the arguments for the tailcall. 2192static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, 2193 unsigned ParamSize) { 2194 2195 if (!isTailCall) return 0; 2196 2197 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>(); 2198 unsigned CallerMinReservedArea = FI->getMinReservedArea(); 2199 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize; 2200 // Remember only if the new adjustement is bigger. 2201 if (SPDiff < FI->getTailCallSPDelta()) 2202 FI->setTailCallSPDelta(SPDiff); 2203 2204 return SPDiff; 2205} 2206 2207/// IsEligibleForTailCallOptimization - Check whether the call is eligible 2208/// for tail call optimization. Targets which want to do tail call 2209/// optimization should implement this function. 2210bool 2211PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2212 CallingConv::ID CalleeCC, 2213 bool isVarArg, 2214 const SmallVectorImpl<ISD::InputArg> &Ins, 2215 SelectionDAG& DAG) const { 2216 if (!GuaranteedTailCallOpt) 2217 return false; 2218 2219 // Variable argument functions are not supported. 2220 if (isVarArg) 2221 return false; 2222 2223 MachineFunction &MF = DAG.getMachineFunction(); 2224 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv(); 2225 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { 2226 // Functions containing by val parameters are not supported. 2227 for (unsigned i = 0; i != Ins.size(); i++) { 2228 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2229 if (Flags.isByVal()) return false; 2230 } 2231 2232 // Non PIC/GOT tail calls are supported. 2233 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 2234 return true; 2235 2236 // At the moment we can only do local tail calls (in same module, hidden 2237 // or protected) if we are generating PIC. 2238 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 2239 return G->getGlobal()->hasHiddenVisibility() 2240 || G->getGlobal()->hasProtectedVisibility(); 2241 } 2242 2243 return false; 2244} 2245 2246/// isCallCompatibleAddress - Return the immediate to use if the specified 2247/// 32-bit value is representable in the immediate field of a BxA instruction. 2248static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { 2249 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2250 if (!C) return 0; 2251 2252 int Addr = C->getZExtValue(); 2253 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. 2254 (Addr << 6 >> 6) != Addr) 2255 return 0; // Top 6 bits have to be sext of immediate. 2256 2257 return DAG.getConstant((int)C->getZExtValue() >> 2, 2258 DAG.getTargetLoweringInfo().getPointerTy()).getNode(); 2259} 2260 2261namespace { 2262 2263struct TailCallArgumentInfo { 2264 SDValue Arg; 2265 SDValue FrameIdxOp; 2266 int FrameIdx; 2267 2268 TailCallArgumentInfo() : FrameIdx(0) {} 2269}; 2270 2271} 2272 2273/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. 2274static void 2275StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, 2276 SDValue Chain, 2277 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, 2278 SmallVector<SDValue, 8> &MemOpChains, 2279 DebugLoc dl) { 2280 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) { 2281 SDValue Arg = TailCallArgs[i].Arg; 2282 SDValue FIN = TailCallArgs[i].FrameIdxOp; 2283 int FI = TailCallArgs[i].FrameIdx; 2284 // Store relative to framepointer. 2285 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN, 2286 MachinePointerInfo::getFixedStack(FI), 2287 false, false, 0)); 2288 } 2289} 2290 2291/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to 2292/// the appropriate stack slot for the tail call optimized function call. 2293static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, 2294 MachineFunction &MF, 2295 SDValue Chain, 2296 SDValue OldRetAddr, 2297 SDValue OldFP, 2298 int SPDiff, 2299 bool isPPC64, 2300 bool isDarwinABI, 2301 DebugLoc dl) { 2302 if (SPDiff) { 2303 // Calculate the new stack slot for the return address. 2304 int SlotSize = isPPC64 ? 8 : 4; 2305 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64, 2306 isDarwinABI); 2307 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, 2308 NewRetAddrLoc, true); 2309 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2310 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); 2311 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, 2312 MachinePointerInfo::getFixedStack(NewRetAddr), 2313 false, false, 0); 2314 2315 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack 2316 // slot as the FP is never overwritten. 2317 if (isDarwinABI) { 2318 int NewFPLoc = 2319 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); 2320 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, 2321 true); 2322 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); 2323 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, 2324 MachinePointerInfo::getFixedStack(NewFPIdx), 2325 false, false, 0); 2326 } 2327 } 2328 return Chain; 2329} 2330 2331/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate 2332/// the position of the argument. 2333static void 2334CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, 2335 SDValue Arg, int SPDiff, unsigned ArgOffset, 2336 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) { 2337 int Offset = ArgOffset + SPDiff; 2338 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; 2339 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2340 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; 2341 SDValue FIN = DAG.getFrameIndex(FI, VT); 2342 TailCallArgumentInfo Info; 2343 Info.Arg = Arg; 2344 Info.FrameIdxOp = FIN; 2345 Info.FrameIdx = FI; 2346 TailCallArguments.push_back(Info); 2347} 2348 2349/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address 2350/// stack slot. Returns the chain as result and the loaded frame pointers in 2351/// LROpOut/FPOpout. Used when tail calling. 2352SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 2353 int SPDiff, 2354 SDValue Chain, 2355 SDValue &LROpOut, 2356 SDValue &FPOpOut, 2357 bool isDarwinABI, 2358 DebugLoc dl) const { 2359 if (SPDiff) { 2360 // Load the LR and FP stack slot for later adjusting. 2361 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; 2362 LROpOut = getReturnAddrFrameIndex(DAG); 2363 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(), 2364 false, false, 0); 2365 Chain = SDValue(LROpOut.getNode(), 1); 2366 2367 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack 2368 // slot as the FP is never overwritten. 2369 if (isDarwinABI) { 2370 FPOpOut = getFramePointerFrameIndex(DAG); 2371 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(), 2372 false, false, 0); 2373 Chain = SDValue(FPOpOut.getNode(), 1); 2374 } 2375 } 2376 return Chain; 2377} 2378 2379/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 2380/// by "Src" to address "Dst" of size "Size". Alignment information is 2381/// specified by the specific parameter attribute. The copy will be passed as 2382/// a byval function parameter. 2383/// Sometimes what we are copying is the end of a larger object, the part that 2384/// does not fit in registers. 2385static SDValue 2386CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 2387 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 2388 DebugLoc dl) { 2389 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 2390 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 2391 false, false, MachinePointerInfo(0), 2392 MachinePointerInfo(0)); 2393} 2394 2395/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of 2396/// tail calls. 2397static void 2398LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, 2399 SDValue Arg, SDValue PtrOff, int SPDiff, 2400 unsigned ArgOffset, bool isPPC64, bool isTailCall, 2401 bool isVector, SmallVector<SDValue, 8> &MemOpChains, 2402 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, 2403 DebugLoc dl) { 2404 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2405 if (!isTailCall) { 2406 if (isVector) { 2407 SDValue StackPtr; 2408 if (isPPC64) 2409 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 2410 else 2411 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2412 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 2413 DAG.getConstant(ArgOffset, PtrVT)); 2414 } 2415 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2416 MachinePointerInfo(), false, false, 0)); 2417 // Calculate and remember argument location. 2418 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, 2419 TailCallArguments); 2420} 2421 2422static 2423void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, 2424 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, 2425 SDValue LROp, SDValue FPOp, bool isDarwinABI, 2426 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) { 2427 MachineFunction &MF = DAG.getMachineFunction(); 2428 2429 // Emit a sequence of copyto/copyfrom virtual registers for arguments that 2430 // might overwrite each other in case of tail call optimization. 2431 SmallVector<SDValue, 8> MemOpChains2; 2432 // Do not flag preceeding copytoreg stuff together with the following stuff. 2433 InFlag = SDValue(); 2434 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, 2435 MemOpChains2, dl); 2436 if (!MemOpChains2.empty()) 2437 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2438 &MemOpChains2[0], MemOpChains2.size()); 2439 2440 // Store the return address to the appropriate stack slot. 2441 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff, 2442 isPPC64, isDarwinABI, dl); 2443 2444 // Emit callseq_end just before tailcall node. 2445 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2446 DAG.getIntPtrConstant(0, true), InFlag); 2447 InFlag = Chain.getValue(1); 2448} 2449 2450static 2451unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, 2452 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, 2453 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, 2454 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, 2455 bool isPPC64, bool isSVR4ABI) { 2456 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2457 NodeTys.push_back(MVT::Other); // Returns a chain 2458 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 2459 2460 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; 2461 2462 bool needIndirectCall = true; 2463 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) { 2464 // If this is an absolute destination address, use the munged value. 2465 Callee = SDValue(Dest, 0); 2466 needIndirectCall = false; 2467 } 2468 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201 2469 // Use indirect calls for ALL functions calls in JIT mode, since the 2470 // far-call stubs may be outside relocation limits for a BL instruction. 2471 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) { 2472 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2473 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2474 // node so that legalize doesn't hack it. 2475 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2476 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2477 Callee.getValueType()); 2478 needIndirectCall = false; 2479 } 2480 } 2481 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2482 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 2483 Callee.getValueType()); 2484 needIndirectCall = false; 2485 } 2486 if (needIndirectCall) { 2487 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 2488 // to do the call, we can't use PPCISD::CALL. 2489 SDValue MTCTROps[] = {Chain, Callee, InFlag}; 2490 2491 if (isSVR4ABI && isPPC64) { 2492 // Function pointers in the 64-bit SVR4 ABI do not point to the function 2493 // entry point, but to the function descriptor (the function entry point 2494 // address is part of the function descriptor though). 2495 // The function descriptor is a three doubleword structure with the 2496 // following fields: function entry point, TOC base address and 2497 // environment pointer. 2498 // Thus for a call through a function pointer, the following actions need 2499 // to be performed: 2500 // 1. Save the TOC of the caller in the TOC save area of its stack 2501 // frame (this is done in LowerCall_Darwin()). 2502 // 2. Load the address of the function entry point from the function 2503 // descriptor. 2504 // 3. Load the TOC of the callee from the function descriptor into r2. 2505 // 4. Load the environment pointer from the function descriptor into 2506 // r11. 2507 // 5. Branch to the function entry point address. 2508 // 6. On return of the callee, the TOC of the caller needs to be 2509 // restored (this is done in FinishCall()). 2510 // 2511 // All those operations are flagged together to ensure that no other 2512 // operations can be scheduled in between. E.g. without flagging the 2513 // operations together, a TOC access in the caller could be scheduled 2514 // between the load of the callee TOC and the branch to the callee, which 2515 // results in the TOC access going through the TOC of the callee instead 2516 // of going through the TOC of the caller, which leads to incorrect code. 2517 2518 // Load the address of the function entry point from the function 2519 // descriptor. 2520 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Flag); 2521 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps, 2522 InFlag.getNode() ? 3 : 2); 2523 Chain = LoadFuncPtr.getValue(1); 2524 InFlag = LoadFuncPtr.getValue(2); 2525 2526 // Load environment pointer into r11. 2527 // Offset of the environment pointer within the function descriptor. 2528 SDValue PtrOff = DAG.getIntPtrConstant(16); 2529 2530 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); 2531 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr, 2532 InFlag); 2533 Chain = LoadEnvPtr.getValue(1); 2534 InFlag = LoadEnvPtr.getValue(2); 2535 2536 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr, 2537 InFlag); 2538 Chain = EnvVal.getValue(0); 2539 InFlag = EnvVal.getValue(1); 2540 2541 // Load TOC of the callee into r2. We are using a target-specific load 2542 // with r2 hard coded, because the result of a target-independent load 2543 // would never go directly into r2, since r2 is a reserved register (which 2544 // prevents the register allocator from allocating it), resulting in an 2545 // additional register being allocated and an unnecessary move instruction 2546 // being generated. 2547 VTs = DAG.getVTList(MVT::Other, MVT::Flag); 2548 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, 2549 Callee, InFlag); 2550 Chain = LoadTOCPtr.getValue(0); 2551 InFlag = LoadTOCPtr.getValue(1); 2552 2553 MTCTROps[0] = Chain; 2554 MTCTROps[1] = LoadFuncPtr; 2555 MTCTROps[2] = InFlag; 2556 } 2557 2558 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 2559 2 + (InFlag.getNode() != 0)); 2560 InFlag = Chain.getValue(1); 2561 2562 NodeTys.clear(); 2563 NodeTys.push_back(MVT::Other); 2564 NodeTys.push_back(MVT::Flag); 2565 Ops.push_back(Chain); 2566 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; 2567 Callee.setNode(0); 2568 // Add CTR register as callee so a bctr can be emitted later. 2569 if (isTailCall) 2570 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT)); 2571 } 2572 2573 // If this is a direct call, pass the chain and the callee. 2574 if (Callee.getNode()) { 2575 Ops.push_back(Chain); 2576 Ops.push_back(Callee); 2577 } 2578 // If this is a tail call add stack pointer delta. 2579 if (isTailCall) 2580 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); 2581 2582 // Add argument registers to the end of the list so that they are known live 2583 // into the call. 2584 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2585 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2586 RegsToPass[i].second.getValueType())); 2587 2588 return CallOpc; 2589} 2590 2591SDValue 2592PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2593 CallingConv::ID CallConv, bool isVarArg, 2594 const SmallVectorImpl<ISD::InputArg> &Ins, 2595 DebugLoc dl, SelectionDAG &DAG, 2596 SmallVectorImpl<SDValue> &InVals) const { 2597 2598 SmallVector<CCValAssign, 16> RVLocs; 2599 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(), 2600 RVLocs, *DAG.getContext()); 2601 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2602 2603 // Copy all of the result registers out of their specified physreg. 2604 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2605 CCValAssign &VA = RVLocs[i]; 2606 EVT VT = VA.getValVT(); 2607 assert(VA.isRegLoc() && "Can only return in registers!"); 2608 Chain = DAG.getCopyFromReg(Chain, dl, 2609 VA.getLocReg(), VT, InFlag).getValue(1); 2610 InVals.push_back(Chain.getValue(0)); 2611 InFlag = Chain.getValue(2); 2612 } 2613 2614 return Chain; 2615} 2616 2617SDValue 2618PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, 2619 bool isTailCall, bool isVarArg, 2620 SelectionDAG &DAG, 2621 SmallVector<std::pair<unsigned, SDValue>, 8> 2622 &RegsToPass, 2623 SDValue InFlag, SDValue Chain, 2624 SDValue &Callee, 2625 int SPDiff, unsigned NumBytes, 2626 const SmallVectorImpl<ISD::InputArg> &Ins, 2627 SmallVectorImpl<SDValue> &InVals) const { 2628 std::vector<EVT> NodeTys; 2629 SmallVector<SDValue, 8> Ops; 2630 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, 2631 isTailCall, RegsToPass, Ops, NodeTys, 2632 PPCSubTarget.isPPC64(), 2633 PPCSubTarget.isSVR4ABI()); 2634 2635 // When performing tail call optimization the callee pops its arguments off 2636 // the stack. Account for this here so these bytes can be pushed back on in 2637 // PPCRegisterInfo::eliminateCallFramePseudoInstr. 2638 int BytesCalleePops = 2639 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0; 2640 2641 if (InFlag.getNode()) 2642 Ops.push_back(InFlag); 2643 2644 // Emit tail call. 2645 if (isTailCall) { 2646 // If this is the first return lowered for this function, add the regs 2647 // to the liveout set for the function. 2648 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2649 SmallVector<CCValAssign, 16> RVLocs; 2650 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 2651 *DAG.getContext()); 2652 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC); 2653 for (unsigned i = 0; i != RVLocs.size(); ++i) 2654 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2655 } 2656 2657 assert(((Callee.getOpcode() == ISD::Register && 2658 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || 2659 Callee.getOpcode() == ISD::TargetExternalSymbol || 2660 Callee.getOpcode() == ISD::TargetGlobalAddress || 2661 isa<ConstantSDNode>(Callee)) && 2662 "Expecting an global address, external symbol, absolute value or register"); 2663 2664 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); 2665 } 2666 2667 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 2668 InFlag = Chain.getValue(1); 2669 2670 // Add a NOP immediately after the branch instruction when using the 64-bit 2671 // SVR4 ABI. At link time, if caller and callee are in a different module and 2672 // thus have a different TOC, the call will be replaced with a call to a stub 2673 // function which saves the current TOC, loads the TOC of the callee and 2674 // branches to the callee. The NOP will be replaced with a load instruction 2675 // which restores the TOC of the caller from the TOC save slot of the current 2676 // stack frame. If caller and callee belong to the same module (and have the 2677 // same TOC), the NOP will remain unchanged. 2678 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) { 2679 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag); 2680 if (CallOpc == PPCISD::BCTRL_SVR4) { 2681 // This is a call through a function pointer. 2682 // Restore the caller TOC from the save area into R2. 2683 // See PrepareCall() for more information about calls through function 2684 // pointers in the 64-bit SVR4 ABI. 2685 // We are using a target-specific load with r2 hard coded, because the 2686 // result of a target-independent load would never go directly into r2, 2687 // since r2 is a reserved register (which prevents the register allocator 2688 // from allocating it), resulting in an additional register being 2689 // allocated and an unnecessary move instruction being generated. 2690 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag); 2691 InFlag = Chain.getValue(1); 2692 } else { 2693 // Otherwise insert NOP. 2694 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag); 2695 } 2696 } 2697 2698 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2699 DAG.getIntPtrConstant(BytesCalleePops, true), 2700 InFlag); 2701 if (!Ins.empty()) 2702 InFlag = Chain.getValue(1); 2703 2704 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2705 Ins, dl, DAG, InVals); 2706} 2707 2708SDValue 2709PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2710 CallingConv::ID CallConv, bool isVarArg, 2711 bool &isTailCall, 2712 const SmallVectorImpl<ISD::OutputArg> &Outs, 2713 const SmallVectorImpl<SDValue> &OutVals, 2714 const SmallVectorImpl<ISD::InputArg> &Ins, 2715 DebugLoc dl, SelectionDAG &DAG, 2716 SmallVectorImpl<SDValue> &InVals) const { 2717 if (isTailCall) 2718 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, 2719 Ins, DAG); 2720 2721 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { 2722 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg, 2723 isTailCall, Outs, OutVals, Ins, 2724 dl, DAG, InVals); 2725 } else { 2726 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg, 2727 isTailCall, Outs, OutVals, Ins, 2728 dl, DAG, InVals); 2729 } 2730} 2731 2732SDValue 2733PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, 2734 CallingConv::ID CallConv, bool isVarArg, 2735 bool isTailCall, 2736 const SmallVectorImpl<ISD::OutputArg> &Outs, 2737 const SmallVectorImpl<SDValue> &OutVals, 2738 const SmallVectorImpl<ISD::InputArg> &Ins, 2739 DebugLoc dl, SelectionDAG &DAG, 2740 SmallVectorImpl<SDValue> &InVals) const { 2741 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description 2742 // of the 32-bit SVR4 ABI stack frame layout. 2743 2744 assert((CallConv == CallingConv::C || 2745 CallConv == CallingConv::Fast) && "Unknown calling convention!"); 2746 2747 unsigned PtrByteSize = 4; 2748 2749 MachineFunction &MF = DAG.getMachineFunction(); 2750 2751 // Mark this function as potentially containing a function that contains a 2752 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2753 // and restoring the callers stack pointer in this functions epilog. This is 2754 // done because by tail calling the called function might overwrite the value 2755 // in this function's (MF) stack pointer stack slot 0(SP). 2756 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2757 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2758 2759 // Count how many bytes are to be pushed on the stack, including the linkage 2760 // area, parameter list area and the part of the local variable space which 2761 // contains copies of aggregates which are passed by value. 2762 2763 // Assign locations to all of the outgoing arguments. 2764 SmallVector<CCValAssign, 16> ArgLocs; 2765 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 2766 ArgLocs, *DAG.getContext()); 2767 2768 // Reserve space for the linkage area on the stack. 2769 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); 2770 2771 if (isVarArg) { 2772 // Handle fixed and variable vector arguments differently. 2773 // Fixed vector arguments go into registers as long as registers are 2774 // available. Variable vector arguments always go into memory. 2775 unsigned NumArgs = Outs.size(); 2776 2777 for (unsigned i = 0; i != NumArgs; ++i) { 2778 EVT ArgVT = Outs[i].VT; 2779 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2780 bool Result; 2781 2782 if (Outs[i].IsFixed) { 2783 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, 2784 CCInfo); 2785 } else { 2786 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, 2787 ArgFlags, CCInfo); 2788 } 2789 2790 if (Result) { 2791#ifndef NDEBUG 2792 errs() << "Call operand #" << i << " has unhandled type " 2793 << ArgVT.getEVTString() << "\n"; 2794#endif 2795 llvm_unreachable(0); 2796 } 2797 } 2798 } else { 2799 // All arguments are treated the same. 2800 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4); 2801 } 2802 2803 // Assign locations to all of the outgoing aggregate by value arguments. 2804 SmallVector<CCValAssign, 16> ByValArgLocs; 2805 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs, 2806 *DAG.getContext()); 2807 2808 // Reserve stack space for the allocations in CCInfo. 2809 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize); 2810 2811 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal); 2812 2813 // Size of the linkage area, parameter list area and the part of the local 2814 // space variable where copies of aggregates which are passed by value are 2815 // stored. 2816 unsigned NumBytes = CCByValInfo.getNextStackOffset(); 2817 2818 // Calculate by how many bytes the stack has to be adjusted in case of tail 2819 // call optimization. 2820 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2821 2822 // Adjust the stack pointer for the new arguments... 2823 // These operations are automatically eliminated by the prolog/epilog pass 2824 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2825 SDValue CallSeqStart = Chain; 2826 2827 // Load the return address and frame pointer so it can be moved somewhere else 2828 // later. 2829 SDValue LROp, FPOp; 2830 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false, 2831 dl); 2832 2833 // Set up a copy of the stack pointer for use loading and storing any 2834 // arguments that may not fit in the registers available for argument 2835 // passing. 2836 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 2837 2838 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2839 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 2840 SmallVector<SDValue, 8> MemOpChains; 2841 2842 // Walk the register/memloc assignments, inserting copies/loads. 2843 for (unsigned i = 0, j = 0, e = ArgLocs.size(); 2844 i != e; 2845 ++i) { 2846 CCValAssign &VA = ArgLocs[i]; 2847 SDValue Arg = OutVals[i]; 2848 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2849 2850 if (Flags.isByVal()) { 2851 // Argument is an aggregate which is passed by value, thus we need to 2852 // create a copy of it in the local variable space of the current stack 2853 // frame (which is the stack frame of the caller) and pass the address of 2854 // this copy to the callee. 2855 assert((j < ByValArgLocs.size()) && "Index out of bounds!"); 2856 CCValAssign &ByValVA = ByValArgLocs[j++]; 2857 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"); 2858 2859 // Memory reserved in the local variable space of the callers stack frame. 2860 unsigned LocMemOffset = ByValVA.getLocMemOffset(); 2861 2862 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2863 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2864 2865 // Create a copy of the argument in the local area of the current 2866 // stack frame. 2867 SDValue MemcpyCall = 2868 CreateCopyOfByValArgument(Arg, PtrOff, 2869 CallSeqStart.getNode()->getOperand(0), 2870 Flags, DAG, dl); 2871 2872 // This must go outside the CALLSEQ_START..END. 2873 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 2874 CallSeqStart.getNode()->getOperand(1)); 2875 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 2876 NewCallSeqStart.getNode()); 2877 Chain = CallSeqStart = NewCallSeqStart; 2878 2879 // Pass the address of the aggregate copy on the stack either in a 2880 // physical register or in the parameter list area of the current stack 2881 // frame to the callee. 2882 Arg = PtrOff; 2883 } 2884 2885 if (VA.isRegLoc()) { 2886 // Put argument in a physical register. 2887 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2888 } else { 2889 // Put argument in the parameter list area of the current stack frame. 2890 assert(VA.isMemLoc()); 2891 unsigned LocMemOffset = VA.getLocMemOffset(); 2892 2893 if (!isTailCall) { 2894 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 2895 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 2896 2897 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2898 MachinePointerInfo(), 2899 false, false, 0)); 2900 } else { 2901 // Calculate and remember argument location. 2902 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset, 2903 TailCallArguments); 2904 } 2905 } 2906 } 2907 2908 if (!MemOpChains.empty()) 2909 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2910 &MemOpChains[0], MemOpChains.size()); 2911 2912 // Build a sequence of copy-to-reg nodes chained together with token chain 2913 // and flag operands which copy the outgoing args into the appropriate regs. 2914 SDValue InFlag; 2915 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2916 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2917 RegsToPass[i].second, InFlag); 2918 InFlag = Chain.getValue(1); 2919 } 2920 2921 // Set CR6 to true if this is a vararg call. 2922 if (isVarArg) { 2923 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0); 2924 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag); 2925 InFlag = Chain.getValue(1); 2926 } 2927 2928 if (isTailCall) { 2929 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp, 2930 false, TailCallArguments); 2931 } 2932 2933 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 2934 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 2935 Ins, InVals); 2936} 2937 2938SDValue 2939PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, 2940 CallingConv::ID CallConv, bool isVarArg, 2941 bool isTailCall, 2942 const SmallVectorImpl<ISD::OutputArg> &Outs, 2943 const SmallVectorImpl<SDValue> &OutVals, 2944 const SmallVectorImpl<ISD::InputArg> &Ins, 2945 DebugLoc dl, SelectionDAG &DAG, 2946 SmallVectorImpl<SDValue> &InVals) const { 2947 2948 unsigned NumOps = Outs.size(); 2949 2950 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2951 bool isPPC64 = PtrVT == MVT::i64; 2952 unsigned PtrByteSize = isPPC64 ? 8 : 4; 2953 2954 MachineFunction &MF = DAG.getMachineFunction(); 2955 2956 // Mark this function as potentially containing a function that contains a 2957 // tail call. As a consequence the frame pointer will be used for dynamicalloc 2958 // and restoring the callers stack pointer in this functions epilog. This is 2959 // done because by tail calling the called function might overwrite the value 2960 // in this function's (MF) stack pointer stack slot 0(SP). 2961 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast) 2962 MF.getInfo<PPCFunctionInfo>()->setHasFastCall(); 2963 2964 unsigned nAltivecParamsAtEnd = 0; 2965 2966 // Count how many bytes are to be pushed on the stack, including the linkage 2967 // area, and parameter passing area. We start with 24/48 bytes, which is 2968 // prereserved space for [SP][CR][LR][3 x unused]. 2969 unsigned NumBytes = 2970 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv, 2971 Outs, OutVals, 2972 nAltivecParamsAtEnd); 2973 2974 // Calculate by how many bytes the stack has to be adjusted in case of tail 2975 // call optimization. 2976 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes); 2977 2978 // To protect arguments on the stack from being clobbered in a tail call, 2979 // force all the loads to happen before doing any other lowering. 2980 if (isTailCall) 2981 Chain = DAG.getStackArgumentTokenFactor(Chain); 2982 2983 // Adjust the stack pointer for the new arguments... 2984 // These operations are automatically eliminated by the prolog/epilog pass 2985 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2986 SDValue CallSeqStart = Chain; 2987 2988 // Load the return address and frame pointer so it can be move somewhere else 2989 // later. 2990 SDValue LROp, FPOp; 2991 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true, 2992 dl); 2993 2994 // Set up a copy of the stack pointer for use loading and storing any 2995 // arguments that may not fit in the registers available for argument 2996 // passing. 2997 SDValue StackPtr; 2998 if (isPPC64) 2999 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); 3000 else 3001 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); 3002 3003 // Figure out which arguments are going to go in registers, and which in 3004 // memory. Also, if this is a vararg function, floating point operations 3005 // must be stored to our stack, and loaded into integer regs as well, if 3006 // any integer regs are available for argument passing. 3007 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); 3008 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; 3009 3010 static const unsigned GPR_32[] = { // 32-bit registers. 3011 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 3012 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 3013 }; 3014 static const unsigned GPR_64[] = { // 64-bit registers. 3015 PPC::X3, PPC::X4, PPC::X5, PPC::X6, 3016 PPC::X7, PPC::X8, PPC::X9, PPC::X10, 3017 }; 3018 static const unsigned *FPR = GetFPR(); 3019 3020 static const unsigned VR[] = { 3021 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, 3022 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 3023 }; 3024 const unsigned NumGPRs = array_lengthof(GPR_32); 3025 const unsigned NumFPRs = 13; 3026 const unsigned NumVRs = array_lengthof(VR); 3027 3028 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; 3029 3030 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 3031 SmallVector<TailCallArgumentInfo, 8> TailCallArguments; 3032 3033 SmallVector<SDValue, 8> MemOpChains; 3034 for (unsigned i = 0; i != NumOps; ++i) { 3035 SDValue Arg = OutVals[i]; 3036 ISD::ArgFlagsTy Flags = Outs[i].Flags; 3037 3038 // PtrOff will be used to store the current argument to the stack if a 3039 // register cannot be found for it. 3040 SDValue PtrOff; 3041 3042 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 3043 3044 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3045 3046 // On PPC64, promote integers to 64-bit values. 3047 if (isPPC64 && Arg.getValueType() == MVT::i32) { 3048 // FIXME: Should this use ANY_EXTEND if neither sext nor zext? 3049 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3050 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); 3051 } 3052 3053 // FIXME memcpy is used way more than necessary. Correctness first. 3054 if (Flags.isByVal()) { 3055 unsigned Size = Flags.getByValSize(); 3056 if (Size==1 || Size==2) { 3057 // Very small objects are passed right-justified. 3058 // Everything else is passed left-justified. 3059 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; 3060 if (GPR_idx != NumGPRs) { 3061 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, dl, Chain, Arg, 3062 MachinePointerInfo(), VT, 3063 false, false, 0); 3064 MemOpChains.push_back(Load.getValue(1)); 3065 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3066 3067 ArgOffset += PtrByteSize; 3068 } else { 3069 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType()); 3070 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); 3071 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, 3072 CallSeqStart.getNode()->getOperand(0), 3073 Flags, DAG, dl); 3074 // This must go outside the CALLSEQ_START..END. 3075 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3076 CallSeqStart.getNode()->getOperand(1)); 3077 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), 3078 NewCallSeqStart.getNode()); 3079 Chain = CallSeqStart = NewCallSeqStart; 3080 ArgOffset += PtrByteSize; 3081 } 3082 continue; 3083 } 3084 // Copy entire object into memory. There are cases where gcc-generated 3085 // code assumes it is there, even if it could be put entirely into 3086 // registers. (This is not what the doc says.) 3087 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, 3088 CallSeqStart.getNode()->getOperand(0), 3089 Flags, DAG, dl); 3090 // This must go outside the CALLSEQ_START..END. 3091 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, 3092 CallSeqStart.getNode()->getOperand(1)); 3093 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); 3094 Chain = CallSeqStart = NewCallSeqStart; 3095 // And copy the pieces of it that fit into registers. 3096 for (unsigned j=0; j<Size; j+=PtrByteSize) { 3097 SDValue Const = DAG.getConstant(j, PtrOff.getValueType()); 3098 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 3099 if (GPR_idx != NumGPRs) { 3100 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 3101 MachinePointerInfo(), 3102 false, false, 0); 3103 MemOpChains.push_back(Load.getValue(1)); 3104 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3105 ArgOffset += PtrByteSize; 3106 } else { 3107 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize; 3108 break; 3109 } 3110 } 3111 continue; 3112 } 3113 3114 switch (Arg.getValueType().getSimpleVT().SimpleTy) { 3115 default: llvm_unreachable("Unexpected ValueType for argument!"); 3116 case MVT::i32: 3117 case MVT::i64: 3118 if (GPR_idx != NumGPRs) { 3119 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); 3120 } else { 3121 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3122 isPPC64, isTailCall, false, MemOpChains, 3123 TailCallArguments, dl); 3124 } 3125 ArgOffset += PtrByteSize; 3126 break; 3127 case MVT::f32: 3128 case MVT::f64: 3129 if (FPR_idx != NumFPRs) { 3130 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); 3131 3132 if (isVarArg) { 3133 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3134 MachinePointerInfo(), false, false, 0); 3135 MemOpChains.push_back(Store); 3136 3137 // Float varargs are always shadowed in available integer registers 3138 if (GPR_idx != NumGPRs) { 3139 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3140 MachinePointerInfo(), false, false, 0); 3141 MemOpChains.push_back(Load.getValue(1)); 3142 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3143 } 3144 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ 3145 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); 3146 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); 3147 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, 3148 MachinePointerInfo(), 3149 false, false, 0); 3150 MemOpChains.push_back(Load.getValue(1)); 3151 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3152 } 3153 } else { 3154 // If we have any FPRs remaining, we may also have GPRs remaining. 3155 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 3156 // GPRs. 3157 if (GPR_idx != NumGPRs) 3158 ++GPR_idx; 3159 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && 3160 !isPPC64) // PPC64 has 64-bit GPR's obviously :) 3161 ++GPR_idx; 3162 } 3163 } else { 3164 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3165 isPPC64, isTailCall, false, MemOpChains, 3166 TailCallArguments, dl); 3167 } 3168 if (isPPC64) 3169 ArgOffset += 8; 3170 else 3171 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; 3172 break; 3173 case MVT::v4f32: 3174 case MVT::v4i32: 3175 case MVT::v8i16: 3176 case MVT::v16i8: 3177 if (isVarArg) { 3178 // These go aligned on the stack, or in the corresponding R registers 3179 // when within range. The Darwin PPC ABI doc claims they also go in 3180 // V registers; in fact gcc does this only for arguments that are 3181 // prototyped, not for those that match the ... We do it for all 3182 // arguments, seems to work. 3183 while (ArgOffset % 16 !=0) { 3184 ArgOffset += PtrByteSize; 3185 if (GPR_idx != NumGPRs) 3186 GPR_idx++; 3187 } 3188 // We could elide this store in the case where the object fits 3189 // entirely in R registers. Maybe later. 3190 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, 3191 DAG.getConstant(ArgOffset, PtrVT)); 3192 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, 3193 MachinePointerInfo(), false, false, 0); 3194 MemOpChains.push_back(Store); 3195 if (VR_idx != NumVRs) { 3196 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, 3197 MachinePointerInfo(), 3198 false, false, 0); 3199 MemOpChains.push_back(Load.getValue(1)); 3200 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); 3201 } 3202 ArgOffset += 16; 3203 for (unsigned i=0; i<16; i+=PtrByteSize) { 3204 if (GPR_idx == NumGPRs) 3205 break; 3206 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, 3207 DAG.getConstant(i, PtrVT)); 3208 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(), 3209 false, false, 0); 3210 MemOpChains.push_back(Load.getValue(1)); 3211 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); 3212 } 3213 break; 3214 } 3215 3216 // Non-varargs Altivec params generally go in registers, but have 3217 // stack space allocated at the end. 3218 if (VR_idx != NumVRs) { 3219 // Doesn't have GPR space allocated. 3220 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg)); 3221 } else if (nAltivecParamsAtEnd==0) { 3222 // We are emitting Altivec params in order. 3223 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3224 isPPC64, isTailCall, true, MemOpChains, 3225 TailCallArguments, dl); 3226 ArgOffset += 16; 3227 } 3228 break; 3229 } 3230 } 3231 // If all Altivec parameters fit in registers, as they usually do, 3232 // they get stack space following the non-Altivec parameters. We 3233 // don't track this here because nobody below needs it. 3234 // If there are more Altivec parameters than fit in registers emit 3235 // the stores here. 3236 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) { 3237 unsigned j = 0; 3238 // Offset is aligned; skip 1st 12 params which go in V registers. 3239 ArgOffset = ((ArgOffset+15)/16)*16; 3240 ArgOffset += 12*16; 3241 for (unsigned i = 0; i != NumOps; ++i) { 3242 SDValue Arg = OutVals[i]; 3243 EVT ArgType = Outs[i].VT; 3244 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || 3245 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { 3246 if (++j > NumVRs) { 3247 SDValue PtrOff; 3248 // We are emitting Altivec params in order. 3249 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset, 3250 isPPC64, isTailCall, true, MemOpChains, 3251 TailCallArguments, dl); 3252 ArgOffset += 16; 3253 } 3254 } 3255 } 3256 } 3257 3258 if (!MemOpChains.empty()) 3259 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 3260 &MemOpChains[0], MemOpChains.size()); 3261 3262 // Check if this is an indirect call (MTCTR/BCTRL). 3263 // See PrepareCall() for more information about calls through function 3264 // pointers in the 64-bit SVR4 ABI. 3265 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() && 3266 !dyn_cast<GlobalAddressSDNode>(Callee) && 3267 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3268 !isBLACompatibleAddress(Callee, DAG)) { 3269 // Load r2 into a virtual register and store it to the TOC save area. 3270 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); 3271 // TOC save area offset. 3272 SDValue PtrOff = DAG.getIntPtrConstant(40); 3273 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); 3274 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(), 3275 false, false, 0); 3276 } 3277 3278 // On Darwin, R12 must contain the address of an indirect callee. This does 3279 // not mean the MTCTR instruction must use R12; it's easier to model this as 3280 // an extra parameter, so do that. 3281 if (!isTailCall && 3282 !dyn_cast<GlobalAddressSDNode>(Callee) && 3283 !dyn_cast<ExternalSymbolSDNode>(Callee) && 3284 !isBLACompatibleAddress(Callee, DAG)) 3285 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 : 3286 PPC::R12), Callee)); 3287 3288 // Build a sequence of copy-to-reg nodes chained together with token chain 3289 // and flag operands which copy the outgoing args into the appropriate regs. 3290 SDValue InFlag; 3291 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 3292 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 3293 RegsToPass[i].second, InFlag); 3294 InFlag = Chain.getValue(1); 3295 } 3296 3297 if (isTailCall) { 3298 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp, 3299 FPOp, true, TailCallArguments); 3300 } 3301 3302 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG, 3303 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes, 3304 Ins, InVals); 3305} 3306 3307SDValue 3308PPCTargetLowering::LowerReturn(SDValue Chain, 3309 CallingConv::ID CallConv, bool isVarArg, 3310 const SmallVectorImpl<ISD::OutputArg> &Outs, 3311 const SmallVectorImpl<SDValue> &OutVals, 3312 DebugLoc dl, SelectionDAG &DAG) const { 3313 3314 SmallVector<CCValAssign, 16> RVLocs; 3315 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 3316 RVLocs, *DAG.getContext()); 3317 CCInfo.AnalyzeReturn(Outs, RetCC_PPC); 3318 3319 // If this is the first return lowered for this function, add the regs to the 3320 // liveout set for the function. 3321 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 3322 for (unsigned i = 0; i != RVLocs.size(); ++i) 3323 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 3324 } 3325 3326 SDValue Flag; 3327 3328 // Copy the result values into the output registers. 3329 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3330 CCValAssign &VA = RVLocs[i]; 3331 assert(VA.isRegLoc() && "Can only return in registers!"); 3332 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 3333 OutVals[i], Flag); 3334 Flag = Chain.getValue(1); 3335 } 3336 3337 if (Flag.getNode()) 3338 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 3339 else 3340 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); 3341} 3342 3343SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 3344 const PPCSubtarget &Subtarget) const { 3345 // When we pop the dynamic allocation we need to restore the SP link. 3346 DebugLoc dl = Op.getDebugLoc(); 3347 3348 // Get the corect type for pointers. 3349 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3350 3351 // Construct the stack pointer operand. 3352 bool isPPC64 = Subtarget.isPPC64(); 3353 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; 3354 SDValue StackPtr = DAG.getRegister(SP, PtrVT); 3355 3356 // Get the operands for the STACKRESTORE. 3357 SDValue Chain = Op.getOperand(0); 3358 SDValue SaveSP = Op.getOperand(1); 3359 3360 // Load the old link SP. 3361 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, 3362 MachinePointerInfo(), 3363 false, false, 0); 3364 3365 // Restore the stack pointer. 3366 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP); 3367 3368 // Store the old link SP. 3369 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(), 3370 false, false, 0); 3371} 3372 3373 3374 3375SDValue 3376PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { 3377 MachineFunction &MF = DAG.getMachineFunction(); 3378 bool isPPC64 = PPCSubTarget.isPPC64(); 3379 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3380 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3381 3382 // Get current frame pointer save index. The users of this index will be 3383 // primarily DYNALLOC instructions. 3384 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3385 int RASI = FI->getReturnAddrSaveIndex(); 3386 3387 // If the frame pointer save index hasn't been defined yet. 3388 if (!RASI) { 3389 // Find out what the fix offset of the frame pointer save area. 3390 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); 3391 // Allocate the frame index for frame pointer save area. 3392 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); 3393 // Save the result. 3394 FI->setReturnAddrSaveIndex(RASI); 3395 } 3396 return DAG.getFrameIndex(RASI, PtrVT); 3397} 3398 3399SDValue 3400PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { 3401 MachineFunction &MF = DAG.getMachineFunction(); 3402 bool isPPC64 = PPCSubTarget.isPPC64(); 3403 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 3404 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3405 3406 // Get current frame pointer save index. The users of this index will be 3407 // primarily DYNALLOC instructions. 3408 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 3409 int FPSI = FI->getFramePointerSaveIndex(); 3410 3411 // If the frame pointer save index hasn't been defined yet. 3412 if (!FPSI) { 3413 // Find out what the fix offset of the frame pointer save area. 3414 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, 3415 isDarwinABI); 3416 3417 // Allocate the frame index for frame pointer save area. 3418 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 3419 // Save the result. 3420 FI->setFramePointerSaveIndex(FPSI); 3421 } 3422 return DAG.getFrameIndex(FPSI, PtrVT); 3423} 3424 3425SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 3426 SelectionDAG &DAG, 3427 const PPCSubtarget &Subtarget) const { 3428 // Get the inputs. 3429 SDValue Chain = Op.getOperand(0); 3430 SDValue Size = Op.getOperand(1); 3431 DebugLoc dl = Op.getDebugLoc(); 3432 3433 // Get the corect type for pointers. 3434 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3435 // Negate the size. 3436 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, 3437 DAG.getConstant(0, PtrVT), Size); 3438 // Construct a node for the frame pointer save index. 3439 SDValue FPSIdx = getFramePointerFrameIndex(DAG); 3440 // Build a DYNALLOC node. 3441 SDValue Ops[3] = { Chain, NegSize, FPSIdx }; 3442 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); 3443 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); 3444} 3445 3446/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when 3447/// possible. 3448SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 3449 // Not FP? Not a fsel. 3450 if (!Op.getOperand(0).getValueType().isFloatingPoint() || 3451 !Op.getOperand(2).getValueType().isFloatingPoint()) 3452 return Op; 3453 3454 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 3455 3456 // Cannot handle SETEQ/SETNE. 3457 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; 3458 3459 EVT ResVT = Op.getValueType(); 3460 EVT CmpVT = Op.getOperand(0).getValueType(); 3461 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 3462 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); 3463 DebugLoc dl = Op.getDebugLoc(); 3464 3465 // If the RHS of the comparison is a 0.0, we don't need to do the 3466 // subtraction at all. 3467 if (isFloatingPointZero(RHS)) 3468 switch (CC) { 3469 default: break; // SETUO etc aren't handled by fsel. 3470 case ISD::SETULT: 3471 case ISD::SETLT: 3472 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3473 case ISD::SETOGE: 3474 case ISD::SETGE: 3475 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3476 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3477 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); 3478 case ISD::SETUGT: 3479 case ISD::SETGT: 3480 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 3481 case ISD::SETOLE: 3482 case ISD::SETLE: 3483 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 3484 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); 3485 return DAG.getNode(PPCISD::FSEL, dl, ResVT, 3486 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); 3487 } 3488 3489 SDValue Cmp; 3490 switch (CC) { 3491 default: break; // SETUO etc aren't handled by fsel. 3492 case ISD::SETULT: 3493 case ISD::SETLT: 3494 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3495 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3496 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3497 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3498 case ISD::SETOGE: 3499 case ISD::SETGE: 3500 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); 3501 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3502 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3503 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3504 case ISD::SETUGT: 3505 case ISD::SETGT: 3506 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3507 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3508 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3509 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); 3510 case ISD::SETOLE: 3511 case ISD::SETLE: 3512 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); 3513 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 3514 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); 3515 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); 3516 } 3517 return Op; 3518} 3519 3520// FIXME: Split this code up when LegalizeDAGTypes lands. 3521SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, 3522 DebugLoc dl) const { 3523 assert(Op.getOperand(0).getValueType().isFloatingPoint()); 3524 SDValue Src = Op.getOperand(0); 3525 if (Src.getValueType() == MVT::f32) 3526 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); 3527 3528 SDValue Tmp; 3529 switch (Op.getValueType().getSimpleVT().SimpleTy) { 3530 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); 3531 case MVT::i32: 3532 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : 3533 PPCISD::FCTIDZ, 3534 dl, MVT::f64, Src); 3535 break; 3536 case MVT::i64: 3537 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); 3538 break; 3539 } 3540 3541 // Convert the FP value to an int value through memory. 3542 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); 3543 3544 // Emit a store to the stack slot. 3545 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, 3546 MachinePointerInfo(), false, false, 0); 3547 3548 // Result is a load from the stack slot. If loading 4 bytes, make sure to 3549 // add in a bias. 3550 if (Op.getValueType() == MVT::i32) 3551 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, 3552 DAG.getConstant(4, FIPtr.getValueType())); 3553 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(), 3554 false, false, 0); 3555} 3556 3557SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, 3558 SelectionDAG &DAG) const { 3559 DebugLoc dl = Op.getDebugLoc(); 3560 // Don't handle ppc_fp128 here; let it be lowered to a libcall. 3561 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) 3562 return SDValue(); 3563 3564 if (Op.getOperand(0).getValueType() == MVT::i64) { 3565 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl, 3566 MVT::f64, Op.getOperand(0)); 3567 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); 3568 if (Op.getValueType() == MVT::f32) 3569 FP = DAG.getNode(ISD::FP_ROUND, dl, 3570 MVT::f32, FP, DAG.getIntPtrConstant(0)); 3571 return FP; 3572 } 3573 3574 assert(Op.getOperand(0).getValueType() == MVT::i32 && 3575 "Unhandled SINT_TO_FP type in custom expander!"); 3576 // Since we only generate this in 64-bit mode, we can take advantage of 3577 // 64-bit registers. In particular, sign extend the input value into the 3578 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack 3579 // then lfd it and fcfid it. 3580 MachineFunction &MF = DAG.getMachineFunction(); 3581 MachineFrameInfo *FrameInfo = MF.getFrameInfo(); 3582 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false); 3583 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3584 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 3585 3586 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, 3587 Op.getOperand(0)); 3588 3589 // STD the extended value into the stack slot. 3590 MachineMemOperand *MMO = 3591 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx), 3592 MachineMemOperand::MOStore, 8, 8); 3593 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx }; 3594 SDValue Store = 3595 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other), 3596 Ops, 4, MVT::i64, MMO); 3597 // Load the value as a double. 3598 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(), 3599 false, false, 0); 3600 3601 // FCFID it and return it. 3602 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); 3603 if (Op.getValueType() == MVT::f32) 3604 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); 3605 return FP; 3606} 3607 3608SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3609 SelectionDAG &DAG) const { 3610 DebugLoc dl = Op.getDebugLoc(); 3611 /* 3612 The rounding mode is in bits 30:31 of FPSR, and has the following 3613 settings: 3614 00 Round to nearest 3615 01 Round to 0 3616 10 Round to +inf 3617 11 Round to -inf 3618 3619 FLT_ROUNDS, on the other hand, expects the following: 3620 -1 Undefined 3621 0 Round to 0 3622 1 Round to nearest 3623 2 Round to +inf 3624 3 Round to -inf 3625 3626 To perform the conversion, we do: 3627 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1)) 3628 */ 3629 3630 MachineFunction &MF = DAG.getMachineFunction(); 3631 EVT VT = Op.getValueType(); 3632 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 3633 std::vector<EVT> NodeTys; 3634 SDValue MFFSreg, InFlag; 3635 3636 // Save FP Control Word to register 3637 NodeTys.push_back(MVT::f64); // return register 3638 NodeTys.push_back(MVT::Flag); // unused in this context 3639 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 3640 3641 // Save FP register to stack slot 3642 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false); 3643 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT); 3644 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain, 3645 StackSlot, MachinePointerInfo(), false, false,0); 3646 3647 // Load FP Control Word from low 32 bits of stack slot. 3648 SDValue Four = DAG.getConstant(4, PtrVT); 3649 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); 3650 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), 3651 false, false, 0); 3652 3653 // Transform as necessary 3654 SDValue CWD1 = 3655 DAG.getNode(ISD::AND, dl, MVT::i32, 3656 CWD, DAG.getConstant(3, MVT::i32)); 3657 SDValue CWD2 = 3658 DAG.getNode(ISD::SRL, dl, MVT::i32, 3659 DAG.getNode(ISD::AND, dl, MVT::i32, 3660 DAG.getNode(ISD::XOR, dl, MVT::i32, 3661 CWD, DAG.getConstant(3, MVT::i32)), 3662 DAG.getConstant(3, MVT::i32)), 3663 DAG.getConstant(1, MVT::i32)); 3664 3665 SDValue RetVal = 3666 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); 3667 3668 return DAG.getNode((VT.getSizeInBits() < 16 ? 3669 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); 3670} 3671 3672SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3673 EVT VT = Op.getValueType(); 3674 unsigned BitWidth = VT.getSizeInBits(); 3675 DebugLoc dl = Op.getDebugLoc(); 3676 assert(Op.getNumOperands() == 3 && 3677 VT == Op.getOperand(1).getValueType() && 3678 "Unexpected SHL!"); 3679 3680 // Expand into a bunch of logical ops. Note that these ops 3681 // depend on the PPC behavior for oversized shift amounts. 3682 SDValue Lo = Op.getOperand(0); 3683 SDValue Hi = Op.getOperand(1); 3684 SDValue Amt = Op.getOperand(2); 3685 EVT AmtVT = Amt.getValueType(); 3686 3687 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3688 DAG.getConstant(BitWidth, AmtVT), Amt); 3689 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 3690 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); 3691 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 3692 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3693 DAG.getConstant(-BitWidth, AmtVT)); 3694 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 3695 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3696 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 3697 SDValue OutOps[] = { OutLo, OutHi }; 3698 return DAG.getMergeValues(OutOps, 2, dl); 3699} 3700 3701SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const { 3702 EVT VT = Op.getValueType(); 3703 DebugLoc dl = Op.getDebugLoc(); 3704 unsigned BitWidth = VT.getSizeInBits(); 3705 assert(Op.getNumOperands() == 3 && 3706 VT == Op.getOperand(1).getValueType() && 3707 "Unexpected SRL!"); 3708 3709 // Expand into a bunch of logical ops. Note that these ops 3710 // depend on the PPC behavior for oversized shift amounts. 3711 SDValue Lo = Op.getOperand(0); 3712 SDValue Hi = Op.getOperand(1); 3713 SDValue Amt = Op.getOperand(2); 3714 EVT AmtVT = Amt.getValueType(); 3715 3716 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3717 DAG.getConstant(BitWidth, AmtVT), Amt); 3718 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3719 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3720 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3721 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3722 DAG.getConstant(-BitWidth, AmtVT)); 3723 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); 3724 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); 3725 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); 3726 SDValue OutOps[] = { OutLo, OutHi }; 3727 return DAG.getMergeValues(OutOps, 2, dl); 3728} 3729 3730SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const { 3731 DebugLoc dl = Op.getDebugLoc(); 3732 EVT VT = Op.getValueType(); 3733 unsigned BitWidth = VT.getSizeInBits(); 3734 assert(Op.getNumOperands() == 3 && 3735 VT == Op.getOperand(1).getValueType() && 3736 "Unexpected SRA!"); 3737 3738 // Expand into a bunch of logical ops, followed by a select_cc. 3739 SDValue Lo = Op.getOperand(0); 3740 SDValue Hi = Op.getOperand(1); 3741 SDValue Amt = Op.getOperand(2); 3742 EVT AmtVT = Amt.getValueType(); 3743 3744 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, 3745 DAG.getConstant(BitWidth, AmtVT), Amt); 3746 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); 3747 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); 3748 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 3749 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, 3750 DAG.getConstant(-BitWidth, AmtVT)); 3751 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); 3752 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); 3753 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), 3754 Tmp4, Tmp6, ISD::SETLE); 3755 SDValue OutOps[] = { OutLo, OutHi }; 3756 return DAG.getMergeValues(OutOps, 2, dl); 3757} 3758 3759//===----------------------------------------------------------------------===// 3760// Vector related lowering. 3761// 3762 3763/// BuildSplatI - Build a canonical splati of Val with an element size of 3764/// SplatSize. Cast the result to VT. 3765static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, 3766 SelectionDAG &DAG, DebugLoc dl) { 3767 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); 3768 3769 static const EVT VTys[] = { // canonical VT to use for each size. 3770 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 3771 }; 3772 3773 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; 3774 3775 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. 3776 if (Val == -1) 3777 SplatSize = 1; 3778 3779 EVT CanonicalVT = VTys[SplatSize-1]; 3780 3781 // Build a canonical splat for this value. 3782 SDValue Elt = DAG.getConstant(Val, MVT::i32); 3783 SmallVector<SDValue, 8> Ops; 3784 Ops.assign(CanonicalVT.getVectorNumElements(), Elt); 3785 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, 3786 &Ops[0], Ops.size()); 3787 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res); 3788} 3789 3790/// BuildIntrinsicOp - Return a binary operator intrinsic node with the 3791/// specified intrinsic ID. 3792static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, 3793 SelectionDAG &DAG, DebugLoc dl, 3794 EVT DestVT = MVT::Other) { 3795 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); 3796 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3797 DAG.getConstant(IID, MVT::i32), LHS, RHS); 3798} 3799 3800/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the 3801/// specified intrinsic ID. 3802static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, 3803 SDValue Op2, SelectionDAG &DAG, 3804 DebugLoc dl, EVT DestVT = MVT::Other) { 3805 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); 3806 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 3807 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); 3808} 3809 3810 3811/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified 3812/// amount. The result has the specified value type. 3813static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, 3814 EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3815 // Force LHS/RHS to be the right type. 3816 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS); 3817 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS); 3818 3819 int Ops[16]; 3820 for (unsigned i = 0; i != 16; ++i) 3821 Ops[i] = i + Amt; 3822 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); 3823 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); 3824} 3825 3826// If this is a case we can't handle, return null and let the default 3827// expansion code take care of it. If we CAN select this case, and if it 3828// selects to a single instruction, return Op. Otherwise, if we can codegen 3829// this case more efficiently than a constant pool load, lower it to the 3830// sequence of ops that should be used. 3831SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, 3832 SelectionDAG &DAG) const { 3833 DebugLoc dl = Op.getDebugLoc(); 3834 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 3835 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); 3836 3837 // Check if this is a splat of a constant value. 3838 APInt APSplatBits, APSplatUndef; 3839 unsigned SplatBitSize; 3840 bool HasAnyUndefs; 3841 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize, 3842 HasAnyUndefs, 0, true) || SplatBitSize > 32) 3843 return SDValue(); 3844 3845 unsigned SplatBits = APSplatBits.getZExtValue(); 3846 unsigned SplatUndef = APSplatUndef.getZExtValue(); 3847 unsigned SplatSize = SplatBitSize / 8; 3848 3849 // First, handle single instruction cases. 3850 3851 // All zeros? 3852 if (SplatBits == 0) { 3853 // Canonicalize all zero vectors to be v4i32. 3854 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { 3855 SDValue Z = DAG.getConstant(0, MVT::i32); 3856 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); 3857 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z); 3858 } 3859 return Op; 3860 } 3861 3862 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. 3863 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> 3864 (32-SplatBitSize)); 3865 if (SextVal >= -16 && SextVal <= 15) 3866 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl); 3867 3868 3869 // Two instruction sequences. 3870 3871 // If this value is in the range [-32,30] and is even, use: 3872 // tmp = VSPLTI[bhw], result = add tmp, tmp 3873 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { 3874 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); 3875 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); 3876 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3877 } 3878 3879 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is 3880 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important 3881 // for fneg/fabs. 3882 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { 3883 // Make -1 and vspltisw -1: 3884 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); 3885 3886 // Make the VSLW intrinsic, computing 0x8000_0000. 3887 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, 3888 OnesV, DAG, dl); 3889 3890 // xor by OnesV to invert it. 3891 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); 3892 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3893 } 3894 3895 // Check to see if this is a wide variety of vsplti*, binop self cases. 3896 static const signed char SplatCsts[] = { 3897 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, 3898 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 3899 }; 3900 3901 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { 3902 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for 3903 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1' 3904 int i = SplatCsts[idx]; 3905 3906 // Figure out what shift amount will be used by altivec if shifted by i in 3907 // this splat size. 3908 unsigned TypeShiftAmt = i & (SplatBitSize-1); 3909 3910 // vsplti + shl self. 3911 if (SextVal == (i << (int)TypeShiftAmt)) { 3912 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3913 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3914 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, 3915 Intrinsic::ppc_altivec_vslw 3916 }; 3917 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3918 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3919 } 3920 3921 // vsplti + srl self. 3922 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3923 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3924 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3925 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, 3926 Intrinsic::ppc_altivec_vsrw 3927 }; 3928 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3929 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3930 } 3931 3932 // vsplti + sra self. 3933 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { 3934 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3935 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3936 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, 3937 Intrinsic::ppc_altivec_vsraw 3938 }; 3939 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3940 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3941 } 3942 3943 // vsplti + rol self. 3944 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | 3945 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { 3946 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); 3947 static const unsigned IIDs[] = { // Intrinsic to use for each size. 3948 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, 3949 Intrinsic::ppc_altivec_vrlw 3950 }; 3951 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); 3952 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); 3953 } 3954 3955 // t = vsplti c, result = vsldoi t, t, 1 3956 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) { 3957 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3958 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); 3959 } 3960 // t = vsplti c, result = vsldoi t, t, 2 3961 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) { 3962 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3963 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); 3964 } 3965 // t = vsplti c, result = vsldoi t, t, 3 3966 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) { 3967 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); 3968 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); 3969 } 3970 } 3971 3972 // Three instruction sequences. 3973 3974 // Odd, in range [17,31]: (vsplti C)-(vsplti -16). 3975 if (SextVal >= 0 && SextVal <= 31) { 3976 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); 3977 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3978 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); 3979 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3980 } 3981 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). 3982 if (SextVal >= -31 && SextVal <= 0) { 3983 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); 3984 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); 3985 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); 3986 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); 3987 } 3988 3989 return SDValue(); 3990} 3991 3992/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 3993/// the specified operations to build the shuffle. 3994static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 3995 SDValue RHS, SelectionDAG &DAG, 3996 DebugLoc dl) { 3997 unsigned OpNum = (PFEntry >> 26) & 0x0F; 3998 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 3999 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 4000 4001 enum { 4002 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4003 OP_VMRGHW, 4004 OP_VMRGLW, 4005 OP_VSPLTISW0, 4006 OP_VSPLTISW1, 4007 OP_VSPLTISW2, 4008 OP_VSPLTISW3, 4009 OP_VSLDOI4, 4010 OP_VSLDOI8, 4011 OP_VSLDOI12 4012 }; 4013 4014 if (OpNum == OP_COPY) { 4015 if (LHSID == (1*9+2)*9+3) return LHS; 4016 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4017 return RHS; 4018 } 4019 4020 SDValue OpLHS, OpRHS; 4021 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4022 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4023 4024 int ShufIdxs[16]; 4025 switch (OpNum) { 4026 default: llvm_unreachable("Unknown i32 permute!"); 4027 case OP_VMRGHW: 4028 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; 4029 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; 4030 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; 4031 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; 4032 break; 4033 case OP_VMRGLW: 4034 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; 4035 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; 4036 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; 4037 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; 4038 break; 4039 case OP_VSPLTISW0: 4040 for (unsigned i = 0; i != 16; ++i) 4041 ShufIdxs[i] = (i&3)+0; 4042 break; 4043 case OP_VSPLTISW1: 4044 for (unsigned i = 0; i != 16; ++i) 4045 ShufIdxs[i] = (i&3)+4; 4046 break; 4047 case OP_VSPLTISW2: 4048 for (unsigned i = 0; i != 16; ++i) 4049 ShufIdxs[i] = (i&3)+8; 4050 break; 4051 case OP_VSPLTISW3: 4052 for (unsigned i = 0; i != 16; ++i) 4053 ShufIdxs[i] = (i&3)+12; 4054 break; 4055 case OP_VSLDOI4: 4056 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); 4057 case OP_VSLDOI8: 4058 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl); 4059 case OP_VSLDOI12: 4060 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); 4061 } 4062 EVT VT = OpLHS.getValueType(); 4063 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS); 4064 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS); 4065 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); 4066 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); 4067} 4068 4069/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this 4070/// is a shuffle we can handle in a single instruction, return it. Otherwise, 4071/// return the code it can be lowered into. Worst case, it can always be 4072/// lowered into a vperm. 4073SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, 4074 SelectionDAG &DAG) const { 4075 DebugLoc dl = Op.getDebugLoc(); 4076 SDValue V1 = Op.getOperand(0); 4077 SDValue V2 = Op.getOperand(1); 4078 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 4079 EVT VT = Op.getValueType(); 4080 4081 // Cases that are handled by instructions that take permute immediates 4082 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be 4083 // selected by the instruction selector. 4084 if (V2.getOpcode() == ISD::UNDEF) { 4085 if (PPC::isSplatShuffleMask(SVOp, 1) || 4086 PPC::isSplatShuffleMask(SVOp, 2) || 4087 PPC::isSplatShuffleMask(SVOp, 4) || 4088 PPC::isVPKUWUMShuffleMask(SVOp, true) || 4089 PPC::isVPKUHUMShuffleMask(SVOp, true) || 4090 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 || 4091 PPC::isVMRGLShuffleMask(SVOp, 1, true) || 4092 PPC::isVMRGLShuffleMask(SVOp, 2, true) || 4093 PPC::isVMRGLShuffleMask(SVOp, 4, true) || 4094 PPC::isVMRGHShuffleMask(SVOp, 1, true) || 4095 PPC::isVMRGHShuffleMask(SVOp, 2, true) || 4096 PPC::isVMRGHShuffleMask(SVOp, 4, true)) { 4097 return Op; 4098 } 4099 } 4100 4101 // Altivec has a variety of "shuffle immediates" that take two vector inputs 4102 // and produce a fixed permutation. If any of these match, do not lower to 4103 // VPERM. 4104 if (PPC::isVPKUWUMShuffleMask(SVOp, false) || 4105 PPC::isVPKUHUMShuffleMask(SVOp, false) || 4106 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 || 4107 PPC::isVMRGLShuffleMask(SVOp, 1, false) || 4108 PPC::isVMRGLShuffleMask(SVOp, 2, false) || 4109 PPC::isVMRGLShuffleMask(SVOp, 4, false) || 4110 PPC::isVMRGHShuffleMask(SVOp, 1, false) || 4111 PPC::isVMRGHShuffleMask(SVOp, 2, false) || 4112 PPC::isVMRGHShuffleMask(SVOp, 4, false)) 4113 return Op; 4114 4115 // Check to see if this is a shuffle of 4-byte values. If so, we can use our 4116 // perfect shuffle table to emit an optimal matching sequence. 4117 SmallVector<int, 16> PermMask; 4118 SVOp->getMask(PermMask); 4119 4120 unsigned PFIndexes[4]; 4121 bool isFourElementShuffle = true; 4122 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number 4123 unsigned EltNo = 8; // Start out undef. 4124 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte. 4125 if (PermMask[i*4+j] < 0) 4126 continue; // Undef, ignore it. 4127 4128 unsigned ByteSource = PermMask[i*4+j]; 4129 if ((ByteSource & 3) != j) { 4130 isFourElementShuffle = false; 4131 break; 4132 } 4133 4134 if (EltNo == 8) { 4135 EltNo = ByteSource/4; 4136 } else if (EltNo != ByteSource/4) { 4137 isFourElementShuffle = false; 4138 break; 4139 } 4140 } 4141 PFIndexes[i] = EltNo; 4142 } 4143 4144 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the 4145 // perfect shuffle vector to determine if it is cost effective to do this as 4146 // discrete instructions, or whether we should use a vperm. 4147 if (isFourElementShuffle) { 4148 // Compute the index in the perfect shuffle table. 4149 unsigned PFTableIndex = 4150 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4151 4152 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4153 unsigned Cost = (PFEntry >> 30); 4154 4155 // Determining when to avoid vperm is tricky. Many things affect the cost 4156 // of vperm, particularly how many times the perm mask needs to be computed. 4157 // For example, if the perm mask can be hoisted out of a loop or is already 4158 // used (perhaps because there are multiple permutes with the same shuffle 4159 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of 4160 // the loop requires an extra register. 4161 // 4162 // As a compromise, we only emit discrete instructions if the shuffle can be 4163 // generated in 3 or fewer operations. When we have loop information 4164 // available, if this block is within a loop, we should avoid using vperm 4165 // for 3-operation perms and use a constant pool load instead. 4166 if (Cost < 3) 4167 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4168 } 4169 4170 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant 4171 // vector that will get spilled to the constant pool. 4172 if (V2.getOpcode() == ISD::UNDEF) V2 = V1; 4173 4174 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except 4175 // that it is in input element units, not in bytes. Convert now. 4176 EVT EltVT = V1.getValueType().getVectorElementType(); 4177 unsigned BytesPerElement = EltVT.getSizeInBits()/8; 4178 4179 SmallVector<SDValue, 16> ResultMask; 4180 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { 4181 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; 4182 4183 for (unsigned j = 0; j != BytesPerElement; ++j) 4184 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, 4185 MVT::i32)); 4186 } 4187 4188 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, 4189 &ResultMask[0], ResultMask.size()); 4190 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); 4191} 4192 4193/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an 4194/// altivec comparison. If it is, return true and fill in Opc/isDot with 4195/// information about the intrinsic. 4196static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc, 4197 bool &isDot) { 4198 unsigned IntrinsicID = 4199 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue(); 4200 CompareOpc = -1; 4201 isDot = false; 4202 switch (IntrinsicID) { 4203 default: return false; 4204 // Comparison predicates. 4205 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break; 4206 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break; 4207 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break; 4208 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break; 4209 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break; 4210 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break; 4211 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break; 4212 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break; 4213 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break; 4214 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break; 4215 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break; 4216 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break; 4217 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break; 4218 4219 // Normal Comparisons. 4220 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break; 4221 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break; 4222 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break; 4223 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break; 4224 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break; 4225 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break; 4226 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break; 4227 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break; 4228 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break; 4229 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break; 4230 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break; 4231 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break; 4232 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break; 4233 } 4234 return true; 4235} 4236 4237/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom 4238/// lower, do it, otherwise return null. 4239SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 4240 SelectionDAG &DAG) const { 4241 // If this is a lowered altivec predicate compare, CompareOpc is set to the 4242 // opcode number of the comparison. 4243 DebugLoc dl = Op.getDebugLoc(); 4244 int CompareOpc; 4245 bool isDot; 4246 if (!getAltivecCompareInfo(Op, CompareOpc, isDot)) 4247 return SDValue(); // Don't custom lower most intrinsics. 4248 4249 // If this is a non-dot comparison, make the VCMP node and we are done. 4250 if (!isDot) { 4251 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), 4252 Op.getOperand(1), Op.getOperand(2), 4253 DAG.getConstant(CompareOpc, MVT::i32)); 4254 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp); 4255 } 4256 4257 // Create the PPCISD altivec 'dot' comparison node. 4258 SDValue Ops[] = { 4259 Op.getOperand(2), // LHS 4260 Op.getOperand(3), // RHS 4261 DAG.getConstant(CompareOpc, MVT::i32) 4262 }; 4263 std::vector<EVT> VTs; 4264 VTs.push_back(Op.getOperand(2).getValueType()); 4265 VTs.push_back(MVT::Flag); 4266 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 4267 4268 // Now that we have the comparison, emit a copy from the CR to a GPR. 4269 // This is flagged to the above dot comparison. 4270 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, 4271 DAG.getRegister(PPC::CR6, MVT::i32), 4272 CompNode.getValue(1)); 4273 4274 // Unpack the result based on how the target uses it. 4275 unsigned BitNo; // Bit # of CR6. 4276 bool InvertBit; // Invert result? 4277 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) { 4278 default: // Can't happen, don't crash on invalid number though. 4279 case 0: // Return the value of the EQ bit of CR6. 4280 BitNo = 0; InvertBit = false; 4281 break; 4282 case 1: // Return the inverted value of the EQ bit of CR6. 4283 BitNo = 0; InvertBit = true; 4284 break; 4285 case 2: // Return the value of the LT bit of CR6. 4286 BitNo = 2; InvertBit = false; 4287 break; 4288 case 3: // Return the inverted value of the LT bit of CR6. 4289 BitNo = 2; InvertBit = true; 4290 break; 4291 } 4292 4293 // Shift the bit into the low position. 4294 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, 4295 DAG.getConstant(8-(3-BitNo), MVT::i32)); 4296 // Isolate the bit. 4297 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, 4298 DAG.getConstant(1, MVT::i32)); 4299 4300 // If we are supposed to, toggle the bit. 4301 if (InvertBit) 4302 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, 4303 DAG.getConstant(1, MVT::i32)); 4304 return Flags; 4305} 4306 4307SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, 4308 SelectionDAG &DAG) const { 4309 DebugLoc dl = Op.getDebugLoc(); 4310 // Create a stack slot that is 16-byte aligned. 4311 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4312 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false); 4313 EVT PtrVT = getPointerTy(); 4314 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); 4315 4316 // Store the input value into Value#0 of the stack slot. 4317 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 4318 Op.getOperand(0), FIdx, MachinePointerInfo(), 4319 false, false, 0); 4320 // Load it out. 4321 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(), 4322 false, false, 0); 4323} 4324 4325SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 4326 DebugLoc dl = Op.getDebugLoc(); 4327 if (Op.getValueType() == MVT::v4i32) { 4328 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4329 4330 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); 4331 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. 4332 4333 SDValue RHSSwap = // = vrlw RHS, 16 4334 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); 4335 4336 // Shrinkify inputs to v8i16. 4337 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS); 4338 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS); 4339 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap); 4340 4341 // Low parts multiplied together, generating 32-bit results (we ignore the 4342 // top parts). 4343 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, 4344 LHS, RHS, DAG, dl, MVT::v4i32); 4345 4346 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, 4347 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); 4348 // Shift the high parts up 16 bits. 4349 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, 4350 Neg16, DAG, dl); 4351 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); 4352 } else if (Op.getValueType() == MVT::v8i16) { 4353 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4354 4355 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); 4356 4357 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, 4358 LHS, RHS, Zero, DAG, dl); 4359 } else if (Op.getValueType() == MVT::v16i8) { 4360 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); 4361 4362 // Multiply the even 8-bit parts, producing 16-bit sums. 4363 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, 4364 LHS, RHS, DAG, dl, MVT::v8i16); 4365 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts); 4366 4367 // Multiply the odd 8-bit parts, producing 16-bit sums. 4368 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, 4369 LHS, RHS, DAG, dl, MVT::v8i16); 4370 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts); 4371 4372 // Merge the results together. 4373 int Ops[16]; 4374 for (unsigned i = 0; i != 8; ++i) { 4375 Ops[i*2 ] = 2*i+1; 4376 Ops[i*2+1] = 2*i+1+16; 4377 } 4378 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); 4379 } else { 4380 llvm_unreachable("Unknown mul to lower!"); 4381 } 4382} 4383 4384/// LowerOperation - Provide custom lowering hooks for some operations. 4385/// 4386SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4387 switch (Op.getOpcode()) { 4388 default: llvm_unreachable("Wasn't expecting to be able to lower this!"); 4389 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4390 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4391 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 4392 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 4393 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 4394 case ISD::SETCC: return LowerSETCC(Op, DAG); 4395 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG); 4396 case ISD::VASTART: 4397 return LowerVASTART(Op, DAG, PPCSubTarget); 4398 4399 case ISD::VAARG: 4400 return LowerVAARG(Op, DAG, PPCSubTarget); 4401 4402 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget); 4403 case ISD::DYNAMIC_STACKALLOC: 4404 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget); 4405 4406 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4407 case ISD::FP_TO_UINT: 4408 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, 4409 Op.getDebugLoc()); 4410 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 4411 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4412 4413 // Lower 64-bit shifts. 4414 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); 4415 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); 4416 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); 4417 4418 // Vector-related lowering. 4419 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 4420 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4421 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 4422 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 4423 case ISD::MUL: return LowerMUL(Op, DAG); 4424 4425 // Frame & Return address. 4426 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4427 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4428 } 4429 return SDValue(); 4430} 4431 4432void PPCTargetLowering::ReplaceNodeResults(SDNode *N, 4433 SmallVectorImpl<SDValue>&Results, 4434 SelectionDAG &DAG) const { 4435 DebugLoc dl = N->getDebugLoc(); 4436 switch (N->getOpcode()) { 4437 default: 4438 assert(false && "Do not know how to custom type legalize this operation!"); 4439 return; 4440 case ISD::FP_ROUND_INREG: { 4441 assert(N->getValueType(0) == MVT::ppcf128); 4442 assert(N->getOperand(0).getValueType() == MVT::ppcf128); 4443 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4444 MVT::f64, N->getOperand(0), 4445 DAG.getIntPtrConstant(0)); 4446 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, 4447 MVT::f64, N->getOperand(0), 4448 DAG.getIntPtrConstant(1)); 4449 4450 // This sequence changes FPSCR to do round-to-zero, adds the two halves 4451 // of the long double, and puts FPSCR back the way it was. We do not 4452 // actually model FPSCR. 4453 std::vector<EVT> NodeTys; 4454 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; 4455 4456 NodeTys.push_back(MVT::f64); // Return register 4457 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns 4458 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); 4459 MFFSreg = Result.getValue(0); 4460 InFlag = Result.getValue(1); 4461 4462 NodeTys.clear(); 4463 NodeTys.push_back(MVT::Flag); // Returns a flag 4464 Ops[0] = DAG.getConstant(31, MVT::i32); 4465 Ops[1] = InFlag; 4466 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); 4467 InFlag = Result.getValue(0); 4468 4469 NodeTys.clear(); 4470 NodeTys.push_back(MVT::Flag); // Returns a flag 4471 Ops[0] = DAG.getConstant(30, MVT::i32); 4472 Ops[1] = InFlag; 4473 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); 4474 InFlag = Result.getValue(0); 4475 4476 NodeTys.clear(); 4477 NodeTys.push_back(MVT::f64); // result of add 4478 NodeTys.push_back(MVT::Flag); // Returns a flag 4479 Ops[0] = Lo; 4480 Ops[1] = Hi; 4481 Ops[2] = InFlag; 4482 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3); 4483 FPreg = Result.getValue(0); 4484 InFlag = Result.getValue(1); 4485 4486 NodeTys.clear(); 4487 NodeTys.push_back(MVT::f64); 4488 Ops[0] = DAG.getConstant(1, MVT::i32); 4489 Ops[1] = MFFSreg; 4490 Ops[2] = FPreg; 4491 Ops[3] = InFlag; 4492 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4); 4493 FPreg = Result.getValue(0); 4494 4495 // We know the low half is about to be thrown away, so just use something 4496 // convenient. 4497 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, 4498 FPreg, FPreg)); 4499 return; 4500 } 4501 case ISD::FP_TO_SINT: 4502 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl)); 4503 return; 4504 } 4505} 4506 4507 4508//===----------------------------------------------------------------------===// 4509// Other Lowering Code 4510//===----------------------------------------------------------------------===// 4511 4512MachineBasicBlock * 4513PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 4514 bool is64bit, unsigned BinOpcode) const { 4515 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4516 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4517 4518 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4519 MachineFunction *F = BB->getParent(); 4520 MachineFunction::iterator It = BB; 4521 ++It; 4522 4523 unsigned dest = MI->getOperand(0).getReg(); 4524 unsigned ptrA = MI->getOperand(1).getReg(); 4525 unsigned ptrB = MI->getOperand(2).getReg(); 4526 unsigned incr = MI->getOperand(3).getReg(); 4527 DebugLoc dl = MI->getDebugLoc(); 4528 4529 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4530 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4531 F->insert(It, loopMBB); 4532 F->insert(It, exitMBB); 4533 exitMBB->splice(exitMBB->begin(), BB, 4534 llvm::next(MachineBasicBlock::iterator(MI)), 4535 BB->end()); 4536 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4537 4538 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4539 unsigned TmpReg = (!BinOpcode) ? incr : 4540 RegInfo.createVirtualRegister( 4541 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4542 (const TargetRegisterClass *) &PPC::GPRCRegClass); 4543 4544 // thisMBB: 4545 // ... 4546 // fallthrough --> loopMBB 4547 BB->addSuccessor(loopMBB); 4548 4549 // loopMBB: 4550 // l[wd]arx dest, ptr 4551 // add r0, dest, incr 4552 // st[wd]cx. r0, ptr 4553 // bne- loopMBB 4554 // fallthrough --> exitMBB 4555 BB = loopMBB; 4556 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4557 .addReg(ptrA).addReg(ptrB); 4558 if (BinOpcode) 4559 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); 4560 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4561 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); 4562 BuildMI(BB, dl, TII->get(PPC::BCC)) 4563 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4564 BB->addSuccessor(loopMBB); 4565 BB->addSuccessor(exitMBB); 4566 4567 // exitMBB: 4568 // ... 4569 BB = exitMBB; 4570 return BB; 4571} 4572 4573MachineBasicBlock * 4574PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI, 4575 MachineBasicBlock *BB, 4576 bool is8bit, // operation 4577 unsigned BinOpcode) const { 4578 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 4579 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4580 // In 64 bit mode we have to use 64 bits for addresses, even though the 4581 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address 4582 // registers without caring whether they're 32 or 64, but here we're 4583 // doing actual arithmetic on the addresses. 4584 bool is64bit = PPCSubTarget.isPPC64(); 4585 4586 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4587 MachineFunction *F = BB->getParent(); 4588 MachineFunction::iterator It = BB; 4589 ++It; 4590 4591 unsigned dest = MI->getOperand(0).getReg(); 4592 unsigned ptrA = MI->getOperand(1).getReg(); 4593 unsigned ptrB = MI->getOperand(2).getReg(); 4594 unsigned incr = MI->getOperand(3).getReg(); 4595 DebugLoc dl = MI->getDebugLoc(); 4596 4597 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); 4598 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4599 F->insert(It, loopMBB); 4600 F->insert(It, exitMBB); 4601 exitMBB->splice(exitMBB->begin(), BB, 4602 llvm::next(MachineBasicBlock::iterator(MI)), 4603 BB->end()); 4604 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4605 4606 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4607 const TargetRegisterClass *RC = 4608 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4609 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4610 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4611 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4612 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4613 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); 4614 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4615 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4616 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4617 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4618 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); 4619 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4620 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4621 unsigned Ptr1Reg; 4622 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); 4623 4624 // thisMBB: 4625 // ... 4626 // fallthrough --> loopMBB 4627 BB->addSuccessor(loopMBB); 4628 4629 // The 4-byte load must be aligned, while a char or short may be 4630 // anywhere in the word. Hence all this nasty bookkeeping code. 4631 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4632 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4633 // xori shift, shift1, 24 [16] 4634 // rlwinm ptr, ptr1, 0, 0, 29 4635 // slw incr2, incr, shift 4636 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4637 // slw mask, mask2, shift 4638 // loopMBB: 4639 // lwarx tmpDest, ptr 4640 // add tmp, tmpDest, incr2 4641 // andc tmp2, tmpDest, mask 4642 // and tmp3, tmp, mask 4643 // or tmp4, tmp3, tmp2 4644 // stwcx. tmp4, ptr 4645 // bne- loopMBB 4646 // fallthrough --> exitMBB 4647 // srw dest, tmpDest, shift 4648 4649 if (ptrA!=PPC::R0) { 4650 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4651 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4652 .addReg(ptrA).addReg(ptrB); 4653 } else { 4654 Ptr1Reg = ptrB; 4655 } 4656 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4657 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4658 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4659 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4660 if (is64bit) 4661 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4662 .addReg(Ptr1Reg).addImm(0).addImm(61); 4663 else 4664 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4665 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4666 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 4667 .addReg(incr).addReg(ShiftReg); 4668 if (is8bit) 4669 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 4670 else { 4671 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 4672 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535); 4673 } 4674 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 4675 .addReg(Mask2Reg).addReg(ShiftReg); 4676 4677 BB = loopMBB; 4678 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 4679 .addReg(PPC::R0).addReg(PtrReg); 4680 if (BinOpcode) 4681 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) 4682 .addReg(Incr2Reg).addReg(TmpDestReg); 4683 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg) 4684 .addReg(TmpDestReg).addReg(MaskReg); 4685 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg) 4686 .addReg(TmpReg).addReg(MaskReg); 4687 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg) 4688 .addReg(Tmp3Reg).addReg(Tmp2Reg); 4689 BuildMI(BB, dl, TII->get(PPC::STWCX)) 4690 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg); 4691 BuildMI(BB, dl, TII->get(PPC::BCC)) 4692 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); 4693 BB->addSuccessor(loopMBB); 4694 BB->addSuccessor(exitMBB); 4695 4696 // exitMBB: 4697 // ... 4698 BB = exitMBB; 4699 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg); 4700 return BB; 4701} 4702 4703MachineBasicBlock * 4704PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 4705 MachineBasicBlock *BB) const { 4706 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 4707 4708 // To "insert" these instructions we actually have to insert their 4709 // control-flow patterns. 4710 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 4711 MachineFunction::iterator It = BB; 4712 ++It; 4713 4714 MachineFunction *F = BB->getParent(); 4715 4716 if (MI->getOpcode() == PPC::SELECT_CC_I4 || 4717 MI->getOpcode() == PPC::SELECT_CC_I8 || 4718 MI->getOpcode() == PPC::SELECT_CC_F4 || 4719 MI->getOpcode() == PPC::SELECT_CC_F8 || 4720 MI->getOpcode() == PPC::SELECT_CC_VRRC) { 4721 4722 // The incoming instruction knows the destination vreg to set, the 4723 // condition code register to branch on, the true/false values to 4724 // select between, and a branch opcode to use. 4725 4726 // thisMBB: 4727 // ... 4728 // TrueVal = ... 4729 // cmpTY ccX, r1, r2 4730 // bCC copy1MBB 4731 // fallthrough --> copy0MBB 4732 MachineBasicBlock *thisMBB = BB; 4733 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 4734 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 4735 unsigned SelectPred = MI->getOperand(4).getImm(); 4736 DebugLoc dl = MI->getDebugLoc(); 4737 F->insert(It, copy0MBB); 4738 F->insert(It, sinkMBB); 4739 4740 // Transfer the remainder of BB and its successor edges to sinkMBB. 4741 sinkMBB->splice(sinkMBB->begin(), BB, 4742 llvm::next(MachineBasicBlock::iterator(MI)), 4743 BB->end()); 4744 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 4745 4746 // Next, add the true and fallthrough blocks as its successors. 4747 BB->addSuccessor(copy0MBB); 4748 BB->addSuccessor(sinkMBB); 4749 4750 BuildMI(BB, dl, TII->get(PPC::BCC)) 4751 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 4752 4753 // copy0MBB: 4754 // %FalseValue = ... 4755 // # fallthrough to sinkMBB 4756 BB = copy0MBB; 4757 4758 // Update machine-CFG edges 4759 BB->addSuccessor(sinkMBB); 4760 4761 // sinkMBB: 4762 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 4763 // ... 4764 BB = sinkMBB; 4765 BuildMI(*BB, BB->begin(), dl, 4766 TII->get(PPC::PHI), MI->getOperand(0).getReg()) 4767 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 4768 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 4769 } 4770 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) 4771 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); 4772 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) 4773 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); 4774 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) 4775 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4); 4776 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) 4777 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8); 4778 4779 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8) 4780 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); 4781 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16) 4782 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); 4783 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32) 4784 BB = EmitAtomicBinary(MI, BB, false, PPC::AND); 4785 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64) 4786 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8); 4787 4788 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8) 4789 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); 4790 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16) 4791 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); 4792 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32) 4793 BB = EmitAtomicBinary(MI, BB, false, PPC::OR); 4794 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64) 4795 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8); 4796 4797 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) 4798 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); 4799 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) 4800 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); 4801 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) 4802 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR); 4803 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) 4804 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8); 4805 4806 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) 4807 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC); 4808 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) 4809 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC); 4810 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) 4811 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC); 4812 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) 4813 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8); 4814 4815 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) 4816 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); 4817 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) 4818 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); 4819 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) 4820 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF); 4821 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) 4822 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8); 4823 4824 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8) 4825 BB = EmitPartwordAtomicBinary(MI, BB, true, 0); 4826 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16) 4827 BB = EmitPartwordAtomicBinary(MI, BB, false, 0); 4828 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32) 4829 BB = EmitAtomicBinary(MI, BB, false, 0); 4830 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64) 4831 BB = EmitAtomicBinary(MI, BB, true, 0); 4832 4833 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || 4834 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) { 4835 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; 4836 4837 unsigned dest = MI->getOperand(0).getReg(); 4838 unsigned ptrA = MI->getOperand(1).getReg(); 4839 unsigned ptrB = MI->getOperand(2).getReg(); 4840 unsigned oldval = MI->getOperand(3).getReg(); 4841 unsigned newval = MI->getOperand(4).getReg(); 4842 DebugLoc dl = MI->getDebugLoc(); 4843 4844 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4845 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4846 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4847 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4848 F->insert(It, loop1MBB); 4849 F->insert(It, loop2MBB); 4850 F->insert(It, midMBB); 4851 F->insert(It, exitMBB); 4852 exitMBB->splice(exitMBB->begin(), BB, 4853 llvm::next(MachineBasicBlock::iterator(MI)), 4854 BB->end()); 4855 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4856 4857 // thisMBB: 4858 // ... 4859 // fallthrough --> loopMBB 4860 BB->addSuccessor(loop1MBB); 4861 4862 // loop1MBB: 4863 // l[wd]arx dest, ptr 4864 // cmp[wd] dest, oldval 4865 // bne- midMBB 4866 // loop2MBB: 4867 // st[wd]cx. newval, ptr 4868 // bne- loopMBB 4869 // b exitBB 4870 // midMBB: 4871 // st[wd]cx. dest, ptr 4872 // exitBB: 4873 BB = loop1MBB; 4874 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) 4875 .addReg(ptrA).addReg(ptrB); 4876 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) 4877 .addReg(oldval).addReg(dest); 4878 BuildMI(BB, dl, TII->get(PPC::BCC)) 4879 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 4880 BB->addSuccessor(loop2MBB); 4881 BB->addSuccessor(midMBB); 4882 4883 BB = loop2MBB; 4884 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4885 .addReg(newval).addReg(ptrA).addReg(ptrB); 4886 BuildMI(BB, dl, TII->get(PPC::BCC)) 4887 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 4888 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 4889 BB->addSuccessor(loop1MBB); 4890 BB->addSuccessor(exitMBB); 4891 4892 BB = midMBB; 4893 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) 4894 .addReg(dest).addReg(ptrA).addReg(ptrB); 4895 BB->addSuccessor(exitMBB); 4896 4897 // exitMBB: 4898 // ... 4899 BB = exitMBB; 4900 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || 4901 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { 4902 // We must use 64-bit registers for addresses when targeting 64-bit, 4903 // since we're actually doing arithmetic on them. Other registers 4904 // can be 32-bit. 4905 bool is64bit = PPCSubTarget.isPPC64(); 4906 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; 4907 4908 unsigned dest = MI->getOperand(0).getReg(); 4909 unsigned ptrA = MI->getOperand(1).getReg(); 4910 unsigned ptrB = MI->getOperand(2).getReg(); 4911 unsigned oldval = MI->getOperand(3).getReg(); 4912 unsigned newval = MI->getOperand(4).getReg(); 4913 DebugLoc dl = MI->getDebugLoc(); 4914 4915 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB); 4916 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB); 4917 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB); 4918 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); 4919 F->insert(It, loop1MBB); 4920 F->insert(It, loop2MBB); 4921 F->insert(It, midMBB); 4922 F->insert(It, exitMBB); 4923 exitMBB->splice(exitMBB->begin(), BB, 4924 llvm::next(MachineBasicBlock::iterator(MI)), 4925 BB->end()); 4926 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 4927 4928 MachineRegisterInfo &RegInfo = F->getRegInfo(); 4929 const TargetRegisterClass *RC = 4930 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass : 4931 (const TargetRegisterClass *) &PPC::GPRCRegClass; 4932 unsigned PtrReg = RegInfo.createVirtualRegister(RC); 4933 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); 4934 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); 4935 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC); 4936 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC); 4937 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC); 4938 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC); 4939 unsigned MaskReg = RegInfo.createVirtualRegister(RC); 4940 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); 4941 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); 4942 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); 4943 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC); 4944 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC); 4945 unsigned Ptr1Reg; 4946 unsigned TmpReg = RegInfo.createVirtualRegister(RC); 4947 // thisMBB: 4948 // ... 4949 // fallthrough --> loopMBB 4950 BB->addSuccessor(loop1MBB); 4951 4952 // The 4-byte load must be aligned, while a char or short may be 4953 // anywhere in the word. Hence all this nasty bookkeeping code. 4954 // add ptr1, ptrA, ptrB [copy if ptrA==0] 4955 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27] 4956 // xori shift, shift1, 24 [16] 4957 // rlwinm ptr, ptr1, 0, 0, 29 4958 // slw newval2, newval, shift 4959 // slw oldval2, oldval,shift 4960 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535] 4961 // slw mask, mask2, shift 4962 // and newval3, newval2, mask 4963 // and oldval3, oldval2, mask 4964 // loop1MBB: 4965 // lwarx tmpDest, ptr 4966 // and tmp, tmpDest, mask 4967 // cmpw tmp, oldval3 4968 // bne- midMBB 4969 // loop2MBB: 4970 // andc tmp2, tmpDest, mask 4971 // or tmp4, tmp2, newval3 4972 // stwcx. tmp4, ptr 4973 // bne- loop1MBB 4974 // b exitBB 4975 // midMBB: 4976 // stwcx. tmpDest, ptr 4977 // exitBB: 4978 // srw dest, tmpDest, shift 4979 if (ptrA!=PPC::R0) { 4980 Ptr1Reg = RegInfo.createVirtualRegister(RC); 4981 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) 4982 .addReg(ptrA).addReg(ptrB); 4983 } else { 4984 Ptr1Reg = ptrB; 4985 } 4986 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg) 4987 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27); 4988 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) 4989 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16); 4990 if (is64bit) 4991 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) 4992 .addReg(Ptr1Reg).addImm(0).addImm(61); 4993 else 4994 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) 4995 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29); 4996 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 4997 .addReg(newval).addReg(ShiftReg); 4998 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 4999 .addReg(oldval).addReg(ShiftReg); 5000 if (is8bit) 5001 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); 5002 else { 5003 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); 5004 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) 5005 .addReg(Mask3Reg).addImm(65535); 5006 } 5007 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5008 .addReg(Mask2Reg).addReg(ShiftReg); 5009 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) 5010 .addReg(NewVal2Reg).addReg(MaskReg); 5011 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) 5012 .addReg(OldVal2Reg).addReg(MaskReg); 5013 5014 BB = loop1MBB; 5015 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) 5016 .addReg(PPC::R0).addReg(PtrReg); 5017 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) 5018 .addReg(TmpDestReg).addReg(MaskReg); 5019 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) 5020 .addReg(TmpReg).addReg(OldVal3Reg); 5021 BuildMI(BB, dl, TII->get(PPC::BCC)) 5022 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); 5023 BB->addSuccessor(loop2MBB); 5024 BB->addSuccessor(midMBB); 5025 5026 BB = loop2MBB; 5027 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg) 5028 .addReg(TmpDestReg).addReg(MaskReg); 5029 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg) 5030 .addReg(Tmp2Reg).addReg(NewVal3Reg); 5031 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg) 5032 .addReg(PPC::R0).addReg(PtrReg); 5033 BuildMI(BB, dl, TII->get(PPC::BCC)) 5034 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); 5035 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); 5036 BB->addSuccessor(loop1MBB); 5037 BB->addSuccessor(exitMBB); 5038 5039 BB = midMBB; 5040 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg) 5041 .addReg(PPC::R0).addReg(PtrReg); 5042 BB->addSuccessor(exitMBB); 5043 5044 // exitMBB: 5045 // ... 5046 BB = exitMBB; 5047 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg); 5048 } else { 5049 llvm_unreachable("Unexpected instr type to insert"); 5050 } 5051 5052 MI->eraseFromParent(); // The pseudo instruction is gone now. 5053 return BB; 5054} 5055 5056//===----------------------------------------------------------------------===// 5057// Target Optimization Hooks 5058//===----------------------------------------------------------------------===// 5059 5060SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, 5061 DAGCombinerInfo &DCI) const { 5062 const TargetMachine &TM = getTargetMachine(); 5063 SelectionDAG &DAG = DCI.DAG; 5064 DebugLoc dl = N->getDebugLoc(); 5065 switch (N->getOpcode()) { 5066 default: break; 5067 case PPCISD::SHL: 5068 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5069 if (C->isNullValue()) // 0 << V -> 0. 5070 return N->getOperand(0); 5071 } 5072 break; 5073 case PPCISD::SRL: 5074 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5075 if (C->isNullValue()) // 0 >>u V -> 0. 5076 return N->getOperand(0); 5077 } 5078 break; 5079 case PPCISD::SRA: 5080 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) { 5081 if (C->isNullValue() || // 0 >>s V -> 0. 5082 C->isAllOnesValue()) // -1 >>s V -> -1. 5083 return N->getOperand(0); 5084 } 5085 break; 5086 5087 case ISD::SINT_TO_FP: 5088 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { 5089 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { 5090 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. 5091 // We allow the src/dst to be either f32/f64, but the intermediate 5092 // type must be i64. 5093 if (N->getOperand(0).getValueType() == MVT::i64 && 5094 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { 5095 SDValue Val = N->getOperand(0).getOperand(0); 5096 if (Val.getValueType() == MVT::f32) { 5097 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5098 DCI.AddToWorklist(Val.getNode()); 5099 } 5100 5101 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); 5102 DCI.AddToWorklist(Val.getNode()); 5103 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); 5104 DCI.AddToWorklist(Val.getNode()); 5105 if (N->getValueType(0) == MVT::f32) { 5106 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, 5107 DAG.getIntPtrConstant(0)); 5108 DCI.AddToWorklist(Val.getNode()); 5109 } 5110 return Val; 5111 } else if (N->getOperand(0).getValueType() == MVT::i32) { 5112 // If the intermediate type is i32, we can avoid the load/store here 5113 // too. 5114 } 5115 } 5116 } 5117 break; 5118 case ISD::STORE: 5119 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)). 5120 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && 5121 !cast<StoreSDNode>(N)->isTruncatingStore() && 5122 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && 5123 N->getOperand(1).getValueType() == MVT::i32 && 5124 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { 5125 SDValue Val = N->getOperand(1).getOperand(0); 5126 if (Val.getValueType() == MVT::f32) { 5127 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); 5128 DCI.AddToWorklist(Val.getNode()); 5129 } 5130 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); 5131 DCI.AddToWorklist(Val.getNode()); 5132 5133 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, 5134 N->getOperand(2), N->getOperand(3)); 5135 DCI.AddToWorklist(Val.getNode()); 5136 return Val; 5137 } 5138 5139 // Turn STORE (BSWAP) -> sthbrx/stwbrx. 5140 if (cast<StoreSDNode>(N)->isUnindexed() && 5141 N->getOperand(1).getOpcode() == ISD::BSWAP && 5142 N->getOperand(1).getNode()->hasOneUse() && 5143 (N->getOperand(1).getValueType() == MVT::i32 || 5144 N->getOperand(1).getValueType() == MVT::i16)) { 5145 SDValue BSwapOp = N->getOperand(1).getOperand(0); 5146 // Do an any-extend to 32-bits if this is a half-word input. 5147 if (BSwapOp.getValueType() == MVT::i16) 5148 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); 5149 5150 SDValue Ops[] = { 5151 N->getOperand(0), BSwapOp, N->getOperand(2), 5152 DAG.getValueType(N->getOperand(1).getValueType()) 5153 }; 5154 return 5155 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), 5156 Ops, array_lengthof(Ops), 5157 cast<StoreSDNode>(N)->getMemoryVT(), 5158 cast<StoreSDNode>(N)->getMemOperand()); 5159 } 5160 break; 5161 case ISD::BSWAP: 5162 // Turn BSWAP (LOAD) -> lhbrx/lwbrx. 5163 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && 5164 N->getOperand(0).hasOneUse() && 5165 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { 5166 SDValue Load = N->getOperand(0); 5167 LoadSDNode *LD = cast<LoadSDNode>(Load); 5168 // Create the byte-swapping load. 5169 SDValue Ops[] = { 5170 LD->getChain(), // Chain 5171 LD->getBasePtr(), // Ptr 5172 DAG.getValueType(N->getValueType(0)) // VT 5173 }; 5174 SDValue BSLoad = 5175 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, 5176 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3, 5177 LD->getMemoryVT(), LD->getMemOperand()); 5178 5179 // If this is an i16 load, insert the truncate. 5180 SDValue ResVal = BSLoad; 5181 if (N->getValueType(0) == MVT::i16) 5182 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); 5183 5184 // First, combine the bswap away. This makes the value produced by the 5185 // load dead. 5186 DCI.CombineTo(N, ResVal); 5187 5188 // Next, combine the load away, we give it a bogus result value but a real 5189 // chain result. The result value is dead because the bswap is dead. 5190 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1)); 5191 5192 // Return N so it doesn't get rechecked! 5193 return SDValue(N, 0); 5194 } 5195 5196 break; 5197 case PPCISD::VCMP: { 5198 // If a VCMPo node already exists with exactly the same operands as this 5199 // node, use its result instead of this node (VCMPo computes both a CR6 and 5200 // a normal output). 5201 // 5202 if (!N->getOperand(0).hasOneUse() && 5203 !N->getOperand(1).hasOneUse() && 5204 !N->getOperand(2).hasOneUse()) { 5205 5206 // Scan all of the users of the LHS, looking for VCMPo's that match. 5207 SDNode *VCMPoNode = 0; 5208 5209 SDNode *LHSN = N->getOperand(0).getNode(); 5210 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end(); 5211 UI != E; ++UI) 5212 if (UI->getOpcode() == PPCISD::VCMPo && 5213 UI->getOperand(1) == N->getOperand(1) && 5214 UI->getOperand(2) == N->getOperand(2) && 5215 UI->getOperand(0) == N->getOperand(0)) { 5216 VCMPoNode = *UI; 5217 break; 5218 } 5219 5220 // If there is no VCMPo node, or if the flag value has a single use, don't 5221 // transform this. 5222 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1)) 5223 break; 5224 5225 // Look at the (necessarily single) use of the flag value. If it has a 5226 // chain, this transformation is more complex. Note that multiple things 5227 // could use the value result, which we should ignore. 5228 SDNode *FlagUser = 0; 5229 for (SDNode::use_iterator UI = VCMPoNode->use_begin(); 5230 FlagUser == 0; ++UI) { 5231 assert(UI != VCMPoNode->use_end() && "Didn't find user!"); 5232 SDNode *User = *UI; 5233 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 5234 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) { 5235 FlagUser = User; 5236 break; 5237 } 5238 } 5239 } 5240 5241 // If the user is a MFCR instruction, we know this is safe. Otherwise we 5242 // give up for right now. 5243 if (FlagUser->getOpcode() == PPCISD::MFCR) 5244 return SDValue(VCMPoNode, 0); 5245 } 5246 break; 5247 } 5248 case ISD::BR_CC: { 5249 // If this is a branch on an altivec predicate comparison, lower this so 5250 // that we don't have to do a MFCR: instead, branch directly on CR6. This 5251 // lowering is done pre-legalize, because the legalizer lowers the predicate 5252 // compare down to code that is difficult to reassemble. 5253 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 5254 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3); 5255 int CompareOpc; 5256 bool isDot; 5257 5258 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN && 5259 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && 5260 getAltivecCompareInfo(LHS, CompareOpc, isDot)) { 5261 assert(isDot && "Can't compare against a vector result!"); 5262 5263 // If this is a comparison against something other than 0/1, then we know 5264 // that the condition is never/always true. 5265 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue(); 5266 if (Val != 0 && Val != 1) { 5267 if (CC == ISD::SETEQ) // Cond never true, remove branch. 5268 return N->getOperand(0); 5269 // Always !=, turn it into an unconditional branch. 5270 return DAG.getNode(ISD::BR, dl, MVT::Other, 5271 N->getOperand(0), N->getOperand(4)); 5272 } 5273 5274 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); 5275 5276 // Create the PPCISD altivec 'dot' comparison node. 5277 std::vector<EVT> VTs; 5278 SDValue Ops[] = { 5279 LHS.getOperand(2), // LHS of compare 5280 LHS.getOperand(3), // RHS of compare 5281 DAG.getConstant(CompareOpc, MVT::i32) 5282 }; 5283 VTs.push_back(LHS.getOperand(2).getValueType()); 5284 VTs.push_back(MVT::Flag); 5285 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); 5286 5287 // Unpack the result based on how the target uses it. 5288 PPC::Predicate CompOpc; 5289 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) { 5290 default: // Can't happen, don't crash on invalid number though. 5291 case 0: // Branch on the value of the EQ bit of CR6. 5292 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; 5293 break; 5294 case 1: // Branch on the inverted value of the EQ bit of CR6. 5295 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; 5296 break; 5297 case 2: // Branch on the value of the LT bit of CR6. 5298 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; 5299 break; 5300 case 3: // Branch on the inverted value of the LT bit of CR6. 5301 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; 5302 break; 5303 } 5304 5305 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), 5306 DAG.getConstant(CompOpc, MVT::i32), 5307 DAG.getRegister(PPC::CR6, MVT::i32), 5308 N->getOperand(4), CompNode.getValue(1)); 5309 } 5310 break; 5311 } 5312 } 5313 5314 return SDValue(); 5315} 5316 5317//===----------------------------------------------------------------------===// 5318// Inline Assembly Support 5319//===----------------------------------------------------------------------===// 5320 5321void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 5322 const APInt &Mask, 5323 APInt &KnownZero, 5324 APInt &KnownOne, 5325 const SelectionDAG &DAG, 5326 unsigned Depth) const { 5327 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 5328 switch (Op.getOpcode()) { 5329 default: break; 5330 case PPCISD::LBRX: { 5331 // lhbrx is known to have the top bits cleared out. 5332 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) 5333 KnownZero = 0xFFFF0000; 5334 break; 5335 } 5336 case ISD::INTRINSIC_WO_CHAIN: { 5337 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) { 5338 default: break; 5339 case Intrinsic::ppc_altivec_vcmpbfp_p: 5340 case Intrinsic::ppc_altivec_vcmpeqfp_p: 5341 case Intrinsic::ppc_altivec_vcmpequb_p: 5342 case Intrinsic::ppc_altivec_vcmpequh_p: 5343 case Intrinsic::ppc_altivec_vcmpequw_p: 5344 case Intrinsic::ppc_altivec_vcmpgefp_p: 5345 case Intrinsic::ppc_altivec_vcmpgtfp_p: 5346 case Intrinsic::ppc_altivec_vcmpgtsb_p: 5347 case Intrinsic::ppc_altivec_vcmpgtsh_p: 5348 case Intrinsic::ppc_altivec_vcmpgtsw_p: 5349 case Intrinsic::ppc_altivec_vcmpgtub_p: 5350 case Intrinsic::ppc_altivec_vcmpgtuh_p: 5351 case Intrinsic::ppc_altivec_vcmpgtuw_p: 5352 KnownZero = ~1U; // All bits but the low one are known to be zero. 5353 break; 5354 } 5355 } 5356 } 5357} 5358 5359 5360/// getConstraintType - Given a constraint, return the type of 5361/// constraint it is for this target. 5362PPCTargetLowering::ConstraintType 5363PPCTargetLowering::getConstraintType(const std::string &Constraint) const { 5364 if (Constraint.size() == 1) { 5365 switch (Constraint[0]) { 5366 default: break; 5367 case 'b': 5368 case 'r': 5369 case 'f': 5370 case 'v': 5371 case 'y': 5372 return C_RegisterClass; 5373 } 5374 } 5375 return TargetLowering::getConstraintType(Constraint); 5376} 5377 5378std::pair<unsigned, const TargetRegisterClass*> 5379PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 5380 EVT VT) const { 5381 if (Constraint.size() == 1) { 5382 // GCC RS6000 Constraint Letters 5383 switch (Constraint[0]) { 5384 case 'b': // R1-R31 5385 case 'r': // R0-R31 5386 if (VT == MVT::i64 && PPCSubTarget.isPPC64()) 5387 return std::make_pair(0U, PPC::G8RCRegisterClass); 5388 return std::make_pair(0U, PPC::GPRCRegisterClass); 5389 case 'f': 5390 if (VT == MVT::f32) 5391 return std::make_pair(0U, PPC::F4RCRegisterClass); 5392 else if (VT == MVT::f64) 5393 return std::make_pair(0U, PPC::F8RCRegisterClass); 5394 break; 5395 case 'v': 5396 return std::make_pair(0U, PPC::VRRCRegisterClass); 5397 case 'y': // crrc 5398 return std::make_pair(0U, PPC::CRRCRegisterClass); 5399 } 5400 } 5401 5402 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 5403} 5404 5405 5406/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 5407/// vector. If it is invalid, don't add anything to Ops. 5408void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, 5409 std::vector<SDValue>&Ops, 5410 SelectionDAG &DAG) const { 5411 SDValue Result(0,0); 5412 switch (Letter) { 5413 default: break; 5414 case 'I': 5415 case 'J': 5416 case 'K': 5417 case 'L': 5418 case 'M': 5419 case 'N': 5420 case 'O': 5421 case 'P': { 5422 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op); 5423 if (!CST) return; // Must be an immediate to match. 5424 unsigned Value = CST->getZExtValue(); 5425 switch (Letter) { 5426 default: llvm_unreachable("Unknown constraint letter!"); 5427 case 'I': // "I" is a signed 16-bit constant. 5428 if ((short)Value == (int)Value) 5429 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5430 break; 5431 case 'J': // "J" is a constant with only the high-order 16 bits nonzero. 5432 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. 5433 if ((short)Value == 0) 5434 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5435 break; 5436 case 'K': // "K" is a constant with only the low-order 16 bits nonzero. 5437 if ((Value >> 16) == 0) 5438 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5439 break; 5440 case 'M': // "M" is a constant that is greater than 31. 5441 if (Value > 31) 5442 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5443 break; 5444 case 'N': // "N" is a positive constant that is an exact power of two. 5445 if ((int)Value > 0 && isPowerOf2_32(Value)) 5446 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5447 break; 5448 case 'O': // "O" is the constant zero. 5449 if (Value == 0) 5450 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5451 break; 5452 case 'P': // "P" is a constant whose negation is a signed 16-bit constant. 5453 if ((short)-Value == (int)-Value) 5454 Result = DAG.getTargetConstant(Value, Op.getValueType()); 5455 break; 5456 } 5457 break; 5458 } 5459 } 5460 5461 if (Result.getNode()) { 5462 Ops.push_back(Result); 5463 return; 5464 } 5465 5466 // Handle standard constraint letters. 5467 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); 5468} 5469 5470// isLegalAddressingMode - Return true if the addressing mode represented 5471// by AM is legal for this target, for a load/store of the specified type. 5472bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 5473 const Type *Ty) const { 5474 // FIXME: PPC does not allow r+i addressing modes for vectors! 5475 5476 // PPC allows a sign-extended 16-bit immediate field. 5477 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 5478 return false; 5479 5480 // No global is ever allowed as a base. 5481 if (AM.BaseGV) 5482 return false; 5483 5484 // PPC only support r+r, 5485 switch (AM.Scale) { 5486 case 0: // "r+i" or just "i", depending on HasBaseReg. 5487 break; 5488 case 1: 5489 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 5490 return false; 5491 // Otherwise we have r+r or r+i. 5492 break; 5493 case 2: 5494 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 5495 return false; 5496 // Allow 2*r as r+r. 5497 break; 5498 default: 5499 // No other scales are supported. 5500 return false; 5501 } 5502 5503 return true; 5504} 5505 5506/// isLegalAddressImmediate - Return true if the integer value can be used 5507/// as the offset of the target addressing mode for load / store of the 5508/// given type. 5509bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{ 5510 // PPC allows a sign-extended 16-bit immediate field. 5511 return (V > -(1 << 16) && V < (1 << 16)-1); 5512} 5513 5514bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { 5515 return false; 5516} 5517 5518SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, 5519 SelectionDAG &DAG) const { 5520 MachineFunction &MF = DAG.getMachineFunction(); 5521 MachineFrameInfo *MFI = MF.getFrameInfo(); 5522 MFI->setReturnAddressIsTaken(true); 5523 5524 DebugLoc dl = Op.getDebugLoc(); 5525 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5526 5527 // Make sure the function does not optimize away the store of the RA to 5528 // the stack. 5529 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 5530 FuncInfo->setLRStoreRequired(); 5531 bool isPPC64 = PPCSubTarget.isPPC64(); 5532 bool isDarwinABI = PPCSubTarget.isDarwinABI(); 5533 5534 if (Depth > 0) { 5535 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 5536 SDValue Offset = 5537 5538 DAG.getConstant(PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI), 5539 isPPC64? MVT::i64 : MVT::i32); 5540 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5541 DAG.getNode(ISD::ADD, dl, getPointerTy(), 5542 FrameAddr, Offset), 5543 MachinePointerInfo(), false, false, 0); 5544 } 5545 5546 // Just load the return address off the stack. 5547 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG); 5548 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 5549 RetAddrFI, MachinePointerInfo(), false, false, 0); 5550} 5551 5552SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, 5553 SelectionDAG &DAG) const { 5554 DebugLoc dl = Op.getDebugLoc(); 5555 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 5556 5557 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 5558 bool isPPC64 = PtrVT == MVT::i64; 5559 5560 MachineFunction &MF = DAG.getMachineFunction(); 5561 MachineFrameInfo *MFI = MF.getFrameInfo(); 5562 MFI->setFrameAddressIsTaken(true); 5563 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) && 5564 MFI->getStackSize() && 5565 !MF.getFunction()->hasFnAttr(Attribute::Naked); 5566 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) : 5567 (is31 ? PPC::R31 : PPC::R1); 5568 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, 5569 PtrVT); 5570 while (Depth--) 5571 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), 5572 FrameAddr, MachinePointerInfo(), false, false, 0); 5573 return FrameAddr; 5574} 5575 5576bool 5577PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 5578 // The PowerPC target isn't yet aware of offsets. 5579 return false; 5580} 5581 5582/// getOptimalMemOpType - Returns the target specific optimal type for load 5583/// and store operations as a result of memset, memcpy, and memmove 5584/// lowering. If DstAlign is zero that means it's safe to destination 5585/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 5586/// means there isn't a need to check it against alignment requirement, 5587/// probably because the source does not need to be loaded. If 5588/// 'NonScalarIntSafe' is true, that means it's safe to return a 5589/// non-scalar-integer type, e.g. empty string source, constant, or loaded 5590/// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 5591/// constant so it does not need to be loaded. 5592/// It returns EVT::Other if the type should be determined using generic 5593/// target-independent logic. 5594EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, 5595 unsigned DstAlign, unsigned SrcAlign, 5596 bool NonScalarIntSafe, 5597 bool MemcpyStrSrc, 5598 MachineFunction &MF) const { 5599 if (this->PPCSubTarget.isPPC64()) { 5600 return MVT::i64; 5601 } else { 5602 return MVT::i32; 5603 } 5604} 5605