PPCISelLowering.cpp revision 53e884587bd4b56c14dc39600eb655e77ae7b905
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the PPCISelLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCISelLowering.h" 15#include "PPCTargetMachine.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "llvm/CodeGen/SSARegMap.h" 21#include "llvm/Constants.h" 22#include "llvm/Function.h" 23using namespace llvm; 24 25PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) 26 : TargetLowering(TM) { 27 28 // Fold away setcc operations if possible. 29 setSetCCIsExpensive(); 30 setPow2DivIsCheap(); 31 32 // Use _setjmp/_longjmp instead of setjmp/longjmp. 33 setUseUnderscoreSetJmpLongJmp(true); 34 35 // Set up the register classes. 36 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); 37 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); 38 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); 39 40 // PowerPC has no intrinsics for these particular operations 41 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 42 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 43 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 44 45 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 46 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand); 47 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand); 48 49 // PowerPC has no SREM/UREM instructions 50 setOperationAction(ISD::SREM, MVT::i32, Expand); 51 setOperationAction(ISD::UREM, MVT::i32, Expand); 52 53 // We don't support sin/cos/sqrt/fmod 54 setOperationAction(ISD::FSIN , MVT::f64, Expand); 55 setOperationAction(ISD::FCOS , MVT::f64, Expand); 56 setOperationAction(ISD::FREM , MVT::f64, Expand); 57 setOperationAction(ISD::FSIN , MVT::f32, Expand); 58 setOperationAction(ISD::FCOS , MVT::f32, Expand); 59 setOperationAction(ISD::FREM , MVT::f32, Expand); 60 61 // If we're enabling GP optimizations, use hardware square root 62 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 63 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 64 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 65 } 66 67 // PowerPC does not have CTPOP or CTTZ 68 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); 69 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); 70 71 // PowerPC does not have Select 72 setOperationAction(ISD::SELECT, MVT::i32, Expand); 73 setOperationAction(ISD::SELECT, MVT::f32, Expand); 74 setOperationAction(ISD::SELECT, MVT::f64, Expand); 75 76 // PowerPC wants to turn select_cc of FP into fsel when possible. 77 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 78 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 79 80 // PowerPC does not have BRCOND* which requires SetCC 81 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 82 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 83 84 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. 85 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 86 87 // PowerPC does not have [U|S]INT_TO_FP 88 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 89 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 90 91 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 92 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 93 94 // PowerPC does not have truncstore for i1. 95 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote); 96 97 // PowerPC doesn't have line number support yet. 98 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 99 100 // We want to legalize GlobalAddress and ConstantPool nodes into the 101 // appropriate instructions to materialize the address. 102 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 103 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 104 105 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) { 106 // They also have instructions for converting between i64 and fp. 107 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 108 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 109 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT 110 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); 111 } else { 112 // PowerPC does not have FP_TO_UINT on 32-bit implementations. 113 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 114 } 115 116 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) { 117 // 64 bit PowerPC implementations can support i64 types directly 118 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); 119 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or 120 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 121 } else { 122 // 32 bit PowerPC wants to expand i64 shifts itself. 123 setOperationAction(ISD::SHL, MVT::i64, Custom); 124 setOperationAction(ISD::SRL, MVT::i64, Custom); 125 setOperationAction(ISD::SRA, MVT::i64, Custom); 126 } 127 128 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { 129 // FIXME: AltiVec supports a wide variety of packed types. For now, we're 130 // bringing up support with just v4f32. 131 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); 132 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); 133 } 134 135 setSetCCResultContents(ZeroOrOneSetCCResult); 136 137 computeRegisterProperties(); 138} 139 140/// isFloatingPointZero - Return true if this is 0.0 or -0.0. 141static bool isFloatingPointZero(SDOperand Op) { 142 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 143 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 144 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) { 145 // Maybe this has already been legalized into the constant pool? 146 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1))) 147 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get())) 148 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0); 149 } 150 return false; 151} 152 153/// LowerOperation - Provide custom lowering hooks for some operations. 154/// 155SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 156 switch (Op.getOpcode()) { 157 default: assert(0 && "Wasn't expecting to be able to lower this!"); 158 case ISD::FP_TO_SINT: { 159 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType())); 160 SDOperand Src = Op.getOperand(0); 161 if (Src.getValueType() == MVT::f32) 162 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src); 163 164 SDOperand Tmp; 165 switch (Op.getValueType()) { 166 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!"); 167 case MVT::i32: 168 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src); 169 break; 170 case MVT::i64: 171 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src); 172 break; 173 } 174 175 // Convert the FP value to an int value through memory. 176 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp); 177 if (Op.getValueType() == MVT::i32) 178 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits); 179 return Bits; 180 } 181 case ISD::SINT_TO_FP: { 182 assert(MVT::i64 == Op.getOperand(0).getValueType() && 183 "Unhandled SINT_TO_FP type in custom expander!"); 184 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); 185 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits); 186 if (MVT::f32 == Op.getValueType()) 187 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); 188 return FP; 189 } 190 case ISD::SELECT_CC: { 191 // Turn FP only select_cc's into fsel instructions. 192 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) || 193 !MVT::isFloatingPoint(Op.getOperand(2).getValueType())) 194 break; 195 196 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 197 198 // Cannot handle SETEQ/SETNE. 199 if (CC == ISD::SETEQ || CC == ISD::SETNE) break; 200 201 MVT::ValueType ResVT = Op.getValueType(); 202 MVT::ValueType CmpVT = Op.getOperand(0).getValueType(); 203 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1); 204 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3); 205 206 // If the RHS of the comparison is a 0.0, we don't need to do the 207 // subtraction at all. 208 if (isFloatingPointZero(RHS)) 209 switch (CC) { 210 default: assert(0 && "Invalid FSEL condition"); abort(); 211 case ISD::SETULT: 212 case ISD::SETLT: 213 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 214 case ISD::SETUGE: 215 case ISD::SETGE: 216 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 217 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 218 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV); 219 case ISD::SETUGT: 220 case ISD::SETGT: 221 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt 222 case ISD::SETULE: 223 case ISD::SETLE: 224 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits 225 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS); 226 return DAG.getNode(PPCISD::FSEL, ResVT, 227 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV); 228 } 229 230 SDOperand Cmp; 231 switch (CC) { 232 default: assert(0 && "Invalid FSEL condition"); abort(); 233 case ISD::SETULT: 234 case ISD::SETLT: 235 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 236 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 237 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 238 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 239 case ISD::SETUGE: 240 case ISD::SETGE: 241 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); 242 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 243 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 244 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 245 case ISD::SETUGT: 246 case ISD::SETGT: 247 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 248 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 249 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 250 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV); 251 case ISD::SETULE: 252 case ISD::SETLE: 253 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS); 254 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits 255 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp); 256 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV); 257 } 258 break; 259 } 260 case ISD::SHL: { 261 assert(Op.getValueType() == MVT::i64 && 262 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 263 // The generic code does a fine job expanding shift by a constant. 264 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 265 266 // Otherwise, expand into a bunch of logical ops. Note that these ops 267 // depend on the PPC behavior for oversized shift amounts. 268 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 269 DAG.getConstant(0, MVT::i32)); 270 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 271 DAG.getConstant(1, MVT::i32)); 272 SDOperand Amt = Op.getOperand(1); 273 274 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 275 DAG.getConstant(32, MVT::i32), Amt); 276 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt); 277 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1); 278 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 279 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 280 DAG.getConstant(-32U, MVT::i32)); 281 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5); 282 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 283 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt); 284 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 285 } 286 case ISD::SRL: { 287 assert(Op.getValueType() == MVT::i64 && 288 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); 289 // The generic code does a fine job expanding shift by a constant. 290 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 291 292 // Otherwise, expand into a bunch of logical ops. Note that these ops 293 // depend on the PPC behavior for oversized shift amounts. 294 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 295 DAG.getConstant(0, MVT::i32)); 296 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 297 DAG.getConstant(1, MVT::i32)); 298 SDOperand Amt = Op.getOperand(1); 299 300 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 301 DAG.getConstant(32, MVT::i32), Amt); 302 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 303 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 304 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 305 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 306 DAG.getConstant(-32U, MVT::i32)); 307 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5); 308 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6); 309 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt); 310 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 311 } 312 case ISD::SRA: { 313 assert(Op.getValueType() == MVT::i64 && 314 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); 315 // The generic code does a fine job expanding shift by a constant. 316 if (isa<ConstantSDNode>(Op.getOperand(1))) break; 317 318 // Otherwise, expand into a bunch of logical ops, followed by a select_cc. 319 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 320 DAG.getConstant(0, MVT::i32)); 321 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 322 DAG.getConstant(1, MVT::i32)); 323 SDOperand Amt = Op.getOperand(1); 324 325 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, 326 DAG.getConstant(32, MVT::i32), Amt); 327 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt); 328 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1); 329 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3); 330 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt, 331 DAG.getConstant(-32U, MVT::i32)); 332 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5); 333 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt); 334 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32), 335 Tmp4, Tmp6, ISD::SETLE); 336 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); 337 } 338 case ISD::ConstantPool: { 339 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 340 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32); 341 SDOperand Zero = DAG.getConstant(0, MVT::i32); 342 343 if (PPCGenerateStaticCode) { 344 // Generate non-pic code that has direct accesses to the constant pool. 345 // The address of the global is just (hi(&g)+lo(&g)). 346 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 347 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 348 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 349 } 350 351 // Only lower ConstantPool on Darwin. 352 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 353 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero); 354 if (PICEnabled) { 355 // With PIC, the first instruction is actually "GR+hi(&G)". 356 Hi = DAG.getNode(ISD::ADD, MVT::i32, 357 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 358 } 359 360 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero); 361 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 362 return Lo; 363 } 364 case ISD::GlobalAddress: { 365 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 366 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 367 SDOperand Zero = DAG.getConstant(0, MVT::i32); 368 369 if (PPCGenerateStaticCode) { 370 // Generate non-pic code that has direct accesses to globals. 371 // The address of the global is just (hi(&g)+lo(&g)). 372 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 373 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 374 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 375 } 376 377 // Only lower GlobalAddress on Darwin. 378 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break; 379 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero); 380 if (PICEnabled) { 381 // With PIC, the first instruction is actually "GR+hi(&G)". 382 Hi = DAG.getNode(ISD::ADD, MVT::i32, 383 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi); 384 } 385 386 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero); 387 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo); 388 389 if (!GV->hasWeakLinkage() && !GV->isExternal()) 390 return Lo; 391 392 // If the global is weak or external, we have to go through the lazy 393 // resolution stub. 394 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0)); 395 } 396 } 397 return SDOperand(); 398} 399 400std::vector<SDOperand> 401PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 402 // 403 // add beautiful description of PPC stack frame format, or at least some docs 404 // 405 MachineFunction &MF = DAG.getMachineFunction(); 406 MachineFrameInfo *MFI = MF.getFrameInfo(); 407 MachineBasicBlock& BB = MF.front(); 408 SSARegMap *RegMap = MF.getSSARegMap(); 409 std::vector<SDOperand> ArgValues; 410 411 unsigned ArgOffset = 24; 412 unsigned GPR_remaining = 8; 413 unsigned FPR_remaining = 13; 414 unsigned GPR_idx = 0, FPR_idx = 0; 415 static const unsigned GPR[] = { 416 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 417 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 418 }; 419 static const unsigned FPR[] = { 420 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 421 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 422 }; 423 424 // Add DAG nodes to load the arguments... On entry to a function on PPC, 425 // the arguments start at offset 24, although they are likely to be passed 426 // in registers. 427 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 428 SDOperand newroot, argt; 429 unsigned ObjSize; 430 bool needsLoad = false; 431 bool ArgLive = !I->use_empty(); 432 MVT::ValueType ObjectVT = getValueType(I->getType()); 433 434 switch (ObjectVT) { 435 default: assert(0 && "Unhandled argument type!"); 436 case MVT::i1: 437 case MVT::i8: 438 case MVT::i16: 439 case MVT::i32: 440 ObjSize = 4; 441 if (!ArgLive) break; 442 if (GPR_remaining > 0) { 443 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 444 MF.addLiveIn(GPR[GPR_idx], VReg); 445 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 446 if (ObjectVT != MVT::i32) { 447 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 448 : ISD::AssertZext; 449 argt = DAG.getNode(AssertOp, MVT::i32, argt, 450 DAG.getValueType(ObjectVT)); 451 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt); 452 } 453 } else { 454 needsLoad = true; 455 } 456 break; 457 case MVT::i64: 458 ObjSize = 8; 459 if (!ArgLive) break; 460 if (GPR_remaining > 0) { 461 SDOperand argHi, argLo; 462 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 463 MF.addLiveIn(GPR[GPR_idx], VReg); 464 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 465 // If we have two or more remaining argument registers, then both halves 466 // of the i64 can be sourced from there. Otherwise, the lower half will 467 // have to come off the stack. This can happen when an i64 is preceded 468 // by 28 bytes of arguments. 469 if (GPR_remaining > 1) { 470 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 471 MF.addLiveIn(GPR[GPR_idx+1], VReg); 472 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32); 473 } else { 474 int FI = MFI->CreateFixedObject(4, ArgOffset+4); 475 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 476 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN, 477 DAG.getSrcValue(NULL)); 478 } 479 // Build the outgoing arg thingy 480 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi); 481 newroot = argLo; 482 } else { 483 needsLoad = true; 484 } 485 break; 486 case MVT::f32: 487 case MVT::f64: 488 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4; 489 if (!ArgLive) break; 490 if (FPR_remaining > 0) { 491 unsigned VReg; 492 if (ObjectVT == MVT::f32) 493 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass); 494 else 495 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass); 496 MF.addLiveIn(FPR[FPR_idx], VReg); 497 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT); 498 --FPR_remaining; 499 ++FPR_idx; 500 } else { 501 needsLoad = true; 502 } 503 break; 504 } 505 506 // We need to load the argument to a virtual register if we determined above 507 // that we ran out of physical registers of the appropriate type 508 if (needsLoad) { 509 unsigned SubregOffset = 0; 510 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3; 511 if (ObjectVT == MVT::i16) SubregOffset = 2; 512 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 513 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 514 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, 515 DAG.getConstant(SubregOffset, MVT::i32)); 516 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN, 517 DAG.getSrcValue(NULL)); 518 } 519 520 // Every 4 bytes of argument space consumes one of the GPRs available for 521 // argument passing. 522 if (GPR_remaining > 0) { 523 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1; 524 GPR_remaining -= delta; 525 GPR_idx += delta; 526 } 527 ArgOffset += ObjSize; 528 if (newroot.Val) 529 DAG.setRoot(newroot.getValue(1)); 530 531 ArgValues.push_back(argt); 532 } 533 534 // If the function takes variable number of arguments, make a frame index for 535 // the start of the first vararg value... for expansion of llvm.va_start. 536 if (F.isVarArg()) { 537 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 538 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 539 // If this function is vararg, store any remaining integer argument regs 540 // to their spots on the stack so that they may be loaded by deferencing the 541 // result of va_next. 542 std::vector<SDOperand> MemOps; 543 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) { 544 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass); 545 MF.addLiveIn(GPR[GPR_idx], VReg); 546 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 547 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 548 Val, FIN, DAG.getSrcValue(NULL)); 549 MemOps.push_back(Store); 550 // Increment the address by four for the next argument to store 551 SDOperand PtrOff = DAG.getConstant(4, getPointerTy()); 552 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff); 553 } 554 if (!MemOps.empty()) { 555 MemOps.push_back(DAG.getRoot()); 556 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps)); 557 } 558 } 559 560 // Finally, inform the code generator which regs we return values in. 561 switch (getValueType(F.getReturnType())) { 562 default: assert(0 && "Unknown type!"); 563 case MVT::isVoid: break; 564 case MVT::i1: 565 case MVT::i8: 566 case MVT::i16: 567 case MVT::i32: 568 MF.addLiveOut(PPC::R3); 569 break; 570 case MVT::i64: 571 MF.addLiveOut(PPC::R3); 572 MF.addLiveOut(PPC::R4); 573 break; 574 case MVT::f32: 575 case MVT::f64: 576 MF.addLiveOut(PPC::F1); 577 break; 578 } 579 580 return ArgValues; 581} 582 583std::pair<SDOperand, SDOperand> 584PPCTargetLowering::LowerCallTo(SDOperand Chain, 585 const Type *RetTy, bool isVarArg, 586 unsigned CallingConv, bool isTailCall, 587 SDOperand Callee, ArgListTy &Args, 588 SelectionDAG &DAG) { 589 // args_to_use will accumulate outgoing args for the ISD::CALL case in 590 // SelectExpr to use to put the arguments in the appropriate registers. 591 std::vector<SDOperand> args_to_use; 592 593 // Count how many bytes are to be pushed on the stack, including the linkage 594 // area, and parameter passing area. 595 unsigned NumBytes = 24; 596 597 if (Args.empty()) { 598 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 599 DAG.getConstant(NumBytes, getPointerTy())); 600 } else { 601 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 602 switch (getValueType(Args[i].second)) { 603 default: assert(0 && "Unknown value type!"); 604 case MVT::i1: 605 case MVT::i8: 606 case MVT::i16: 607 case MVT::i32: 608 case MVT::f32: 609 NumBytes += 4; 610 break; 611 case MVT::i64: 612 case MVT::f64: 613 NumBytes += 8; 614 break; 615 } 616 } 617 618 // Just to be safe, we'll always reserve the full 24 bytes of linkage area 619 // plus 32 bytes of argument space in case any called code gets funky on us. 620 // (Required by ABI to support var arg) 621 if (NumBytes < 56) NumBytes = 56; 622 623 // Adjust the stack pointer for the new arguments... 624 // These operations are automatically eliminated by the prolog/epilog pass 625 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 626 DAG.getConstant(NumBytes, getPointerTy())); 627 628 // Set up a copy of the stack pointer for use loading and storing any 629 // arguments that may not fit in the registers available for argument 630 // passing. 631 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), 632 PPC::R1, MVT::i32); 633 634 // Figure out which arguments are going to go in registers, and which in 635 // memory. Also, if this is a vararg function, floating point operations 636 // must be stored to our stack, and loaded into integer regs as well, if 637 // any integer regs are available for argument passing. 638 unsigned ArgOffset = 24; 639 unsigned GPR_remaining = 8; 640 unsigned FPR_remaining = 13; 641 642 std::vector<SDOperand> MemOps; 643 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 644 // PtrOff will be used to store the current argument to the stack if a 645 // register cannot be found for it. 646 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 647 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 648 MVT::ValueType ArgVT = getValueType(Args[i].second); 649 650 switch (ArgVT) { 651 default: assert(0 && "Unexpected ValueType for argument!"); 652 case MVT::i1: 653 case MVT::i8: 654 case MVT::i16: 655 // Promote the integer to 32 bits. If the input type is signed use a 656 // sign extend, otherwise use a zero extend. 657 if (Args[i].second->isSigned()) 658 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first); 659 else 660 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first); 661 // FALL THROUGH 662 case MVT::i32: 663 if (GPR_remaining > 0) { 664 args_to_use.push_back(Args[i].first); 665 --GPR_remaining; 666 } else { 667 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 668 Args[i].first, PtrOff, 669 DAG.getSrcValue(NULL))); 670 } 671 ArgOffset += 4; 672 break; 673 case MVT::i64: 674 // If we have one free GPR left, we can place the upper half of the i64 675 // in it, and store the other half to the stack. If we have two or more 676 // free GPRs, then we can pass both halves of the i64 in registers. 677 if (GPR_remaining > 0) { 678 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 679 Args[i].first, DAG.getConstant(1, MVT::i32)); 680 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 681 Args[i].first, DAG.getConstant(0, MVT::i32)); 682 args_to_use.push_back(Hi); 683 --GPR_remaining; 684 if (GPR_remaining > 0) { 685 args_to_use.push_back(Lo); 686 --GPR_remaining; 687 } else { 688 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 689 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 690 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 691 Lo, PtrOff, DAG.getSrcValue(NULL))); 692 } 693 } else { 694 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 695 Args[i].first, PtrOff, 696 DAG.getSrcValue(NULL))); 697 } 698 ArgOffset += 8; 699 break; 700 case MVT::f32: 701 case MVT::f64: 702 if (FPR_remaining > 0) { 703 args_to_use.push_back(Args[i].first); 704 --FPR_remaining; 705 if (isVarArg) { 706 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 707 Args[i].first, PtrOff, 708 DAG.getSrcValue(NULL)); 709 MemOps.push_back(Store); 710 // Float varargs are always shadowed in available integer registers 711 if (GPR_remaining > 0) { 712 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 713 DAG.getSrcValue(NULL)); 714 MemOps.push_back(Load.getValue(1)); 715 args_to_use.push_back(Load); 716 --GPR_remaining; 717 } 718 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 719 SDOperand ConstFour = DAG.getConstant(4, getPointerTy()); 720 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour); 721 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff, 722 DAG.getSrcValue(NULL)); 723 MemOps.push_back(Load.getValue(1)); 724 args_to_use.push_back(Load); 725 --GPR_remaining; 726 } 727 } else { 728 // If we have any FPRs remaining, we may also have GPRs remaining. 729 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available 730 // GPRs. 731 if (GPR_remaining > 0) { 732 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 733 --GPR_remaining; 734 } 735 if (GPR_remaining > 0 && MVT::f64 == ArgVT) { 736 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 737 --GPR_remaining; 738 } 739 } 740 } else { 741 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 742 Args[i].first, PtrOff, 743 DAG.getSrcValue(NULL))); 744 } 745 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8; 746 break; 747 } 748 } 749 if (!MemOps.empty()) 750 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps); 751 } 752 753 std::vector<MVT::ValueType> RetVals; 754 MVT::ValueType RetTyVT = getValueType(RetTy); 755 MVT::ValueType ActualRetTyVT = RetTyVT; 756 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 757 ActualRetTyVT = MVT::i32; // Promote result to i32. 758 759 if (RetTyVT != MVT::isVoid) 760 RetVals.push_back(ActualRetTyVT); 761 RetVals.push_back(MVT::Other); 762 763 // If the callee is a GlobalAddress node (quite common, every direct call is) 764 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 765 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 766 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 767 768 SDOperand TheCall = SDOperand(DAG.getCall(RetVals, 769 Chain, Callee, args_to_use), 0); 770 Chain = TheCall.getValue(RetTyVT != MVT::isVoid); 771 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 772 DAG.getConstant(NumBytes, getPointerTy())); 773 SDOperand RetVal = TheCall; 774 775 // If the result is a small value, add a note so that we keep track of the 776 // information about whether it is sign or zero extended. 777 if (RetTyVT != ActualRetTyVT) { 778 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext, 779 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 780 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 781 } 782 783 return std::make_pair(RetVal, Chain); 784} 785 786SDOperand PPCTargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 787 SelectionDAG &DAG) { 788 SDOperand Copy; 789 switch (Op.getValueType()) { 790 default: assert(0 && "Unknown type to return!"); 791 case MVT::i32: 792 Copy = DAG.getCopyToReg(Chain, PPC::R3, Op, SDOperand()); 793 break; 794 case MVT::f32: 795 case MVT::f64: 796 Copy = DAG.getCopyToReg(Chain, PPC::F1, Op, SDOperand()); 797 break; 798 case MVT::i64: 799 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 800 DAG.getConstant(1, MVT::i32)); 801 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 802 DAG.getConstant(0, MVT::i32)); 803 Copy = DAG.getCopyToReg(Chain, PPC::R3, Hi, SDOperand()); 804 Copy = DAG.getCopyToReg(Copy, PPC::R4, Lo, Copy.getValue(1)); 805 break; 806 } 807 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 808} 809 810SDOperand PPCTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP, 811 Value *VAListV, SelectionDAG &DAG) { 812 // vastart just stores the address of the VarArgsFrameIndex slot into the 813 // memory location argument. 814 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32); 815 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP, 816 DAG.getSrcValue(VAListV)); 817} 818 819std::pair<SDOperand,SDOperand> 820PPCTargetLowering::LowerVAArg(SDOperand Chain, 821 SDOperand VAListP, Value *VAListV, 822 const Type *ArgTy, SelectionDAG &DAG) { 823 MVT::ValueType ArgVT = getValueType(ArgTy); 824 825 SDOperand VAList = 826 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV)); 827 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL)); 828 unsigned Amt; 829 if (ArgVT == MVT::i32 || ArgVT == MVT::f32) 830 Amt = 4; 831 else { 832 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) && 833 "Other types should have been promoted for varargs!"); 834 Amt = 8; 835 } 836 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList, 837 DAG.getConstant(Amt, VAList.getValueType())); 838 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, 839 VAList, VAListP, DAG.getSrcValue(VAListV)); 840 return std::make_pair(Result, Chain); 841} 842 843 844std::pair<SDOperand, SDOperand> PPCTargetLowering:: 845LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth, 846 SelectionDAG &DAG) { 847 assert(0 && "LowerFrameReturnAddress unimplemented"); 848 abort(); 849} 850 851MachineBasicBlock * 852PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 853 MachineBasicBlock *BB) { 854 assert((MI->getOpcode() == PPC::SELECT_CC_Int || 855 MI->getOpcode() == PPC::SELECT_CC_F4 || 856 MI->getOpcode() == PPC::SELECT_CC_F8) && 857 "Unexpected instr type to insert"); 858 859 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 860 // control-flow pattern. The incoming instruction knows the destination vreg 861 // to set, the condition code register to branch on, the true/false values to 862 // select between, and a branch opcode to use. 863 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 864 ilist<MachineBasicBlock>::iterator It = BB; 865 ++It; 866 867 // thisMBB: 868 // ... 869 // TrueVal = ... 870 // cmpTY ccX, r1, r2 871 // bCC copy1MBB 872 // fallthrough --> copy0MBB 873 MachineBasicBlock *thisMBB = BB; 874 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 875 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 876 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2) 877 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 878 MachineFunction *F = BB->getParent(); 879 F->getBasicBlockList().insert(It, copy0MBB); 880 F->getBasicBlockList().insert(It, sinkMBB); 881 // Update machine-CFG edges 882 BB->addSuccessor(copy0MBB); 883 BB->addSuccessor(sinkMBB); 884 885 // copy0MBB: 886 // %FalseValue = ... 887 // # fallthrough to sinkMBB 888 BB = copy0MBB; 889 890 // Update machine-CFG edges 891 BB->addSuccessor(sinkMBB); 892 893 // sinkMBB: 894 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 895 // ... 896 BB = sinkMBB; 897 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg()) 898 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 899 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 900 901 delete MI; // The pseudo instruction is gone now. 902 return BB; 903} 904 905